Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3 clock framework |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2008 Nokia Corporation |
| 6 | * |
| 7 | * Written by Paul Walmsley |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
| 9 | * DPLL bypass clock support added by Roman Tereshonkov |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Virtual clocks are introduced as convenient tools. |
| 15 | * They are sources for other clocks and not supposed |
| 16 | * to be requested from drivers directly. |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 21 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/control.h> |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 23 | |
| 24 | #include "clock.h" |
| 25 | #include "cm.h" |
| 26 | #include "cm-regbits-34xx.h" |
| 27 | #include "prm.h" |
| 28 | #include "prm-regbits-34xx.h" |
| 29 | |
| 30 | static void omap3_dpll_recalc(struct clk *clk); |
| 31 | static void omap3_clkoutx2_recalc(struct clk *clk); |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 32 | static void omap3_dpll_allow_idle(struct clk *clk); |
| 33 | static void omap3_dpll_deny_idle(struct clk *clk); |
| 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 35 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 36 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 37 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 38 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
| 39 | #define OMAP3_MAX_DPLL_MULT 2048 |
| 40 | #define OMAP3_MAX_DPLL_DIV 128 |
| 41 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 42 | /* |
| 43 | * DPLL1 supplies clock to the MPU. |
| 44 | * DPLL2 supplies clock to the IVA2. |
| 45 | * DPLL3 supplies CORE domain clocks. |
| 46 | * DPLL4 supplies peripheral clocks. |
| 47 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). |
| 48 | */ |
| 49 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 50 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 51 | #define DPLL_LOW_POWER_STOP 0x1 |
| 52 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 53 | #define DPLL_LOCKED 0x7 |
| 54 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 55 | /* PRM CLOCKS */ |
| 56 | |
| 57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
| 58 | static struct clk omap_32k_fck = { |
| 59 | .name = "omap_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 60 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 61 | .rate = 32768, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 62 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | static struct clk secure_32k_fck = { |
| 66 | .name = "secure_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 67 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 68 | .rate = 32768, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 69 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | /* Virtual source clocks for osc_sys_ck */ |
| 73 | static struct clk virt_12m_ck = { |
| 74 | .name = "virt_12m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 75 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 76 | .rate = 12000000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 77 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | static struct clk virt_13m_ck = { |
| 81 | .name = "virt_13m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 82 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 83 | .rate = 13000000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 84 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | static struct clk virt_16_8m_ck = { |
| 88 | .name = "virt_16_8m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 89 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 90 | .rate = 16800000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 91 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | static struct clk virt_19_2m_ck = { |
| 95 | .name = "virt_19_2m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 96 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 97 | .rate = 19200000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 98 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 99 | }; |
| 100 | |
| 101 | static struct clk virt_26m_ck = { |
| 102 | .name = "virt_26m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 103 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 104 | .rate = 26000000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 105 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | static struct clk virt_38_4m_ck = { |
| 109 | .name = "virt_38_4m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 110 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 111 | .rate = 38400000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 112 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | static const struct clksel_rate osc_sys_12m_rates[] = { |
| 116 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 117 | { .div = 0 } |
| 118 | }; |
| 119 | |
| 120 | static const struct clksel_rate osc_sys_13m_rates[] = { |
| 121 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 122 | { .div = 0 } |
| 123 | }; |
| 124 | |
| 125 | static const struct clksel_rate osc_sys_16_8m_rates[] = { |
| 126 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, |
| 127 | { .div = 0 } |
| 128 | }; |
| 129 | |
| 130 | static const struct clksel_rate osc_sys_19_2m_rates[] = { |
| 131 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 132 | { .div = 0 } |
| 133 | }; |
| 134 | |
| 135 | static const struct clksel_rate osc_sys_26m_rates[] = { |
| 136 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 137 | { .div = 0 } |
| 138 | }; |
| 139 | |
| 140 | static const struct clksel_rate osc_sys_38_4m_rates[] = { |
| 141 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 142 | { .div = 0 } |
| 143 | }; |
| 144 | |
| 145 | static const struct clksel osc_sys_clksel[] = { |
| 146 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, |
| 147 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, |
| 148 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, |
| 149 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, |
| 150 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, |
| 151 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, |
| 152 | { .parent = NULL }, |
| 153 | }; |
| 154 | |
| 155 | /* Oscillator clock */ |
| 156 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
| 157 | static struct clk osc_sys_ck = { |
| 158 | .name = "osc_sys_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 159 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 160 | .init = &omap2_init_clksel_parent, |
| 161 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
| 162 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 163 | .clksel = osc_sys_clksel, |
| 164 | /* REVISIT: deal with autoextclkmode? */ |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 165 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 166 | .recalc = &omap2_clksel_recalc, |
| 167 | }; |
| 168 | |
| 169 | static const struct clksel_rate div2_rates[] = { |
| 170 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 171 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 172 | { .div = 0 } |
| 173 | }; |
| 174 | |
| 175 | static const struct clksel sys_clksel[] = { |
| 176 | { .parent = &osc_sys_ck, .rates = div2_rates }, |
| 177 | { .parent = NULL } |
| 178 | }; |
| 179 | |
| 180 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ |
| 181 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
| 182 | static struct clk sys_ck = { |
| 183 | .name = "sys_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 184 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 185 | .parent = &osc_sys_ck, |
| 186 | .init = &omap2_init_clksel_parent, |
| 187 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
| 188 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
| 189 | .clksel = sys_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 190 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 191 | .recalc = &omap2_clksel_recalc, |
| 192 | }; |
| 193 | |
| 194 | static struct clk sys_altclk = { |
| 195 | .name = "sys_altclk", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 196 | .ops = &clkops_null, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 197 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 198 | }; |
| 199 | |
| 200 | /* Optional external clock input for some McBSPs */ |
| 201 | static struct clk mcbsp_clks = { |
| 202 | .name = "mcbsp_clks", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 203 | .ops = &clkops_null, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 204 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | /* PRM EXTERNAL CLOCK OUTPUT */ |
| 208 | |
| 209 | static struct clk sys_clkout1 = { |
| 210 | .name = "sys_clkout1", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 211 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 212 | .parent = &osc_sys_ck, |
| 213 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, |
| 214 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 215 | .recalc = &followparent_recalc, |
| 216 | }; |
| 217 | |
| 218 | /* DPLLS */ |
| 219 | |
| 220 | /* CM CLOCKS */ |
| 221 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 222 | static const struct clksel_rate dpll_bypass_rates[] = { |
| 223 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 224 | { .div = 0 } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 225 | }; |
| 226 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 227 | static const struct clksel_rate dpll_locked_rates[] = { |
| 228 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 229 | { .div = 0 } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 230 | }; |
| 231 | |
| 232 | static const struct clksel_rate div16_dpll_rates[] = { |
| 233 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 234 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 235 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 236 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 237 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, |
| 238 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 239 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, |
| 240 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 241 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, |
| 242 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, |
| 243 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, |
| 244 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, |
| 245 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, |
| 246 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, |
| 247 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, |
| 248 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, |
| 249 | { .div = 0 } |
| 250 | }; |
| 251 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 252 | /* DPLL1 */ |
| 253 | /* MPU clock source */ |
| 254 | /* Type: DPLL */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 255 | static struct dpll_data dpll1_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 256 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 257 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, |
| 258 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 259 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 260 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
| 261 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 262 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 263 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
| 264 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, |
| 265 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 266 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 267 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, |
| 268 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 269 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 270 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 271 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 272 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 273 | }; |
| 274 | |
| 275 | static struct clk dpll1_ck = { |
| 276 | .name = "dpll1_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 277 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 278 | .parent = &sys_ck, |
| 279 | .dpll_data = &dpll1_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 280 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 281 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 282 | .set_rate = &omap3_noncore_dpll_set_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 283 | .recalc = &omap3_dpll_recalc, |
| 284 | }; |
| 285 | |
| 286 | /* |
| 287 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 288 | * DPLL isn't bypassed. |
| 289 | */ |
| 290 | static struct clk dpll1_x2_ck = { |
| 291 | .name = "dpll1_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 292 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 293 | .parent = &dpll1_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 294 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 295 | .recalc = &omap3_clkoutx2_recalc, |
| 296 | }; |
| 297 | |
| 298 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ |
| 299 | static const struct clksel div16_dpll1_x2m2_clksel[] = { |
| 300 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, |
| 301 | { .parent = NULL } |
| 302 | }; |
| 303 | |
| 304 | /* |
| 305 | * Does not exist in the TRM - needed to separate the M2 divider from |
| 306 | * bypass selection in mpu_ck |
| 307 | */ |
| 308 | static struct clk dpll1_x2m2_ck = { |
| 309 | .name = "dpll1_x2m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 310 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 311 | .parent = &dpll1_x2_ck, |
| 312 | .init = &omap2_init_clksel_parent, |
| 313 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), |
| 314 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, |
| 315 | .clksel = div16_dpll1_x2m2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 316 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 317 | .recalc = &omap2_clksel_recalc, |
| 318 | }; |
| 319 | |
| 320 | /* DPLL2 */ |
| 321 | /* IVA2 clock source */ |
| 322 | /* Type: DPLL */ |
| 323 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 324 | static struct dpll_data dpll2_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 325 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 326 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, |
| 327 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 328 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 329 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
| 330 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 331 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
| 332 | (1 << DPLL_LOW_POWER_BYPASS), |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 333 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
| 334 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, |
| 335 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 336 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 337 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, |
| 338 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 339 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, |
| 340 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 341 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 342 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 343 | }; |
| 344 | |
| 345 | static struct clk dpll2_ck = { |
| 346 | .name = "dpll2_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 347 | .ops = &clkops_noncore_dpll_ops, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 348 | .parent = &sys_ck, |
| 349 | .dpll_data = &dpll2_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 350 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 351 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 352 | .set_rate = &omap3_noncore_dpll_set_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 353 | .recalc = &omap3_dpll_recalc, |
| 354 | }; |
| 355 | |
| 356 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
| 357 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, |
| 358 | { .parent = NULL } |
| 359 | }; |
| 360 | |
| 361 | /* |
| 362 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT |
| 363 | * or CLKOUTX2. CLKOUT seems most plausible. |
| 364 | */ |
| 365 | static struct clk dpll2_m2_ck = { |
| 366 | .name = "dpll2_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 367 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 368 | .parent = &dpll2_ck, |
| 369 | .init = &omap2_init_clksel_parent, |
| 370 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 371 | OMAP3430_CM_CLKSEL2_PLL), |
| 372 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, |
| 373 | .clksel = div16_dpll2_m2x2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 374 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 375 | .recalc = &omap2_clksel_recalc, |
| 376 | }; |
| 377 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 378 | /* |
| 379 | * DPLL3 |
| 380 | * Source clock for all interfaces and for some device fclks |
| 381 | * REVISIT: Also supports fast relock bypass - not included below |
| 382 | */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 383 | static struct dpll_data dpll3_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 384 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 385 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, |
| 386 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 387 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 388 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 389 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, |
| 390 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, |
| 391 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, |
| 392 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 393 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 394 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 395 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 396 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 397 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 398 | }; |
| 399 | |
| 400 | static struct clk dpll3_ck = { |
| 401 | .name = "dpll3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 402 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 403 | .parent = &sys_ck, |
| 404 | .dpll_data = &dpll3_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 405 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 406 | .round_rate = &omap2_dpll_round_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 407 | .recalc = &omap3_dpll_recalc, |
| 408 | }; |
| 409 | |
| 410 | /* |
| 411 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 412 | * DPLL isn't bypassed |
| 413 | */ |
| 414 | static struct clk dpll3_x2_ck = { |
| 415 | .name = "dpll3_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 416 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 417 | .parent = &dpll3_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 418 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 419 | .recalc = &omap3_clkoutx2_recalc, |
| 420 | }; |
| 421 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 422 | static const struct clksel_rate div31_dpll3_rates[] = { |
| 423 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 424 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 425 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, |
| 426 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, |
| 427 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, |
| 428 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, |
| 429 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, |
| 430 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, |
| 431 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, |
| 432 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, |
| 433 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, |
| 434 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, |
| 435 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, |
| 436 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, |
| 437 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, |
| 438 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, |
| 439 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, |
| 440 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, |
| 441 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, |
| 442 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, |
| 443 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, |
| 444 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, |
| 445 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, |
| 446 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, |
| 447 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, |
| 448 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, |
| 449 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, |
| 450 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, |
| 451 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, |
| 452 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, |
| 453 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, |
| 454 | { .div = 0 }, |
| 455 | }; |
| 456 | |
| 457 | static const struct clksel div31_dpll3m2_clksel[] = { |
| 458 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, |
| 459 | { .parent = NULL } |
| 460 | }; |
| 461 | |
| 462 | /* |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 463 | * DPLL3 output M2 |
| 464 | * REVISIT: This DPLL output divider must be changed in SRAM, so until |
| 465 | * that code is ready, this should remain a 'read-only' clksel clock. |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 466 | */ |
| 467 | static struct clk dpll3_m2_ck = { |
| 468 | .name = "dpll3_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 469 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 470 | .parent = &dpll3_ck, |
| 471 | .init = &omap2_init_clksel_parent, |
| 472 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 473 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, |
| 474 | .clksel = div31_dpll3m2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 475 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 476 | .recalc = &omap2_clksel_recalc, |
| 477 | }; |
| 478 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 479 | static const struct clksel core_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 480 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 481 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, |
| 482 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 483 | }; |
| 484 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 485 | static struct clk core_ck = { |
| 486 | .name = "core_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 487 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 488 | .init = &omap2_init_clksel_parent, |
| 489 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 490 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 491 | .clksel = core_ck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 492 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 493 | .recalc = &omap2_clksel_recalc, |
| 494 | }; |
| 495 | |
| 496 | static const struct clksel dpll3_m2x2_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 497 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 498 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, |
| 499 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 500 | }; |
| 501 | |
| 502 | static struct clk dpll3_m2x2_ck = { |
| 503 | .name = "dpll3_m2x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 504 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 505 | .init = &omap2_init_clksel_parent, |
| 506 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 507 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 508 | .clksel = dpll3_m2x2_ck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 509 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 510 | .recalc = &omap2_clksel_recalc, |
| 511 | }; |
| 512 | |
| 513 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 514 | static const struct clksel div16_dpll3_clksel[] = { |
| 515 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, |
| 516 | { .parent = NULL } |
| 517 | }; |
| 518 | |
| 519 | /* This virtual clock is the source for dpll3_m3x2_ck */ |
| 520 | static struct clk dpll3_m3_ck = { |
| 521 | .name = "dpll3_m3_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 522 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 523 | .parent = &dpll3_ck, |
| 524 | .init = &omap2_init_clksel_parent, |
| 525 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 526 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, |
| 527 | .clksel = div16_dpll3_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 528 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 529 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 530 | }; |
| 531 | |
| 532 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 533 | static struct clk dpll3_m3x2_ck = { |
| 534 | .name = "dpll3_m3x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 535 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 536 | .parent = &dpll3_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 537 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 538 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 539 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 540 | .recalc = &omap3_clkoutx2_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 541 | }; |
| 542 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 543 | static const struct clksel emu_core_alwon_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 544 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 545 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 546 | { .parent = NULL } |
| 547 | }; |
| 548 | |
| 549 | static struct clk emu_core_alwon_ck = { |
| 550 | .name = "emu_core_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 551 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 552 | .parent = &dpll3_m3x2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 553 | .init = &omap2_init_clksel_parent, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 554 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 555 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 556 | .clksel = emu_core_alwon_ck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 557 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 558 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 559 | }; |
| 560 | |
| 561 | /* DPLL4 */ |
| 562 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ |
| 563 | /* Type: DPLL */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 564 | static struct dpll_data dpll4_dd = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 565 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 566 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 567 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 568 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 569 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 570 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 571 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 572 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
| 573 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 574 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 575 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 576 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 577 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 578 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 579 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 580 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 581 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 582 | }; |
| 583 | |
| 584 | static struct clk dpll4_ck = { |
| 585 | .name = "dpll4_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 586 | .ops = &clkops_noncore_dpll_ops, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 587 | .parent = &sys_ck, |
| 588 | .dpll_data = &dpll4_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 589 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 590 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 591 | .set_rate = &omap3_dpll4_set_rate, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 592 | .recalc = &omap3_dpll_recalc, |
| 593 | }; |
| 594 | |
| 595 | /* |
| 596 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 597 | * DPLL isn't bypassed -- |
| 598 | * XXX does this serve any downstream clocks? |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 599 | */ |
| 600 | static struct clk dpll4_x2_ck = { |
| 601 | .name = "dpll4_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 602 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 603 | .parent = &dpll4_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 604 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 605 | .recalc = &omap3_clkoutx2_recalc, |
| 606 | }; |
| 607 | |
| 608 | static const struct clksel div16_dpll4_clksel[] = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 609 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 610 | { .parent = NULL } |
| 611 | }; |
| 612 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 613 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
| 614 | static struct clk dpll4_m2_ck = { |
| 615 | .name = "dpll4_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 616 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 617 | .parent = &dpll4_ck, |
| 618 | .init = &omap2_init_clksel_parent, |
| 619 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), |
| 620 | .clksel_mask = OMAP3430_DIV_96M_MASK, |
| 621 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 622 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 623 | .recalc = &omap2_clksel_recalc, |
| 624 | }; |
| 625 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 626 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 627 | static struct clk dpll4_m2x2_ck = { |
| 628 | .name = "dpll4_m2x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 629 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 630 | .parent = &dpll4_m2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 631 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 632 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 633 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 634 | .recalc = &omap3_clkoutx2_recalc, |
| 635 | }; |
| 636 | |
| 637 | static const struct clksel omap_96m_alwon_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 638 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 639 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
| 640 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 641 | }; |
| 642 | |
| 643 | static struct clk omap_96m_alwon_fck = { |
| 644 | .name = "omap_96m_alwon_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 645 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 646 | .parent = &dpll4_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 647 | .init = &omap2_init_clksel_parent, |
| 648 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 649 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 650 | .clksel = omap_96m_alwon_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 651 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 652 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 653 | }; |
| 654 | |
| 655 | static struct clk omap_96m_fck = { |
| 656 | .name = "omap_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 657 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 658 | .parent = &omap_96m_alwon_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 659 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 660 | .recalc = &followparent_recalc, |
| 661 | }; |
| 662 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 663 | static const struct clksel cm_96m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 664 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 665 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
| 666 | { .parent = NULL } |
| 667 | }; |
| 668 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 669 | static struct clk cm_96m_fck = { |
| 670 | .name = "cm_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 671 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 672 | .parent = &dpll4_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 673 | .init = &omap2_init_clksel_parent, |
| 674 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 675 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 676 | .clksel = cm_96m_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 677 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 678 | .recalc = &omap2_clksel_recalc, |
| 679 | }; |
| 680 | |
| 681 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
| 682 | static struct clk dpll4_m3_ck = { |
| 683 | .name = "dpll4_m3_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 684 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 685 | .parent = &dpll4_ck, |
| 686 | .init = &omap2_init_clksel_parent, |
| 687 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 688 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, |
| 689 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 690 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 691 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 692 | }; |
| 693 | |
| 694 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 695 | static struct clk dpll4_m3x2_ck = { |
| 696 | .name = "dpll4_m3x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 697 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 698 | .parent = &dpll4_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 699 | .init = &omap2_init_clksel_parent, |
| 700 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 701 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 702 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 703 | .recalc = &omap3_clkoutx2_recalc, |
| 704 | }; |
| 705 | |
| 706 | static const struct clksel virt_omap_54m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 707 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 708 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, |
| 709 | { .parent = NULL } |
| 710 | }; |
| 711 | |
| 712 | static struct clk virt_omap_54m_fck = { |
| 713 | .name = "virt_omap_54m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 714 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 715 | .parent = &dpll4_m3x2_ck, |
| 716 | .init = &omap2_init_clksel_parent, |
| 717 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 718 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 719 | .clksel = virt_omap_54m_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 720 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 721 | .recalc = &omap2_clksel_recalc, |
| 722 | }; |
| 723 | |
| 724 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
| 725 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 726 | { .div = 0 } |
| 727 | }; |
| 728 | |
| 729 | static const struct clksel_rate omap_54m_alt_rates[] = { |
| 730 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 731 | { .div = 0 } |
| 732 | }; |
| 733 | |
| 734 | static const struct clksel omap_54m_clksel[] = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 735 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 736 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
| 737 | { .parent = NULL } |
| 738 | }; |
| 739 | |
| 740 | static struct clk omap_54m_fck = { |
| 741 | .name = "omap_54m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 742 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 743 | .init = &omap2_init_clksel_parent, |
| 744 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 745 | .clksel_mask = OMAP3430_SOURCE_54M, |
| 746 | .clksel = omap_54m_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 747 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 748 | .recalc = &omap2_clksel_recalc, |
| 749 | }; |
| 750 | |
| 751 | static const struct clksel_rate omap_48m_96md2_rates[] = { |
| 752 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 753 | { .div = 0 } |
| 754 | }; |
| 755 | |
| 756 | static const struct clksel_rate omap_48m_alt_rates[] = { |
| 757 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 758 | { .div = 0 } |
| 759 | }; |
| 760 | |
| 761 | static const struct clksel omap_48m_clksel[] = { |
| 762 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, |
| 763 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
| 764 | { .parent = NULL } |
| 765 | }; |
| 766 | |
| 767 | static struct clk omap_48m_fck = { |
| 768 | .name = "omap_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 769 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 770 | .init = &omap2_init_clksel_parent, |
| 771 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 772 | .clksel_mask = OMAP3430_SOURCE_48M, |
| 773 | .clksel = omap_48m_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 774 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 775 | .recalc = &omap2_clksel_recalc, |
| 776 | }; |
| 777 | |
| 778 | static struct clk omap_12m_fck = { |
| 779 | .name = "omap_12m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 780 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 781 | .parent = &omap_48m_fck, |
| 782 | .fixed_div = 4, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 783 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 784 | .recalc = &omap2_fixed_divisor_recalc, |
| 785 | }; |
| 786 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 787 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
| 788 | static struct clk dpll4_m4_ck = { |
| 789 | .name = "dpll4_m4_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 790 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 791 | .parent = &dpll4_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 792 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 793 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 794 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, |
| 795 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 796 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 797 | .recalc = &omap2_clksel_recalc, |
| 798 | }; |
| 799 | |
| 800 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 801 | static struct clk dpll4_m4x2_ck = { |
| 802 | .name = "dpll4_m4x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 803 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 804 | .parent = &dpll4_m4_ck, |
| 805 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 806 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 807 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 808 | .recalc = &omap3_clkoutx2_recalc, |
| 809 | }; |
| 810 | |
| 811 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
| 812 | static struct clk dpll4_m5_ck = { |
| 813 | .name = "dpll4_m5_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 814 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 815 | .parent = &dpll4_ck, |
| 816 | .init = &omap2_init_clksel_parent, |
| 817 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
| 818 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, |
| 819 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 820 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 821 | .recalc = &omap2_clksel_recalc, |
| 822 | }; |
| 823 | |
| 824 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 825 | static struct clk dpll4_m5x2_ck = { |
| 826 | .name = "dpll4_m5x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 827 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 828 | .parent = &dpll4_m5_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 829 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 830 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 831 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 832 | .recalc = &omap3_clkoutx2_recalc, |
| 833 | }; |
| 834 | |
| 835 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
| 836 | static struct clk dpll4_m6_ck = { |
| 837 | .name = "dpll4_m6_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 838 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 839 | .parent = &dpll4_ck, |
| 840 | .init = &omap2_init_clksel_parent, |
| 841 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 842 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, |
| 843 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 844 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 845 | .recalc = &omap2_clksel_recalc, |
| 846 | }; |
| 847 | |
| 848 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 849 | static struct clk dpll4_m6x2_ck = { |
| 850 | .name = "dpll4_m6x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 851 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 852 | .parent = &dpll4_m6_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 853 | .init = &omap2_init_clksel_parent, |
| 854 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 855 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 856 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 857 | .recalc = &omap3_clkoutx2_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 858 | }; |
| 859 | |
| 860 | static struct clk emu_per_alwon_ck = { |
| 861 | .name = "emu_per_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 862 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 863 | .parent = &dpll4_m6x2_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 864 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 865 | .recalc = &followparent_recalc, |
| 866 | }; |
| 867 | |
| 868 | /* DPLL5 */ |
| 869 | /* Supplies 120MHz clock, USIM source clock */ |
| 870 | /* Type: DPLL */ |
| 871 | /* 3430ES2 only */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 872 | static struct dpll_data dpll5_dd = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 873 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
| 874 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, |
| 875 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 876 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 877 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
| 878 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 879 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 880 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
| 881 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 882 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 883 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
| 884 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, |
| 885 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 886 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 887 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 888 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 889 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 890 | }; |
| 891 | |
| 892 | static struct clk dpll5_ck = { |
| 893 | .name = "dpll5_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 894 | .ops = &clkops_noncore_dpll_ops, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 895 | .parent = &sys_ck, |
| 896 | .dpll_data = &dpll5_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 897 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 898 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 899 | .set_rate = &omap3_noncore_dpll_set_rate, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 900 | .recalc = &omap3_dpll_recalc, |
| 901 | }; |
| 902 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 903 | static const struct clksel div16_dpll5_clksel[] = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 904 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
| 905 | { .parent = NULL } |
| 906 | }; |
| 907 | |
| 908 | static struct clk dpll5_m2_ck = { |
| 909 | .name = "dpll5_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 910 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 911 | .parent = &dpll5_ck, |
| 912 | .init = &omap2_init_clksel_parent, |
| 913 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), |
| 914 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 915 | .clksel = div16_dpll5_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 916 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 917 | .recalc = &omap2_clksel_recalc, |
| 918 | }; |
| 919 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 920 | static const struct clksel omap_120m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 921 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 922 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, |
| 923 | { .parent = NULL } |
| 924 | }; |
| 925 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 926 | static struct clk omap_120m_fck = { |
| 927 | .name = "omap_120m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 928 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 929 | .parent = &dpll5_m2_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 930 | .init = &omap2_init_clksel_parent, |
| 931 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 932 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
| 933 | .clksel = omap_120m_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 934 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 935 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 936 | }; |
| 937 | |
| 938 | /* CM EXTERNAL CLOCK OUTPUTS */ |
| 939 | |
| 940 | static const struct clksel_rate clkout2_src_core_rates[] = { |
| 941 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 942 | { .div = 0 } |
| 943 | }; |
| 944 | |
| 945 | static const struct clksel_rate clkout2_src_sys_rates[] = { |
| 946 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 947 | { .div = 0 } |
| 948 | }; |
| 949 | |
| 950 | static const struct clksel_rate clkout2_src_96m_rates[] = { |
| 951 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 952 | { .div = 0 } |
| 953 | }; |
| 954 | |
| 955 | static const struct clksel_rate clkout2_src_54m_rates[] = { |
| 956 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 957 | { .div = 0 } |
| 958 | }; |
| 959 | |
| 960 | static const struct clksel clkout2_src_clksel[] = { |
| 961 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
| 962 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, |
| 963 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, |
| 964 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, |
| 965 | { .parent = NULL } |
| 966 | }; |
| 967 | |
| 968 | static struct clk clkout2_src_ck = { |
| 969 | .name = "clkout2_src_ck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 970 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 971 | .init = &omap2_init_clksel_parent, |
| 972 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 973 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, |
| 974 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 975 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, |
| 976 | .clksel = clkout2_src_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 977 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 978 | .recalc = &omap2_clksel_recalc, |
| 979 | }; |
| 980 | |
| 981 | static const struct clksel_rate sys_clkout2_rates[] = { |
| 982 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 983 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, |
| 984 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, |
| 985 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, |
| 986 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, |
| 987 | { .div = 0 }, |
| 988 | }; |
| 989 | |
| 990 | static const struct clksel sys_clkout2_clksel[] = { |
| 991 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, |
| 992 | { .parent = NULL }, |
| 993 | }; |
| 994 | |
| 995 | static struct clk sys_clkout2 = { |
| 996 | .name = "sys_clkout2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 997 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 998 | .init = &omap2_init_clksel_parent, |
| 999 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 1000 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, |
| 1001 | .clksel = sys_clkout2_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1002 | .recalc = &omap2_clksel_recalc, |
| 1003 | }; |
| 1004 | |
| 1005 | /* CM OUTPUT CLOCKS */ |
| 1006 | |
| 1007 | static struct clk corex2_fck = { |
| 1008 | .name = "corex2_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1009 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1010 | .parent = &dpll3_m2x2_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1011 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1012 | .recalc = &followparent_recalc, |
| 1013 | }; |
| 1014 | |
| 1015 | /* DPLL power domain clock controls */ |
| 1016 | |
| 1017 | static const struct clksel div2_core_clksel[] = { |
| 1018 | { .parent = &core_ck, .rates = div2_rates }, |
| 1019 | { .parent = NULL } |
| 1020 | }; |
| 1021 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1022 | /* |
| 1023 | * REVISIT: Are these in DPLL power domain or CM power domain? docs |
| 1024 | * may be inconsistent here? |
| 1025 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1026 | static struct clk dpll1_fck = { |
| 1027 | .name = "dpll1_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1028 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1029 | .parent = &core_ck, |
| 1030 | .init = &omap2_init_clksel_parent, |
| 1031 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1032 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, |
| 1033 | .clksel = div2_core_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1034 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1035 | .recalc = &omap2_clksel_recalc, |
| 1036 | }; |
| 1037 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1038 | /* |
| 1039 | * MPU clksel: |
| 1040 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck |
| 1041 | * derives from the high-frequency bypass clock originating from DPLL3, |
| 1042 | * called 'dpll1_fck' |
| 1043 | */ |
| 1044 | static const struct clksel mpu_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1045 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1046 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, |
| 1047 | { .parent = NULL } |
| 1048 | }; |
| 1049 | |
| 1050 | static struct clk mpu_ck = { |
| 1051 | .name = "mpu_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1052 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1053 | .parent = &dpll1_x2m2_ck, |
| 1054 | .init = &omap2_init_clksel_parent, |
| 1055 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1056 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1057 | .clksel = mpu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1058 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1059 | .clkdm_name = "mpu_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1060 | .recalc = &omap2_clksel_recalc, |
| 1061 | }; |
| 1062 | |
| 1063 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ |
| 1064 | static const struct clksel_rate arm_fck_rates[] = { |
| 1065 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1066 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, |
| 1067 | { .div = 0 }, |
| 1068 | }; |
| 1069 | |
| 1070 | static const struct clksel arm_fck_clksel[] = { |
| 1071 | { .parent = &mpu_ck, .rates = arm_fck_rates }, |
| 1072 | { .parent = NULL } |
| 1073 | }; |
| 1074 | |
| 1075 | static struct clk arm_fck = { |
| 1076 | .name = "arm_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1077 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1078 | .parent = &mpu_ck, |
| 1079 | .init = &omap2_init_clksel_parent, |
| 1080 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1081 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1082 | .clksel = arm_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1083 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1084 | .recalc = &omap2_clksel_recalc, |
| 1085 | }; |
| 1086 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1087 | /* XXX What about neon_clkdm ? */ |
| 1088 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1089 | /* |
| 1090 | * REVISIT: This clock is never specifically defined in the 3430 TRM, |
| 1091 | * although it is referenced - so this is a guess |
| 1092 | */ |
| 1093 | static struct clk emu_mpu_alwon_ck = { |
| 1094 | .name = "emu_mpu_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1095 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1096 | .parent = &mpu_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1097 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1098 | .recalc = &followparent_recalc, |
| 1099 | }; |
| 1100 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1101 | static struct clk dpll2_fck = { |
| 1102 | .name = "dpll2_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1103 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1104 | .parent = &core_ck, |
| 1105 | .init = &omap2_init_clksel_parent, |
| 1106 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1107 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, |
| 1108 | .clksel = div2_core_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1109 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1110 | .recalc = &omap2_clksel_recalc, |
| 1111 | }; |
| 1112 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1113 | /* |
| 1114 | * IVA2 clksel: |
| 1115 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck |
| 1116 | * derives from the high-frequency bypass clock originating from DPLL3, |
| 1117 | * called 'dpll2_fck' |
| 1118 | */ |
| 1119 | |
| 1120 | static const struct clksel iva2_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1121 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1122 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, |
| 1123 | { .parent = NULL } |
| 1124 | }; |
| 1125 | |
| 1126 | static struct clk iva2_ck = { |
| 1127 | .name = "iva2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1128 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1129 | .parent = &dpll2_m2_ck, |
| 1130 | .init = &omap2_init_clksel_parent, |
Hiroshi DOYU | 31c203d | 2008-04-01 10:11:22 +0300 | [diff] [blame] | 1131 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
| 1132 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1133 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 1134 | OMAP3430_CM_IDLEST_PLL), |
| 1135 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, |
| 1136 | .clksel = iva2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1137 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1138 | .clkdm_name = "iva2_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1139 | .recalc = &omap2_clksel_recalc, |
| 1140 | }; |
| 1141 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1142 | /* Common interface clocks */ |
| 1143 | |
| 1144 | static struct clk l3_ick = { |
| 1145 | .name = "l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1146 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1147 | .parent = &core_ck, |
| 1148 | .init = &omap2_init_clksel_parent, |
| 1149 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1150 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, |
| 1151 | .clksel = div2_core_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1152 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1153 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1154 | .recalc = &omap2_clksel_recalc, |
| 1155 | }; |
| 1156 | |
| 1157 | static const struct clksel div2_l3_clksel[] = { |
| 1158 | { .parent = &l3_ick, .rates = div2_rates }, |
| 1159 | { .parent = NULL } |
| 1160 | }; |
| 1161 | |
| 1162 | static struct clk l4_ick = { |
| 1163 | .name = "l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1164 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1165 | .parent = &l3_ick, |
| 1166 | .init = &omap2_init_clksel_parent, |
| 1167 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1168 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, |
| 1169 | .clksel = div2_l3_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1170 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1171 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1172 | .recalc = &omap2_clksel_recalc, |
| 1173 | |
| 1174 | }; |
| 1175 | |
| 1176 | static const struct clksel div2_l4_clksel[] = { |
| 1177 | { .parent = &l4_ick, .rates = div2_rates }, |
| 1178 | { .parent = NULL } |
| 1179 | }; |
| 1180 | |
| 1181 | static struct clk rm_ick = { |
| 1182 | .name = "rm_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1183 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1184 | .parent = &l4_ick, |
| 1185 | .init = &omap2_init_clksel_parent, |
| 1186 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 1187 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, |
| 1188 | .clksel = div2_l4_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1189 | .recalc = &omap2_clksel_recalc, |
| 1190 | }; |
| 1191 | |
| 1192 | /* GFX power domain */ |
| 1193 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1194 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1195 | |
| 1196 | static const struct clksel gfx_l3_clksel[] = { |
| 1197 | { .parent = &l3_ick, .rates = gfx_l3_rates }, |
| 1198 | { .parent = NULL } |
| 1199 | }; |
| 1200 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1201 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ |
| 1202 | static struct clk gfx_l3_ck = { |
| 1203 | .name = "gfx_l3_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1204 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1205 | .parent = &l3_ick, |
| 1206 | .init = &omap2_init_clksel_parent, |
| 1207 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1208 | .enable_bit = OMAP_EN_GFX_SHIFT, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1209 | .recalc = &followparent_recalc, |
| 1210 | }; |
| 1211 | |
| 1212 | static struct clk gfx_l3_fck = { |
| 1213 | .name = "gfx_l3_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1214 | .ops = &clkops_null, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1215 | .parent = &gfx_l3_ck, |
| 1216 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1217 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1218 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1219 | .clksel = gfx_l3_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1220 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1221 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1222 | .recalc = &omap2_clksel_recalc, |
| 1223 | }; |
| 1224 | |
| 1225 | static struct clk gfx_l3_ick = { |
| 1226 | .name = "gfx_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1227 | .ops = &clkops_null, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1228 | .parent = &gfx_l3_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1229 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1230 | .recalc = &followparent_recalc, |
| 1231 | }; |
| 1232 | |
| 1233 | static struct clk gfx_cg1_ck = { |
| 1234 | .name = "gfx_cg1_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1235 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1236 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1237 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1238 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1239 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1240 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1241 | .recalc = &followparent_recalc, |
| 1242 | }; |
| 1243 | |
| 1244 | static struct clk gfx_cg2_ck = { |
| 1245 | .name = "gfx_cg2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1246 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1247 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1248 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1249 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1250 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1251 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1252 | .recalc = &followparent_recalc, |
| 1253 | }; |
| 1254 | |
| 1255 | /* SGX power domain - 3430ES2 only */ |
| 1256 | |
| 1257 | static const struct clksel_rate sgx_core_rates[] = { |
| 1258 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1259 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, |
| 1260 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, |
| 1261 | { .div = 0 }, |
| 1262 | }; |
| 1263 | |
| 1264 | static const struct clksel_rate sgx_96m_rates[] = { |
| 1265 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1266 | { .div = 0 }, |
| 1267 | }; |
| 1268 | |
| 1269 | static const struct clksel sgx_clksel[] = { |
| 1270 | { .parent = &core_ck, .rates = sgx_core_rates }, |
| 1271 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
| 1272 | { .parent = NULL }, |
| 1273 | }; |
| 1274 | |
| 1275 | static struct clk sgx_fck = { |
| 1276 | .name = "sgx_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1277 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1278 | .init = &omap2_init_clksel_parent, |
| 1279 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), |
| 1280 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, |
| 1281 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
| 1282 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
| 1283 | .clksel = sgx_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1284 | .clkdm_name = "sgx_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1285 | .recalc = &omap2_clksel_recalc, |
| 1286 | }; |
| 1287 | |
| 1288 | static struct clk sgx_ick = { |
| 1289 | .name = "sgx_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1290 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1291 | .parent = &l3_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1292 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1293 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
| 1294 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1295 | .clkdm_name = "sgx_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1296 | .recalc = &followparent_recalc, |
| 1297 | }; |
| 1298 | |
| 1299 | /* CORE power domain */ |
| 1300 | |
| 1301 | static struct clk d2d_26m_fck = { |
| 1302 | .name = "d2d_26m_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1303 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1304 | .parent = &sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1305 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1306 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1307 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1308 | .clkdm_name = "d2d_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1309 | .recalc = &followparent_recalc, |
| 1310 | }; |
| 1311 | |
| 1312 | static const struct clksel omap343x_gpt_clksel[] = { |
| 1313 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, |
| 1314 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 1315 | { .parent = NULL} |
| 1316 | }; |
| 1317 | |
| 1318 | static struct clk gpt10_fck = { |
| 1319 | .name = "gpt10_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1320 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1321 | .parent = &sys_ck, |
| 1322 | .init = &omap2_init_clksel_parent, |
| 1323 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1324 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1325 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1326 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
| 1327 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1328 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1329 | .recalc = &omap2_clksel_recalc, |
| 1330 | }; |
| 1331 | |
| 1332 | static struct clk gpt11_fck = { |
| 1333 | .name = "gpt11_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1334 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1335 | .parent = &sys_ck, |
| 1336 | .init = &omap2_init_clksel_parent, |
| 1337 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1338 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1339 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1340 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
| 1341 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1342 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1343 | .recalc = &omap2_clksel_recalc, |
| 1344 | }; |
| 1345 | |
| 1346 | static struct clk cpefuse_fck = { |
| 1347 | .name = "cpefuse_fck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1348 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1349 | .parent = &sys_ck, |
| 1350 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1351 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1352 | .recalc = &followparent_recalc, |
| 1353 | }; |
| 1354 | |
| 1355 | static struct clk ts_fck = { |
| 1356 | .name = "ts_fck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1357 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1358 | .parent = &omap_32k_fck, |
| 1359 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1360 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1361 | .recalc = &followparent_recalc, |
| 1362 | }; |
| 1363 | |
| 1364 | static struct clk usbtll_fck = { |
| 1365 | .name = "usbtll_fck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1366 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1367 | .parent = &omap_120m_fck, |
| 1368 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1369 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1370 | .recalc = &followparent_recalc, |
| 1371 | }; |
| 1372 | |
| 1373 | /* CORE 96M FCLK-derived clocks */ |
| 1374 | |
| 1375 | static struct clk core_96m_fck = { |
| 1376 | .name = "core_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1377 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1378 | .parent = &omap_96m_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1379 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1380 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1381 | .recalc = &followparent_recalc, |
| 1382 | }; |
| 1383 | |
| 1384 | static struct clk mmchs3_fck = { |
| 1385 | .name = "mmchs_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1386 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1387 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1388 | .parent = &core_96m_fck, |
| 1389 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1390 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1391 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1392 | .recalc = &followparent_recalc, |
| 1393 | }; |
| 1394 | |
| 1395 | static struct clk mmchs2_fck = { |
| 1396 | .name = "mmchs_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1397 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1398 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1399 | .parent = &core_96m_fck, |
| 1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1401 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1402 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1403 | .recalc = &followparent_recalc, |
| 1404 | }; |
| 1405 | |
| 1406 | static struct clk mspro_fck = { |
| 1407 | .name = "mspro_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1408 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1409 | .parent = &core_96m_fck, |
| 1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1411 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1412 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1413 | .recalc = &followparent_recalc, |
| 1414 | }; |
| 1415 | |
| 1416 | static struct clk mmchs1_fck = { |
| 1417 | .name = "mmchs_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1418 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1419 | .parent = &core_96m_fck, |
| 1420 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1421 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1422 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1423 | .recalc = &followparent_recalc, |
| 1424 | }; |
| 1425 | |
| 1426 | static struct clk i2c3_fck = { |
| 1427 | .name = "i2c_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1428 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1429 | .id = 3, |
| 1430 | .parent = &core_96m_fck, |
| 1431 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1432 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1433 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1434 | .recalc = &followparent_recalc, |
| 1435 | }; |
| 1436 | |
| 1437 | static struct clk i2c2_fck = { |
| 1438 | .name = "i2c_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1439 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1440 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1441 | .parent = &core_96m_fck, |
| 1442 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1443 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1444 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1445 | .recalc = &followparent_recalc, |
| 1446 | }; |
| 1447 | |
| 1448 | static struct clk i2c1_fck = { |
| 1449 | .name = "i2c_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1450 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1451 | .id = 1, |
| 1452 | .parent = &core_96m_fck, |
| 1453 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1454 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1455 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1456 | .recalc = &followparent_recalc, |
| 1457 | }; |
| 1458 | |
| 1459 | /* |
| 1460 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; |
| 1461 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. |
| 1462 | */ |
| 1463 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
| 1464 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1465 | { .div = 0 } |
| 1466 | }; |
| 1467 | |
| 1468 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { |
| 1469 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1470 | { .div = 0 } |
| 1471 | }; |
| 1472 | |
| 1473 | static const struct clksel mcbsp_15_clksel[] = { |
| 1474 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 1475 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 1476 | { .parent = NULL } |
| 1477 | }; |
| 1478 | |
| 1479 | static struct clk mcbsp5_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1480 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1481 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1482 | .id = 5, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1483 | .init = &omap2_init_clksel_parent, |
| 1484 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1485 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1486 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 1487 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1488 | .clksel = mcbsp_15_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1489 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1490 | .recalc = &omap2_clksel_recalc, |
| 1491 | }; |
| 1492 | |
| 1493 | static struct clk mcbsp1_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1494 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1495 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1496 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1497 | .init = &omap2_init_clksel_parent, |
| 1498 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1499 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1500 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1501 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1502 | .clksel = mcbsp_15_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1503 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1504 | .recalc = &omap2_clksel_recalc, |
| 1505 | }; |
| 1506 | |
| 1507 | /* CORE_48M_FCK-derived clocks */ |
| 1508 | |
| 1509 | static struct clk core_48m_fck = { |
| 1510 | .name = "core_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1511 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1512 | .parent = &omap_48m_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1513 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1514 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1515 | .recalc = &followparent_recalc, |
| 1516 | }; |
| 1517 | |
| 1518 | static struct clk mcspi4_fck = { |
| 1519 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1520 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1521 | .id = 4, |
| 1522 | .parent = &core_48m_fck, |
| 1523 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1524 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1525 | .recalc = &followparent_recalc, |
| 1526 | }; |
| 1527 | |
| 1528 | static struct clk mcspi3_fck = { |
| 1529 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1530 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1531 | .id = 3, |
| 1532 | .parent = &core_48m_fck, |
| 1533 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1534 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1535 | .recalc = &followparent_recalc, |
| 1536 | }; |
| 1537 | |
| 1538 | static struct clk mcspi2_fck = { |
| 1539 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1540 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1541 | .id = 2, |
| 1542 | .parent = &core_48m_fck, |
| 1543 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1544 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1545 | .recalc = &followparent_recalc, |
| 1546 | }; |
| 1547 | |
| 1548 | static struct clk mcspi1_fck = { |
| 1549 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1550 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1551 | .id = 1, |
| 1552 | .parent = &core_48m_fck, |
| 1553 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1554 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1555 | .recalc = &followparent_recalc, |
| 1556 | }; |
| 1557 | |
| 1558 | static struct clk uart2_fck = { |
| 1559 | .name = "uart2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1560 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1561 | .parent = &core_48m_fck, |
| 1562 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1563 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1564 | .recalc = &followparent_recalc, |
| 1565 | }; |
| 1566 | |
| 1567 | static struct clk uart1_fck = { |
| 1568 | .name = "uart1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1569 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1570 | .parent = &core_48m_fck, |
| 1571 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1572 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1573 | .recalc = &followparent_recalc, |
| 1574 | }; |
| 1575 | |
| 1576 | static struct clk fshostusb_fck = { |
| 1577 | .name = "fshostusb_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1578 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1579 | .parent = &core_48m_fck, |
| 1580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1581 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1582 | .recalc = &followparent_recalc, |
| 1583 | }; |
| 1584 | |
| 1585 | /* CORE_12M_FCK based clocks */ |
| 1586 | |
| 1587 | static struct clk core_12m_fck = { |
| 1588 | .name = "core_12m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1589 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1590 | .parent = &omap_12m_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1591 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1592 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1593 | .recalc = &followparent_recalc, |
| 1594 | }; |
| 1595 | |
| 1596 | static struct clk hdq_fck = { |
| 1597 | .name = "hdq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1598 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1599 | .parent = &core_12m_fck, |
| 1600 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1601 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1602 | .recalc = &followparent_recalc, |
| 1603 | }; |
| 1604 | |
| 1605 | /* DPLL3-derived clock */ |
| 1606 | |
| 1607 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { |
| 1608 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1609 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 1610 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 1611 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 1612 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 1613 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 1614 | { .div = 0 } |
| 1615 | }; |
| 1616 | |
| 1617 | static const struct clksel ssi_ssr_clksel[] = { |
| 1618 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, |
| 1619 | { .parent = NULL } |
| 1620 | }; |
| 1621 | |
| 1622 | static struct clk ssi_ssr_fck = { |
| 1623 | .name = "ssi_ssr_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1624 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1625 | .init = &omap2_init_clksel_parent, |
| 1626 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1627 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1628 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1629 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1630 | .clksel = ssi_ssr_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1631 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1632 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1633 | .recalc = &omap2_clksel_recalc, |
| 1634 | }; |
| 1635 | |
| 1636 | static struct clk ssi_sst_fck = { |
| 1637 | .name = "ssi_sst_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1638 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1639 | .parent = &ssi_ssr_fck, |
| 1640 | .fixed_div = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1641 | .recalc = &omap2_fixed_divisor_recalc, |
| 1642 | }; |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | /* CORE_L3_ICK based clocks */ |
| 1647 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1648 | /* |
| 1649 | * XXX must add clk_enable/clk_disable for these if standard code won't |
| 1650 | * handle it |
| 1651 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1652 | static struct clk core_l3_ick = { |
| 1653 | .name = "core_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1654 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1655 | .parent = &l3_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1656 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1657 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1658 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1659 | .recalc = &followparent_recalc, |
| 1660 | }; |
| 1661 | |
| 1662 | static struct clk hsotgusb_ick = { |
| 1663 | .name = "hsotgusb_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1664 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1665 | .parent = &core_l3_ick, |
| 1666 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1667 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1668 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1669 | .recalc = &followparent_recalc, |
| 1670 | }; |
| 1671 | |
| 1672 | static struct clk sdrc_ick = { |
| 1673 | .name = "sdrc_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1674 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1675 | .parent = &core_l3_ick, |
| 1676 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1677 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1678 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1679 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1680 | .recalc = &followparent_recalc, |
| 1681 | }; |
| 1682 | |
| 1683 | static struct clk gpmc_fck = { |
| 1684 | .name = "gpmc_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1685 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1686 | .parent = &core_l3_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1687 | .flags = ENABLE_ON_INIT, /* huh? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1688 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1689 | .recalc = &followparent_recalc, |
| 1690 | }; |
| 1691 | |
| 1692 | /* SECURITY_L3_ICK based clocks */ |
| 1693 | |
| 1694 | static struct clk security_l3_ick = { |
| 1695 | .name = "security_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1696 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1697 | .parent = &l3_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1698 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1699 | .recalc = &followparent_recalc, |
| 1700 | }; |
| 1701 | |
| 1702 | static struct clk pka_ick = { |
| 1703 | .name = "pka_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1704 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1705 | .parent = &security_l3_ick, |
| 1706 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1707 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1708 | .recalc = &followparent_recalc, |
| 1709 | }; |
| 1710 | |
| 1711 | /* CORE_L4_ICK based clocks */ |
| 1712 | |
| 1713 | static struct clk core_l4_ick = { |
| 1714 | .name = "core_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1715 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1716 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1717 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1718 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1719 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1720 | .recalc = &followparent_recalc, |
| 1721 | }; |
| 1722 | |
| 1723 | static struct clk usbtll_ick = { |
| 1724 | .name = "usbtll_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1725 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1726 | .parent = &core_l4_ick, |
| 1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1728 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1729 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1730 | .recalc = &followparent_recalc, |
| 1731 | }; |
| 1732 | |
| 1733 | static struct clk mmchs3_ick = { |
| 1734 | .name = "mmchs_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1735 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1736 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1737 | .parent = &core_l4_ick, |
| 1738 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1739 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1740 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1741 | .recalc = &followparent_recalc, |
| 1742 | }; |
| 1743 | |
| 1744 | /* Intersystem Communication Registers - chassis mode only */ |
| 1745 | static struct clk icr_ick = { |
| 1746 | .name = "icr_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1747 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1748 | .parent = &core_l4_ick, |
| 1749 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1750 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1751 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1752 | .recalc = &followparent_recalc, |
| 1753 | }; |
| 1754 | |
| 1755 | static struct clk aes2_ick = { |
| 1756 | .name = "aes2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1757 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1758 | .parent = &core_l4_ick, |
| 1759 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1760 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1761 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1762 | .recalc = &followparent_recalc, |
| 1763 | }; |
| 1764 | |
| 1765 | static struct clk sha12_ick = { |
| 1766 | .name = "sha12_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1767 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1768 | .parent = &core_l4_ick, |
| 1769 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1770 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1771 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1772 | .recalc = &followparent_recalc, |
| 1773 | }; |
| 1774 | |
| 1775 | static struct clk des2_ick = { |
| 1776 | .name = "des2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1777 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1778 | .parent = &core_l4_ick, |
| 1779 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1780 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1781 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1782 | .recalc = &followparent_recalc, |
| 1783 | }; |
| 1784 | |
| 1785 | static struct clk mmchs2_ick = { |
| 1786 | .name = "mmchs_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1787 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1788 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1789 | .parent = &core_l4_ick, |
| 1790 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1791 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1792 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1793 | .recalc = &followparent_recalc, |
| 1794 | }; |
| 1795 | |
| 1796 | static struct clk mmchs1_ick = { |
| 1797 | .name = "mmchs_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1798 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1799 | .parent = &core_l4_ick, |
| 1800 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1801 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1802 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1803 | .recalc = &followparent_recalc, |
| 1804 | }; |
| 1805 | |
| 1806 | static struct clk mspro_ick = { |
| 1807 | .name = "mspro_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1808 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1809 | .parent = &core_l4_ick, |
| 1810 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1811 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1812 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1813 | .recalc = &followparent_recalc, |
| 1814 | }; |
| 1815 | |
| 1816 | static struct clk hdq_ick = { |
| 1817 | .name = "hdq_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1818 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1819 | .parent = &core_l4_ick, |
| 1820 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1821 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1822 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1823 | .recalc = &followparent_recalc, |
| 1824 | }; |
| 1825 | |
| 1826 | static struct clk mcspi4_ick = { |
| 1827 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1828 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1829 | .id = 4, |
| 1830 | .parent = &core_l4_ick, |
| 1831 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1832 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1833 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1834 | .recalc = &followparent_recalc, |
| 1835 | }; |
| 1836 | |
| 1837 | static struct clk mcspi3_ick = { |
| 1838 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1839 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1840 | .id = 3, |
| 1841 | .parent = &core_l4_ick, |
| 1842 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1843 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1844 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1845 | .recalc = &followparent_recalc, |
| 1846 | }; |
| 1847 | |
| 1848 | static struct clk mcspi2_ick = { |
| 1849 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1850 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1851 | .id = 2, |
| 1852 | .parent = &core_l4_ick, |
| 1853 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1854 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1855 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1856 | .recalc = &followparent_recalc, |
| 1857 | }; |
| 1858 | |
| 1859 | static struct clk mcspi1_ick = { |
| 1860 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1861 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1862 | .id = 1, |
| 1863 | .parent = &core_l4_ick, |
| 1864 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1865 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1866 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1867 | .recalc = &followparent_recalc, |
| 1868 | }; |
| 1869 | |
| 1870 | static struct clk i2c3_ick = { |
| 1871 | .name = "i2c_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1872 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1873 | .id = 3, |
| 1874 | .parent = &core_l4_ick, |
| 1875 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1876 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1877 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1878 | .recalc = &followparent_recalc, |
| 1879 | }; |
| 1880 | |
| 1881 | static struct clk i2c2_ick = { |
| 1882 | .name = "i2c_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1883 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1884 | .id = 2, |
| 1885 | .parent = &core_l4_ick, |
| 1886 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1887 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1888 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1889 | .recalc = &followparent_recalc, |
| 1890 | }; |
| 1891 | |
| 1892 | static struct clk i2c1_ick = { |
| 1893 | .name = "i2c_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1894 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1895 | .id = 1, |
| 1896 | .parent = &core_l4_ick, |
| 1897 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1898 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1899 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1900 | .recalc = &followparent_recalc, |
| 1901 | }; |
| 1902 | |
| 1903 | static struct clk uart2_ick = { |
| 1904 | .name = "uart2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1905 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1906 | .parent = &core_l4_ick, |
| 1907 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1908 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1909 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1910 | .recalc = &followparent_recalc, |
| 1911 | }; |
| 1912 | |
| 1913 | static struct clk uart1_ick = { |
| 1914 | .name = "uart1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1915 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1916 | .parent = &core_l4_ick, |
| 1917 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1918 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1919 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1920 | .recalc = &followparent_recalc, |
| 1921 | }; |
| 1922 | |
| 1923 | static struct clk gpt11_ick = { |
| 1924 | .name = "gpt11_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1925 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1926 | .parent = &core_l4_ick, |
| 1927 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1928 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1929 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1930 | .recalc = &followparent_recalc, |
| 1931 | }; |
| 1932 | |
| 1933 | static struct clk gpt10_ick = { |
| 1934 | .name = "gpt10_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1935 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1936 | .parent = &core_l4_ick, |
| 1937 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1938 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1939 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1940 | .recalc = &followparent_recalc, |
| 1941 | }; |
| 1942 | |
| 1943 | static struct clk mcbsp5_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1944 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1945 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1946 | .id = 5, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1947 | .parent = &core_l4_ick, |
| 1948 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1949 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1950 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1951 | .recalc = &followparent_recalc, |
| 1952 | }; |
| 1953 | |
| 1954 | static struct clk mcbsp1_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1955 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1956 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1957 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1958 | .parent = &core_l4_ick, |
| 1959 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1960 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1961 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1962 | .recalc = &followparent_recalc, |
| 1963 | }; |
| 1964 | |
| 1965 | static struct clk fac_ick = { |
| 1966 | .name = "fac_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1967 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1968 | .parent = &core_l4_ick, |
| 1969 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1970 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1971 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1972 | .recalc = &followparent_recalc, |
| 1973 | }; |
| 1974 | |
| 1975 | static struct clk mailboxes_ick = { |
| 1976 | .name = "mailboxes_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1977 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1978 | .parent = &core_l4_ick, |
| 1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1980 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1981 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1982 | .recalc = &followparent_recalc, |
| 1983 | }; |
| 1984 | |
| 1985 | static struct clk omapctrl_ick = { |
| 1986 | .name = "omapctrl_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1987 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1988 | .parent = &core_l4_ick, |
| 1989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1990 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1991 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1992 | .recalc = &followparent_recalc, |
| 1993 | }; |
| 1994 | |
| 1995 | /* SSI_L4_ICK based clocks */ |
| 1996 | |
| 1997 | static struct clk ssi_l4_ick = { |
| 1998 | .name = "ssi_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1999 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2000 | .parent = &l4_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2001 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2002 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2003 | .recalc = &followparent_recalc, |
| 2004 | }; |
| 2005 | |
| 2006 | static struct clk ssi_ick = { |
| 2007 | .name = "ssi_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2008 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2009 | .parent = &ssi_l4_ick, |
| 2010 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2011 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2012 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2013 | .recalc = &followparent_recalc, |
| 2014 | }; |
| 2015 | |
| 2016 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, |
| 2017 | * but l4_ick makes more sense to me */ |
| 2018 | |
| 2019 | static const struct clksel usb_l4_clksel[] = { |
| 2020 | { .parent = &l4_ick, .rates = div2_rates }, |
| 2021 | { .parent = NULL }, |
| 2022 | }; |
| 2023 | |
| 2024 | static struct clk usb_l4_ick = { |
| 2025 | .name = "usb_l4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2026 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2027 | .parent = &l4_ick, |
| 2028 | .init = &omap2_init_clksel_parent, |
| 2029 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2030 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 2031 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 2032 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
| 2033 | .clksel = usb_l4_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2034 | .recalc = &omap2_clksel_recalc, |
| 2035 | }; |
| 2036 | |
| 2037 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ |
| 2038 | |
| 2039 | /* SECURITY_L4_ICK2 based clocks */ |
| 2040 | |
| 2041 | static struct clk security_l4_ick2 = { |
| 2042 | .name = "security_l4_ick2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2043 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2044 | .parent = &l4_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2045 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2046 | .recalc = &followparent_recalc, |
| 2047 | }; |
| 2048 | |
| 2049 | static struct clk aes1_ick = { |
| 2050 | .name = "aes1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2051 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2052 | .parent = &security_l4_ick2, |
| 2053 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2054 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2055 | .recalc = &followparent_recalc, |
| 2056 | }; |
| 2057 | |
| 2058 | static struct clk rng_ick = { |
| 2059 | .name = "rng_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2060 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2061 | .parent = &security_l4_ick2, |
| 2062 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2063 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2064 | .recalc = &followparent_recalc, |
| 2065 | }; |
| 2066 | |
| 2067 | static struct clk sha11_ick = { |
| 2068 | .name = "sha11_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2069 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2070 | .parent = &security_l4_ick2, |
| 2071 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2072 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2073 | .recalc = &followparent_recalc, |
| 2074 | }; |
| 2075 | |
| 2076 | static struct clk des1_ick = { |
| 2077 | .name = "des1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2078 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2079 | .parent = &security_l4_ick2, |
| 2080 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2081 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2082 | .recalc = &followparent_recalc, |
| 2083 | }; |
| 2084 | |
| 2085 | /* DSS */ |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2086 | static const struct clksel dss1_alwon_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2087 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2088 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, |
| 2089 | { .parent = NULL } |
| 2090 | }; |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2091 | |
| 2092 | static struct clk dss1_alwon_fck = { |
| 2093 | .name = "dss1_alwon_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2094 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2095 | .parent = &dpll4_m4x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2096 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2097 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2098 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2099 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 2100 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2101 | .clksel = dss1_alwon_fck_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2102 | .clkdm_name = "dss_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2103 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2104 | }; |
| 2105 | |
| 2106 | static struct clk dss_tv_fck = { |
| 2107 | .name = "dss_tv_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2108 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2109 | .parent = &omap_54m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2110 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2111 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2112 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2113 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2114 | .recalc = &followparent_recalc, |
| 2115 | }; |
| 2116 | |
| 2117 | static struct clk dss_96m_fck = { |
| 2118 | .name = "dss_96m_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2119 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2120 | .parent = &omap_96m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2121 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2122 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2123 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2124 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2125 | .recalc = &followparent_recalc, |
| 2126 | }; |
| 2127 | |
| 2128 | static struct clk dss2_alwon_fck = { |
| 2129 | .name = "dss2_alwon_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2130 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2131 | .parent = &sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2132 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2133 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2134 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2135 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2136 | .recalc = &followparent_recalc, |
| 2137 | }; |
| 2138 | |
| 2139 | static struct clk dss_ick = { |
| 2140 | /* Handles both L3 and L4 clocks */ |
| 2141 | .name = "dss_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2142 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2143 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2144 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2145 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2146 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2147 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2148 | .recalc = &followparent_recalc, |
| 2149 | }; |
| 2150 | |
| 2151 | /* CAM */ |
| 2152 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2153 | static const struct clksel cam_mclk_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2154 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2155 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, |
| 2156 | { .parent = NULL } |
| 2157 | }; |
| 2158 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2159 | static struct clk cam_mclk = { |
| 2160 | .name = "cam_mclk", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2161 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2162 | .parent = &dpll4_m5x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2163 | .init = &omap2_init_clksel_parent, |
| 2164 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 2165 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2166 | .clksel = cam_mclk_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2167 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2168 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2169 | .clkdm_name = "cam_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2170 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2171 | }; |
| 2172 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2173 | static struct clk cam_ick = { |
| 2174 | /* Handles both L3 and L4 clocks */ |
| 2175 | .name = "cam_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2176 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2177 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2178 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2179 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
| 2180 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2181 | .clkdm_name = "cam_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2182 | .recalc = &followparent_recalc, |
| 2183 | }; |
| 2184 | |
| 2185 | /* USBHOST - 3430ES2 only */ |
| 2186 | |
| 2187 | static struct clk usbhost_120m_fck = { |
| 2188 | .name = "usbhost_120m_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2189 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2190 | .parent = &omap_120m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2191 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2192 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2193 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2194 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2195 | .recalc = &followparent_recalc, |
| 2196 | }; |
| 2197 | |
| 2198 | static struct clk usbhost_48m_fck = { |
| 2199 | .name = "usbhost_48m_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2200 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2201 | .parent = &omap_48m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2202 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2203 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2204 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2205 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2206 | .recalc = &followparent_recalc, |
| 2207 | }; |
| 2208 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2209 | static struct clk usbhost_ick = { |
| 2210 | /* Handles both L3 and L4 clocks */ |
| 2211 | .name = "usbhost_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2212 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2213 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2214 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2215 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
| 2216 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2217 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2218 | .recalc = &followparent_recalc, |
| 2219 | }; |
| 2220 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2221 | /* WKUP */ |
| 2222 | |
| 2223 | static const struct clksel_rate usim_96m_rates[] = { |
| 2224 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2225 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2226 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, |
| 2227 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, |
| 2228 | { .div = 0 }, |
| 2229 | }; |
| 2230 | |
| 2231 | static const struct clksel_rate usim_120m_rates[] = { |
| 2232 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2233 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 2234 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, |
| 2235 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, |
| 2236 | { .div = 0 }, |
| 2237 | }; |
| 2238 | |
| 2239 | static const struct clksel usim_clksel[] = { |
| 2240 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, |
| 2241 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, |
| 2242 | { .parent = &sys_ck, .rates = div2_rates }, |
| 2243 | { .parent = NULL }, |
| 2244 | }; |
| 2245 | |
| 2246 | /* 3430ES2 only */ |
| 2247 | static struct clk usim_fck = { |
| 2248 | .name = "usim_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2249 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2250 | .init = &omap2_init_clksel_parent, |
| 2251 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2252 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2253 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2254 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, |
| 2255 | .clksel = usim_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2256 | .recalc = &omap2_clksel_recalc, |
| 2257 | }; |
| 2258 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2259 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2260 | static struct clk gpt1_fck = { |
| 2261 | .name = "gpt1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2262 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2263 | .init = &omap2_init_clksel_parent, |
| 2264 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2265 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2266 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2267 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
| 2268 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2269 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2270 | .recalc = &omap2_clksel_recalc, |
| 2271 | }; |
| 2272 | |
| 2273 | static struct clk wkup_32k_fck = { |
| 2274 | .name = "wkup_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2275 | .ops = &clkops_null, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2276 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2277 | .parent = &omap_32k_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2278 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2279 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2280 | .recalc = &followparent_recalc, |
| 2281 | }; |
| 2282 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2283 | static struct clk gpio1_dbck = { |
| 2284 | .name = "gpio1_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2285 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2286 | .parent = &wkup_32k_fck, |
| 2287 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2288 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2289 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2290 | .recalc = &followparent_recalc, |
| 2291 | }; |
| 2292 | |
| 2293 | static struct clk wdt2_fck = { |
| 2294 | .name = "wdt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2295 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2296 | .parent = &wkup_32k_fck, |
| 2297 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2298 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2299 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2300 | .recalc = &followparent_recalc, |
| 2301 | }; |
| 2302 | |
| 2303 | static struct clk wkup_l4_ick = { |
| 2304 | .name = "wkup_l4_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2305 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2306 | .parent = &sys_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2307 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2308 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2309 | .recalc = &followparent_recalc, |
| 2310 | }; |
| 2311 | |
| 2312 | /* 3430ES2 only */ |
| 2313 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
| 2314 | static struct clk usim_ick = { |
| 2315 | .name = "usim_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2316 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2317 | .parent = &wkup_l4_ick, |
| 2318 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2319 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2320 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2321 | .recalc = &followparent_recalc, |
| 2322 | }; |
| 2323 | |
| 2324 | static struct clk wdt2_ick = { |
| 2325 | .name = "wdt2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2326 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2327 | .parent = &wkup_l4_ick, |
| 2328 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2329 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2330 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2331 | .recalc = &followparent_recalc, |
| 2332 | }; |
| 2333 | |
| 2334 | static struct clk wdt1_ick = { |
| 2335 | .name = "wdt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2336 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2337 | .parent = &wkup_l4_ick, |
| 2338 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2339 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2340 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2341 | .recalc = &followparent_recalc, |
| 2342 | }; |
| 2343 | |
| 2344 | static struct clk gpio1_ick = { |
| 2345 | .name = "gpio1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2346 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2347 | .parent = &wkup_l4_ick, |
| 2348 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2349 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2350 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2351 | .recalc = &followparent_recalc, |
| 2352 | }; |
| 2353 | |
| 2354 | static struct clk omap_32ksync_ick = { |
| 2355 | .name = "omap_32ksync_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2356 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2357 | .parent = &wkup_l4_ick, |
| 2358 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2359 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2360 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2361 | .recalc = &followparent_recalc, |
| 2362 | }; |
| 2363 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2364 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2365 | static struct clk gpt12_ick = { |
| 2366 | .name = "gpt12_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2367 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2368 | .parent = &wkup_l4_ick, |
| 2369 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2370 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2371 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2372 | .recalc = &followparent_recalc, |
| 2373 | }; |
| 2374 | |
| 2375 | static struct clk gpt1_ick = { |
| 2376 | .name = "gpt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2377 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2378 | .parent = &wkup_l4_ick, |
| 2379 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2380 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2381 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2382 | .recalc = &followparent_recalc, |
| 2383 | }; |
| 2384 | |
| 2385 | |
| 2386 | |
| 2387 | /* PER clock domain */ |
| 2388 | |
| 2389 | static struct clk per_96m_fck = { |
| 2390 | .name = "per_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2391 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2392 | .parent = &omap_96m_alwon_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2393 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2394 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2395 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2396 | .recalc = &followparent_recalc, |
| 2397 | }; |
| 2398 | |
| 2399 | static struct clk per_48m_fck = { |
| 2400 | .name = "per_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2401 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2402 | .parent = &omap_48m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2403 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2404 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2405 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2406 | .recalc = &followparent_recalc, |
| 2407 | }; |
| 2408 | |
| 2409 | static struct clk uart3_fck = { |
| 2410 | .name = "uart3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2411 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2412 | .parent = &per_48m_fck, |
| 2413 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2414 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2415 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2416 | .recalc = &followparent_recalc, |
| 2417 | }; |
| 2418 | |
| 2419 | static struct clk gpt2_fck = { |
| 2420 | .name = "gpt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2421 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2422 | .init = &omap2_init_clksel_parent, |
| 2423 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2424 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2425 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2426 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
| 2427 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2428 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2429 | .recalc = &omap2_clksel_recalc, |
| 2430 | }; |
| 2431 | |
| 2432 | static struct clk gpt3_fck = { |
| 2433 | .name = "gpt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2434 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2435 | .init = &omap2_init_clksel_parent, |
| 2436 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2437 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2438 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2439 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
| 2440 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2441 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2442 | .recalc = &omap2_clksel_recalc, |
| 2443 | }; |
| 2444 | |
| 2445 | static struct clk gpt4_fck = { |
| 2446 | .name = "gpt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2447 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2448 | .init = &omap2_init_clksel_parent, |
| 2449 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2450 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2451 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2452 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
| 2453 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2454 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2455 | .recalc = &omap2_clksel_recalc, |
| 2456 | }; |
| 2457 | |
| 2458 | static struct clk gpt5_fck = { |
| 2459 | .name = "gpt5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2460 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2461 | .init = &omap2_init_clksel_parent, |
| 2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2463 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2464 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2465 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
| 2466 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2467 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2468 | .recalc = &omap2_clksel_recalc, |
| 2469 | }; |
| 2470 | |
| 2471 | static struct clk gpt6_fck = { |
| 2472 | .name = "gpt6_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2473 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2474 | .init = &omap2_init_clksel_parent, |
| 2475 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2476 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2477 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2478 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
| 2479 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2480 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2481 | .recalc = &omap2_clksel_recalc, |
| 2482 | }; |
| 2483 | |
| 2484 | static struct clk gpt7_fck = { |
| 2485 | .name = "gpt7_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2486 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2487 | .init = &omap2_init_clksel_parent, |
| 2488 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2489 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2490 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2491 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
| 2492 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2493 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2494 | .recalc = &omap2_clksel_recalc, |
| 2495 | }; |
| 2496 | |
| 2497 | static struct clk gpt8_fck = { |
| 2498 | .name = "gpt8_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2499 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2500 | .init = &omap2_init_clksel_parent, |
| 2501 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2502 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2503 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2504 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
| 2505 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2506 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2507 | .recalc = &omap2_clksel_recalc, |
| 2508 | }; |
| 2509 | |
| 2510 | static struct clk gpt9_fck = { |
| 2511 | .name = "gpt9_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2512 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2513 | .init = &omap2_init_clksel_parent, |
| 2514 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2515 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2516 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2517 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
| 2518 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2519 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2520 | .recalc = &omap2_clksel_recalc, |
| 2521 | }; |
| 2522 | |
| 2523 | static struct clk per_32k_alwon_fck = { |
| 2524 | .name = "per_32k_alwon_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2525 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2526 | .parent = &omap_32k_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2527 | .clkdm_name = "per_clkdm", |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2528 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2529 | .recalc = &followparent_recalc, |
| 2530 | }; |
| 2531 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2532 | static struct clk gpio6_dbck = { |
| 2533 | .name = "gpio6_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2534 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2535 | .parent = &per_32k_alwon_fck, |
| 2536 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2537 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2538 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2539 | .recalc = &followparent_recalc, |
| 2540 | }; |
| 2541 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2542 | static struct clk gpio5_dbck = { |
| 2543 | .name = "gpio5_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2544 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2545 | .parent = &per_32k_alwon_fck, |
| 2546 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2547 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2548 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2549 | .recalc = &followparent_recalc, |
| 2550 | }; |
| 2551 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2552 | static struct clk gpio4_dbck = { |
| 2553 | .name = "gpio4_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2554 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2555 | .parent = &per_32k_alwon_fck, |
| 2556 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2557 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2558 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2559 | .recalc = &followparent_recalc, |
| 2560 | }; |
| 2561 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2562 | static struct clk gpio3_dbck = { |
| 2563 | .name = "gpio3_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2564 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2565 | .parent = &per_32k_alwon_fck, |
| 2566 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2567 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2568 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2569 | .recalc = &followparent_recalc, |
| 2570 | }; |
| 2571 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2572 | static struct clk gpio2_dbck = { |
| 2573 | .name = "gpio2_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2574 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2575 | .parent = &per_32k_alwon_fck, |
| 2576 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2577 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2578 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2579 | .recalc = &followparent_recalc, |
| 2580 | }; |
| 2581 | |
| 2582 | static struct clk wdt3_fck = { |
| 2583 | .name = "wdt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2584 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2585 | .parent = &per_32k_alwon_fck, |
| 2586 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2587 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2588 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2589 | .recalc = &followparent_recalc, |
| 2590 | }; |
| 2591 | |
| 2592 | static struct clk per_l4_ick = { |
| 2593 | .name = "per_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2594 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2595 | .parent = &l4_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2596 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2597 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2598 | .recalc = &followparent_recalc, |
| 2599 | }; |
| 2600 | |
| 2601 | static struct clk gpio6_ick = { |
| 2602 | .name = "gpio6_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2603 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2604 | .parent = &per_l4_ick, |
| 2605 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2606 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2607 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2608 | .recalc = &followparent_recalc, |
| 2609 | }; |
| 2610 | |
| 2611 | static struct clk gpio5_ick = { |
| 2612 | .name = "gpio5_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2613 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2614 | .parent = &per_l4_ick, |
| 2615 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2616 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2617 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2618 | .recalc = &followparent_recalc, |
| 2619 | }; |
| 2620 | |
| 2621 | static struct clk gpio4_ick = { |
| 2622 | .name = "gpio4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2623 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2624 | .parent = &per_l4_ick, |
| 2625 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2626 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2627 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2628 | .recalc = &followparent_recalc, |
| 2629 | }; |
| 2630 | |
| 2631 | static struct clk gpio3_ick = { |
| 2632 | .name = "gpio3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2633 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2634 | .parent = &per_l4_ick, |
| 2635 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2636 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2637 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2638 | .recalc = &followparent_recalc, |
| 2639 | }; |
| 2640 | |
| 2641 | static struct clk gpio2_ick = { |
| 2642 | .name = "gpio2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2643 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2644 | .parent = &per_l4_ick, |
| 2645 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2646 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2647 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2648 | .recalc = &followparent_recalc, |
| 2649 | }; |
| 2650 | |
| 2651 | static struct clk wdt3_ick = { |
| 2652 | .name = "wdt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2653 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2654 | .parent = &per_l4_ick, |
| 2655 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2656 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2657 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2658 | .recalc = &followparent_recalc, |
| 2659 | }; |
| 2660 | |
| 2661 | static struct clk uart3_ick = { |
| 2662 | .name = "uart3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2663 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2664 | .parent = &per_l4_ick, |
| 2665 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2666 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2667 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2668 | .recalc = &followparent_recalc, |
| 2669 | }; |
| 2670 | |
| 2671 | static struct clk gpt9_ick = { |
| 2672 | .name = "gpt9_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2673 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2674 | .parent = &per_l4_ick, |
| 2675 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2676 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2677 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2678 | .recalc = &followparent_recalc, |
| 2679 | }; |
| 2680 | |
| 2681 | static struct clk gpt8_ick = { |
| 2682 | .name = "gpt8_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2683 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2684 | .parent = &per_l4_ick, |
| 2685 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2686 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2687 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2688 | .recalc = &followparent_recalc, |
| 2689 | }; |
| 2690 | |
| 2691 | static struct clk gpt7_ick = { |
| 2692 | .name = "gpt7_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2693 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2694 | .parent = &per_l4_ick, |
| 2695 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2696 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2697 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2698 | .recalc = &followparent_recalc, |
| 2699 | }; |
| 2700 | |
| 2701 | static struct clk gpt6_ick = { |
| 2702 | .name = "gpt6_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2703 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2704 | .parent = &per_l4_ick, |
| 2705 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2706 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2707 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2708 | .recalc = &followparent_recalc, |
| 2709 | }; |
| 2710 | |
| 2711 | static struct clk gpt5_ick = { |
| 2712 | .name = "gpt5_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2713 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2714 | .parent = &per_l4_ick, |
| 2715 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2716 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2717 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2718 | .recalc = &followparent_recalc, |
| 2719 | }; |
| 2720 | |
| 2721 | static struct clk gpt4_ick = { |
| 2722 | .name = "gpt4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2723 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2724 | .parent = &per_l4_ick, |
| 2725 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2726 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2727 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2728 | .recalc = &followparent_recalc, |
| 2729 | }; |
| 2730 | |
| 2731 | static struct clk gpt3_ick = { |
| 2732 | .name = "gpt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2733 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2734 | .parent = &per_l4_ick, |
| 2735 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2736 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2737 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2738 | .recalc = &followparent_recalc, |
| 2739 | }; |
| 2740 | |
| 2741 | static struct clk gpt2_ick = { |
| 2742 | .name = "gpt2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2743 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2744 | .parent = &per_l4_ick, |
| 2745 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2746 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2747 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2748 | .recalc = &followparent_recalc, |
| 2749 | }; |
| 2750 | |
| 2751 | static struct clk mcbsp2_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2752 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2753 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2754 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2755 | .parent = &per_l4_ick, |
| 2756 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2757 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2758 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2759 | .recalc = &followparent_recalc, |
| 2760 | }; |
| 2761 | |
| 2762 | static struct clk mcbsp3_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2763 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2764 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2765 | .id = 3, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2766 | .parent = &per_l4_ick, |
| 2767 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2768 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2769 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2770 | .recalc = &followparent_recalc, |
| 2771 | }; |
| 2772 | |
| 2773 | static struct clk mcbsp4_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2774 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2775 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2776 | .id = 4, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2777 | .parent = &per_l4_ick, |
| 2778 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2779 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2780 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2781 | .recalc = &followparent_recalc, |
| 2782 | }; |
| 2783 | |
| 2784 | static const struct clksel mcbsp_234_clksel[] = { |
| 2785 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2786 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2787 | { .parent = NULL } |
| 2788 | }; |
| 2789 | |
| 2790 | static struct clk mcbsp2_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2791 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2792 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2793 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2794 | .init = &omap2_init_clksel_parent, |
| 2795 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2796 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2797 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 2798 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 2799 | .clksel = mcbsp_234_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2800 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2801 | .recalc = &omap2_clksel_recalc, |
| 2802 | }; |
| 2803 | |
| 2804 | static struct clk mcbsp3_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2805 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2806 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2807 | .id = 3, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2808 | .init = &omap2_init_clksel_parent, |
| 2809 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2810 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2811 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2812 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 2813 | .clksel = mcbsp_234_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2814 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2815 | .recalc = &omap2_clksel_recalc, |
| 2816 | }; |
| 2817 | |
| 2818 | static struct clk mcbsp4_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2819 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2820 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2821 | .id = 4, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2822 | .init = &omap2_init_clksel_parent, |
| 2823 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2824 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2825 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2826 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 2827 | .clksel = mcbsp_234_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2828 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2829 | .recalc = &omap2_clksel_recalc, |
| 2830 | }; |
| 2831 | |
| 2832 | /* EMU clocks */ |
| 2833 | |
| 2834 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ |
| 2835 | |
| 2836 | static const struct clksel_rate emu_src_sys_rates[] = { |
| 2837 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2838 | { .div = 0 }, |
| 2839 | }; |
| 2840 | |
| 2841 | static const struct clksel_rate emu_src_core_rates[] = { |
| 2842 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2843 | { .div = 0 }, |
| 2844 | }; |
| 2845 | |
| 2846 | static const struct clksel_rate emu_src_per_rates[] = { |
| 2847 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2848 | { .div = 0 }, |
| 2849 | }; |
| 2850 | |
| 2851 | static const struct clksel_rate emu_src_mpu_rates[] = { |
| 2852 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2853 | { .div = 0 }, |
| 2854 | }; |
| 2855 | |
| 2856 | static const struct clksel emu_src_clksel[] = { |
| 2857 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, |
| 2858 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, |
| 2859 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, |
| 2860 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, |
| 2861 | { .parent = NULL }, |
| 2862 | }; |
| 2863 | |
| 2864 | /* |
| 2865 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only |
| 2866 | * to switch the source of some of the EMU clocks. |
| 2867 | * XXX Are there CLKEN bits for these EMU clks? |
| 2868 | */ |
| 2869 | static struct clk emu_src_ck = { |
| 2870 | .name = "emu_src_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2871 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2872 | .init = &omap2_init_clksel_parent, |
| 2873 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2874 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
| 2875 | .clksel = emu_src_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2876 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2877 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2878 | .recalc = &omap2_clksel_recalc, |
| 2879 | }; |
| 2880 | |
| 2881 | static const struct clksel_rate pclk_emu_rates[] = { |
| 2882 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2883 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 2884 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2885 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 2886 | { .div = 0 }, |
| 2887 | }; |
| 2888 | |
| 2889 | static const struct clksel pclk_emu_clksel[] = { |
| 2890 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, |
| 2891 | { .parent = NULL }, |
| 2892 | }; |
| 2893 | |
| 2894 | static struct clk pclk_fck = { |
| 2895 | .name = "pclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2896 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2897 | .init = &omap2_init_clksel_parent, |
| 2898 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2899 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
| 2900 | .clksel = pclk_emu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2901 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2902 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2903 | .recalc = &omap2_clksel_recalc, |
| 2904 | }; |
| 2905 | |
| 2906 | static const struct clksel_rate pclkx2_emu_rates[] = { |
| 2907 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2908 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 2909 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 2910 | { .div = 0 }, |
| 2911 | }; |
| 2912 | |
| 2913 | static const struct clksel pclkx2_emu_clksel[] = { |
| 2914 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, |
| 2915 | { .parent = NULL }, |
| 2916 | }; |
| 2917 | |
| 2918 | static struct clk pclkx2_fck = { |
| 2919 | .name = "pclkx2_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2920 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2921 | .init = &omap2_init_clksel_parent, |
| 2922 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2923 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
| 2924 | .clksel = pclkx2_emu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2925 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2926 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2927 | .recalc = &omap2_clksel_recalc, |
| 2928 | }; |
| 2929 | |
| 2930 | static const struct clksel atclk_emu_clksel[] = { |
| 2931 | { .parent = &emu_src_ck, .rates = div2_rates }, |
| 2932 | { .parent = NULL }, |
| 2933 | }; |
| 2934 | |
| 2935 | static struct clk atclk_fck = { |
| 2936 | .name = "atclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2937 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2938 | .init = &omap2_init_clksel_parent, |
| 2939 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2940 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
| 2941 | .clksel = atclk_emu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2942 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2943 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2944 | .recalc = &omap2_clksel_recalc, |
| 2945 | }; |
| 2946 | |
| 2947 | static struct clk traceclk_src_fck = { |
| 2948 | .name = "traceclk_src_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2949 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2950 | .init = &omap2_init_clksel_parent, |
| 2951 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2952 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
| 2953 | .clksel = emu_src_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2954 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2955 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2956 | .recalc = &omap2_clksel_recalc, |
| 2957 | }; |
| 2958 | |
| 2959 | static const struct clksel_rate traceclk_rates[] = { |
| 2960 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2961 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 2962 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2963 | { .div = 0 }, |
| 2964 | }; |
| 2965 | |
| 2966 | static const struct clksel traceclk_clksel[] = { |
| 2967 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, |
| 2968 | { .parent = NULL }, |
| 2969 | }; |
| 2970 | |
| 2971 | static struct clk traceclk_fck = { |
| 2972 | .name = "traceclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2973 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2974 | .init = &omap2_init_clksel_parent, |
| 2975 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2976 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
| 2977 | .clksel = traceclk_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2978 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2979 | .recalc = &omap2_clksel_recalc, |
| 2980 | }; |
| 2981 | |
| 2982 | /* SR clocks */ |
| 2983 | |
| 2984 | /* SmartReflex fclk (VDD1) */ |
| 2985 | static struct clk sr1_fck = { |
| 2986 | .name = "sr1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2987 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2988 | .parent = &sys_ck, |
| 2989 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2990 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2991 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2992 | .recalc = &followparent_recalc, |
| 2993 | }; |
| 2994 | |
| 2995 | /* SmartReflex fclk (VDD2) */ |
| 2996 | static struct clk sr2_fck = { |
| 2997 | .name = "sr2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2998 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2999 | .parent = &sys_ck, |
| 3000 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3001 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 3002 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3003 | .recalc = &followparent_recalc, |
| 3004 | }; |
| 3005 | |
| 3006 | static struct clk sr_l4_ick = { |
| 3007 | .name = "sr_l4_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3008 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3009 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3010 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3011 | .recalc = &followparent_recalc, |
| 3012 | }; |
| 3013 | |
| 3014 | /* SECURE_32K_FCK clocks */ |
| 3015 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3016 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3017 | static struct clk gpt12_fck = { |
| 3018 | .name = "gpt12_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3019 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3020 | .parent = &secure_32k_fck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3021 | .recalc = &followparent_recalc, |
| 3022 | }; |
| 3023 | |
| 3024 | static struct clk wdt1_fck = { |
| 3025 | .name = "wdt1_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3026 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3027 | .parent = &secure_32k_fck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3028 | .recalc = &followparent_recalc, |
| 3029 | }; |
| 3030 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3031 | #endif |