blob: 6247d186177ed6c7ff4660c5644ae8d49a604ebd [file] [log] [blame]
Arthur Jones8f421c592008-07-25 01:49:04 -07001/*
2 * Intel 5100 Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * This module is based on the following document:
8 *
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
10 * http://download.intel.com/design/chipsets/datashts/318378.pdf
11 *
Nils Carlsonbbead212009-12-15 16:47:42 -080012 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
Lucas De Marchi25985ed2011-03-30 22:57:33 -030014 * rows for each respective channel are laid out one after another,
Nils Carlsonbbead212009-12-15 16:47:42 -080015 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -030017 *
18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
19 * several ranks. However, instead of showing memories as ranks, it outputs
20 * them as DIMM's. An internal table creates the association between ranks
21 * and DIMM's.
Arthur Jones8f421c592008-07-25 01:49:04 -070022 */
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/pci.h>
26#include <linux/pci_ids.h>
Arthur Jones8f421c592008-07-25 01:49:04 -070027#include <linux/edac.h>
28#include <linux/delay.h>
29#include <linux/mmzone.h>
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -030030#include <linux/debugfs.h>
Arthur Jones8f421c592008-07-25 01:49:04 -070031
32#include "edac_core.h"
33
Arthur Jonesb238e572008-07-25 01:49:08 -070034/* register addresses */
Arthur Jones8f421c592008-07-25 01:49:04 -070035
36/* device 16, func 1 */
Arthur Jones43920a52008-07-25 01:49:06 -070037#define I5100_MC 0x40 /* Memory Control Register */
Nils Carlson295439f2009-12-15 16:47:42 -080038#define I5100_MC_SCRBEN_MASK (1 << 7)
39#define I5100_MC_SCRBDONE_MASK (1 << 4)
Arthur Jones8f421c592008-07-25 01:49:04 -070040#define I5100_MS 0x44 /* Memory Status Register */
41#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
Arthur Jones8f421c592008-07-25 01:49:04 -070042#define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
Arthur Jones8f421c592008-07-25 01:49:04 -070043#define I5100_TOLM 0x6c /* Top of Low Memory */
Arthur Jones8f421c592008-07-25 01:49:04 -070044#define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
45#define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
46#define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
47#define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
Arthur Jones8f421c592008-07-25 01:49:04 -070048#define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
Arthur Jones8f421c592008-07-25 01:49:04 -070049#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
50#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
51#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
Arthur Jonesf7952ff2008-07-25 01:49:05 -070052#define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
53#define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
54#define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
55#define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
56#define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
57#define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
Niklas Söderlundb6378cb2012-02-17 07:36:54 -030058#define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
Arthur Jones8f421c592008-07-25 01:49:04 -070059#define I5100_FERR_NF_MEM_ANY_MASK \
60 (I5100_FERR_NF_MEM_M16ERR_MASK | \
61 I5100_FERR_NF_MEM_M15ERR_MASK | \
Arthur Jonesf7952ff2008-07-25 01:49:05 -070062 I5100_FERR_NF_MEM_M14ERR_MASK | \
63 I5100_FERR_NF_MEM_M12ERR_MASK | \
64 I5100_FERR_NF_MEM_M11ERR_MASK | \
65 I5100_FERR_NF_MEM_M10ERR_MASK | \
66 I5100_FERR_NF_MEM_M6ERR_MASK | \
67 I5100_FERR_NF_MEM_M5ERR_MASK | \
68 I5100_FERR_NF_MEM_M4ERR_MASK | \
69 I5100_FERR_NF_MEM_M1ERR_MASK)
Arthur Jones8f421c592008-07-25 01:49:04 -070070#define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
Arthur Jones178d5a72008-07-25 01:49:06 -070071#define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
Niklas Söderlund53ceafd2012-08-08 12:30:57 -030072#define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */
73#define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */
74#define I5100_MEMXEINJMSK0_EINJEN (1 << 27)
75#define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */
76#define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */
77
78/* Device 19, Function 0 */
79#define I5100_DINJ0 0x9a
Arthur Jones8f421c592008-07-25 01:49:04 -070080
81/* device 21 and 22, func 0 */
82#define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
83#define I5100_DMIR 0x15c /* DIMM Interleave Range */
Arthur Jones8f421c592008-07-25 01:49:04 -070084#define I5100_VALIDLOG 0x18c /* Valid Log Markers */
Arthur Jones8f421c592008-07-25 01:49:04 -070085#define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
Arthur Jones8f421c592008-07-25 01:49:04 -070086#define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
Arthur Jones8f421c592008-07-25 01:49:04 -070087#define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
Arthur Jones8f421c592008-07-25 01:49:04 -070088#define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
Arthur Jones8f421c592008-07-25 01:49:04 -070089#define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
Arthur Jones8f421c592008-07-25 01:49:04 -070090#define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
Arthur Jonesb238e572008-07-25 01:49:08 -070091#define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
92
93/* bit field accessors */
94
Nils Carlson295439f2009-12-15 16:47:42 -080095static inline u32 i5100_mc_scrben(u32 mc)
96{
97 return mc >> 7 & 1;
98}
99
Arthur Jonesb238e572008-07-25 01:49:08 -0700100static inline u32 i5100_mc_errdeten(u32 mc)
101{
102 return mc >> 5 & 1;
103}
104
Nils Carlson295439f2009-12-15 16:47:42 -0800105static inline u32 i5100_mc_scrbdone(u32 mc)
106{
107 return mc >> 4 & 1;
108}
109
Arthur Jonesb238e572008-07-25 01:49:08 -0700110static inline u16 i5100_spddata_rdo(u16 a)
111{
112 return a >> 15 & 1;
113}
114
115static inline u16 i5100_spddata_sbe(u16 a)
116{
117 return a >> 13 & 1;
118}
119
120static inline u16 i5100_spddata_busy(u16 a)
121{
122 return a >> 12 & 1;
123}
124
125static inline u16 i5100_spddata_data(u16 a)
126{
127 return a & ((1 << 8) - 1);
128}
129
130static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
131 u32 data, u32 cmd)
132{
133 return ((dti & ((1 << 4) - 1)) << 28) |
134 ((ckovrd & 1) << 27) |
135 ((sa & ((1 << 3) - 1)) << 24) |
136 ((ba & ((1 << 8) - 1)) << 16) |
137 ((data & ((1 << 8) - 1)) << 8) |
138 (cmd & 1);
139}
140
141static inline u16 i5100_tolm_tolm(u16 a)
142{
143 return a >> 12 & ((1 << 4) - 1);
144}
145
146static inline u16 i5100_mir_limit(u16 a)
147{
148 return a >> 4 & ((1 << 12) - 1);
149}
150
151static inline u16 i5100_mir_way1(u16 a)
152{
153 return a >> 1 & 1;
154}
155
156static inline u16 i5100_mir_way0(u16 a)
157{
158 return a & 1;
159}
160
161static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
162{
163 return a >> 28 & 1;
164}
165
166static inline u32 i5100_ferr_nf_mem_any(u32 a)
167{
168 return a & I5100_FERR_NF_MEM_ANY_MASK;
169}
170
171static inline u32 i5100_nerr_nf_mem_any(u32 a)
172{
173 return i5100_ferr_nf_mem_any(a);
174}
175
176static inline u32 i5100_dmir_limit(u32 a)
177{
178 return a >> 16 & ((1 << 11) - 1);
179}
180
181static inline u32 i5100_dmir_rank(u32 a, u32 i)
182{
183 return a >> (4 * i) & ((1 << 2) - 1);
184}
185
186static inline u16 i5100_mtr_present(u16 a)
187{
188 return a >> 10 & 1;
189}
190
191static inline u16 i5100_mtr_ethrottle(u16 a)
192{
193 return a >> 9 & 1;
194}
195
196static inline u16 i5100_mtr_width(u16 a)
197{
198 return a >> 8 & 1;
199}
200
201static inline u16 i5100_mtr_numbank(u16 a)
202{
203 return a >> 6 & 1;
204}
205
206static inline u16 i5100_mtr_numrow(u16 a)
207{
208 return a >> 2 & ((1 << 2) - 1);
209}
210
211static inline u16 i5100_mtr_numcol(u16 a)
212{
213 return a & ((1 << 2) - 1);
214}
215
216
217static inline u32 i5100_validlog_redmemvalid(u32 a)
218{
219 return a >> 2 & 1;
220}
221
222static inline u32 i5100_validlog_recmemvalid(u32 a)
223{
224 return a >> 1 & 1;
225}
226
227static inline u32 i5100_validlog_nrecmemvalid(u32 a)
228{
229 return a & 1;
230}
231
232static inline u32 i5100_nrecmema_merr(u32 a)
233{
234 return a >> 15 & ((1 << 5) - 1);
235}
236
237static inline u32 i5100_nrecmema_bank(u32 a)
238{
239 return a >> 12 & ((1 << 3) - 1);
240}
241
242static inline u32 i5100_nrecmema_rank(u32 a)
243{
244 return a >> 8 & ((1 << 3) - 1);
245}
246
247static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
248{
249 return a & ((1 << 8) - 1);
250}
251
252static inline u32 i5100_nrecmemb_cas(u32 a)
253{
254 return a >> 16 & ((1 << 13) - 1);
255}
256
257static inline u32 i5100_nrecmemb_ras(u32 a)
258{
259 return a & ((1 << 16) - 1);
260}
261
262static inline u32 i5100_redmemb_ecc_locator(u32 a)
263{
264 return a & ((1 << 18) - 1);
265}
266
267static inline u32 i5100_recmema_merr(u32 a)
268{
269 return i5100_nrecmema_merr(a);
270}
271
272static inline u32 i5100_recmema_bank(u32 a)
273{
274 return i5100_nrecmema_bank(a);
275}
276
277static inline u32 i5100_recmema_rank(u32 a)
278{
279 return i5100_nrecmema_rank(a);
280}
281
282static inline u32 i5100_recmema_dm_buf_id(u32 a)
283{
284 return i5100_nrecmema_dm_buf_id(a);
285}
286
287static inline u32 i5100_recmemb_cas(u32 a)
288{
289 return i5100_nrecmemb_cas(a);
290}
291
292static inline u32 i5100_recmemb_ras(u32 a)
293{
294 return i5100_nrecmemb_ras(a);
295}
Arthur Jones8f421c592008-07-25 01:49:04 -0700296
297/* some generic limits */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800298#define I5100_MAX_RANKS_PER_CHAN 6
299#define I5100_CHANNELS 2
Arthur Jones8f421c592008-07-25 01:49:04 -0700300#define I5100_MAX_RANKS_PER_DIMM 4
301#define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800302#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
Arthur Jones8f421c592008-07-25 01:49:04 -0700303#define I5100_MAX_RANK_INTERLEAVE 4
304#define I5100_MAX_DMIRS 5
Nils Carlson295439f2009-12-15 16:47:42 -0800305#define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
Arthur Jones8f421c592008-07-25 01:49:04 -0700306
307struct i5100_priv {
308 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800309 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
Arthur Jones8f421c592008-07-25 01:49:04 -0700310
311 /*
312 * mainboard chip select map -- maps i5100 chip selects to
313 * DIMM slot chip selects. In the case of only 4 ranks per
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800314 * channel, the mapping is fairly obvious but not unique.
315 * we map -1 -> NC and assume both channels use the same
Arthur Jones8f421c592008-07-25 01:49:04 -0700316 * map...
317 *
318 */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800319 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
Arthur Jones8f421c592008-07-25 01:49:04 -0700320
321 /* memory interleave range */
322 struct {
323 u64 limit;
324 unsigned way[2];
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800325 } mir[I5100_CHANNELS];
Arthur Jones8f421c592008-07-25 01:49:04 -0700326
327 /* adjusted memory interleave range register */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800328 unsigned amir[I5100_CHANNELS];
Arthur Jones8f421c592008-07-25 01:49:04 -0700329
330 /* dimm interleave range */
331 struct {
332 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
333 u64 limit;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800334 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
Arthur Jones8f421c592008-07-25 01:49:04 -0700335
336 /* memory technology registers... */
337 struct {
338 unsigned present; /* 0 or 1 */
339 unsigned ethrottle; /* 0 or 1 */
340 unsigned width; /* 4 or 8 bits */
341 unsigned numbank; /* 2 or 3 lines */
342 unsigned numrow; /* 13 .. 16 lines */
343 unsigned numcol; /* 11 .. 12 lines */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800344 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
Arthur Jones8f421c592008-07-25 01:49:04 -0700345
346 u64 tolm; /* top of low memory in bytes */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800347 unsigned ranksperchan; /* number of ranks per channel */
Arthur Jones8f421c592008-07-25 01:49:04 -0700348
349 struct pci_dev *mc; /* device 16 func 1 */
Niklas Söderlund52608ba2012-08-08 12:30:56 -0300350 struct pci_dev *einj; /* device 19 func 0 */
Arthur Jones8f421c592008-07-25 01:49:04 -0700351 struct pci_dev *ch0mm; /* device 21 func 0 */
352 struct pci_dev *ch1mm; /* device 22 func 0 */
Nils Carlson295439f2009-12-15 16:47:42 -0800353
354 struct delayed_work i5100_scrubbing;
355 int scrub_enable;
Niklas Söderlund53ceafd2012-08-08 12:30:57 -0300356
357 /* Error injection */
358 u8 inject_channel;
359 u8 inject_hlinesel;
360 u8 inject_deviceptr1;
361 u8 inject_deviceptr2;
362 u16 inject_eccmask1;
363 u16 inject_eccmask2;
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300364
365 struct dentry *debugfs;
Arthur Jones8f421c592008-07-25 01:49:04 -0700366};
367
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300368static struct dentry *i5100_debugfs;
369
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800370/* map a rank/chan to a slot number on the mainboard */
Arthur Jones8f421c592008-07-25 01:49:04 -0700371static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800372 int chan, int rank)
Arthur Jones8f421c592008-07-25 01:49:04 -0700373{
374 const struct i5100_priv *priv = mci->pvt_info;
375 int i;
376
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800377 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700378 int j;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800379 const int numrank = priv->dimm_numrank[chan][i];
Arthur Jones8f421c592008-07-25 01:49:04 -0700380
381 for (j = 0; j < numrank; j++)
382 if (priv->dimm_csmap[i][j] == rank)
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800383 return i * 2 + chan;
Arthur Jones8f421c592008-07-25 01:49:04 -0700384 }
385
386 return -1;
387}
388
Arthur Jones8f421c592008-07-25 01:49:04 -0700389static const char *i5100_err_msg(unsigned err)
390{
Arthur Jonesb238e572008-07-25 01:49:08 -0700391 static const char *merrs[] = {
Arthur Jones8f421c592008-07-25 01:49:04 -0700392 "unknown", /* 0 */
393 "uncorrectable data ECC on replay", /* 1 */
394 "unknown", /* 2 */
395 "unknown", /* 3 */
396 "aliased uncorrectable demand data ECC", /* 4 */
397 "aliased uncorrectable spare-copy data ECC", /* 5 */
398 "aliased uncorrectable patrol data ECC", /* 6 */
399 "unknown", /* 7 */
400 "unknown", /* 8 */
401 "unknown", /* 9 */
402 "non-aliased uncorrectable demand data ECC", /* 10 */
403 "non-aliased uncorrectable spare-copy data ECC", /* 11 */
404 "non-aliased uncorrectable patrol data ECC", /* 12 */
405 "unknown", /* 13 */
406 "correctable demand data ECC", /* 14 */
407 "correctable spare-copy data ECC", /* 15 */
408 "correctable patrol data ECC", /* 16 */
409 "unknown", /* 17 */
410 "SPD protocol error", /* 18 */
411 "unknown", /* 19 */
412 "spare copy initiated", /* 20 */
413 "spare copy completed", /* 21 */
414 };
415 unsigned i;
416
417 for (i = 0; i < ARRAY_SIZE(merrs); i++)
418 if (1 << i & err)
419 return merrs[i];
420
421 return "none";
422}
423
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800424/* convert csrow index into a rank (per channel -- 0..5) */
Arthur Jones8f421c592008-07-25 01:49:04 -0700425static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
426{
427 const struct i5100_priv *priv = mci->pvt_info;
428
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800429 return csrow % priv->ranksperchan;
Arthur Jones8f421c592008-07-25 01:49:04 -0700430}
431
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800432/* convert csrow index into a channel (0..1) */
433static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
Arthur Jones8f421c592008-07-25 01:49:04 -0700434{
435 const struct i5100_priv *priv = mci->pvt_info;
436
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800437 return csrow / priv->ranksperchan;
Arthur Jones8f421c592008-07-25 01:49:04 -0700438}
439
Arthur Jones8f421c592008-07-25 01:49:04 -0700440static void i5100_handle_ce(struct mem_ctl_info *mci,
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800441 int chan,
Arthur Jones8f421c592008-07-25 01:49:04 -0700442 unsigned bank,
443 unsigned rank,
444 unsigned long syndrome,
445 unsigned cas,
446 unsigned ras,
447 const char *msg)
448{
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300449 char detail[80];
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300450
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300451 /* Form out message */
452 snprintf(detail, sizeof(detail),
453 "bank %u, cas %u, ras %u\n",
454 bank, cas, ras);
Arthur Jones8f421c592008-07-25 01:49:04 -0700455
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300456 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300457 0, 0, syndrome,
458 chan, rank, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300459 msg, detail);
Arthur Jones8f421c592008-07-25 01:49:04 -0700460}
461
462static void i5100_handle_ue(struct mem_ctl_info *mci,
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800463 int chan,
Arthur Jones8f421c592008-07-25 01:49:04 -0700464 unsigned bank,
465 unsigned rank,
466 unsigned long syndrome,
467 unsigned cas,
468 unsigned ras,
469 const char *msg)
470{
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300471 char detail[80];
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300472
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300473 /* Form out message */
474 snprintf(detail, sizeof(detail),
475 "bank %u, cas %u, ras %u\n",
476 bank, cas, ras);
Arthur Jones8f421c592008-07-25 01:49:04 -0700477
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300478 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300479 0, 0, syndrome,
480 chan, rank, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300481 msg, detail);
Arthur Jones8f421c592008-07-25 01:49:04 -0700482}
483
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800484static void i5100_read_log(struct mem_ctl_info *mci, int chan,
Arthur Jones8f421c592008-07-25 01:49:04 -0700485 u32 ferr, u32 nerr)
486{
487 struct i5100_priv *priv = mci->pvt_info;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800488 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
Arthur Jones8f421c592008-07-25 01:49:04 -0700489 u32 dw;
490 u32 dw2;
491 unsigned syndrome = 0;
492 unsigned ecc_loc = 0;
493 unsigned merr;
494 unsigned bank;
495 unsigned rank;
496 unsigned cas;
497 unsigned ras;
498
499 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
500
Arthur Jonesb238e572008-07-25 01:49:08 -0700501 if (i5100_validlog_redmemvalid(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700502 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700503 syndrome = dw2;
Arthur Jones8f421c592008-07-25 01:49:04 -0700504 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700505 ecc_loc = i5100_redmemb_ecc_locator(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700506 }
507
Arthur Jonesb238e572008-07-25 01:49:08 -0700508 if (i5100_validlog_recmemvalid(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700509 const char *msg;
510
511 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700512 merr = i5100_recmema_merr(dw2);
513 bank = i5100_recmema_bank(dw2);
514 rank = i5100_recmema_rank(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700515
516 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700517 cas = i5100_recmemb_cas(dw2);
518 ras = i5100_recmemb_ras(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700519
520 /* FIXME: not really sure if this is what merr is...
521 */
522 if (!merr)
523 msg = i5100_err_msg(ferr);
524 else
525 msg = i5100_err_msg(nerr);
526
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800527 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
Arthur Jones8f421c592008-07-25 01:49:04 -0700528 }
529
Arthur Jonesb238e572008-07-25 01:49:08 -0700530 if (i5100_validlog_nrecmemvalid(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700531 const char *msg;
532
533 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700534 merr = i5100_nrecmema_merr(dw2);
535 bank = i5100_nrecmema_bank(dw2);
536 rank = i5100_nrecmema_rank(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700537
538 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700539 cas = i5100_nrecmemb_cas(dw2);
540 ras = i5100_nrecmemb_ras(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700541
542 /* FIXME: not really sure if this is what merr is...
543 */
544 if (!merr)
545 msg = i5100_err_msg(ferr);
546 else
547 msg = i5100_err_msg(nerr);
548
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800549 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
Arthur Jones8f421c592008-07-25 01:49:04 -0700550 }
551
552 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
553}
554
555static void i5100_check_error(struct mem_ctl_info *mci)
556{
557 struct i5100_priv *priv = mci->pvt_info;
Niklas Söderlunddf95e422011-12-09 13:12:15 -0300558 u32 dw, dw2;
Arthur Jones8f421c592008-07-25 01:49:04 -0700559
560 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
Arthur Jonesb238e572008-07-25 01:49:08 -0700561 if (i5100_ferr_nf_mem_any(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700562
563 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700564
Arthur Jonesb238e572008-07-25 01:49:08 -0700565 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
566 i5100_ferr_nf_mem_any(dw),
567 i5100_nerr_nf_mem_any(dw2));
Niklas Söderlunddf95e422011-12-09 13:12:15 -0300568
569 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700570 }
Niklas Söderlunddf95e422011-12-09 13:12:15 -0300571 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
Arthur Jones8f421c592008-07-25 01:49:04 -0700572}
573
Nils Carlson295439f2009-12-15 16:47:42 -0800574/* The i5100 chipset will scrub the entire memory once, then
575 * set a done bit. Continuous scrubbing is achieved by enqueing
576 * delayed work to a workqueue, checking every few minutes if
577 * the scrubbing has completed and if so reinitiating it.
578 */
579
580static void i5100_refresh_scrubbing(struct work_struct *work)
581{
582 struct delayed_work *i5100_scrubbing = container_of(work,
583 struct delayed_work,
584 work);
585 struct i5100_priv *priv = container_of(i5100_scrubbing,
586 struct i5100_priv,
587 i5100_scrubbing);
588 u32 dw;
589
590 pci_read_config_dword(priv->mc, I5100_MC, &dw);
591
592 if (priv->scrub_enable) {
593
594 pci_read_config_dword(priv->mc, I5100_MC, &dw);
595
596 if (i5100_mc_scrbdone(dw)) {
597 dw |= I5100_MC_SCRBEN_MASK;
598 pci_write_config_dword(priv->mc, I5100_MC, dw);
599 pci_read_config_dword(priv->mc, I5100_MC, &dw);
600 }
601
602 schedule_delayed_work(&(priv->i5100_scrubbing),
603 I5100_SCRUB_REFRESH_RATE);
604 }
605}
606/*
607 * The bandwidth is based on experimentation, feel free to refine it.
608 */
Borislav Petkoveba042a2010-05-25 18:21:07 +0200609static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
Nils Carlson295439f2009-12-15 16:47:42 -0800610{
611 struct i5100_priv *priv = mci->pvt_info;
612 u32 dw;
613
614 pci_read_config_dword(priv->mc, I5100_MC, &dw);
Borislav Petkoveba042a2010-05-25 18:21:07 +0200615 if (bandwidth) {
Nils Carlson295439f2009-12-15 16:47:42 -0800616 priv->scrub_enable = 1;
617 dw |= I5100_MC_SCRBEN_MASK;
618 schedule_delayed_work(&(priv->i5100_scrubbing),
619 I5100_SCRUB_REFRESH_RATE);
620 } else {
621 priv->scrub_enable = 0;
622 dw &= ~I5100_MC_SCRBEN_MASK;
623 cancel_delayed_work(&(priv->i5100_scrubbing));
624 }
625 pci_write_config_dword(priv->mc, I5100_MC, dw);
626
627 pci_read_config_dword(priv->mc, I5100_MC, &dw);
628
Borislav Petkoveba042a2010-05-25 18:21:07 +0200629 bandwidth = 5900000 * i5100_mc_scrben(dw);
Nils Carlson295439f2009-12-15 16:47:42 -0800630
Borislav Petkov39094442010-11-24 19:52:09 +0100631 return bandwidth;
Nils Carlson295439f2009-12-15 16:47:42 -0800632}
633
Borislav Petkov39094442010-11-24 19:52:09 +0100634static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
Nils Carlson295439f2009-12-15 16:47:42 -0800635{
636 struct i5100_priv *priv = mci->pvt_info;
637 u32 dw;
638
639 pci_read_config_dword(priv->mc, I5100_MC, &dw);
640
Borislav Petkov39094442010-11-24 19:52:09 +0100641 return 5900000 * i5100_mc_scrben(dw);
Nils Carlson295439f2009-12-15 16:47:42 -0800642}
643
Arthur Jones8f421c592008-07-25 01:49:04 -0700644static struct pci_dev *pci_get_device_func(unsigned vendor,
645 unsigned device,
646 unsigned func)
647{
648 struct pci_dev *ret = NULL;
649
650 while (1) {
651 ret = pci_get_device(vendor, device, ret);
652
653 if (!ret)
654 break;
655
656 if (PCI_FUNC(ret->devfn) == func)
657 break;
658 }
659
660 return ret;
661}
662
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800663static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)
Arthur Jones8f421c592008-07-25 01:49:04 -0700664{
665 struct i5100_priv *priv = mci->pvt_info;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800666 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
667 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
Arthur Jones8f421c592008-07-25 01:49:04 -0700668 unsigned addr_lines;
669
670 /* dimm present? */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800671 if (!priv->mtr[chan][chan_rank].present)
Arthur Jones8f421c592008-07-25 01:49:04 -0700672 return 0ULL;
673
674 addr_lines =
675 I5100_DIMM_ADDR_LINES +
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800676 priv->mtr[chan][chan_rank].numcol +
677 priv->mtr[chan][chan_rank].numrow +
678 priv->mtr[chan][chan_rank].numbank;
Arthur Jones8f421c592008-07-25 01:49:04 -0700679
680 return (unsigned long)
681 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
682}
683
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800684static void i5100_init_mtr(struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700685{
686 struct i5100_priv *priv = mci->pvt_info;
687 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
688 int i;
689
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800690 for (i = 0; i < I5100_CHANNELS; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700691 int j;
692 struct pci_dev *pdev = mms[i];
693
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800694 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700695 const unsigned addr =
696 (j < 4) ? I5100_MTR_0 + j * 2 :
697 I5100_MTR_4 + (j - 4) * 2;
698 u16 w;
699
700 pci_read_config_word(pdev, addr, &w);
701
Arthur Jonesb238e572008-07-25 01:49:08 -0700702 priv->mtr[i][j].present = i5100_mtr_present(w);
703 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
704 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
705 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
706 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
707 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700708 }
709 }
710}
711
712/*
713 * FIXME: make this into a real i2c adapter (so that dimm-decode
714 * will work)?
715 */
716static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
717 u8 ch, u8 slot, u8 addr, u8 *byte)
718{
719 struct i5100_priv *priv = mci->pvt_info;
720 u16 w;
Arthur Jones8f421c592008-07-25 01:49:04 -0700721 unsigned long et;
722
723 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700724 if (i5100_spddata_busy(w))
Arthur Jones8f421c592008-07-25 01:49:04 -0700725 return -1;
726
Arthur Jonesb238e572008-07-25 01:49:08 -0700727 pci_write_config_dword(priv->mc, I5100_SPDCMD,
728 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
729 0, 0));
Arthur Jones8f421c592008-07-25 01:49:04 -0700730
731 /* wait up to 100ms */
732 et = jiffies + HZ / 10;
733 udelay(100);
734 while (1) {
735 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700736 if (!i5100_spddata_busy(w))
Arthur Jones8f421c592008-07-25 01:49:04 -0700737 break;
738 udelay(100);
739 }
740
Arthur Jonesb238e572008-07-25 01:49:08 -0700741 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
Arthur Jones8f421c592008-07-25 01:49:04 -0700742 return -1;
743
Arthur Jonesb238e572008-07-25 01:49:08 -0700744 *byte = i5100_spddata_data(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700745
746 return 0;
747}
748
749/*
750 * fill dimm chip select map
751 *
752 * FIXME:
Arthur Jones8f421c592008-07-25 01:49:04 -0700753 * o not the only way to may chip selects to dimm slots
754 * o investigate if there is some way to obtain this map from the bios
755 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800756static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700757{
758 struct i5100_priv *priv = mci->pvt_info;
759 int i;
760
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800761 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700762 int j;
763
764 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
765 priv->dimm_csmap[i][j] = -1; /* default NC */
766 }
767
768 /* only 2 chip selects per slot... */
Nils Carlsonbbead212009-12-15 16:47:42 -0800769 if (priv->ranksperchan == 4) {
770 priv->dimm_csmap[0][0] = 0;
771 priv->dimm_csmap[0][1] = 3;
772 priv->dimm_csmap[1][0] = 1;
773 priv->dimm_csmap[1][1] = 2;
774 priv->dimm_csmap[2][0] = 2;
775 priv->dimm_csmap[3][0] = 3;
776 } else {
777 priv->dimm_csmap[0][0] = 0;
778 priv->dimm_csmap[0][1] = 1;
779 priv->dimm_csmap[1][0] = 2;
780 priv->dimm_csmap[1][1] = 3;
781 priv->dimm_csmap[2][0] = 4;
782 priv->dimm_csmap[2][1] = 5;
783 }
Arthur Jones8f421c592008-07-25 01:49:04 -0700784}
785
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800786static void i5100_init_dimm_layout(struct pci_dev *pdev,
787 struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700788{
789 struct i5100_priv *priv = mci->pvt_info;
790 int i;
791
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800792 for (i = 0; i < I5100_CHANNELS; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700793 int j;
794
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800795 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700796 u8 rank;
797
798 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
799 priv->dimm_numrank[i][j] = 0;
800 else
801 priv->dimm_numrank[i][j] = (rank & 3) + 1;
802 }
803 }
804
805 i5100_init_dimm_csmap(mci);
806}
807
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800808static void i5100_init_interleaving(struct pci_dev *pdev,
809 struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700810{
811 u16 w;
812 u32 dw;
813 struct i5100_priv *priv = mci->pvt_info;
814 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
815 int i;
816
817 pci_read_config_word(pdev, I5100_TOLM, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700818 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
Arthur Jones8f421c592008-07-25 01:49:04 -0700819
820 pci_read_config_word(pdev, I5100_MIR0, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700821 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
822 priv->mir[0].way[1] = i5100_mir_way1(w);
823 priv->mir[0].way[0] = i5100_mir_way0(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700824
825 pci_read_config_word(pdev, I5100_MIR1, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700826 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
827 priv->mir[1].way[1] = i5100_mir_way1(w);
828 priv->mir[1].way[0] = i5100_mir_way0(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700829
830 pci_read_config_word(pdev, I5100_AMIR_0, &w);
831 priv->amir[0] = w;
832 pci_read_config_word(pdev, I5100_AMIR_1, &w);
833 priv->amir[1] = w;
834
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800835 for (i = 0; i < I5100_CHANNELS; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700836 int j;
837
838 for (j = 0; j < 5; j++) {
839 int k;
840
841 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
842
843 priv->dmir[i][j].limit =
Arthur Jonesb238e572008-07-25 01:49:08 -0700844 (u64) i5100_dmir_limit(dw) << 28;
Arthur Jones8f421c592008-07-25 01:49:04 -0700845 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
846 priv->dmir[i][j].rank[k] =
Arthur Jonesb238e572008-07-25 01:49:08 -0700847 i5100_dmir_rank(dw, k);
Arthur Jones8f421c592008-07-25 01:49:04 -0700848 }
849 }
850
851 i5100_init_mtr(mci);
852}
853
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800854static void i5100_init_csrows(struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700855{
856 int i;
Arthur Jones8f421c592008-07-25 01:49:04 -0700857 struct i5100_priv *priv = mci->pvt_info;
858
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300859 for (i = 0; i < mci->tot_dimms; i++) {
860 struct dimm_info *dimm;
Arthur Jones8f421c592008-07-25 01:49:04 -0700861 const unsigned long npages = i5100_npages(mci, i);
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800862 const unsigned chan = i5100_csrow_to_chan(mci, i);
Arthur Jones8f421c592008-07-25 01:49:04 -0700863 const unsigned rank = i5100_csrow_to_rank(mci, i);
864
865 if (!npages)
866 continue;
867
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300868 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
869 chan, rank, 0);
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300870
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300871 dimm->nr_pages = npages;
Dan Carpenter9d6c7cb2014-02-13 14:17:38 +0300872 dimm->grain = 32;
873 dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
874 DEV_X4 : DEV_X8;
875 dimm->mtype = MEM_RDDR2;
876 dimm->edac_mode = EDAC_SECDED;
877 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u",
878 i5100_rank_to_slot(mci, chan, rank));
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300879
Joe Perches956b9ba2012-04-29 17:08:39 -0300880 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
881 chan, rank, (long)PAGES_TO_MiB(npages));
Arthur Jones8f421c592008-07-25 01:49:04 -0700882 }
883}
884
Niklas Söderlund53ceafd2012-08-08 12:30:57 -0300885/****************************************************************************
886 * Error injection routines
887 ****************************************************************************/
888
889static void i5100_do_inject(struct mem_ctl_info *mci)
890{
891 struct i5100_priv *priv = mci->pvt_info;
892 u32 mask0;
893 u16 mask1;
894
895 /* MEM[1:0]EINJMSK0
896 * 31 - ADDRMATCHEN
897 * 29:28 - HLINESEL
898 * 00 Reserved
899 * 01 Lower half of cache line
900 * 10 Upper half of cache line
901 * 11 Both upper and lower parts of cache line
902 * 27 - EINJEN
903 * 25:19 - XORMASK1 for deviceptr1
904 * 9:5 - SEC2RAM for deviceptr2
905 * 4:0 - FIR2RAM for deviceptr1
906 */
907 mask0 = ((priv->inject_hlinesel & 0x3) << 28) |
908 I5100_MEMXEINJMSK0_EINJEN |
909 ((priv->inject_eccmask1 & 0xffff) << 10) |
910 ((priv->inject_deviceptr2 & 0x1f) << 5) |
911 (priv->inject_deviceptr1 & 0x1f);
912
913 /* MEM[1:0]EINJMSK1
914 * 15:0 - XORMASK2 for deviceptr2
915 */
916 mask1 = priv->inject_eccmask2;
917
918 if (priv->inject_channel == 0) {
919 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);
920 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);
921 } else {
922 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);
923 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);
924 }
925
926 /* Error Injection Response Function
927 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet
928 * hints about this register but carry no data about them. All
929 * data regarding device 19 is based on experimentation and the
930 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet
931 * which appears to be accurate for the i5100 in this area.
932 *
933 * The injection code don't work without setting this register.
934 * The register needs to be flipped off then on else the hardware
935 * will only preform the first injection.
936 *
937 * Stop condition bits 7:4
938 * 1010 - Stop after one injection
939 * 1011 - Never stop injecting faults
940 *
941 * Start condition bits 3:0
942 * 1010 - Never start
943 * 1011 - Start immediately
944 */
945 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);
946 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);
947}
948
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300949#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
950static ssize_t inject_enable_write(struct file *file, const char __user *data,
951 size_t count, loff_t *ppos)
952{
953 struct device *dev = file->private_data;
954 struct mem_ctl_info *mci = to_mci(dev);
955
956 i5100_do_inject(mci);
957
958 return count;
959}
960
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300961static const struct file_operations i5100_inject_enable_fops = {
Wei Yongjunb0769892013-02-26 17:18:34 +0800962 .open = simple_open,
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300963 .write = inject_enable_write,
964 .llseek = generic_file_llseek,
965};
966
967static int i5100_setup_debugfs(struct mem_ctl_info *mci)
968{
969 struct i5100_priv *priv = mci->pvt_info;
970
971 if (!i5100_debugfs)
972 return -ENODEV;
973
Borislav Petkov88d84ac2013-07-19 12:28:25 +0200974 priv->debugfs = debugfs_create_dir(mci->bus->name, i5100_debugfs);
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300975
976 if (!priv->debugfs)
977 return -ENOMEM;
978
979 debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,
980 &priv->inject_channel);
981 debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,
982 &priv->inject_hlinesel);
983 debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,
984 &priv->inject_deviceptr1);
985 debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,
986 &priv->inject_deviceptr2);
987 debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,
988 &priv->inject_eccmask1);
989 debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,
990 &priv->inject_eccmask2);
991 debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,
992 &mci->dev, &i5100_inject_enable_fops);
993
994 return 0;
995
996}
997
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800998static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
Arthur Jones8f421c592008-07-25 01:49:04 -0700999{
1000 int rc;
1001 struct mem_ctl_info *mci;
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -03001002 struct edac_mc_layer layers[2];
Arthur Jones8f421c592008-07-25 01:49:04 -07001003 struct i5100_priv *priv;
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001004 struct pci_dev *ch0mm, *ch1mm, *einj;
Arthur Jones8f421c592008-07-25 01:49:04 -07001005 int ret = 0;
1006 u32 dw;
1007 int ranksperch;
1008
1009 if (PCI_FUNC(pdev->devfn) != 1)
1010 return -ENODEV;
1011
1012 rc = pci_enable_device(pdev);
1013 if (rc < 0) {
1014 ret = rc;
1015 goto bail;
1016 }
1017
Arthur Jones43920a52008-07-25 01:49:06 -07001018 /* ECC enabled? */
1019 pci_read_config_dword(pdev, I5100_MC, &dw);
Arthur Jonesb238e572008-07-25 01:49:08 -07001020 if (!i5100_mc_errdeten(dw)) {
Arthur Jones43920a52008-07-25 01:49:06 -07001021 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
1022 ret = -ENODEV;
Arthur Jonesb238e572008-07-25 01:49:08 -07001023 goto bail_pdev;
Arthur Jones43920a52008-07-25 01:49:06 -07001024 }
1025
Arthur Jones8f421c592008-07-25 01:49:04 -07001026 /* figure out how many ranks, from strapped state of 48GB_Mode input */
1027 pci_read_config_dword(pdev, I5100_MS, &dw);
1028 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
1029
Arthur Jones178d5a72008-07-25 01:49:06 -07001030 /* enable error reporting... */
1031 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
1032 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
1033 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
1034
Arthur Jones8f421c592008-07-25 01:49:04 -07001035 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
1036 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1037 PCI_DEVICE_ID_INTEL_5100_21, 0);
Arthur Jonesb238e572008-07-25 01:49:08 -07001038 if (!ch0mm) {
1039 ret = -ENODEV;
1040 goto bail_pdev;
1041 }
Arthur Jones8f421c592008-07-25 01:49:04 -07001042
1043 rc = pci_enable_device(ch0mm);
1044 if (rc < 0) {
1045 ret = rc;
1046 goto bail_ch0;
1047 }
1048
1049 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
1050 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1051 PCI_DEVICE_ID_INTEL_5100_22, 0);
1052 if (!ch1mm) {
1053 ret = -ENODEV;
Arthur Jonesb238e572008-07-25 01:49:08 -07001054 goto bail_disable_ch0;
Arthur Jones8f421c592008-07-25 01:49:04 -07001055 }
1056
1057 rc = pci_enable_device(ch1mm);
1058 if (rc < 0) {
1059 ret = rc;
1060 goto bail_ch1;
1061 }
1062
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -03001063 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1064 layers[0].size = 2;
1065 layers[0].is_virt_csrow = false;
1066 layers[1].type = EDAC_MC_LAYER_SLOT;
1067 layers[1].size = ranksperch;
1068 layers[1].is_virt_csrow = true;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -03001069 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -03001070 sizeof(*priv));
Arthur Jones8f421c592008-07-25 01:49:04 -07001071 if (!mci) {
1072 ret = -ENOMEM;
Arthur Jonesb238e572008-07-25 01:49:08 -07001073 goto bail_disable_ch1;
Arthur Jones8f421c592008-07-25 01:49:04 -07001074 }
1075
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001076
1077 /* device 19, func 0, Error injection */
1078 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1079 PCI_DEVICE_ID_INTEL_5100_19, 0);
1080 if (!einj) {
1081 ret = -ENODEV;
1082 goto bail_einj;
1083 }
1084
1085 rc = pci_enable_device(einj);
1086 if (rc < 0) {
1087 ret = rc;
1088 goto bail_disable_einj;
1089 }
1090
1091
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03001092 mci->pdev = &pdev->dev;
Arthur Jones8f421c592008-07-25 01:49:04 -07001093
1094 priv = mci->pvt_info;
Nils Carlsonb18dfd02009-12-15 16:47:40 -08001095 priv->ranksperchan = ranksperch;
Arthur Jones8f421c592008-07-25 01:49:04 -07001096 priv->mc = pdev;
1097 priv->ch0mm = ch0mm;
1098 priv->ch1mm = ch1mm;
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001099 priv->einj = einj;
Arthur Jones8f421c592008-07-25 01:49:04 -07001100
Nils Carlson295439f2009-12-15 16:47:42 -08001101 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
1102
1103 /* If scrubbing was already enabled by the bios, start maintaining it */
1104 pci_read_config_dword(pdev, I5100_MC, &dw);
1105 if (i5100_mc_scrben(dw)) {
1106 priv->scrub_enable = 1;
1107 schedule_delayed_work(&(priv->i5100_scrubbing),
1108 I5100_SCRUB_REFRESH_RATE);
1109 }
1110
Arthur Jones8f421c592008-07-25 01:49:04 -07001111 i5100_init_dimm_layout(pdev, mci);
1112 i5100_init_interleaving(pdev, mci);
1113
1114 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1115 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
1116 mci->edac_cap = EDAC_FLAG_SECDED;
1117 mci->mod_name = "i5100_edac.c";
1118 mci->mod_ver = "not versioned";
1119 mci->ctl_name = "i5100";
1120 mci->dev_name = pci_name(pdev);
Arthur Jonesb238e572008-07-25 01:49:08 -07001121 mci->ctl_page_to_phys = NULL;
Arthur Jones8f421c592008-07-25 01:49:04 -07001122
1123 mci->edac_check = i5100_check_error;
Nils Carlson295439f2009-12-15 16:47:42 -08001124 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
1125 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
Arthur Jones8f421c592008-07-25 01:49:04 -07001126
Niklas Söderlund53ceafd2012-08-08 12:30:57 -03001127 priv->inject_channel = 0;
1128 priv->inject_hlinesel = 0;
1129 priv->inject_deviceptr1 = 0;
1130 priv->inject_deviceptr2 = 0;
1131 priv->inject_eccmask1 = 0;
1132 priv->inject_eccmask2 = 0;
1133
Arthur Jones8f421c592008-07-25 01:49:04 -07001134 i5100_init_csrows(mci);
1135
1136 /* this strange construction seems to be in every driver, dunno why */
1137 switch (edac_op_state) {
1138 case EDAC_OPSTATE_POLL:
1139 case EDAC_OPSTATE_NMI:
1140 break;
1141 default:
1142 edac_op_state = EDAC_OPSTATE_POLL;
1143 break;
1144 }
1145
1146 if (edac_mc_add_mc(mci)) {
1147 ret = -ENODEV;
Nils Carlson295439f2009-12-15 16:47:42 -08001148 goto bail_scrub;
Arthur Jones8f421c592008-07-25 01:49:04 -07001149 }
1150
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001151 i5100_setup_debugfs(mci);
1152
Arthur Jonesb238e572008-07-25 01:49:08 -07001153 return ret;
Arthur Jones8f421c592008-07-25 01:49:04 -07001154
Nils Carlson295439f2009-12-15 16:47:42 -08001155bail_scrub:
1156 priv->scrub_enable = 0;
1157 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
Arthur Jones8f421c592008-07-25 01:49:04 -07001158 edac_mc_free(mci);
1159
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001160bail_disable_einj:
1161 pci_disable_device(einj);
1162
1163bail_einj:
1164 pci_dev_put(einj);
1165
Arthur Jonesb238e572008-07-25 01:49:08 -07001166bail_disable_ch1:
1167 pci_disable_device(ch1mm);
1168
Arthur Jones8f421c592008-07-25 01:49:04 -07001169bail_ch1:
1170 pci_dev_put(ch1mm);
1171
Arthur Jonesb238e572008-07-25 01:49:08 -07001172bail_disable_ch0:
1173 pci_disable_device(ch0mm);
1174
Arthur Jones8f421c592008-07-25 01:49:04 -07001175bail_ch0:
1176 pci_dev_put(ch0mm);
1177
Arthur Jonesb238e572008-07-25 01:49:08 -07001178bail_pdev:
1179 pci_disable_device(pdev);
1180
Arthur Jones8f421c592008-07-25 01:49:04 -07001181bail:
1182 return ret;
1183}
1184
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001185static void i5100_remove_one(struct pci_dev *pdev)
Arthur Jones8f421c592008-07-25 01:49:04 -07001186{
1187 struct mem_ctl_info *mci;
1188 struct i5100_priv *priv;
1189
1190 mci = edac_mc_del_mc(&pdev->dev);
1191
1192 if (!mci)
1193 return;
1194
1195 priv = mci->pvt_info;
Nils Carlson295439f2009-12-15 16:47:42 -08001196
Mauro Carvalho Chehab59b97962013-02-21 11:01:23 -03001197 debugfs_remove_recursive(priv->debugfs);
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001198
Nils Carlson295439f2009-12-15 16:47:42 -08001199 priv->scrub_enable = 0;
1200 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1201
Arthur Jonesb238e572008-07-25 01:49:08 -07001202 pci_disable_device(pdev);
1203 pci_disable_device(priv->ch0mm);
1204 pci_disable_device(priv->ch1mm);
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001205 pci_disable_device(priv->einj);
Arthur Jones8f421c592008-07-25 01:49:04 -07001206 pci_dev_put(priv->ch0mm);
1207 pci_dev_put(priv->ch1mm);
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001208 pci_dev_put(priv->einj);
Arthur Jones8f421c592008-07-25 01:49:04 -07001209
1210 edac_mc_free(mci);
1211}
1212
Jingoo Hanba935f42013-12-06 10:23:08 +01001213static const struct pci_device_id i5100_pci_tbl[] = {
Arthur Jones8f421c592008-07-25 01:49:04 -07001214 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1215 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1216 { 0, }
1217};
1218MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1219
1220static struct pci_driver i5100_driver = {
1221 .name = KBUILD_BASENAME,
1222 .probe = i5100_init_one,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001223 .remove = i5100_remove_one,
Arthur Jones8f421c592008-07-25 01:49:04 -07001224 .id_table = i5100_pci_tbl,
1225};
1226
1227static int __init i5100_init(void)
1228{
1229 int pci_rc;
1230
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001231 i5100_debugfs = debugfs_create_dir("i5100_edac", NULL);
Arthur Jones8f421c592008-07-25 01:49:04 -07001232
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001233 pci_rc = pci_register_driver(&i5100_driver);
Arthur Jones8f421c592008-07-25 01:49:04 -07001234 return (pci_rc < 0) ? pci_rc : 0;
1235}
1236
1237static void __exit i5100_exit(void)
1238{
Mauro Carvalho Chehab59b97962013-02-21 11:01:23 -03001239 debugfs_remove(i5100_debugfs);
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001240
Arthur Jones8f421c592008-07-25 01:49:04 -07001241 pci_unregister_driver(&i5100_driver);
1242}
1243
1244module_init(i5100_init);
1245module_exit(i5100_exit);
1246
1247MODULE_LICENSE("GPL");
1248MODULE_AUTHOR
1249 ("Arthur Jones <ajones@riverbed.com>");
1250MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");