Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_dma.c -- DMA support for the I915 -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 31 | #include "drm_crtc_helper.h" |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 32 | #include "drm_fb_helper.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 33 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include "i915_drm.h" |
| 35 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 36 | #include "i915_trace.h" |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 37 | #include "../../../platform/x86/intel_ips.h" |
Jordan Crouse | dcdb167 | 2010-05-27 13:40:25 -0600 | [diff] [blame] | 38 | #include <linux/pci.h> |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 39 | #include <linux/vgaarb.h> |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 40 | #include <linux/acpi.h> |
| 41 | #include <linux/pnp.h> |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 42 | #include <linux/vga_switcheroo.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 43 | #include <linux/slab.h> |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 44 | #include <acpi/video.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 46 | /** |
| 47 | * Sets up the hardware status page for devices that need a physical address |
| 48 | * in the register. |
| 49 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 50 | static int i915_init_phys_hws(struct drm_device *dev) |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 51 | { |
| 52 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 53 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
| 54 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 55 | /* Program Hardware Status Page */ |
| 56 | dev_priv->status_page_dmah = |
Zhenyu Wang | e6be8d9 | 2010-01-05 11:25:05 +0800 | [diff] [blame] | 57 | drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 58 | |
| 59 | if (!dev_priv->status_page_dmah) { |
| 60 | DRM_ERROR("Can not allocate hardware status page\n"); |
| 61 | return -ENOMEM; |
| 62 | } |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 63 | ring->status_page.page_addr = |
| 64 | (void __force __iomem *)dev_priv->status_page_dmah->vaddr; |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 65 | dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; |
| 66 | |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 67 | memset_io(ring->status_page.page_addr, 0, PAGE_SIZE); |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 68 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 69 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | 9b974cc | 2010-01-05 11:25:06 +0800 | [diff] [blame] | 70 | dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & |
| 71 | 0xf0; |
| 72 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 73 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 74 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | /** |
| 79 | * Frees the hardware status page, whether it's a physical address or a virtual |
| 80 | * address set up by the X Server. |
| 81 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 82 | static void i915_free_hws(struct drm_device *dev) |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 83 | { |
| 84 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 85 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
| 86 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 87 | if (dev_priv->status_page_dmah) { |
| 88 | drm_pci_free(dev, dev_priv->status_page_dmah); |
| 89 | dev_priv->status_page_dmah = NULL; |
| 90 | } |
| 91 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 92 | if (ring->status_page.gfx_addr) { |
| 93 | ring->status_page.gfx_addr = 0; |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 94 | drm_core_ioremapfree(&dev_priv->hws_map, dev); |
| 95 | } |
| 96 | |
| 97 | /* Need to rewrite hardware status page */ |
| 98 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 99 | } |
| 100 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 101 | void i915_kernel_lost_context(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | { |
| 103 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 104 | struct drm_i915_master_private *master_priv; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 105 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 107 | /* |
| 108 | * We should never lose context on the ring with modesetting |
| 109 | * as we don't expose it to userspace |
| 110 | */ |
| 111 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 112 | return; |
| 113 | |
Chris Wilson | 8168bd4 | 2010-11-11 17:54:52 +0000 | [diff] [blame] | 114 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
| 115 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | ring->space = ring->head - (ring->tail + 8); |
| 117 | if (ring->space < 0) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 118 | ring->space += ring->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 120 | if (!dev->primary->master) |
| 121 | return; |
| 122 | |
| 123 | master_priv = dev->primary->master->driver_priv; |
| 124 | if (ring->head == ring->tail && master_priv->sarea_priv) |
| 125 | master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | } |
| 127 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 128 | static int i915_dma_cleanup(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 130 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 131 | int i; |
| 132 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | /* Make sure interrupts are disabled here because the uninstall ioctl |
| 134 | * may not have been called from userspace and after dev_private |
| 135 | * is freed, it's too late. |
| 136 | */ |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 137 | if (dev->irq_enabled) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 138 | drm_irq_uninstall(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | |
Dan Carpenter | ee0c6bf | 2010-06-23 13:19:55 +0200 | [diff] [blame] | 140 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 141 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 142 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Dan Carpenter | ee0c6bf | 2010-06-23 13:19:55 +0200 | [diff] [blame] | 143 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 145 | /* Clear the HWS virtual address at teardown */ |
| 146 | if (I915_NEED_GFX_HWS(dev)) |
| 147 | i915_free_hws(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | |
| 149 | return 0; |
| 150 | } |
| 151 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 152 | static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 154 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 155 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 156 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | |
Dave Airlie | 3a03ac1 | 2009-01-11 09:03:49 +1000 | [diff] [blame] | 158 | master_priv->sarea = drm_getsarea(dev); |
| 159 | if (master_priv->sarea) { |
| 160 | master_priv->sarea_priv = (drm_i915_sarea_t *) |
| 161 | ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); |
| 162 | } else { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 163 | DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n"); |
Dave Airlie | 3a03ac1 | 2009-01-11 09:03:49 +1000 | [diff] [blame] | 164 | } |
| 165 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 166 | if (init->ring_size != 0) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 167 | if (LP_RING(dev_priv)->obj != NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 168 | i915_dma_cleanup(dev); |
| 169 | DRM_ERROR("Client tried to initialize ringbuffer in " |
| 170 | "GEM mode\n"); |
| 171 | return -EINVAL; |
| 172 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 174 | ret = intel_render_ring_init_dri(dev, |
| 175 | init->ring_start, |
| 176 | init->ring_size); |
| 177 | if (ret) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 178 | i915_dma_cleanup(dev); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 179 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 180 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | } |
| 182 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 183 | dev_priv->cpp = init->cpp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | dev_priv->back_offset = init->back_offset; |
| 185 | dev_priv->front_offset = init->front_offset; |
| 186 | dev_priv->current_page = 0; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 187 | if (master_priv->sarea_priv) |
| 188 | master_priv->sarea_priv->pf_current_page = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | /* Allow hardware batchbuffers unless told otherwise. |
| 191 | */ |
| 192 | dev_priv->allow_batchbuffer = 1; |
| 193 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | return 0; |
| 195 | } |
| 196 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 197 | static int i915_dma_resume(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | { |
| 199 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 200 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 202 | DRM_DEBUG_DRIVER("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 204 | if (ring->map.handle == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | DRM_ERROR("can not ioremap virtual address for" |
| 206 | " ring buffer\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 207 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /* Program Hardware Status Page */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 211 | if (!ring->status_page.page_addr) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | DRM_ERROR("Can not find hardware status page\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 213 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | } |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 215 | DRM_DEBUG_DRIVER("hw status page @ %p\n", |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 216 | ring->status_page.page_addr); |
| 217 | if (ring->status_page.gfx_addr != 0) |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 218 | intel_ring_setup_status_page(ring); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 219 | else |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 220 | I915_WRITE(HWS_PGA, dev_priv->dma_status_page); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 221 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 222 | DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | |
| 224 | return 0; |
| 225 | } |
| 226 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 227 | static int i915_dma_init(struct drm_device *dev, void *data, |
| 228 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | { |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 230 | drm_i915_init_t *init = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | int retcode = 0; |
| 232 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 233 | switch (init->func) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | case I915_INIT_DMA: |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 235 | retcode = i915_initialize(dev, init); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | break; |
| 237 | case I915_CLEANUP_DMA: |
| 238 | retcode = i915_dma_cleanup(dev); |
| 239 | break; |
| 240 | case I915_RESUME_DMA: |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 241 | retcode = i915_dma_resume(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | break; |
| 243 | default: |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 244 | retcode = -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | break; |
| 246 | } |
| 247 | |
| 248 | return retcode; |
| 249 | } |
| 250 | |
| 251 | /* Implement basically the same security restrictions as hardware does |
| 252 | * for MI_BATCH_NON_SECURE. These can be made stricter at any time. |
| 253 | * |
| 254 | * Most of the calculations below involve calculating the size of a |
| 255 | * particular instruction. It's important to get the size right as |
| 256 | * that tells us where the next instruction to check is. Any illegal |
| 257 | * instruction detected will be given a size of zero, which is a |
| 258 | * signal to abort the rest of the buffer. |
| 259 | */ |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 260 | static int validate_cmd(int cmd) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | { |
| 262 | switch (((cmd >> 29) & 0x7)) { |
| 263 | case 0x0: |
| 264 | switch ((cmd >> 23) & 0x3f) { |
| 265 | case 0x0: |
| 266 | return 1; /* MI_NOOP */ |
| 267 | case 0x4: |
| 268 | return 1; /* MI_FLUSH */ |
| 269 | default: |
| 270 | return 0; /* disallow everything else */ |
| 271 | } |
| 272 | break; |
| 273 | case 0x1: |
| 274 | return 0; /* reserved */ |
| 275 | case 0x2: |
| 276 | return (cmd & 0xff) + 2; /* 2d commands */ |
| 277 | case 0x3: |
| 278 | if (((cmd >> 24) & 0x1f) <= 0x18) |
| 279 | return 1; |
| 280 | |
| 281 | switch ((cmd >> 24) & 0x1f) { |
| 282 | case 0x1c: |
| 283 | return 1; |
| 284 | case 0x1d: |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 285 | switch ((cmd >> 16) & 0xff) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | case 0x3: |
| 287 | return (cmd & 0x1f) + 2; |
| 288 | case 0x4: |
| 289 | return (cmd & 0xf) + 2; |
| 290 | default: |
| 291 | return (cmd & 0xffff) + 2; |
| 292 | } |
| 293 | case 0x1e: |
| 294 | if (cmd & (1 << 23)) |
| 295 | return (cmd & 0xffff) + 1; |
| 296 | else |
| 297 | return 1; |
| 298 | case 0x1f: |
| 299 | if ((cmd & (1 << 23)) == 0) /* inline vertices */ |
| 300 | return (cmd & 0x1ffff) + 2; |
| 301 | else if (cmd & (1 << 17)) /* indirect random */ |
| 302 | if ((cmd & 0xffff) == 0) |
| 303 | return 0; /* unknown length, too hard */ |
| 304 | else |
| 305 | return (((cmd & 0xffff) + 1) / 2) + 1; |
| 306 | else |
| 307 | return 2; /* indirect sequential */ |
| 308 | default: |
| 309 | return 0; |
| 310 | } |
| 311 | default: |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | return 0; |
| 316 | } |
| 317 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 318 | static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | { |
| 320 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 321 | int i, ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 323 | if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 324 | return -EINVAL; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 325 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | for (i = 0; i < dwords;) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 327 | int sz = validate_cmd(buffer[i]); |
| 328 | if (sz == 0 || i + sz > dwords) |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 329 | return -EINVAL; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 330 | i += sz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | } |
| 332 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 333 | ret = BEGIN_LP_RING((dwords+1)&~1); |
| 334 | if (ret) |
| 335 | return ret; |
| 336 | |
| 337 | for (i = 0; i < dwords; i++) |
| 338 | OUT_RING(buffer[i]); |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 339 | if (dwords & 1) |
| 340 | OUT_RING(0); |
| 341 | |
| 342 | ADVANCE_LP_RING(); |
| 343 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 344 | return 0; |
| 345 | } |
| 346 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 347 | int |
| 348 | i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 349 | struct drm_clip_rect *box, |
| 350 | int DR1, int DR4) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 352 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 353 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 354 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 355 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || |
| 356 | box->y2 <= 0 || box->x2 <= 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | DRM_ERROR("Bad box %d,%d..%d,%d\n", |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 358 | box->x1, box->y1, box->x2, box->y2); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 359 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 360 | } |
| 361 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 362 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 363 | ret = BEGIN_LP_RING(4); |
| 364 | if (ret) |
| 365 | return ret; |
| 366 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 367 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 368 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
| 369 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 370 | OUT_RING(DR4); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 371 | } else { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 372 | ret = BEGIN_LP_RING(6); |
| 373 | if (ret) |
| 374 | return ret; |
| 375 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 376 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
| 377 | OUT_RING(DR1); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 378 | OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); |
| 379 | OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 380 | OUT_RING(DR4); |
| 381 | OUT_RING(0); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 382 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 383 | ADVANCE_LP_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | |
| 385 | return 0; |
| 386 | } |
| 387 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 388 | /* XXX: Emitting the counter should really be moved to part of the IRQ |
| 389 | * emit. For now, do it in both places: |
| 390 | */ |
| 391 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 392 | static void i915_emit_breadcrumb(struct drm_device *dev) |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 393 | { |
| 394 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 395 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 396 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 397 | dev_priv->counter++; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 398 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 399 | dev_priv->counter = 0; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 400 | if (master_priv->sarea_priv) |
| 401 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 402 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 403 | if (BEGIN_LP_RING(4) == 0) { |
| 404 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 405 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 406 | OUT_RING(dev_priv->counter); |
| 407 | OUT_RING(0); |
| 408 | ADVANCE_LP_RING(); |
| 409 | } |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 410 | } |
| 411 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 412 | static int i915_dispatch_cmdbuffer(struct drm_device * dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 413 | drm_i915_cmdbuffer_t *cmd, |
| 414 | struct drm_clip_rect *cliprects, |
| 415 | void *cmdbuf) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | { |
| 417 | int nbox = cmd->num_cliprects; |
| 418 | int i = 0, count, ret; |
| 419 | |
| 420 | if (cmd->sz & 0x3) { |
| 421 | DRM_ERROR("alignment"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 422 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | i915_kernel_lost_context(dev); |
| 426 | |
| 427 | count = nbox ? nbox : 1; |
| 428 | |
| 429 | for (i = 0; i < count; i++) { |
| 430 | if (i < nbox) { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 431 | ret = i915_emit_box(dev, &cliprects[i], |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | cmd->DR1, cmd->DR4); |
| 433 | if (ret) |
| 434 | return ret; |
| 435 | } |
| 436 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 437 | ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | if (ret) |
| 439 | return ret; |
| 440 | } |
| 441 | |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 442 | i915_emit_breadcrumb(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | return 0; |
| 444 | } |
| 445 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 446 | static int i915_dispatch_batchbuffer(struct drm_device * dev, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 447 | drm_i915_batchbuffer_t * batch, |
| 448 | struct drm_clip_rect *cliprects) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 449 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 450 | struct drm_i915_private *dev_priv = dev->dev_private; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 451 | int nbox = batch->num_cliprects; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 452 | int i, count, ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | |
| 454 | if ((batch->start | batch->used) & 0x7) { |
| 455 | DRM_ERROR("alignment"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 456 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | i915_kernel_lost_context(dev); |
| 460 | |
| 461 | count = nbox ? nbox : 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | for (i = 0; i < count; i++) { |
| 463 | if (i < nbox) { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 464 | ret = i915_emit_box(dev, &cliprects[i], |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 465 | batch->DR1, batch->DR4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | if (ret) |
| 467 | return ret; |
| 468 | } |
| 469 | |
Keith Packard | 0790d5e | 2008-07-30 12:28:47 -0700 | [diff] [blame] | 470 | if (!IS_I830(dev) && !IS_845G(dev)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 471 | ret = BEGIN_LP_RING(2); |
| 472 | if (ret) |
| 473 | return ret; |
| 474 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 475 | if (INTEL_INFO(dev)->gen >= 4) { |
Dave Airlie | 21f1628 | 2007-08-07 09:09:51 +1000 | [diff] [blame] | 476 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); |
| 477 | OUT_RING(batch->start); |
| 478 | } else { |
| 479 | OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); |
| 480 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); |
| 481 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 482 | } else { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 483 | ret = BEGIN_LP_RING(4); |
| 484 | if (ret) |
| 485 | return ret; |
| 486 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | OUT_RING(MI_BATCH_BUFFER); |
| 488 | OUT_RING(batch->start | MI_BATCH_NON_SECURE); |
| 489 | OUT_RING(batch->start + batch->used - 4); |
| 490 | OUT_RING(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 492 | ADVANCE_LP_RING(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | } |
| 494 | |
Zou Nan hai | 1cafd34 | 2010-06-25 13:40:24 +0800 | [diff] [blame] | 495 | |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 496 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 497 | if (BEGIN_LP_RING(2) == 0) { |
| 498 | OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); |
| 499 | OUT_RING(MI_NOOP); |
| 500 | ADVANCE_LP_RING(); |
| 501 | } |
Zou Nan hai | 1cafd34 | 2010-06-25 13:40:24 +0800 | [diff] [blame] | 502 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 504 | i915_emit_breadcrumb(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | return 0; |
| 506 | } |
| 507 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 508 | static int i915_dispatch_flip(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | { |
| 510 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 511 | struct drm_i915_master_private *master_priv = |
| 512 | dev->primary->master->driver_priv; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 513 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 515 | if (!master_priv->sarea_priv) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 516 | return -EINVAL; |
| 517 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 518 | DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 519 | __func__, |
| 520 | dev_priv->current_page, |
| 521 | master_priv->sarea_priv->pf_current_page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 523 | i915_kernel_lost_context(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 524 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 525 | ret = BEGIN_LP_RING(10); |
| 526 | if (ret) |
| 527 | return ret; |
| 528 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 529 | OUT_RING(MI_FLUSH | MI_READ_FLUSH); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 530 | OUT_RING(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 532 | OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); |
| 533 | OUT_RING(0); |
| 534 | if (dev_priv->current_page == 0) { |
| 535 | OUT_RING(dev_priv->back_offset); |
| 536 | dev_priv->current_page = 1; |
| 537 | } else { |
| 538 | OUT_RING(dev_priv->front_offset); |
| 539 | dev_priv->current_page = 0; |
| 540 | } |
| 541 | OUT_RING(0); |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 542 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 543 | OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); |
| 544 | OUT_RING(0); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 545 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 546 | ADVANCE_LP_RING(); |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 547 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 548 | master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 549 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 550 | if (BEGIN_LP_RING(4) == 0) { |
| 551 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 552 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 553 | OUT_RING(dev_priv->counter); |
| 554 | OUT_RING(0); |
| 555 | ADVANCE_LP_RING(); |
| 556 | } |
Jesse Barnes | ac741ab | 2008-04-22 16:03:07 +1000 | [diff] [blame] | 557 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 558 | master_priv->sarea_priv->pf_current_page = dev_priv->current_page; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 559 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | } |
| 561 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 562 | static int i915_quiescent(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 563 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 564 | struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 565 | |
| 566 | i915_kernel_lost_context(dev); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 567 | return intel_wait_ring_buffer(ring, ring->size - 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | } |
| 569 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 570 | static int i915_flush_ioctl(struct drm_device *dev, void *data, |
| 571 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 572 | { |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 573 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 574 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 575 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 576 | |
| 577 | mutex_lock(&dev->struct_mutex); |
| 578 | ret = i915_quiescent(dev); |
| 579 | mutex_unlock(&dev->struct_mutex); |
| 580 | |
| 581 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | } |
| 583 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 584 | static int i915_batchbuffer(struct drm_device *dev, void *data, |
| 585 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 586 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 587 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 588 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 589 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 590 | master_priv->sarea_priv; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 591 | drm_i915_batchbuffer_t *batch = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | int ret; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 593 | struct drm_clip_rect *cliprects = NULL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | |
| 595 | if (!dev_priv->allow_batchbuffer) { |
| 596 | DRM_ERROR("Batchbuffer ioctl disabled\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 597 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 598 | } |
| 599 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 600 | DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 601 | batch->start, batch->used, batch->num_cliprects); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 603 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 604 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 605 | if (batch->num_cliprects < 0) |
| 606 | return -EINVAL; |
| 607 | |
| 608 | if (batch->num_cliprects) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 609 | cliprects = kcalloc(batch->num_cliprects, |
| 610 | sizeof(struct drm_clip_rect), |
| 611 | GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 612 | if (cliprects == NULL) |
| 613 | return -ENOMEM; |
| 614 | |
| 615 | ret = copy_from_user(cliprects, batch->cliprects, |
| 616 | batch->num_cliprects * |
| 617 | sizeof(struct drm_clip_rect)); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 618 | if (ret != 0) { |
| 619 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 620 | goto fail_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 621 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 622 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 624 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 625 | ret = i915_dispatch_batchbuffer(dev, batch, cliprects); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 626 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 628 | if (sarea_priv) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 629 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 630 | |
| 631 | fail_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 632 | kfree(cliprects); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 633 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | return ret; |
| 635 | } |
| 636 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 637 | static int i915_cmdbuffer(struct drm_device *dev, void *data, |
| 638 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 641 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 643 | master_priv->sarea_priv; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 644 | drm_i915_cmdbuffer_t *cmdbuf = data; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 645 | struct drm_clip_rect *cliprects = NULL; |
| 646 | void *batch_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | int ret; |
| 648 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 649 | DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 650 | cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 652 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 654 | if (cmdbuf->num_cliprects < 0) |
| 655 | return -EINVAL; |
| 656 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 657 | batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 658 | if (batch_data == NULL) |
| 659 | return -ENOMEM; |
| 660 | |
| 661 | ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 662 | if (ret != 0) { |
| 663 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 664 | goto fail_batch_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 665 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 666 | |
| 667 | if (cmdbuf->num_cliprects) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 668 | cliprects = kcalloc(cmdbuf->num_cliprects, |
| 669 | sizeof(struct drm_clip_rect), GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 670 | if (cliprects == NULL) { |
| 671 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 672 | goto fail_batch_free; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 673 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 674 | |
| 675 | ret = copy_from_user(cliprects, cmdbuf->cliprects, |
| 676 | cmdbuf->num_cliprects * |
| 677 | sizeof(struct drm_clip_rect)); |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 678 | if (ret != 0) { |
| 679 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 680 | goto fail_clip_free; |
Dan Carpenter | 9927a40 | 2010-06-19 15:12:51 +0200 | [diff] [blame] | 681 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | } |
| 683 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 684 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 685 | ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 686 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 687 | if (ret) { |
| 688 | DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); |
Chris Wright | 355d7f3 | 2009-04-17 01:18:55 +0000 | [diff] [blame] | 689 | goto fail_clip_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 690 | } |
| 691 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 692 | if (sarea_priv) |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 693 | sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 694 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 695 | fail_clip_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 696 | kfree(cliprects); |
Chris Wright | 355d7f3 | 2009-04-17 01:18:55 +0000 | [diff] [blame] | 697 | fail_batch_free: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 698 | kfree(batch_data); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 699 | |
| 700 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 701 | } |
| 702 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 703 | static int i915_flip_bufs(struct drm_device *dev, void *data, |
| 704 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | { |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 706 | int ret; |
| 707 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 708 | DRM_DEBUG_DRIVER("%s\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 709 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 710 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 712 | mutex_lock(&dev->struct_mutex); |
| 713 | ret = i915_dispatch_flip(dev); |
| 714 | mutex_unlock(&dev->struct_mutex); |
| 715 | |
| 716 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | } |
| 718 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 719 | static int i915_getparam(struct drm_device *dev, void *data, |
| 720 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 722 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 723 | drm_i915_getparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | int value; |
| 725 | |
| 726 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 727 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 728 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | } |
| 730 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 731 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | case I915_PARAM_IRQ_ACTIVE: |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 733 | value = dev->pdev->irq ? 1 : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 734 | break; |
| 735 | case I915_PARAM_ALLOW_BATCHBUFFER: |
| 736 | value = dev_priv->allow_batchbuffer ? 1 : 0; |
| 737 | break; |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 738 | case I915_PARAM_LAST_DISPATCH: |
| 739 | value = READ_BREADCRUMB(dev_priv); |
| 740 | break; |
Kristian Høgsberg | ed4c9c4 | 2008-08-20 11:08:52 -0400 | [diff] [blame] | 741 | case I915_PARAM_CHIPSET_ID: |
| 742 | value = dev->pci_device; |
| 743 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 744 | case I915_PARAM_HAS_GEM: |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 745 | value = dev_priv->has_gem; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 746 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 747 | case I915_PARAM_NUM_FENCES_AVAIL: |
| 748 | value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; |
| 749 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 750 | case I915_PARAM_HAS_OVERLAY: |
| 751 | value = dev_priv->overlay ? 1 : 0; |
| 752 | break; |
Jesse Barnes | e9560f7 | 2009-11-19 10:49:07 -0800 | [diff] [blame] | 753 | case I915_PARAM_HAS_PAGEFLIPPING: |
| 754 | value = 1; |
| 755 | break; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 756 | case I915_PARAM_HAS_EXECBUF2: |
| 757 | /* depends on GEM */ |
| 758 | value = dev_priv->has_gem; |
| 759 | break; |
Zou Nan hai | e3a815f | 2010-05-31 13:58:47 +0800 | [diff] [blame] | 760 | case I915_PARAM_HAS_BSD: |
| 761 | value = HAS_BSD(dev); |
| 762 | break; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 763 | case I915_PARAM_HAS_BLT: |
| 764 | value = HAS_BLT(dev); |
| 765 | break; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 766 | case I915_PARAM_HAS_RELAXED_FENCING: |
| 767 | value = 1; |
| 768 | break; |
Daniel Vetter | bbf0c6b | 2010-12-05 11:30:40 +0100 | [diff] [blame] | 769 | case I915_PARAM_HAS_COHERENT_RINGS: |
| 770 | value = 1; |
| 771 | break; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 772 | case I915_PARAM_HAS_EXEC_CONSTANTS: |
| 773 | value = INTEL_INFO(dev)->gen >= 4; |
| 774 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | default: |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 776 | DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 777 | param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 778 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 779 | } |
| 780 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 781 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 783 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | } |
| 785 | |
| 786 | return 0; |
| 787 | } |
| 788 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 789 | static int i915_setparam(struct drm_device *dev, void *data, |
| 790 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 791 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 793 | drm_i915_setparam_t *param = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 794 | |
| 795 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 796 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 797 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 798 | } |
| 799 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 800 | switch (param->param) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | case I915_SETPARAM_USE_MI_BATCHBUFFER_START: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | break; |
| 803 | case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 804 | dev_priv->tex_lru_log_granularity = param->value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | break; |
| 806 | case I915_SETPARAM_ALLOW_BATCHBUFFER: |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 807 | dev_priv->allow_batchbuffer = param->value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 808 | break; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 809 | case I915_SETPARAM_NUM_USED_FENCES: |
| 810 | if (param->value > dev_priv->num_fence_regs || |
| 811 | param->value < 0) |
| 812 | return -EINVAL; |
| 813 | /* Userspace can use first N regs */ |
| 814 | dev_priv->fence_reg_start = param->value; |
| 815 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | default: |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 817 | DRM_DEBUG_DRIVER("unknown parameter %d\n", |
yakui_zhao | be25ed9 | 2009-06-02 14:13:55 +0800 | [diff] [blame] | 818 | param->param); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 819 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | return 0; |
| 823 | } |
| 824 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 825 | static int i915_set_status_page(struct drm_device *dev, void *data, |
| 826 | struct drm_file *file_priv) |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 827 | { |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 828 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 829 | drm_i915_hws_addr_t *hws = data; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 830 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 831 | |
Zhenyu Wang | b39d50e | 2008-02-19 20:59:09 +1000 | [diff] [blame] | 832 | if (!I915_NEED_GFX_HWS(dev)) |
| 833 | return -EINVAL; |
| 834 | |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 835 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 836 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 837 | return -EINVAL; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 838 | } |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 839 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 840 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 841 | WARN(1, "tried to set status page when mode setting active\n"); |
| 842 | return 0; |
| 843 | } |
| 844 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 845 | DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 846 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 847 | ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 848 | |
Eric Anholt | 8b40958 | 2007-11-22 16:40:37 +1000 | [diff] [blame] | 849 | dev_priv->hws_map.offset = dev->agp->base + hws->addr; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 850 | dev_priv->hws_map.size = 4*1024; |
| 851 | dev_priv->hws_map.type = 0; |
| 852 | dev_priv->hws_map.flags = 0; |
| 853 | dev_priv->hws_map.mtrr = 0; |
| 854 | |
Dave Airlie | dd0910b | 2009-02-25 14:49:21 +1000 | [diff] [blame] | 855 | drm_core_ioremap_wc(&dev_priv->hws_map, dev); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 856 | if (dev_priv->hws_map.handle == NULL) { |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 857 | i915_dma_cleanup(dev); |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 858 | ring->status_page.gfx_addr = 0; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 859 | DRM_ERROR("can not ioremap virtual address for" |
| 860 | " G33 hw status page\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 861 | return -ENOMEM; |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 862 | } |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 863 | ring->status_page.page_addr = |
| 864 | (void __force __iomem *)dev_priv->hws_map.handle; |
| 865 | memset_io(ring->status_page.page_addr, 0, PAGE_SIZE); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 866 | I915_WRITE(HWS_PGA, ring->status_page.gfx_addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 867 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 868 | DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n", |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 869 | ring->status_page.gfx_addr); |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 870 | DRM_DEBUG_DRIVER("load hws at %p\n", |
Eric Anholt | e20f9c6 | 2010-05-26 14:51:06 -0700 | [diff] [blame] | 871 | ring->status_page.page_addr); |
Wang Zhenyu | dc7a931 | 2007-06-10 15:58:19 +1000 | [diff] [blame] | 872 | return 0; |
| 873 | } |
| 874 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 875 | static int i915_get_bridge_dev(struct drm_device *dev) |
| 876 | { |
| 877 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 878 | |
| 879 | dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
| 880 | if (!dev_priv->bridge_dev) { |
| 881 | DRM_ERROR("bridge device not found\n"); |
| 882 | return -1; |
| 883 | } |
| 884 | return 0; |
| 885 | } |
| 886 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 887 | #define MCHBAR_I915 0x44 |
| 888 | #define MCHBAR_I965 0x48 |
| 889 | #define MCHBAR_SIZE (4*4096) |
| 890 | |
| 891 | #define DEVEN_REG 0x54 |
| 892 | #define DEVEN_MCHBAR_EN (1 << 28) |
| 893 | |
| 894 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
| 895 | static int |
| 896 | intel_alloc_mchbar_resource(struct drm_device *dev) |
| 897 | { |
| 898 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 899 | int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 900 | u32 temp_lo, temp_hi = 0; |
| 901 | u64 mchbar_addr; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 902 | int ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 903 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 904 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 905 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
| 906 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); |
| 907 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
| 908 | |
| 909 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ |
| 910 | #ifdef CONFIG_PNP |
| 911 | if (mchbar_addr && |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 912 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) |
| 913 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 914 | #endif |
| 915 | |
| 916 | /* Get some space for it */ |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 917 | dev_priv->mch_res.name = "i915 MCHBAR"; |
| 918 | dev_priv->mch_res.flags = IORESOURCE_MEM; |
| 919 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, |
| 920 | &dev_priv->mch_res, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 921 | MCHBAR_SIZE, MCHBAR_SIZE, |
| 922 | PCIBIOS_MIN_MEM, |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 923 | 0, pcibios_align_resource, |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 924 | dev_priv->bridge_dev); |
| 925 | if (ret) { |
| 926 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); |
| 927 | dev_priv->mch_res.start = 0; |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 928 | return ret; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 929 | } |
| 930 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 931 | if (INTEL_INFO(dev)->gen >= 4) |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 932 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
| 933 | upper_32_bits(dev_priv->mch_res.start)); |
| 934 | |
| 935 | pci_write_config_dword(dev_priv->bridge_dev, reg, |
| 936 | lower_32_bits(dev_priv->mch_res.start)); |
Chris Wilson | a25c25c | 2010-08-20 14:36:45 +0100 | [diff] [blame] | 937 | return 0; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
| 941 | static void |
| 942 | intel_setup_mchbar(struct drm_device *dev) |
| 943 | { |
| 944 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 945 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 946 | u32 temp; |
| 947 | bool enabled; |
| 948 | |
| 949 | dev_priv->mchbar_need_disable = false; |
| 950 | |
| 951 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 952 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 953 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
| 954 | } else { |
| 955 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 956 | enabled = temp & 1; |
| 957 | } |
| 958 | |
| 959 | /* If it's already enabled, don't have to do anything */ |
| 960 | if (enabled) |
| 961 | return; |
| 962 | |
| 963 | if (intel_alloc_mchbar_resource(dev)) |
| 964 | return; |
| 965 | |
| 966 | dev_priv->mchbar_need_disable = true; |
| 967 | |
| 968 | /* Space is allocated or reserved, so enable it. */ |
| 969 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 970 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, |
| 971 | temp | DEVEN_MCHBAR_EN); |
| 972 | } else { |
| 973 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 974 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); |
| 975 | } |
| 976 | } |
| 977 | |
| 978 | static void |
| 979 | intel_teardown_mchbar(struct drm_device *dev) |
| 980 | { |
| 981 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 982 | int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 983 | u32 temp; |
| 984 | |
| 985 | if (dev_priv->mchbar_need_disable) { |
| 986 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 987 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
| 988 | temp &= ~DEVEN_MCHBAR_EN; |
| 989 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); |
| 990 | } else { |
| 991 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
| 992 | temp &= ~1; |
| 993 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); |
| 994 | } |
| 995 | } |
| 996 | |
| 997 | if (dev_priv->mch_res.start) |
| 998 | release_resource(&dev_priv->mch_res); |
| 999 | } |
| 1000 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1001 | #define PTE_ADDRESS_MASK 0xfffff000 |
| 1002 | #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ |
| 1003 | #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) |
| 1004 | #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ |
| 1005 | #define PTE_MAPPING_TYPE_CACHED (3 << 1) |
| 1006 | #define PTE_MAPPING_TYPE_MASK (3 << 1) |
| 1007 | #define PTE_VALID (1 << 0) |
| 1008 | |
| 1009 | /** |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1010 | * i915_stolen_to_phys - take an offset into stolen memory and turn it into |
| 1011 | * a physical one |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1012 | * @dev: drm device |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1013 | * @offset: address to translate |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1014 | * |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1015 | * Some chip functions require allocations from stolen space and need the |
| 1016 | * physical address of the memory in question. |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1017 | */ |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1018 | static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset) |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1019 | { |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1021 | struct pci_dev *pdev = dev_priv->bridge_dev; |
| 1022 | u32 base; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1023 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1024 | #if 0 |
| 1025 | /* On the machines I have tested the Graphics Base of Stolen Memory |
| 1026 | * is unreliable, so compute the base by subtracting the stolen memory |
| 1027 | * from the Top of Low Usable DRAM which is where the BIOS places |
| 1028 | * the graphics stolen memory. |
| 1029 | */ |
| 1030 | if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { |
| 1031 | /* top 32bits are reserved = 0 */ |
| 1032 | pci_read_config_dword(pdev, 0xA4, &base); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1033 | } else { |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1034 | /* XXX presume 8xx is the same as i915 */ |
| 1035 | pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1036 | } |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1037 | #else |
| 1038 | if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { |
| 1039 | u16 val; |
| 1040 | pci_read_config_word(pdev, 0xb0, &val); |
| 1041 | base = val >> 4 << 20; |
| 1042 | } else { |
| 1043 | u8 val; |
| 1044 | pci_read_config_byte(pdev, 0x9c, &val); |
| 1045 | base = val >> 3 << 27; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1046 | } |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 1047 | base -= dev_priv->mm.gtt->stolen_size; |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1048 | #endif |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1049 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1050 | return base + offset; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1051 | } |
| 1052 | |
| 1053 | static void i915_warn_stolen(struct drm_device *dev) |
| 1054 | { |
| 1055 | DRM_ERROR("not enough stolen space for compressed buffer, disabling\n"); |
| 1056 | DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); |
| 1057 | } |
| 1058 | |
| 1059 | static void i915_setup_compression(struct drm_device *dev, int size) |
| 1060 | { |
| 1061 | struct drm_i915_private *dev_priv = dev->dev_private; |
Prarit Bhargava | 132b6aa | 2010-05-27 13:37:56 -0400 | [diff] [blame] | 1062 | struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb); |
Andrew Morton | 29bd0ae | 2009-11-17 14:08:52 -0800 | [diff] [blame] | 1063 | unsigned long cfb_base; |
| 1064 | unsigned long ll_base = 0; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1065 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1066 | compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0); |
| 1067 | if (compressed_fb) |
| 1068 | compressed_fb = drm_mm_get_block(compressed_fb, size, 4096); |
| 1069 | if (!compressed_fb) |
| 1070 | goto err; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1071 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1072 | cfb_base = i915_stolen_to_phys(dev, compressed_fb->start); |
| 1073 | if (!cfb_base) |
| 1074 | goto err_fb; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1075 | |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 1076 | if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) { |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1077 | compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen, |
| 1078 | 4096, 4096, 0); |
| 1079 | if (compressed_llb) |
| 1080 | compressed_llb = drm_mm_get_block(compressed_llb, |
| 1081 | 4096, 4096); |
| 1082 | if (!compressed_llb) |
| 1083 | goto err_fb; |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1084 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1085 | ll_base = i915_stolen_to_phys(dev, compressed_llb->start); |
| 1086 | if (!ll_base) |
| 1087 | goto err_llb; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1088 | } |
| 1089 | |
| 1090 | dev_priv->cfb_size = size; |
| 1091 | |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 1092 | intel_disable_fbc(dev); |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 1093 | dev_priv->compressed_fb = compressed_fb; |
Yuanhan Liu | 9c04f01 | 2010-12-15 15:42:32 +0800 | [diff] [blame] | 1094 | if (HAS_PCH_SPLIT(dev)) |
Zhao Yakui | b52eb4d | 2010-06-12 14:32:27 +0800 | [diff] [blame] | 1095 | I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); |
| 1096 | else if (IS_GM45(dev)) { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1097 | I915_WRITE(DPFC_CB_BASE, compressed_fb->start); |
| 1098 | } else { |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 1099 | I915_WRITE(FBC_CFB_BASE, cfb_base); |
| 1100 | I915_WRITE(FBC_LL_BASE, ll_base); |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 1101 | dev_priv->compressed_llb = compressed_llb; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1102 | } |
| 1103 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1104 | DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", |
| 1105 | cfb_base, ll_base, size >> 20); |
| 1106 | return; |
| 1107 | |
| 1108 | err_llb: |
| 1109 | drm_mm_put_block(compressed_llb); |
| 1110 | err_fb: |
| 1111 | drm_mm_put_block(compressed_fb); |
| 1112 | err: |
| 1113 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
| 1114 | i915_warn_stolen(dev); |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1115 | } |
| 1116 | |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 1117 | static void i915_cleanup_compression(struct drm_device *dev) |
| 1118 | { |
| 1119 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1120 | |
| 1121 | drm_mm_put_block(dev_priv->compressed_fb); |
Jesse Barnes | aebf0da | 2010-07-22 08:12:20 -0700 | [diff] [blame] | 1122 | if (dev_priv->compressed_llb) |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 1123 | drm_mm_put_block(dev_priv->compressed_llb); |
| 1124 | } |
| 1125 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1126 | /* true = enable decode, false = disable decoder */ |
| 1127 | static unsigned int i915_vga_set_decode(void *cookie, bool state) |
| 1128 | { |
| 1129 | struct drm_device *dev = cookie; |
| 1130 | |
| 1131 | intel_modeset_vga_set_state(dev, state); |
| 1132 | if (state) |
| 1133 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
| 1134 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1135 | else |
| 1136 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
| 1137 | } |
| 1138 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1139 | static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) |
| 1140 | { |
| 1141 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1142 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
| 1143 | if (state == VGA_SWITCHEROO_ON) { |
Dave Airlie | fbf8176 | 2010-06-01 09:09:06 +1000 | [diff] [blame] | 1144 | printk(KERN_INFO "i915: switched on\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1145 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1146 | /* i915 resume handler doesn't set to D0 */ |
| 1147 | pci_set_power_state(dev->pdev, PCI_D0); |
| 1148 | i915_resume(dev); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1149 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1150 | } else { |
| 1151 | printk(KERN_ERR "i915: switched off\n"); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1152 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1153 | i915_suspend(dev, pmm); |
Dave Airlie | 5bcf719 | 2010-12-07 09:20:40 +1000 | [diff] [blame] | 1154 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1155 | } |
| 1156 | } |
| 1157 | |
| 1158 | static bool i915_switcheroo_can_switch(struct pci_dev *pdev) |
| 1159 | { |
| 1160 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 1161 | bool can_switch; |
| 1162 | |
| 1163 | spin_lock(&dev->count_lock); |
| 1164 | can_switch = (dev->open_count == 0); |
| 1165 | spin_unlock(&dev->count_lock); |
| 1166 | return can_switch; |
| 1167 | } |
| 1168 | |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 1169 | static int i915_load_modeset_init(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1170 | { |
| 1171 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 1172 | unsigned long prealloc_size, gtt_size, mappable_size; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1173 | int ret = 0; |
| 1174 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 1175 | prealloc_size = dev_priv->mm.gtt->stolen_size; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 1176 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
| 1177 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 1178 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1179 | /* Basic memrange allocator for stolen space */ |
| 1180 | drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1181 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1182 | /* Let GEM Manage all of the aperture. |
Eric Anholt | 13f4c43 | 2009-05-12 15:27:36 -0700 | [diff] [blame] | 1183 | * |
| 1184 | * However, leave one page at the end still bound to the scratch page. |
| 1185 | * There are a number of places where the hardware apparently |
| 1186 | * prefetches past the end of the object, and we've seen multiple |
| 1187 | * hangs with the GPU head pointer stuck in a batchbuffer bound |
| 1188 | * at the last page of the aperture. One page should be enough to |
| 1189 | * keep any prefetching inside of the aperture. |
| 1190 | */ |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1191 | i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1192 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1193 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1194 | ret = i915_gem_init_ringbuffer(dev); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1195 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1196 | if (ret) |
Dave Airlie | b8da7de | 2009-06-02 16:50:35 +1000 | [diff] [blame] | 1197 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1198 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1199 | /* Try to set up FBC with a reasonable compressed buffer size */ |
Shaohua Li | 9216d44 | 2009-10-10 15:20:55 +0800 | [diff] [blame] | 1200 | if (I915_HAS_FBC(dev) && i915_powersave) { |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1201 | int cfb_size; |
| 1202 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1203 | /* Leave 1M for line length buffer & misc. */ |
| 1204 | |
| 1205 | /* Try to get a 32M buffer... */ |
| 1206 | if (prealloc_size > (36*1024*1024)) |
| 1207 | cfb_size = 32*1024*1024; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 1208 | else /* fall back to 7/8 of the stolen space */ |
| 1209 | cfb_size = prealloc_size * 7 / 8; |
| 1210 | i915_setup_compression(dev, cfb_size); |
| 1211 | } |
| 1212 | |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1213 | /* Allow hardware batchbuffers unless told otherwise. */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1214 | dev_priv->allow_batchbuffer = 1; |
| 1215 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 1216 | ret = intel_parse_bios(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1217 | if (ret) |
| 1218 | DRM_INFO("failed to find VBIOS tables\n"); |
| 1219 | |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 1220 | /* If we have > 1 VGA cards, then we need to arbitrate access |
| 1221 | * to the common VGA resources. |
| 1222 | * |
| 1223 | * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA), |
| 1224 | * then we do not take part in VGA arbitration and the |
| 1225 | * vga_client_register() fails with -ENODEV. |
| 1226 | */ |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1227 | ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); |
Chris Wilson | 934f992 | 2011-01-20 13:09:12 +0000 | [diff] [blame] | 1228 | if (ret && ret != -ENODEV) |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1229 | goto cleanup_ringbuffer; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1230 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 1231 | intel_register_dsm_handler(); |
| 1232 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1233 | ret = vga_switcheroo_register_client(dev->pdev, |
| 1234 | i915_switcheroo_set_state, |
Dave Airlie | 8d608aa | 2010-12-07 08:57:57 +1000 | [diff] [blame] | 1235 | NULL, |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1236 | i915_switcheroo_can_switch); |
| 1237 | if (ret) |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1238 | goto cleanup_vga_client; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1239 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 1240 | /* IIR "flip pending" bit means done if this bit is set */ |
| 1241 | if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) |
| 1242 | dev_priv->flip_pending_is_done = true; |
| 1243 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 1244 | intel_modeset_init(dev); |
| 1245 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1246 | ret = drm_irq_install(dev); |
| 1247 | if (ret) |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1248 | goto cleanup_vga_switcheroo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1249 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1250 | /* Always safe in the mode setting case. */ |
| 1251 | /* FIXME: do pre/post-mode set stuff in core KMS code */ |
| 1252 | dev->vblank_disable_allowed = 1; |
| 1253 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1254 | ret = intel_fbdev_init(dev); |
| 1255 | if (ret) |
| 1256 | goto cleanup_irq; |
| 1257 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 1258 | drm_kms_helper_poll_init(dev); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1259 | |
| 1260 | /* We're off and running w/KMS */ |
| 1261 | dev_priv->mm.suspended = 0; |
| 1262 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1263 | return 0; |
| 1264 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 1265 | cleanup_irq: |
| 1266 | drm_irq_uninstall(dev); |
| 1267 | cleanup_vga_switcheroo: |
| 1268 | vga_switcheroo_unregister_client(dev->pdev); |
| 1269 | cleanup_vga_client: |
| 1270 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
| 1271 | cleanup_ringbuffer: |
Eric Anholt | 2109953 | 2009-11-09 14:57:34 -0800 | [diff] [blame] | 1272 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1273 | i915_gem_cleanup_ringbuffer(dev); |
Eric Anholt | 2109953 | 2009-11-09 14:57:34 -0800 | [diff] [blame] | 1274 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1275 | out: |
| 1276 | return ret; |
| 1277 | } |
| 1278 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1279 | int i915_master_create(struct drm_device *dev, struct drm_master *master) |
| 1280 | { |
| 1281 | struct drm_i915_master_private *master_priv; |
| 1282 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1283 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1284 | if (!master_priv) |
| 1285 | return -ENOMEM; |
| 1286 | |
| 1287 | master->driver_priv = master_priv; |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
| 1291 | void i915_master_destroy(struct drm_device *dev, struct drm_master *master) |
| 1292 | { |
| 1293 | struct drm_i915_master_private *master_priv = master->driver_priv; |
| 1294 | |
| 1295 | if (!master_priv) |
| 1296 | return; |
| 1297 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1298 | kfree(master_priv); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1299 | |
| 1300 | master->driver_priv = NULL; |
| 1301 | } |
| 1302 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1303 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1304 | { |
| 1305 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1306 | u32 tmp; |
| 1307 | |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1308 | tmp = I915_READ(CLKCFG); |
| 1309 | |
| 1310 | switch (tmp & CLKCFG_FSB_MASK) { |
| 1311 | case CLKCFG_FSB_533: |
| 1312 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 1313 | break; |
| 1314 | case CLKCFG_FSB_800: |
| 1315 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 1316 | break; |
| 1317 | case CLKCFG_FSB_667: |
| 1318 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 1319 | break; |
| 1320 | case CLKCFG_FSB_400: |
| 1321 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 1322 | break; |
| 1323 | } |
| 1324 | |
| 1325 | switch (tmp & CLKCFG_MEM_MASK) { |
| 1326 | case CLKCFG_MEM_533: |
| 1327 | dev_priv->mem_freq = 533; |
| 1328 | break; |
| 1329 | case CLKCFG_MEM_667: |
| 1330 | dev_priv->mem_freq = 667; |
| 1331 | break; |
| 1332 | case CLKCFG_MEM_800: |
| 1333 | dev_priv->mem_freq = 800; |
| 1334 | break; |
| 1335 | } |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 1336 | |
| 1337 | /* detect pineview DDR3 setting */ |
| 1338 | tmp = I915_READ(CSHRDDR3CTL); |
| 1339 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1340 | } |
| 1341 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1342 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 1343 | { |
| 1344 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1345 | u16 ddrpll, csipll; |
| 1346 | |
| 1347 | ddrpll = I915_READ16(DDRMPLL1); |
| 1348 | csipll = I915_READ16(CSIPLL0); |
| 1349 | |
| 1350 | switch (ddrpll & 0xff) { |
| 1351 | case 0xc: |
| 1352 | dev_priv->mem_freq = 800; |
| 1353 | break; |
| 1354 | case 0x10: |
| 1355 | dev_priv->mem_freq = 1066; |
| 1356 | break; |
| 1357 | case 0x14: |
| 1358 | dev_priv->mem_freq = 1333; |
| 1359 | break; |
| 1360 | case 0x18: |
| 1361 | dev_priv->mem_freq = 1600; |
| 1362 | break; |
| 1363 | default: |
| 1364 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 1365 | ddrpll & 0xff); |
| 1366 | dev_priv->mem_freq = 0; |
| 1367 | break; |
| 1368 | } |
| 1369 | |
| 1370 | dev_priv->r_t = dev_priv->mem_freq; |
| 1371 | |
| 1372 | switch (csipll & 0x3ff) { |
| 1373 | case 0x00c: |
| 1374 | dev_priv->fsb_freq = 3200; |
| 1375 | break; |
| 1376 | case 0x00e: |
| 1377 | dev_priv->fsb_freq = 3733; |
| 1378 | break; |
| 1379 | case 0x010: |
| 1380 | dev_priv->fsb_freq = 4266; |
| 1381 | break; |
| 1382 | case 0x012: |
| 1383 | dev_priv->fsb_freq = 4800; |
| 1384 | break; |
| 1385 | case 0x014: |
| 1386 | dev_priv->fsb_freq = 5333; |
| 1387 | break; |
| 1388 | case 0x016: |
| 1389 | dev_priv->fsb_freq = 5866; |
| 1390 | break; |
| 1391 | case 0x018: |
| 1392 | dev_priv->fsb_freq = 6400; |
| 1393 | break; |
| 1394 | default: |
| 1395 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 1396 | csipll & 0x3ff); |
| 1397 | dev_priv->fsb_freq = 0; |
| 1398 | break; |
| 1399 | } |
| 1400 | |
| 1401 | if (dev_priv->fsb_freq == 3200) { |
| 1402 | dev_priv->c_m = 0; |
| 1403 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
| 1404 | dev_priv->c_m = 1; |
| 1405 | } else { |
| 1406 | dev_priv->c_m = 2; |
| 1407 | } |
| 1408 | } |
| 1409 | |
Chris Wilson | faa60c4 | 2010-11-23 13:50:14 +0000 | [diff] [blame] | 1410 | static const struct cparams { |
| 1411 | u16 i; |
| 1412 | u16 t; |
| 1413 | u16 m; |
| 1414 | u16 c; |
| 1415 | } cparams[] = { |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1416 | { 1, 1333, 301, 28664 }, |
| 1417 | { 1, 1066, 294, 24460 }, |
| 1418 | { 1, 800, 294, 25192 }, |
| 1419 | { 0, 1333, 276, 27605 }, |
| 1420 | { 0, 1066, 276, 27605 }, |
| 1421 | { 0, 800, 231, 23784 }, |
| 1422 | }; |
| 1423 | |
| 1424 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 1425 | { |
| 1426 | u64 total_count, diff, ret; |
| 1427 | u32 count1, count2, count3, m = 0, c = 0; |
| 1428 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 1429 | int i; |
| 1430 | |
| 1431 | diff1 = now - dev_priv->last_time1; |
| 1432 | |
| 1433 | count1 = I915_READ(DMIEC); |
| 1434 | count2 = I915_READ(DDREC); |
| 1435 | count3 = I915_READ(CSIEC); |
| 1436 | |
| 1437 | total_count = count1 + count2 + count3; |
| 1438 | |
| 1439 | /* FIXME: handle per-counter overflow */ |
| 1440 | if (total_count < dev_priv->last_count1) { |
| 1441 | diff = ~0UL - dev_priv->last_count1; |
| 1442 | diff += total_count; |
| 1443 | } else { |
| 1444 | diff = total_count - dev_priv->last_count1; |
| 1445 | } |
| 1446 | |
| 1447 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
| 1448 | if (cparams[i].i == dev_priv->c_m && |
| 1449 | cparams[i].t == dev_priv->r_t) { |
| 1450 | m = cparams[i].m; |
| 1451 | c = cparams[i].c; |
| 1452 | break; |
| 1453 | } |
| 1454 | } |
| 1455 | |
Jesse Barnes | d270ae3 | 2010-09-27 10:35:44 -0700 | [diff] [blame] | 1456 | diff = div_u64(diff, diff1); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1457 | ret = ((m * diff) + c); |
Jesse Barnes | d270ae3 | 2010-09-27 10:35:44 -0700 | [diff] [blame] | 1458 | ret = div_u64(ret, 10); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1459 | |
| 1460 | dev_priv->last_count1 = total_count; |
| 1461 | dev_priv->last_time1 = now; |
| 1462 | |
| 1463 | return ret; |
| 1464 | } |
| 1465 | |
| 1466 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 1467 | { |
| 1468 | unsigned long m, x, b; |
| 1469 | u32 tsfs; |
| 1470 | |
| 1471 | tsfs = I915_READ(TSFS); |
| 1472 | |
| 1473 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 1474 | x = I915_READ8(TR1); |
| 1475 | |
| 1476 | b = tsfs & TSFS_INTR_MASK; |
| 1477 | |
| 1478 | return ((m * x) / 127) - b; |
| 1479 | } |
| 1480 | |
Chris Wilson | faa60c4 | 2010-11-23 13:50:14 +0000 | [diff] [blame] | 1481 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1482 | { |
Chris Wilson | faa60c4 | 2010-11-23 13:50:14 +0000 | [diff] [blame] | 1483 | static const struct v_table { |
| 1484 | u16 vd; /* in .1 mil */ |
| 1485 | u16 vm; /* in .1 mil */ |
| 1486 | } v_table[] = { |
| 1487 | { 0, 0, }, |
| 1488 | { 375, 0, }, |
| 1489 | { 500, 0, }, |
| 1490 | { 625, 0, }, |
| 1491 | { 750, 0, }, |
| 1492 | { 875, 0, }, |
| 1493 | { 1000, 0, }, |
| 1494 | { 1125, 0, }, |
| 1495 | { 4125, 3000, }, |
| 1496 | { 4125, 3000, }, |
| 1497 | { 4125, 3000, }, |
| 1498 | { 4125, 3000, }, |
| 1499 | { 4125, 3000, }, |
| 1500 | { 4125, 3000, }, |
| 1501 | { 4125, 3000, }, |
| 1502 | { 4125, 3000, }, |
| 1503 | { 4125, 3000, }, |
| 1504 | { 4125, 3000, }, |
| 1505 | { 4125, 3000, }, |
| 1506 | { 4125, 3000, }, |
| 1507 | { 4125, 3000, }, |
| 1508 | { 4125, 3000, }, |
| 1509 | { 4125, 3000, }, |
| 1510 | { 4125, 3000, }, |
| 1511 | { 4125, 3000, }, |
| 1512 | { 4125, 3000, }, |
| 1513 | { 4125, 3000, }, |
| 1514 | { 4125, 3000, }, |
| 1515 | { 4125, 3000, }, |
| 1516 | { 4125, 3000, }, |
| 1517 | { 4125, 3000, }, |
| 1518 | { 4125, 3000, }, |
| 1519 | { 4250, 3125, }, |
| 1520 | { 4375, 3250, }, |
| 1521 | { 4500, 3375, }, |
| 1522 | { 4625, 3500, }, |
| 1523 | { 4750, 3625, }, |
| 1524 | { 4875, 3750, }, |
| 1525 | { 5000, 3875, }, |
| 1526 | { 5125, 4000, }, |
| 1527 | { 5250, 4125, }, |
| 1528 | { 5375, 4250, }, |
| 1529 | { 5500, 4375, }, |
| 1530 | { 5625, 4500, }, |
| 1531 | { 5750, 4625, }, |
| 1532 | { 5875, 4750, }, |
| 1533 | { 6000, 4875, }, |
| 1534 | { 6125, 5000, }, |
| 1535 | { 6250, 5125, }, |
| 1536 | { 6375, 5250, }, |
| 1537 | { 6500, 5375, }, |
| 1538 | { 6625, 5500, }, |
| 1539 | { 6750, 5625, }, |
| 1540 | { 6875, 5750, }, |
| 1541 | { 7000, 5875, }, |
| 1542 | { 7125, 6000, }, |
| 1543 | { 7250, 6125, }, |
| 1544 | { 7375, 6250, }, |
| 1545 | { 7500, 6375, }, |
| 1546 | { 7625, 6500, }, |
| 1547 | { 7750, 6625, }, |
| 1548 | { 7875, 6750, }, |
| 1549 | { 8000, 6875, }, |
| 1550 | { 8125, 7000, }, |
| 1551 | { 8250, 7125, }, |
| 1552 | { 8375, 7250, }, |
| 1553 | { 8500, 7375, }, |
| 1554 | { 8625, 7500, }, |
| 1555 | { 8750, 7625, }, |
| 1556 | { 8875, 7750, }, |
| 1557 | { 9000, 7875, }, |
| 1558 | { 9125, 8000, }, |
| 1559 | { 9250, 8125, }, |
| 1560 | { 9375, 8250, }, |
| 1561 | { 9500, 8375, }, |
| 1562 | { 9625, 8500, }, |
| 1563 | { 9750, 8625, }, |
| 1564 | { 9875, 8750, }, |
| 1565 | { 10000, 8875, }, |
| 1566 | { 10125, 9000, }, |
| 1567 | { 10250, 9125, }, |
| 1568 | { 10375, 9250, }, |
| 1569 | { 10500, 9375, }, |
| 1570 | { 10625, 9500, }, |
| 1571 | { 10750, 9625, }, |
| 1572 | { 10875, 9750, }, |
| 1573 | { 11000, 9875, }, |
| 1574 | { 11125, 10000, }, |
| 1575 | { 11250, 10125, }, |
| 1576 | { 11375, 10250, }, |
| 1577 | { 11500, 10375, }, |
| 1578 | { 11625, 10500, }, |
| 1579 | { 11750, 10625, }, |
| 1580 | { 11875, 10750, }, |
| 1581 | { 12000, 10875, }, |
| 1582 | { 12125, 11000, }, |
| 1583 | { 12250, 11125, }, |
| 1584 | { 12375, 11250, }, |
| 1585 | { 12500, 11375, }, |
| 1586 | { 12625, 11500, }, |
| 1587 | { 12750, 11625, }, |
| 1588 | { 12875, 11750, }, |
| 1589 | { 13000, 11875, }, |
| 1590 | { 13125, 12000, }, |
| 1591 | { 13250, 12125, }, |
| 1592 | { 13375, 12250, }, |
| 1593 | { 13500, 12375, }, |
| 1594 | { 13625, 12500, }, |
| 1595 | { 13750, 12625, }, |
| 1596 | { 13875, 12750, }, |
| 1597 | { 14000, 12875, }, |
| 1598 | { 14125, 13000, }, |
| 1599 | { 14250, 13125, }, |
| 1600 | { 14375, 13250, }, |
| 1601 | { 14500, 13375, }, |
| 1602 | { 14625, 13500, }, |
| 1603 | { 14750, 13625, }, |
| 1604 | { 14875, 13750, }, |
| 1605 | { 15000, 13875, }, |
| 1606 | { 15125, 14000, }, |
| 1607 | { 15250, 14125, }, |
| 1608 | { 15375, 14250, }, |
| 1609 | { 15500, 14375, }, |
| 1610 | { 15625, 14500, }, |
| 1611 | { 15750, 14625, }, |
| 1612 | { 15875, 14750, }, |
| 1613 | { 16000, 14875, }, |
| 1614 | { 16125, 15000, }, |
| 1615 | }; |
| 1616 | if (dev_priv->info->is_mobile) |
| 1617 | return v_table[pxvid].vm; |
| 1618 | else |
| 1619 | return v_table[pxvid].vd; |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1620 | } |
| 1621 | |
| 1622 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 1623 | { |
| 1624 | struct timespec now, diff1; |
| 1625 | u64 diff; |
| 1626 | unsigned long diffms; |
| 1627 | u32 count; |
| 1628 | |
| 1629 | getrawmonotonic(&now); |
| 1630 | diff1 = timespec_sub(now, dev_priv->last_time2); |
| 1631 | |
| 1632 | /* Don't divide by 0 */ |
| 1633 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
| 1634 | if (!diffms) |
| 1635 | return; |
| 1636 | |
| 1637 | count = I915_READ(GFXEC); |
| 1638 | |
| 1639 | if (count < dev_priv->last_count2) { |
| 1640 | diff = ~0UL - dev_priv->last_count2; |
| 1641 | diff += count; |
| 1642 | } else { |
| 1643 | diff = count - dev_priv->last_count2; |
| 1644 | } |
| 1645 | |
| 1646 | dev_priv->last_count2 = count; |
| 1647 | dev_priv->last_time2 = now; |
| 1648 | |
| 1649 | /* More magic constants... */ |
| 1650 | diff = diff * 1181; |
Jesse Barnes | d270ae3 | 2010-09-27 10:35:44 -0700 | [diff] [blame] | 1651 | diff = div_u64(diff, diffms * 10); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1652 | dev_priv->gfx_power = diff; |
| 1653 | } |
| 1654 | |
| 1655 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 1656 | { |
| 1657 | unsigned long t, corr, state1, corr2, state2; |
| 1658 | u32 pxvid, ext_v; |
| 1659 | |
| 1660 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); |
| 1661 | pxvid = (pxvid >> 24) & 0x7f; |
| 1662 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 1663 | |
| 1664 | state1 = ext_v; |
| 1665 | |
| 1666 | t = i915_mch_val(dev_priv); |
| 1667 | |
| 1668 | /* Revel in the empirically derived constants */ |
| 1669 | |
| 1670 | /* Correction factor in 1/100000 units */ |
| 1671 | if (t > 80) |
| 1672 | corr = ((t * 2349) + 135940); |
| 1673 | else if (t >= 50) |
| 1674 | corr = ((t * 964) + 29317); |
| 1675 | else /* < 50 */ |
| 1676 | corr = ((t * 301) + 1004); |
| 1677 | |
| 1678 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 1679 | corr /= 100000; |
| 1680 | corr2 = (corr * dev_priv->corr); |
| 1681 | |
| 1682 | state2 = (corr2 * state1) / 10000; |
| 1683 | state2 /= 100; /* convert to mW */ |
| 1684 | |
| 1685 | i915_update_gfx_val(dev_priv); |
| 1686 | |
| 1687 | return dev_priv->gfx_power + state2; |
| 1688 | } |
| 1689 | |
| 1690 | /* Global for IPS driver to get at the current i915 device */ |
| 1691 | static struct drm_i915_private *i915_mch_dev; |
| 1692 | /* |
| 1693 | * Lock protecting IPS related data structures |
| 1694 | * - i915_mch_dev |
| 1695 | * - dev_priv->max_delay |
| 1696 | * - dev_priv->min_delay |
| 1697 | * - dev_priv->fmax |
| 1698 | * - dev_priv->gpu_busy |
| 1699 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 1700 | static DEFINE_SPINLOCK(mchdev_lock); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1701 | |
| 1702 | /** |
| 1703 | * i915_read_mch_val - return value for IPS use |
| 1704 | * |
| 1705 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 1706 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 1707 | */ |
| 1708 | unsigned long i915_read_mch_val(void) |
| 1709 | { |
| 1710 | struct drm_i915_private *dev_priv; |
| 1711 | unsigned long chipset_val, graphics_val, ret = 0; |
| 1712 | |
| 1713 | spin_lock(&mchdev_lock); |
| 1714 | if (!i915_mch_dev) |
| 1715 | goto out_unlock; |
| 1716 | dev_priv = i915_mch_dev; |
| 1717 | |
| 1718 | chipset_val = i915_chipset_val(dev_priv); |
| 1719 | graphics_val = i915_gfx_val(dev_priv); |
| 1720 | |
| 1721 | ret = chipset_val + graphics_val; |
| 1722 | |
| 1723 | out_unlock: |
| 1724 | spin_unlock(&mchdev_lock); |
| 1725 | |
| 1726 | return ret; |
| 1727 | } |
| 1728 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 1729 | |
| 1730 | /** |
| 1731 | * i915_gpu_raise - raise GPU frequency limit |
| 1732 | * |
| 1733 | * Raise the limit; IPS indicates we have thermal headroom. |
| 1734 | */ |
| 1735 | bool i915_gpu_raise(void) |
| 1736 | { |
| 1737 | struct drm_i915_private *dev_priv; |
| 1738 | bool ret = true; |
| 1739 | |
| 1740 | spin_lock(&mchdev_lock); |
| 1741 | if (!i915_mch_dev) { |
| 1742 | ret = false; |
| 1743 | goto out_unlock; |
| 1744 | } |
| 1745 | dev_priv = i915_mch_dev; |
| 1746 | |
| 1747 | if (dev_priv->max_delay > dev_priv->fmax) |
| 1748 | dev_priv->max_delay--; |
| 1749 | |
| 1750 | out_unlock: |
| 1751 | spin_unlock(&mchdev_lock); |
| 1752 | |
| 1753 | return ret; |
| 1754 | } |
| 1755 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 1756 | |
| 1757 | /** |
| 1758 | * i915_gpu_lower - lower GPU frequency limit |
| 1759 | * |
| 1760 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 1761 | * frequency maximum. |
| 1762 | */ |
| 1763 | bool i915_gpu_lower(void) |
| 1764 | { |
| 1765 | struct drm_i915_private *dev_priv; |
| 1766 | bool ret = true; |
| 1767 | |
| 1768 | spin_lock(&mchdev_lock); |
| 1769 | if (!i915_mch_dev) { |
| 1770 | ret = false; |
| 1771 | goto out_unlock; |
| 1772 | } |
| 1773 | dev_priv = i915_mch_dev; |
| 1774 | |
| 1775 | if (dev_priv->max_delay < dev_priv->min_delay) |
| 1776 | dev_priv->max_delay++; |
| 1777 | |
| 1778 | out_unlock: |
| 1779 | spin_unlock(&mchdev_lock); |
| 1780 | |
| 1781 | return ret; |
| 1782 | } |
| 1783 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 1784 | |
| 1785 | /** |
| 1786 | * i915_gpu_busy - indicate GPU business to IPS |
| 1787 | * |
| 1788 | * Tell the IPS driver whether or not the GPU is busy. |
| 1789 | */ |
| 1790 | bool i915_gpu_busy(void) |
| 1791 | { |
| 1792 | struct drm_i915_private *dev_priv; |
| 1793 | bool ret = false; |
| 1794 | |
| 1795 | spin_lock(&mchdev_lock); |
| 1796 | if (!i915_mch_dev) |
| 1797 | goto out_unlock; |
| 1798 | dev_priv = i915_mch_dev; |
| 1799 | |
| 1800 | ret = dev_priv->busy; |
| 1801 | |
| 1802 | out_unlock: |
| 1803 | spin_unlock(&mchdev_lock); |
| 1804 | |
| 1805 | return ret; |
| 1806 | } |
| 1807 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 1808 | |
| 1809 | /** |
| 1810 | * i915_gpu_turbo_disable - disable graphics turbo |
| 1811 | * |
| 1812 | * Disable graphics turbo by resetting the max frequency and setting the |
| 1813 | * current frequency to the default. |
| 1814 | */ |
| 1815 | bool i915_gpu_turbo_disable(void) |
| 1816 | { |
| 1817 | struct drm_i915_private *dev_priv; |
| 1818 | bool ret = true; |
| 1819 | |
| 1820 | spin_lock(&mchdev_lock); |
| 1821 | if (!i915_mch_dev) { |
| 1822 | ret = false; |
| 1823 | goto out_unlock; |
| 1824 | } |
| 1825 | dev_priv = i915_mch_dev; |
| 1826 | |
| 1827 | dev_priv->max_delay = dev_priv->fstart; |
| 1828 | |
| 1829 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) |
| 1830 | ret = false; |
| 1831 | |
| 1832 | out_unlock: |
| 1833 | spin_unlock(&mchdev_lock); |
| 1834 | |
| 1835 | return ret; |
| 1836 | } |
| 1837 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 1838 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1839 | /** |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 1840 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 1841 | * IPS got loaded first. |
| 1842 | * |
| 1843 | * This awkward dance is so that neither module has to depend on the |
| 1844 | * other in order for IPS to do the appropriate communication of |
| 1845 | * GPU turbo limits to i915. |
| 1846 | */ |
| 1847 | static void |
| 1848 | ips_ping_for_i915_load(void) |
| 1849 | { |
| 1850 | void (*link)(void); |
| 1851 | |
| 1852 | link = symbol_get(ips_link_to_i915_driver); |
| 1853 | if (link) { |
| 1854 | link(); |
| 1855 | symbol_put(ips_link_to_i915_driver); |
| 1856 | } |
| 1857 | } |
| 1858 | |
| 1859 | /** |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1860 | * i915_driver_load - setup chip and create an initial config |
| 1861 | * @dev: DRM device |
| 1862 | * @flags: startup flags |
| 1863 | * |
| 1864 | * The driver load routine has to do several things: |
| 1865 | * - drive output discovery via intel_modeset_init() |
| 1866 | * - initialize the memory manager |
| 1867 | * - allocate initial config memory |
| 1868 | * - setup the DRM framebuffer with the allocated memory |
| 1869 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1870 | int i915_driver_load(struct drm_device *dev, unsigned long flags) |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1871 | { |
Luca Tettamanti | ea059a1 | 2010-04-08 21:41:59 +0200 | [diff] [blame] | 1872 | struct drm_i915_private *dev_priv; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1873 | int ret = 0, mmio_bar; |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 1874 | uint32_t agp_size; |
| 1875 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1876 | /* i915 has 4 more counters */ |
| 1877 | dev->counters += 4; |
| 1878 | dev->types[6] = _DRM_STAT_IRQ; |
| 1879 | dev->types[7] = _DRM_STAT_PRIMARY; |
| 1880 | dev->types[8] = _DRM_STAT_SECONDARY; |
| 1881 | dev->types[9] = _DRM_STAT_DMA; |
| 1882 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1883 | dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1884 | if (dev_priv == NULL) |
| 1885 | return -ENOMEM; |
| 1886 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1887 | dev->dev_private = (void *)dev_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1888 | dev_priv->dev = dev; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 1889 | dev_priv->info = (struct intel_device_info *) flags; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1890 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 1891 | if (i915_get_bridge_dev(dev)) { |
| 1892 | ret = -EIO; |
| 1893 | goto free_priv; |
| 1894 | } |
| 1895 | |
Daniel Vetter | 9f82d23 | 2010-08-30 21:25:23 +0200 | [diff] [blame] | 1896 | /* overlay on gen2 is broken and can't address above 1G */ |
| 1897 | if (IS_GEN2(dev)) |
| 1898 | dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
| 1899 | |
Chris Wilson | b4ce0f8 | 2010-10-28 11:26:06 +0100 | [diff] [blame] | 1900 | mmio_bar = IS_GEN2(dev) ? 1 : 0; |
| 1901 | dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); |
| 1902 | if (!dev_priv->regs) { |
| 1903 | DRM_ERROR("failed to map registers\n"); |
| 1904 | ret = -EIO; |
| 1905 | goto put_bridge; |
| 1906 | } |
| 1907 | |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1908 | dev_priv->mm.gtt = intel_gtt_get(); |
| 1909 | if (!dev_priv->mm.gtt) { |
| 1910 | DRM_ERROR("Failed to initialize GTT\n"); |
| 1911 | ret = -ENODEV; |
| 1912 | goto out_iomapfree; |
| 1913 | } |
| 1914 | |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1915 | agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
| 1916 | |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1917 | dev_priv->mm.gtt_mapping = |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1918 | io_mapping_create_wc(dev->agp->base, agp_size); |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 1919 | if (dev_priv->mm.gtt_mapping == NULL) { |
| 1920 | ret = -EIO; |
| 1921 | goto out_rmmap; |
| 1922 | } |
| 1923 | |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1924 | /* Set up a WC MTRR for non-PAT systems. This is more common than |
| 1925 | * one would think, because the kernel disables PAT on first |
| 1926 | * generation Core chips because WC PAT gets overridden by a UC |
| 1927 | * MTRR if present. Even if a UC MTRR isn't present. |
| 1928 | */ |
| 1929 | dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base, |
Chris Wilson | 71e9339 | 2010-10-27 18:46:52 +0100 | [diff] [blame] | 1930 | agp_size, |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1931 | MTRR_TYPE_WRCOMB, 1); |
| 1932 | if (dev_priv->mm.gtt_mtrr < 0) { |
Eric Anholt | 040aefa | 2009-03-10 12:31:12 -0700 | [diff] [blame] | 1933 | DRM_INFO("MTRR allocation failed. Graphics " |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 1934 | "performance may suffer.\n"); |
| 1935 | } |
| 1936 | |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1937 | /* The i915 workqueue is primarily used for batched retirement of |
| 1938 | * requests (and thus managing bo) once the task has been completed |
| 1939 | * by the GPU. i915_gem_retire_requests() is called directly when we |
| 1940 | * need high-priority retirement, such as waiting for an explicit |
| 1941 | * bo. |
| 1942 | * |
| 1943 | * It is also used for periodic low-priority events, such as |
Eric Anholt | df9c204 | 2010-11-18 09:31:12 +0800 | [diff] [blame] | 1944 | * idle-timers and recording error state. |
Chris Wilson | e642abb | 2010-09-09 12:46:34 +0100 | [diff] [blame] | 1945 | * |
| 1946 | * All tasks on the workqueue are expected to acquire the dev mutex |
| 1947 | * so there is no point in running more than one instance of the |
| 1948 | * workqueue at any time: max_active = 1 and NON_REENTRANT. |
| 1949 | */ |
| 1950 | dev_priv->wq = alloc_workqueue("i915", |
| 1951 | WQ_UNBOUND | WQ_NON_REENTRANT, |
| 1952 | 1); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1953 | if (dev_priv->wq == NULL) { |
| 1954 | DRM_ERROR("Failed to create our workqueue.\n"); |
| 1955 | ret = -ENOMEM; |
| 1956 | goto out_iomapfree; |
| 1957 | } |
| 1958 | |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 1959 | /* enable GEM by default */ |
| 1960 | dev_priv->has_gem = 1; |
Dave Airlie | ac5c4e7 | 2008-12-19 15:38:34 +1000 | [diff] [blame] | 1961 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1962 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
Jesse Barnes | 42c2798 | 2009-05-05 13:13:16 -0700 | [diff] [blame] | 1963 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 1964 | if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { |
Jesse Barnes | 42c2798 | 2009-05-05 13:13:16 -0700 | [diff] [blame] | 1965 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1966 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
Jesse Barnes | 42c2798 | 2009-05-05 13:13:16 -0700 | [diff] [blame] | 1967 | } |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 1968 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1969 | /* Try to make sure MCHBAR is enabled before poking at it */ |
| 1970 | intel_setup_mchbar(dev); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1971 | intel_setup_gmbus(dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 1972 | intel_opregion_setup(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1973 | |
Bryan Freed | 6d139a8 | 2010-10-14 09:14:51 +0100 | [diff] [blame] | 1974 | /* Make sure the bios did its job and set up vital registers */ |
| 1975 | intel_setup_bios(dev); |
| 1976 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1977 | i915_gem_load(dev); |
| 1978 | |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 1979 | /* Init HWS */ |
| 1980 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1981 | ret = i915_init_phys_hws(dev); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 1982 | if (ret) |
| 1983 | goto out_gem_unload; |
Keith Packard | 398c9cb | 2008-07-30 13:03:43 -0700 | [diff] [blame] | 1984 | } |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1985 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1986 | if (IS_PINEVIEW(dev)) |
| 1987 | i915_pineview_get_mem_freq(dev); |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 1988 | else if (IS_GEN5(dev)) |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1989 | i915_ironlake_get_mem_freq(dev); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 1990 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 1991 | /* On the 945G/GM, the chipset reports the MSI capability on the |
| 1992 | * integrated graphics even though the support isn't actually there |
| 1993 | * according to the published specs. It doesn't appear to function |
| 1994 | * correctly in testing on 945G. |
| 1995 | * This may be a side effect of MSI having been made available for PEG |
| 1996 | * and the registers being closely associated. |
Keith Packard | d1ed629 | 2008-10-17 00:44:42 -0700 | [diff] [blame] | 1997 | * |
| 1998 | * According to chipset errata, on the 965GM, MSI interrupts may |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 1999 | * be lost or delayed, but we use them anyways to avoid |
| 2000 | * stuck interrupts on some machines. |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 2001 | */ |
Keith Packard | b60678a | 2008-12-08 11:12:28 -0800 | [diff] [blame] | 2002 | if (!IS_I945G(dev) && !IS_I945GM(dev)) |
Eric Anholt | d3e74d0 | 2008-11-03 14:46:17 -0800 | [diff] [blame] | 2003 | pci_enable_msi(dev->pdev); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 2004 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2005 | spin_lock_init(&dev_priv->irq_lock); |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 2006 | spin_lock_init(&dev_priv->error_lock); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 2007 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame^] | 2008 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
| 2009 | dev_priv->num_pipe = 2; |
| 2010 | else |
| 2011 | dev_priv->num_pipe = 1; |
| 2012 | |
| 2013 | ret = drm_vblank_init(dev, dev_priv->num_pipe); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 2014 | if (ret) |
| 2015 | goto out_gem_unload; |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 2016 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2017 | /* Start out suspended */ |
| 2018 | dev_priv->mm.suspended = 1; |
| 2019 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 2020 | intel_detect_pch(dev); |
| 2021 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2022 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 2023 | ret = i915_load_modeset_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2024 | if (ret < 0) { |
| 2025 | DRM_ERROR("failed to init modeset\n"); |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 2026 | goto out_gem_unload; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2027 | } |
| 2028 | } |
| 2029 | |
Matthew Garrett | 74a365b | 2009-03-19 21:35:39 +0000 | [diff] [blame] | 2030 | /* Must be done after probing outputs */ |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2031 | intel_opregion_init(dev); |
| 2032 | acpi_video_register(); |
Matthew Garrett | 74a365b | 2009-03-19 21:35:39 +0000 | [diff] [blame] | 2033 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2034 | setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
| 2035 | (unsigned long) dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2036 | |
| 2037 | spin_lock(&mchdev_lock); |
| 2038 | i915_mch_dev = dev_priv; |
| 2039 | dev_priv->mchdev_lock = &mchdev_lock; |
| 2040 | spin_unlock(&mchdev_lock); |
| 2041 | |
Eric Anholt | 63ee41d | 2010-12-20 18:40:06 -0800 | [diff] [blame] | 2042 | ips_ping_for_i915_load(); |
| 2043 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2044 | return 0; |
| 2045 | |
Chris Wilson | 56e2ea3 | 2010-11-08 17:10:29 +0000 | [diff] [blame] | 2046 | out_gem_unload: |
| 2047 | if (dev->pdev->msi_enabled) |
| 2048 | pci_disable_msi(dev->pdev); |
| 2049 | |
| 2050 | intel_teardown_gmbus(dev); |
| 2051 | intel_teardown_mchbar(dev); |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2052 | destroy_workqueue(dev_priv->wq); |
Venkatesh Pallipadi | 6644107 | 2009-02-24 17:35:11 -0800 | [diff] [blame] | 2053 | out_iomapfree: |
| 2054 | io_mapping_free(dev_priv->mm.gtt_mapping); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2055 | out_rmmap: |
Chris Wilson | 6dda569 | 2010-10-29 21:02:18 +0100 | [diff] [blame] | 2056 | pci_iounmap(dev->pdev, dev_priv->regs); |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 2057 | put_bridge: |
| 2058 | pci_dev_put(dev_priv->bridge_dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2059 | free_priv: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 2060 | kfree(dev_priv); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2061 | return ret; |
| 2062 | } |
| 2063 | |
| 2064 | int i915_driver_unload(struct drm_device *dev) |
| 2065 | { |
| 2066 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 2067 | int ret; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2068 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2069 | spin_lock(&mchdev_lock); |
| 2070 | i915_mch_dev = NULL; |
| 2071 | spin_unlock(&mchdev_lock); |
| 2072 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 2073 | if (dev_priv->mm.inactive_shrinker.shrink) |
| 2074 | unregister_shrinker(&dev_priv->mm.inactive_shrinker); |
| 2075 | |
Daniel Vetter | c911fc1 | 2010-08-20 21:23:20 +0200 | [diff] [blame] | 2076 | mutex_lock(&dev->struct_mutex); |
| 2077 | ret = i915_gpu_idle(dev); |
| 2078 | if (ret) |
| 2079 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
| 2080 | mutex_unlock(&dev->struct_mutex); |
| 2081 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2082 | /* Cancel the retire work handler, which should be idle now. */ |
| 2083 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 2084 | |
Eric Anholt | ab657db1 | 2009-01-23 12:57:47 -0800 | [diff] [blame] | 2085 | io_mapping_free(dev_priv->mm.gtt_mapping); |
| 2086 | if (dev_priv->mm.gtt_mtrr >= 0) { |
| 2087 | mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, |
| 2088 | dev->agp->agp_info.aper_size * 1024 * 1024); |
| 2089 | dev_priv->mm.gtt_mtrr = -1; |
| 2090 | } |
| 2091 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2092 | acpi_video_unregister(); |
| 2093 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2094 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 7b4f399 | 2010-10-04 15:33:04 +0100 | [diff] [blame] | 2095 | intel_fbdev_fini(dev); |
Jesse Barnes | 3d8620c | 2010-03-26 11:07:21 -0700 | [diff] [blame] | 2096 | intel_modeset_cleanup(dev); |
| 2097 | |
Zhao Yakui | 6363ee6 | 2009-11-24 09:48:44 +0800 | [diff] [blame] | 2098 | /* |
| 2099 | * free the memory space allocated for the child device |
| 2100 | * config parsed from VBT |
| 2101 | */ |
| 2102 | if (dev_priv->child_dev && dev_priv->child_dev_num) { |
| 2103 | kfree(dev_priv->child_dev); |
| 2104 | dev_priv->child_dev = NULL; |
| 2105 | dev_priv->child_dev_num = 0; |
| 2106 | } |
Daniel Vetter | 6c0d9350 | 2010-08-20 18:26:46 +0200 | [diff] [blame] | 2107 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 2108 | vga_switcheroo_unregister_client(dev->pdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2109 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2110 | } |
| 2111 | |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 2112 | /* Free error state after interrupts are fully disabled. */ |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 2113 | del_timer_sync(&dev_priv->hangcheck_timer); |
| 2114 | cancel_work_sync(&dev_priv->error_work); |
Daniel Vetter | a8b4899 | 2010-08-20 21:25:11 +0200 | [diff] [blame] | 2115 | i915_destroy_error_state(dev); |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 2116 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 2117 | if (dev->pdev->msi_enabled) |
| 2118 | pci_disable_msi(dev->pdev); |
| 2119 | |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2120 | intel_opregion_fini(dev); |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 2121 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2122 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 2123 | /* Flush any outstanding unpin_work. */ |
| 2124 | flush_workqueue(dev_priv->wq); |
| 2125 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2126 | i915_gem_free_all_phys_object(dev); |
| 2127 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2128 | mutex_lock(&dev->struct_mutex); |
| 2129 | i915_gem_cleanup_ringbuffer(dev); |
| 2130 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 20bf377 | 2010-04-21 11:39:22 -0700 | [diff] [blame] | 2131 | if (I915_HAS_FBC(dev) && i915_powersave) |
| 2132 | i915_cleanup_compression(dev); |
Chris Wilson | fe669bf | 2010-11-23 12:09:30 +0000 | [diff] [blame] | 2133 | drm_mm_takedown(&dev_priv->mm.stolen); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 2134 | |
| 2135 | intel_cleanup_overlay(dev); |
Keith Packard | c2873e9 | 2010-10-07 09:20:12 +0100 | [diff] [blame] | 2136 | |
| 2137 | if (!I915_NEED_GFX_HWS(dev)) |
| 2138 | i915_free_hws(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2139 | } |
| 2140 | |
Daniel Vetter | 701394c | 2010-10-10 18:54:08 +0100 | [diff] [blame] | 2141 | if (dev_priv->regs != NULL) |
Chris Wilson | 6dda569 | 2010-10-29 21:02:18 +0100 | [diff] [blame] | 2142 | pci_iounmap(dev->pdev, dev_priv->regs); |
Daniel Vetter | 701394c | 2010-10-10 18:54:08 +0100 | [diff] [blame] | 2143 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2144 | intel_teardown_gmbus(dev); |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 2145 | intel_teardown_mchbar(dev); |
| 2146 | |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 2147 | destroy_workqueue(dev_priv->wq); |
| 2148 | |
Dave Airlie | ec2a4c3 | 2009-08-04 11:43:41 +1000 | [diff] [blame] | 2149 | pci_dev_put(dev_priv->bridge_dev); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 2150 | kfree(dev->dev_private); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2151 | |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 2152 | return 0; |
| 2153 | } |
| 2154 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2155 | int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2156 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2157 | struct drm_i915_file_private *file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2158 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2159 | DRM_DEBUG_DRIVER("\n"); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2160 | file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL); |
| 2161 | if (!file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2162 | return -ENOMEM; |
| 2163 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2164 | file->driver_priv = file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2165 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2166 | spin_lock_init(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2167 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2168 | |
| 2169 | return 0; |
| 2170 | } |
| 2171 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2172 | /** |
| 2173 | * i915_driver_lastclose - clean up after all DRM clients have exited |
| 2174 | * @dev: DRM device |
| 2175 | * |
| 2176 | * Take care of cleaning up after all DRM clients have exited. In the |
| 2177 | * mode setting case, we want to restore the kernel's initial mode (just |
| 2178 | * in case the last client left us in a bad state). |
| 2179 | * |
| 2180 | * Additionally, in the non-mode setting case, we'll tear down the AGP |
| 2181 | * and DMA structures, since the kernel won't be using them, and clea |
| 2182 | * up any GEM state. |
| 2183 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2184 | void i915_driver_lastclose(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2185 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2186 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2187 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2188 | if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 2189 | drm_fb_helper_restore(); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 2190 | vga_switcheroo_process_delayed_switch(); |
Dave Airlie | 144a75f | 2008-03-30 07:53:58 +1000 | [diff] [blame] | 2191 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2192 | } |
Dave Airlie | 144a75f | 2008-03-30 07:53:58 +1000 | [diff] [blame] | 2193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2194 | i915_gem_lastclose(dev); |
| 2195 | |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2196 | if (dev_priv->agp_heap) |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2197 | i915_mem_takedown(&(dev_priv->agp_heap)); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2198 | |
Dave Airlie | b5e89ed | 2005-09-25 14:28:13 +1000 | [diff] [blame] | 2199 | i915_dma_cleanup(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2200 | } |
| 2201 | |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 2202 | void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2203 | { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2204 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2205 | i915_gem_release(dev, file_priv); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2206 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 2207 | i915_mem_release(dev, file_priv, dev_priv->agp_heap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2208 | } |
| 2209 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2210 | void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2211 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2212 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2213 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2214 | kfree(file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2215 | } |
| 2216 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 2217 | struct drm_ioctl_desc i915_ioctls[] = { |
Dave Airlie | 1b2f148 | 2010-08-14 20:20:34 +1000 | [diff] [blame] | 2218 | DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 2219 | DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH), |
| 2220 | DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH), |
| 2221 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), |
| 2222 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), |
| 2223 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), |
| 2224 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), |
| 2225 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 2226 | DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH), |
| 2227 | DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH), |
| 2228 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 2229 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), |
| 2230 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 2231 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 2232 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), |
| 2233 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), |
| 2234 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
| 2235 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 2236 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), |
| 2237 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), |
| 2238 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 2239 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 2240 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| 2241 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), |
| 2242 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 2243 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), |
| 2244 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), |
| 2245 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), |
| 2246 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), |
| 2247 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), |
| 2248 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), |
| 2249 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), |
| 2250 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), |
| 2251 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), |
| 2252 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), |
| 2253 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), |
| 2254 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), |
| 2255 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), |
| 2256 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
| 2257 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), |
Dave Airlie | c94f702 | 2005-07-07 21:03:38 +1000 | [diff] [blame] | 2258 | }; |
| 2259 | |
| 2260 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 2261 | |
| 2262 | /** |
| 2263 | * Determine if the device really is AGP or not. |
| 2264 | * |
| 2265 | * All Intel graphics chipsets are treated as AGP, even if they are really |
| 2266 | * PCI-e. |
| 2267 | * |
| 2268 | * \param dev The device to be tested. |
| 2269 | * |
| 2270 | * \returns |
| 2271 | * A value of 1 is always retured to indictate every i9x5 is AGP. |
| 2272 | */ |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2273 | int i915_driver_device_is_agp(struct drm_device * dev) |
Dave Airlie | cda1738 | 2005-07-10 17:31:26 +1000 | [diff] [blame] | 2274 | { |
| 2275 | return 1; |
| 2276 | } |