John Crispin | e316cb2 | 2012-05-20 00:33:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/pinctrl/pinmux-falcon.c |
| 3 | * based on linux/drivers/pinctrl/pinmux-pxa910.c |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published |
| 7 | * by the Free Software Foundation. |
| 8 | * |
| 9 | * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> |
| 10 | * Copyright (C) 2012 John Crispin <blogic@openwrt.org> |
| 11 | */ |
| 12 | |
| 13 | #include <linux/gpio.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <linux/export.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_platform.h> |
| 21 | #include <linux/of_address.h> |
| 22 | #include <linux/of_gpio.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | |
| 25 | #include "pinctrl-lantiq.h" |
| 26 | |
| 27 | #include <lantiq_soc.h> |
| 28 | |
| 29 | /* Multiplexer Control Register */ |
| 30 | #define LTQ_PADC_MUX(x) (x * 0x4) |
| 31 | /* Pull Up Enable Register */ |
| 32 | #define LTQ_PADC_PUEN 0x80 |
| 33 | /* Pull Down Enable Register */ |
| 34 | #define LTQ_PADC_PDEN 0x84 |
| 35 | /* Slew Rate Control Register */ |
| 36 | #define LTQ_PADC_SRC 0x88 |
| 37 | /* Drive Current Control Register */ |
| 38 | #define LTQ_PADC_DCC 0x8C |
| 39 | /* Pad Control Availability Register */ |
| 40 | #define LTQ_PADC_AVAIL 0xF0 |
| 41 | |
| 42 | #define pad_r32(p, reg) ltq_r32(p + reg) |
| 43 | #define pad_w32(p, val, reg) ltq_w32(val, p + reg) |
| 44 | #define pad_w32_mask(c, clear, set, reg) \ |
| 45 | pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg) |
| 46 | |
| 47 | #define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) |
| 48 | |
| 49 | #define PORTS 5 |
| 50 | #define PINS 32 |
| 51 | #define PORT(x) (x / PINS) |
| 52 | #define PORT_PIN(x) (x % PINS) |
| 53 | |
| 54 | #define MFP_FALCON(a, f0, f1, f2, f3) \ |
| 55 | { \ |
| 56 | .name = #a, \ |
| 57 | .pin = a, \ |
| 58 | .func = { \ |
| 59 | FALCON_MUX_##f0, \ |
| 60 | FALCON_MUX_##f1, \ |
| 61 | FALCON_MUX_##f2, \ |
| 62 | FALCON_MUX_##f3, \ |
| 63 | }, \ |
| 64 | } |
| 65 | |
| 66 | #define GRP_MUX(a, m, p) \ |
| 67 | { \ |
| 68 | .name = a, \ |
| 69 | .mux = FALCON_MUX_##m, \ |
| 70 | .pins = p, \ |
| 71 | .npins = ARRAY_SIZE(p), \ |
| 72 | } |
| 73 | |
| 74 | enum falcon_mux { |
| 75 | FALCON_MUX_GPIO = 0, |
| 76 | FALCON_MUX_RST, |
| 77 | FALCON_MUX_NTR, |
| 78 | FALCON_MUX_MDIO, |
| 79 | FALCON_MUX_LED, |
| 80 | FALCON_MUX_SPI, |
| 81 | FALCON_MUX_ASC, |
| 82 | FALCON_MUX_I2C, |
| 83 | FALCON_MUX_HOSTIF, |
| 84 | FALCON_MUX_SLIC, |
| 85 | FALCON_MUX_JTAG, |
| 86 | FALCON_MUX_PCM, |
| 87 | FALCON_MUX_MII, |
| 88 | FALCON_MUX_PHY, |
| 89 | FALCON_MUX_NONE = 0xffff, |
| 90 | }; |
| 91 | |
| 92 | static struct pinctrl_pin_desc falcon_pads[PORTS * PINS]; |
| 93 | static int pad_count[PORTS]; |
| 94 | |
| 95 | static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) |
| 96 | { |
| 97 | int base = bank * PINS; |
| 98 | int i; |
| 99 | |
| 100 | for (i = 0; i < len; i++) { |
| 101 | /* strlen("ioXYZ") + 1 = 6 */ |
| 102 | char *name = kzalloc(6, GFP_KERNEL); |
| 103 | snprintf(name, 6, "io%d", base + i); |
| 104 | d[i].number = base + i; |
| 105 | d[i].name = name; |
| 106 | } |
| 107 | pad_count[bank] = len; |
| 108 | } |
| 109 | |
| 110 | static struct ltq_mfp_pin falcon_mfp[] = { |
| 111 | /* pin f0 f1 f2 f3 */ |
| 112 | MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE), |
| 113 | MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE), |
| 114 | MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE), |
| 115 | MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE), |
| 116 | MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE), |
| 117 | MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE), |
| 118 | MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE), |
| 119 | MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE), |
| 120 | MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE), |
| 121 | MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE), |
| 122 | MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE), |
| 123 | MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE), |
| 124 | MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE), |
| 125 | MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE), |
| 126 | MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE), |
| 127 | MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE), |
| 128 | MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE), |
| 129 | MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE), |
| 130 | MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE), |
| 131 | MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE), |
| 132 | MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE), |
| 133 | MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE), |
| 134 | MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE), |
| 135 | MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE), |
| 136 | MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG), |
| 137 | MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE), |
| 138 | MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE), |
| 139 | MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC), |
| 140 | MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC), |
| 141 | MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE), |
| 142 | MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE), |
| 143 | MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE), |
| 144 | MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE), |
| 145 | MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE), |
| 146 | MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE), |
| 147 | MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE), |
| 148 | MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE), |
| 149 | MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE), |
| 150 | MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE), |
| 151 | MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE), |
| 152 | MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE), |
| 153 | MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE), |
| 154 | MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE), |
| 155 | MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE), |
| 156 | MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE), |
| 157 | MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE), |
| 158 | MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE), |
| 159 | MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE), |
| 160 | MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE), |
| 161 | MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE), |
| 162 | MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE), |
| 163 | MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE), |
| 164 | MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE), |
| 165 | MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE), |
| 166 | }; |
| 167 | |
| 168 | static const unsigned pins_por[] = {GPIO0}; |
| 169 | static const unsigned pins_ntr[] = {GPIO4}; |
| 170 | static const unsigned pins_ntr8k[] = {GPIO5}; |
| 171 | static const unsigned pins_hrst[] = {GPIO6}; |
| 172 | static const unsigned pins_mdio[] = {GPIO7, GPIO8}; |
| 173 | static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11, |
| 174 | GPIO12, GPIO13, GPIO14}; |
| 175 | static const unsigned pins_asc0[] = {GPIO32, GPIO33}; |
| 176 | static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36}; |
| 177 | static const unsigned pins_spi_cs0[] = {GPIO37}; |
| 178 | static const unsigned pins_spi_cs1[] = {GPIO38}; |
| 179 | static const unsigned pins_i2c[] = {GPIO39, GPIO40}; |
| 180 | static const unsigned pins_jtag[] = {GPIO41}; |
| 181 | static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45}; |
| 182 | static const unsigned pins_pcm[] = {GPIO44, GPIO45}; |
| 183 | static const unsigned pins_asc1[] = {GPIO44, GPIO45}; |
| 184 | |
| 185 | static struct ltq_pin_group falcon_grps[] = { |
| 186 | GRP_MUX("por", RST, pins_por), |
| 187 | GRP_MUX("ntr", NTR, pins_ntr), |
| 188 | GRP_MUX("ntr8k", NTR, pins_ntr8k), |
| 189 | GRP_MUX("hrst", RST, pins_hrst), |
| 190 | GRP_MUX("mdio", MDIO, pins_mdio), |
| 191 | GRP_MUX("bootled", LED, pins_bled), |
| 192 | GRP_MUX("asc0", ASC, pins_asc0), |
| 193 | GRP_MUX("spi", SPI, pins_spi), |
| 194 | GRP_MUX("spi cs0", SPI, pins_spi_cs0), |
| 195 | GRP_MUX("spi cs1", SPI, pins_spi_cs1), |
| 196 | GRP_MUX("i2c", I2C, pins_i2c), |
| 197 | GRP_MUX("jtag", JTAG, pins_jtag), |
| 198 | GRP_MUX("slic", SLIC, pins_slic), |
| 199 | GRP_MUX("pcm", PCM, pins_pcm), |
| 200 | GRP_MUX("asc1", ASC, pins_asc1), |
| 201 | }; |
| 202 | |
| 203 | static const char * const ltq_rst_grps[] = {"por", "hrst"}; |
| 204 | static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"}; |
| 205 | static const char * const ltq_mdio_grps[] = {"mdio"}; |
| 206 | static const char * const ltq_bled_grps[] = {"bootled"}; |
| 207 | static const char * const ltq_asc_grps[] = {"asc0", "asc1"}; |
| 208 | static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"}; |
| 209 | static const char * const ltq_i2c_grps[] = {"i2c"}; |
| 210 | static const char * const ltq_jtag_grps[] = {"jtag"}; |
| 211 | static const char * const ltq_slic_grps[] = {"slic"}; |
| 212 | static const char * const ltq_pcm_grps[] = {"pcm"}; |
| 213 | |
| 214 | static struct ltq_pmx_func falcon_funcs[] = { |
| 215 | {"rst", ARRAY_AND_SIZE(ltq_rst_grps)}, |
| 216 | {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)}, |
| 217 | {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)}, |
| 218 | {"led", ARRAY_AND_SIZE(ltq_bled_grps)}, |
| 219 | {"asc", ARRAY_AND_SIZE(ltq_asc_grps)}, |
| 220 | {"spi", ARRAY_AND_SIZE(ltq_spi_grps)}, |
| 221 | {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)}, |
| 222 | {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)}, |
| 223 | {"slic", ARRAY_AND_SIZE(ltq_slic_grps)}, |
| 224 | {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)}, |
| 225 | }; |
| 226 | |
| 227 | |
| 228 | |
| 229 | |
| 230 | /* --------- pinconf related code --------- */ |
| 231 | static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev, |
| 232 | unsigned group, unsigned long *config) |
| 233 | { |
| 234 | return -ENOTSUPP; |
| 235 | } |
| 236 | |
| 237 | static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev, |
| 238 | unsigned group, unsigned long config) |
| 239 | { |
| 240 | return -ENOTSUPP; |
| 241 | } |
| 242 | |
| 243 | static int falcon_pinconf_get(struct pinctrl_dev *pctrldev, |
| 244 | unsigned pin, unsigned long *config) |
| 245 | { |
| 246 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); |
| 247 | enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config); |
| 248 | void __iomem *mem = info->membase[PORT(pin)]; |
| 249 | |
| 250 | switch (param) { |
| 251 | case LTQ_PINCONF_PARAM_DRIVE_CURRENT: |
| 252 | *config = LTQ_PINCONF_PACK(param, |
| 253 | !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin))); |
| 254 | break; |
| 255 | |
| 256 | case LTQ_PINCONF_PARAM_SLEW_RATE: |
| 257 | *config = LTQ_PINCONF_PACK(param, |
| 258 | !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin))); |
| 259 | break; |
| 260 | |
| 261 | case LTQ_PINCONF_PARAM_PULL: |
| 262 | if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin))) |
| 263 | *config = LTQ_PINCONF_PACK(param, 1); |
| 264 | else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin))) |
| 265 | *config = LTQ_PINCONF_PACK(param, 2); |
| 266 | else |
| 267 | *config = LTQ_PINCONF_PACK(param, 0); |
| 268 | |
| 269 | break; |
| 270 | |
| 271 | default: |
| 272 | return -ENOTSUPP; |
| 273 | } |
| 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | static int falcon_pinconf_set(struct pinctrl_dev *pctrldev, |
| 279 | unsigned pin, unsigned long config) |
| 280 | { |
| 281 | enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config); |
| 282 | int arg = LTQ_PINCONF_UNPACK_ARG(config); |
| 283 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); |
| 284 | void __iomem *mem = info->membase[PORT(pin)]; |
| 285 | u32 reg; |
| 286 | |
| 287 | switch (param) { |
| 288 | case LTQ_PINCONF_PARAM_DRIVE_CURRENT: |
| 289 | reg = LTQ_PADC_DCC; |
| 290 | break; |
| 291 | |
| 292 | case LTQ_PINCONF_PARAM_SLEW_RATE: |
| 293 | reg = LTQ_PADC_SRC; |
| 294 | break; |
| 295 | |
| 296 | case LTQ_PINCONF_PARAM_PULL: |
| 297 | if (arg == 1) |
| 298 | reg = LTQ_PADC_PDEN; |
| 299 | else |
| 300 | reg = LTQ_PADC_PUEN; |
| 301 | break; |
| 302 | |
| 303 | default: |
| 304 | pr_err("%s: Invalid config param %04x\n", |
| 305 | pinctrl_dev_get_name(pctrldev), param); |
| 306 | return -ENOTSUPP; |
| 307 | } |
| 308 | |
| 309 | pad_w32(mem, BIT(PORT_PIN(pin)), reg); |
| 310 | if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) |
| 311 | return -ENOTSUPP; |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev, |
| 316 | struct seq_file *s, unsigned offset) |
| 317 | { |
| 318 | } |
| 319 | |
| 320 | static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, |
| 321 | struct seq_file *s, unsigned selector) |
| 322 | { |
| 323 | } |
| 324 | |
Axel Lin | 6bb0700 | 2012-11-07 13:37:08 +0800 | [diff] [blame] | 325 | static struct pinconf_ops falcon_pinconf_ops = { |
John Crispin | e316cb2 | 2012-05-20 00:33:56 +0200 | [diff] [blame] | 326 | .pin_config_get = falcon_pinconf_get, |
| 327 | .pin_config_set = falcon_pinconf_set, |
| 328 | .pin_config_group_get = falcon_pinconf_group_get, |
| 329 | .pin_config_group_set = falcon_pinconf_group_set, |
| 330 | .pin_config_dbg_show = falcon_pinconf_dbg_show, |
| 331 | .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show, |
| 332 | }; |
| 333 | |
| 334 | static struct pinctrl_desc falcon_pctrl_desc = { |
| 335 | .owner = THIS_MODULE, |
| 336 | .pins = falcon_pads, |
| 337 | .confops = &falcon_pinconf_ops, |
| 338 | }; |
| 339 | |
| 340 | static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev, |
| 341 | int mfp, int mux) |
| 342 | { |
| 343 | struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); |
| 344 | int port = PORT(info->mfp[mfp].pin); |
| 345 | |
| 346 | if ((port >= PORTS) || (!info->membase[port])) |
| 347 | return -ENODEV; |
| 348 | |
| 349 | pad_w32(info->membase[port], mux, |
| 350 | LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin))); |
| 351 | return 0; |
| 352 | } |
| 353 | |
| 354 | static const struct ltq_cfg_param falcon_cfg_params[] = { |
| 355 | {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, |
| 356 | {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT}, |
| 357 | {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE}, |
| 358 | }; |
| 359 | |
| 360 | static struct ltq_pinmux_info falcon_info = { |
| 361 | .desc = &falcon_pctrl_desc, |
| 362 | .apply_mux = falcon_mux_apply, |
| 363 | }; |
| 364 | |
| 365 | |
| 366 | |
| 367 | |
| 368 | /* --------- register the pinctrl layer --------- */ |
| 369 | |
| 370 | int pinctrl_falcon_get_range_size(int id) |
| 371 | { |
| 372 | u32 avail; |
| 373 | |
| 374 | if ((id >= PORTS) || (!falcon_info.membase[id])) |
| 375 | return -EINVAL; |
| 376 | |
| 377 | avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL); |
| 378 | |
| 379 | return fls(avail); |
| 380 | } |
| 381 | |
| 382 | void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range) |
| 383 | { |
| 384 | pinctrl_add_gpio_range(falcon_info.pctrl, range); |
| 385 | } |
| 386 | |
| 387 | static int pinctrl_falcon_probe(struct platform_device *pdev) |
| 388 | { |
| 389 | struct device_node *np; |
| 390 | int pad_count = 0; |
| 391 | int ret = 0; |
| 392 | |
| 393 | /* load and remap the pad resources of the different banks */ |
| 394 | for_each_compatible_node(np, NULL, "lantiq,pad-falcon") { |
| 395 | struct platform_device *ppdev = of_find_device_by_node(np); |
| 396 | const __be32 *bank = of_get_property(np, "lantiq,bank", NULL); |
| 397 | struct resource res; |
| 398 | u32 avail; |
| 399 | int pins; |
| 400 | |
| 401 | if (!ppdev) { |
| 402 | dev_err(&pdev->dev, "failed to find pad pdev\n"); |
| 403 | continue; |
| 404 | } |
| 405 | if (!bank || *bank >= PORTS) |
| 406 | continue; |
| 407 | if (of_address_to_resource(np, 0, &res)) |
| 408 | continue; |
| 409 | falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); |
| 410 | if (IS_ERR(falcon_info.clk[*bank])) { |
| 411 | dev_err(&ppdev->dev, "failed to get clock\n"); |
| 412 | return PTR_ERR(falcon_info.clk[*bank]); |
| 413 | } |
Thierry Reding | 9e0c1fb | 2013-01-21 11:09:14 +0100 | [diff] [blame^] | 414 | falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev, |
| 415 | &res); |
| 416 | if (IS_ERR(falcon_info.membase[*bank])) |
| 417 | return PTR_ERR(falcon_info.membase[*bank]); |
| 418 | |
John Crispin | e316cb2 | 2012-05-20 00:33:56 +0200 | [diff] [blame] | 419 | avail = pad_r32(falcon_info.membase[*bank], |
| 420 | LTQ_PADC_AVAIL); |
| 421 | pins = fls(avail); |
| 422 | lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins); |
| 423 | pad_count += pins; |
| 424 | clk_enable(falcon_info.clk[*bank]); |
| 425 | dev_dbg(&pdev->dev, "found %s with %d pads\n", |
| 426 | res.name, pins); |
| 427 | } |
| 428 | dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count); |
| 429 | falcon_pctrl_desc.name = dev_name(&pdev->dev); |
| 430 | falcon_pctrl_desc.npins = pad_count; |
| 431 | |
| 432 | falcon_info.mfp = falcon_mfp; |
| 433 | falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp); |
| 434 | falcon_info.grps = falcon_grps; |
| 435 | falcon_info.num_grps = ARRAY_SIZE(falcon_grps); |
| 436 | falcon_info.funcs = falcon_funcs; |
| 437 | falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs); |
| 438 | |
| 439 | ret = ltq_pinctrl_register(pdev, &falcon_info); |
| 440 | if (!ret) |
| 441 | dev_info(&pdev->dev, "Init done\n"); |
| 442 | return ret; |
| 443 | } |
| 444 | |
| 445 | static const struct of_device_id falcon_match[] = { |
| 446 | { .compatible = "lantiq,pinctrl-falcon" }, |
| 447 | {}, |
| 448 | }; |
| 449 | MODULE_DEVICE_TABLE(of, falcon_match); |
| 450 | |
| 451 | static struct platform_driver pinctrl_falcon_driver = { |
| 452 | .probe = pinctrl_falcon_probe, |
| 453 | .driver = { |
| 454 | .name = "pinctrl-falcon", |
| 455 | .owner = THIS_MODULE, |
| 456 | .of_match_table = falcon_match, |
| 457 | }, |
| 458 | }; |
| 459 | |
| 460 | int __init pinctrl_falcon_init(void) |
| 461 | { |
| 462 | return platform_driver_register(&pinctrl_falcon_driver); |
| 463 | } |
| 464 | |
| 465 | core_initcall_sync(pinctrl_falcon_init); |