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Kukjin Kim0c1945d2010-02-24 16:40:36 +09001/* linux/arch/arm/mach-s5pv210/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/map.h>
24
25#include <plat/cpu-freq.h>
26#include <mach/regs-clock.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/pll.h>
30#include <plat/s5p-clock.h>
31#include <plat/clock-clksrc.h>
32#include <plat/s5pv210.h>
33
Jaecheol Lee88695842010-10-12 09:19:26 +090034static unsigned long xtal;
35
Thomas Abraham59cda522010-05-17 09:38:01 +090036static struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static struct clksrc_clk clk_mout_epll = {
46 .clk = {
47 .name = "mout_epll",
48 .id = -1,
49 },
50 .sources = &clk_src_epll,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52};
53
54static struct clksrc_clk clk_mout_mpll = {
55 .clk = {
56 .name = "mout_mpll",
57 .id = -1,
58 },
59 .sources = &clk_src_mpll,
60 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61};
62
Thomas Abraham374e0bf2010-05-17 09:38:31 +090063static struct clk *clkset_armclk_list[] = {
64 [0] = &clk_mout_apll.clk,
65 [1] = &clk_mout_mpll.clk,
66};
67
68static struct clksrc_sources clkset_armclk = {
69 .sources = clkset_armclk_list,
70 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71};
72
73static struct clksrc_clk clk_armclk = {
74 .clk = {
75 .name = "armclk",
76 .id = -1,
77 },
78 .sources = &clkset_armclk,
79 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
80 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81};
82
Thomas Abrahamaf76a202010-05-17 09:38:34 +090083static struct clksrc_clk clk_hclk_msys = {
84 .clk = {
85 .name = "hclk_msys",
86 .id = -1,
87 .parent = &clk_armclk.clk,
88 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90};
91
Thomas Abraham6ed91a22010-05-17 09:38:42 +090092static struct clksrc_clk clk_pclk_msys = {
93 .clk = {
94 .name = "pclk_msys",
95 .id = -1,
96 .parent = &clk_hclk_msys.clk,
97 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
99};
100
Thomas Abraham0fe967a2010-05-17 09:38:37 +0900101static struct clksrc_clk clk_sclk_a2m = {
102 .clk = {
103 .name = "sclk_a2m",
104 .id = -1,
105 .parent = &clk_mout_apll.clk,
106 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
108};
109
110static struct clk *clkset_hclk_sys_list[] = {
111 [0] = &clk_mout_mpll.clk,
112 [1] = &clk_sclk_a2m.clk,
113};
114
115static struct clksrc_sources clkset_hclk_sys = {
116 .sources = clkset_hclk_sys_list,
117 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
118};
119
120static struct clksrc_clk clk_hclk_dsys = {
121 .clk = {
122 .name = "hclk_dsys",
123 .id = -1,
124 },
125 .sources = &clkset_hclk_sys,
126 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128};
129
Thomas Abraham58772cd2010-05-17 09:38:48 +0900130static struct clksrc_clk clk_pclk_dsys = {
131 .clk = {
132 .name = "pclk_dsys",
133 .id = -1,
134 .parent = &clk_hclk_dsys.clk,
135 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137};
138
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900139static struct clksrc_clk clk_hclk_psys = {
140 .clk = {
141 .name = "hclk_psys",
142 .id = -1,
143 },
144 .sources = &clkset_hclk_sys,
145 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
146 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
147};
148
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900149static struct clksrc_clk clk_pclk_psys = {
150 .clk = {
151 .name = "pclk_psys",
152 .id = -1,
153 .parent = &clk_hclk_psys.clk,
154 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
156};
157
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900158static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
159{
160 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
161}
162
163static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
164{
165 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
166}
167
168static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
169{
170 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
171}
172
173static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
174{
175 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
176}
177
Thomas Abrahamf445dbd2010-05-17 09:38:52 +0900178static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
179{
180 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
181}
182
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900183static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
184{
185 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
186}
187
Thomas Abrahamf445dbd2010-05-17 09:38:52 +0900188static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m",
190 .id = -1,
191 .rate = 27000000,
192};
193
Thomas Abraham2cf4c2e2010-05-17 09:38:55 +0900194static struct clk clk_sclk_hdmiphy = {
195 .name = "sclk_hdmiphy",
196 .id = -1,
197};
198
199static struct clk clk_sclk_usbphy0 = {
200 .name = "sclk_usbphy0",
201 .id = -1,
202};
203
204static struct clk clk_sclk_usbphy1 = {
205 .name = "sclk_usbphy1",
206 .id = -1,
207};
208
Thomas Abraham45834872010-05-17 09:39:00 +0900209static struct clk clk_pcmcdclk0 = {
210 .name = "pcmcdclk",
211 .id = -1,
212};
213
214static struct clk clk_pcmcdclk1 = {
215 .name = "pcmcdclk",
216 .id = -1,
217};
218
219static struct clk clk_pcmcdclk2 = {
220 .name = "pcmcdclk",
221 .id = -1,
222};
223
Thomas Abrahamf445dbd2010-05-17 09:38:52 +0900224static struct clk *clkset_vpllsrc_list[] = {
225 [0] = &clk_fin_vpll,
226 [1] = &clk_sclk_hdmi27m,
227};
228
229static struct clksrc_sources clkset_vpllsrc = {
230 .sources = clkset_vpllsrc_list,
231 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
232};
233
234static struct clksrc_clk clk_vpllsrc = {
235 .clk = {
236 .name = "vpll_src",
237 .id = -1,
238 .enable = s5pv210_clk_mask0_ctrl,
239 .ctrlbit = (1 << 7),
240 },
241 .sources = &clkset_vpllsrc,
242 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
243};
244
245static struct clk *clkset_sclk_vpll_list[] = {
246 [0] = &clk_vpllsrc.clk,
247 [1] = &clk_fout_vpll,
248};
249
250static struct clksrc_sources clkset_sclk_vpll = {
251 .sources = clkset_sclk_vpll_list,
252 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
253};
254
255static struct clksrc_clk clk_sclk_vpll = {
256 .clk = {
257 .name = "sclk_vpll",
258 .id = -1,
259 },
260 .sources = &clkset_sclk_vpll,
261 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
262};
263
Jaecheol Lee08f49d12010-10-12 09:19:30 +0900264static struct clk *clkset_moutdmc0src_list[] = {
265 [0] = &clk_sclk_a2m.clk,
266 [1] = &clk_mout_mpll.clk,
267 [2] = NULL,
268 [3] = NULL,
269};
270
271static struct clksrc_sources clkset_moutdmc0src = {
272 .sources = clkset_moutdmc0src_list,
273 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
274};
275
276static struct clksrc_clk clk_mout_dmc0 = {
277 .clk = {
278 .name = "mout_dmc0",
279 .id = -1,
280 },
281 .sources = &clkset_moutdmc0src,
282 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
283};
284
285static struct clksrc_clk clk_sclk_dmc0 = {
286 .clk = {
287 .name = "sclk_dmc0",
288 .id = -1,
289 .parent = &clk_mout_dmc0.clk,
290 },
291 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
292};
293
Thomas Abraham664f5b22010-05-17 09:38:44 +0900294static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
295{
296 return clk_get_rate(clk->parent) / 2;
297}
298
299static struct clk_ops clk_hclk_imem_ops = {
300 .get_rate = s5pv210_clk_imem_get_rate,
301};
302
Jaecheol Lee88695842010-10-12 09:19:26 +0900303static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
304{
305 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
306}
307
308static struct clk_ops clk_fout_apll_ops = {
309 .get_rate = s5pv210_clk_fout_apll_get_rate,
310};
311
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900312static struct clk init_clocks_disable[] = {
313 {
Seungwhan Youn313068f2010-10-19 18:10:53 +0900314 .name = "pdma",
315 .id = 0,
316 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 3),
319 }, {
320 .name = "pdma",
321 .id = 1,
322 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 4),
325 }, {
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900326 .name = "rot",
327 .id = -1,
Thomas Abraham0fe967a2010-05-17 09:38:37 +0900328 .parent = &clk_hclk_dsys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900329 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1<<29),
331 }, {
Marek Szyprowskida01c2f2010-09-10 19:43:12 +0900332 .name = "fimc",
333 .id = 0,
334 .parent = &clk_hclk_dsys.clk,
335 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 24),
337 }, {
338 .name = "fimc",
339 .id = 1,
340 .parent = &clk_hclk_dsys.clk,
341 .enable = s5pv210_clk_ip0_ctrl,
342 .ctrlbit = (1 << 25),
343 }, {
344 .name = "fimc",
345 .id = 2,
346 .parent = &clk_hclk_dsys.clk,
347 .enable = s5pv210_clk_ip0_ctrl,
348 .ctrlbit = (1 << 26),
349 }, {
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900350 .name = "otg",
351 .id = -1,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900352 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900353 .enable = s5pv210_clk_ip1_ctrl,
354 .ctrlbit = (1<<16),
355 }, {
356 .name = "usb-host",
357 .id = -1,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900358 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900359 .enable = s5pv210_clk_ip1_ctrl,
360 .ctrlbit = (1<<17),
361 }, {
362 .name = "lcd",
363 .id = -1,
Thomas Abraham0fe967a2010-05-17 09:38:37 +0900364 .parent = &clk_hclk_dsys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900365 .enable = s5pv210_clk_ip1_ctrl,
366 .ctrlbit = (1<<0),
367 }, {
368 .name = "cfcon",
369 .id = 0,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900370 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900371 .enable = s5pv210_clk_ip1_ctrl,
372 .ctrlbit = (1<<25),
373 }, {
374 .name = "hsmmc",
375 .id = 0,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900376 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900377 .enable = s5pv210_clk_ip2_ctrl,
378 .ctrlbit = (1<<16),
379 }, {
380 .name = "hsmmc",
381 .id = 1,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900382 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900383 .enable = s5pv210_clk_ip2_ctrl,
384 .ctrlbit = (1<<17),
385 }, {
386 .name = "hsmmc",
387 .id = 2,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900388 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900389 .enable = s5pv210_clk_ip2_ctrl,
390 .ctrlbit = (1<<18),
391 }, {
392 .name = "hsmmc",
393 .id = 3,
Thomas Abrahamacfa2452010-05-17 09:38:40 +0900394 .parent = &clk_hclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900395 .enable = s5pv210_clk_ip2_ctrl,
396 .ctrlbit = (1<<19),
397 }, {
398 .name = "systimer",
399 .id = -1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900400 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900401 .enable = s5pv210_clk_ip3_ctrl,
402 .ctrlbit = (1<<16),
403 }, {
404 .name = "watchdog",
405 .id = -1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900406 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900407 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<22),
409 }, {
410 .name = "rtc",
411 .id = -1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900412 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900413 .enable = s5pv210_clk_ip3_ctrl,
414 .ctrlbit = (1<<15),
415 }, {
416 .name = "i2c",
417 .id = 0,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900418 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900419 .enable = s5pv210_clk_ip3_ctrl,
420 .ctrlbit = (1<<7),
421 }, {
422 .name = "i2c",
423 .id = 1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900424 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900425 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Hamf1c894d2010-08-21 09:18:19 +0900426 .ctrlbit = (1 << 10),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900427 }, {
428 .name = "i2c",
429 .id = 2,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900430 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900431 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<9),
433 }, {
434 .name = "spi",
435 .id = 0,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900436 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900437 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<12),
439 }, {
440 .name = "spi",
441 .id = 1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900442 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900443 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<13),
445 }, {
446 .name = "spi",
447 .id = 2,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900448 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900449 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<14),
451 }, {
452 .name = "timers",
453 .id = -1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900454 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900455 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<23),
457 }, {
458 .name = "adc",
459 .id = -1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900460 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900461 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1<<24),
463 }, {
464 .name = "keypad",
465 .id = -1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900466 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900467 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21),
469 }, {
470 .name = "i2s_v50",
471 .id = 0,
472 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4),
475 }, {
476 .name = "i2s_v32",
477 .id = 0,
478 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900480 .ctrlbit = (1 << 5),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900481 }, {
482 .name = "i2s_v32",
483 .id = 1,
484 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900486 .ctrlbit = (1 << 6),
Seungwhan Younaa21ae32010-10-14 10:35:24 +0900487 }, {
488 .name = "spdif",
489 .id = -1,
490 .parent = &clk_p,
491 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 0),
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900493 },
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900494};
495
496static struct clk init_clocks[] = {
497 {
Thomas Abraham664f5b22010-05-17 09:38:44 +0900498 .name = "hclk_imem",
499 .id = -1,
500 .parent = &clk_hclk_msys.clk,
501 .ctrlbit = (1 << 5),
502 .enable = s5pv210_clk_ip0_ctrl,
503 .ops = &clk_hclk_imem_ops,
504 }, {
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900505 .name = "uart",
506 .id = 0,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900507 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900508 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900509 .ctrlbit = (1 << 17),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900510 }, {
511 .name = "uart",
512 .id = 1,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900513 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900514 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900515 .ctrlbit = (1 << 18),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900516 }, {
517 .name = "uart",
518 .id = 2,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900519 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900520 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900521 .ctrlbit = (1 << 19),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900522 }, {
523 .name = "uart",
524 .id = 3,
Thomas Abrahamf44cf782010-05-17 09:38:50 +0900525 .parent = &clk_pclk_psys.clk,
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900526 .enable = s5pv210_clk_ip3_ctrl,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900527 .ctrlbit = (1 << 20),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900528 },
529};
530
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900531static struct clk *clkset_uart_list[] = {
532 [6] = &clk_mout_mpll.clk,
533 [7] = &clk_mout_epll.clk,
534};
535
536static struct clksrc_sources clkset_uart = {
537 .sources = clkset_uart_list,
538 .nr_sources = ARRAY_SIZE(clkset_uart_list),
539};
540
Thomas Abraham2cf4c2e2010-05-17 09:38:55 +0900541static struct clk *clkset_group1_list[] = {
542 [0] = &clk_sclk_a2m.clk,
543 [1] = &clk_mout_mpll.clk,
544 [2] = &clk_mout_epll.clk,
545 [3] = &clk_sclk_vpll.clk,
546};
547
548static struct clksrc_sources clkset_group1 = {
549 .sources = clkset_group1_list,
550 .nr_sources = ARRAY_SIZE(clkset_group1_list),
551};
552
553static struct clk *clkset_sclk_onenand_list[] = {
554 [0] = &clk_hclk_psys.clk,
555 [1] = &clk_hclk_dsys.clk,
556};
557
558static struct clksrc_sources clkset_sclk_onenand = {
559 .sources = clkset_sclk_onenand_list,
560 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
561};
562
Thomas Abraham9e206142010-05-17 09:38:57 +0900563static struct clk *clkset_sclk_dac_list[] = {
564 [0] = &clk_sclk_vpll.clk,
565 [1] = &clk_sclk_hdmiphy,
566};
567
568static struct clksrc_sources clkset_sclk_dac = {
569 .sources = clkset_sclk_dac_list,
570 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
571};
572
573static struct clksrc_clk clk_sclk_dac = {
574 .clk = {
575 .name = "sclk_dac",
576 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900577 .enable = s5pv210_clk_mask0_ctrl,
578 .ctrlbit = (1 << 2),
Thomas Abraham9e206142010-05-17 09:38:57 +0900579 },
580 .sources = &clkset_sclk_dac,
581 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
582};
583
584static struct clksrc_clk clk_sclk_pixel = {
585 .clk = {
586 .name = "sclk_pixel",
587 .id = -1,
588 .parent = &clk_sclk_vpll.clk,
589 },
590 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
591};
592
593static struct clk *clkset_sclk_hdmi_list[] = {
594 [0] = &clk_sclk_pixel.clk,
595 [1] = &clk_sclk_hdmiphy,
596};
597
598static struct clksrc_sources clkset_sclk_hdmi = {
599 .sources = clkset_sclk_hdmi_list,
600 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
601};
602
603static struct clksrc_clk clk_sclk_hdmi = {
604 .clk = {
605 .name = "sclk_hdmi",
606 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900607 .enable = s5pv210_clk_mask0_ctrl,
608 .ctrlbit = (1 << 0),
Thomas Abraham9e206142010-05-17 09:38:57 +0900609 },
610 .sources = &clkset_sclk_hdmi,
611 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
612};
613
614static struct clk *clkset_sclk_mixer_list[] = {
615 [0] = &clk_sclk_dac.clk,
616 [1] = &clk_sclk_hdmi.clk,
617};
618
619static struct clksrc_sources clkset_sclk_mixer = {
620 .sources = clkset_sclk_mixer_list,
621 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
622};
623
Thomas Abraham45834872010-05-17 09:39:00 +0900624static struct clk *clkset_sclk_audio0_list[] = {
625 [0] = &clk_ext_xtal_mux,
626 [1] = &clk_pcmcdclk0,
627 [2] = &clk_sclk_hdmi27m,
628 [3] = &clk_sclk_usbphy0,
629 [4] = &clk_sclk_usbphy1,
630 [5] = &clk_sclk_hdmiphy,
631 [6] = &clk_mout_mpll.clk,
632 [7] = &clk_mout_epll.clk,
633 [8] = &clk_sclk_vpll.clk,
634};
635
636static struct clksrc_sources clkset_sclk_audio0 = {
637 .sources = clkset_sclk_audio0_list,
638 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
639};
640
641static struct clksrc_clk clk_sclk_audio0 = {
642 .clk = {
643 .name = "sclk_audio",
644 .id = 0,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900645 .enable = s5pv210_clk_mask0_ctrl,
646 .ctrlbit = (1 << 24),
Thomas Abraham45834872010-05-17 09:39:00 +0900647 },
648 .sources = &clkset_sclk_audio0,
649 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
650 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
651};
652
653static struct clk *clkset_sclk_audio1_list[] = {
654 [0] = &clk_ext_xtal_mux,
655 [1] = &clk_pcmcdclk1,
656 [2] = &clk_sclk_hdmi27m,
657 [3] = &clk_sclk_usbphy0,
658 [4] = &clk_sclk_usbphy1,
659 [5] = &clk_sclk_hdmiphy,
660 [6] = &clk_mout_mpll.clk,
661 [7] = &clk_mout_epll.clk,
662 [8] = &clk_sclk_vpll.clk,
663};
664
665static struct clksrc_sources clkset_sclk_audio1 = {
666 .sources = clkset_sclk_audio1_list,
667 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
668};
669
670static struct clksrc_clk clk_sclk_audio1 = {
671 .clk = {
672 .name = "sclk_audio",
673 .id = 1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900674 .enable = s5pv210_clk_mask0_ctrl,
675 .ctrlbit = (1 << 25),
Thomas Abraham45834872010-05-17 09:39:00 +0900676 },
677 .sources = &clkset_sclk_audio1,
678 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
679 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
680};
681
682static struct clk *clkset_sclk_audio2_list[] = {
683 [0] = &clk_ext_xtal_mux,
684 [1] = &clk_pcmcdclk0,
685 [2] = &clk_sclk_hdmi27m,
686 [3] = &clk_sclk_usbphy0,
687 [4] = &clk_sclk_usbphy1,
688 [5] = &clk_sclk_hdmiphy,
689 [6] = &clk_mout_mpll.clk,
690 [7] = &clk_mout_epll.clk,
691 [8] = &clk_sclk_vpll.clk,
692};
693
694static struct clksrc_sources clkset_sclk_audio2 = {
695 .sources = clkset_sclk_audio2_list,
696 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
697};
698
699static struct clksrc_clk clk_sclk_audio2 = {
700 .clk = {
701 .name = "sclk_audio",
702 .id = 2,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900703 .enable = s5pv210_clk_mask0_ctrl,
704 .ctrlbit = (1 << 26),
Thomas Abraham45834872010-05-17 09:39:00 +0900705 },
706 .sources = &clkset_sclk_audio2,
707 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
708 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
709};
710
711static struct clk *clkset_sclk_spdif_list[] = {
712 [0] = &clk_sclk_audio0.clk,
713 [1] = &clk_sclk_audio1.clk,
714 [2] = &clk_sclk_audio2.clk,
715};
716
717static struct clksrc_sources clkset_sclk_spdif = {
718 .sources = clkset_sclk_spdif_list,
719 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
720};
721
Seungwhan Younaa21ae32010-10-14 10:35:24 +0900722static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
723{
724 struct clk *pclk;
725 int ret;
726
727 pclk = clk_get_parent(clk);
728 if (IS_ERR(pclk))
729 return -EINVAL;
730
731 ret = pclk->ops->set_rate(pclk, rate);
732 clk_put(pclk);
733
734 return ret;
735}
736
737static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
738{
739 struct clk *pclk;
740 int rate;
741
742 pclk = clk_get_parent(clk);
743 if (IS_ERR(pclk))
744 return -EINVAL;
745
746 rate = pclk->ops->get_rate(clk);
747 clk_put(pclk);
748
749 return rate;
750}
751
752static struct clk_ops s5pv210_sclk_spdif_ops = {
753 .set_rate = s5pv210_spdif_set_rate,
754 .get_rate = s5pv210_spdif_get_rate,
755};
756
757static struct clksrc_clk clk_sclk_spdif = {
758 .clk = {
759 .name = "sclk_spdif",
760 .id = -1,
761 .enable = s5pv210_clk_mask0_ctrl,
762 .ctrlbit = (1 << 27),
763 .ops = &s5pv210_sclk_spdif_ops,
764 },
765 .sources = &clkset_sclk_spdif,
766 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
767};
768
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900769static struct clk *clkset_group2_list[] = {
770 [0] = &clk_ext_xtal_mux,
771 [1] = &clk_xusbxti,
772 [2] = &clk_sclk_hdmi27m,
773 [3] = &clk_sclk_usbphy0,
774 [4] = &clk_sclk_usbphy1,
775 [5] = &clk_sclk_hdmiphy,
776 [6] = &clk_mout_mpll.clk,
777 [7] = &clk_mout_epll.clk,
778 [8] = &clk_sclk_vpll.clk,
779};
780
781static struct clksrc_sources clkset_group2 = {
782 .sources = clkset_group2_list,
783 .nr_sources = ARRAY_SIZE(clkset_group2_list),
784};
785
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900786static struct clksrc_clk clksrcs[] = {
787 {
788 .clk = {
Thomas Abraham2cf4c2e2010-05-17 09:38:55 +0900789 .name = "sclk_dmc",
790 .id = -1,
791 },
792 .sources = &clkset_group1,
793 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
794 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
795 }, {
796 .clk = {
797 .name = "sclk_onenand",
798 .id = -1,
799 },
800 .sources = &clkset_sclk_onenand,
801 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
802 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
803 }, {
804 .clk = {
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900805 .name = "uclk1",
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900806 .id = 0,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900807 .enable = s5pv210_clk_mask0_ctrl,
808 .ctrlbit = (1 << 12),
Kukjin Kim0c1945d2010-02-24 16:40:36 +0900809 },
810 .sources = &clkset_uart,
811 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
812 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
Thomas Abraham9e206142010-05-17 09:38:57 +0900813 }, {
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900814 .clk = {
815 .name = "uclk1",
816 .id = 1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900817 .enable = s5pv210_clk_mask0_ctrl,
818 .ctrlbit = (1 << 13),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900819 },
820 .sources = &clkset_uart,
821 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
822 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
823 }, {
824 .clk = {
825 .name = "uclk1",
826 .id = 2,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900827 .enable = s5pv210_clk_mask0_ctrl,
828 .ctrlbit = (1 << 14),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900829 },
830 .sources = &clkset_uart,
831 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
832 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
833 }, {
834 .clk = {
835 .name = "uclk1",
836 .id = 3,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900837 .enable = s5pv210_clk_mask0_ctrl,
838 .ctrlbit = (1 << 15),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900839 },
840 .sources = &clkset_uart,
841 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
842 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
843 }, {
Thomas Abraham9e206142010-05-17 09:38:57 +0900844 .clk = {
845 .name = "sclk_mixer",
846 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900847 .enable = s5pv210_clk_mask0_ctrl,
848 .ctrlbit = (1 << 1),
Thomas Abraham9e206142010-05-17 09:38:57 +0900849 },
850 .sources = &clkset_sclk_mixer,
851 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
Thomas Abraham45834872010-05-17 09:39:00 +0900852 }, {
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900853 .clk = {
854 .name = "sclk_fimc",
855 .id = 0,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900856 .enable = s5pv210_clk_mask1_ctrl,
857 .ctrlbit = (1 << 2),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900858 },
859 .sources = &clkset_group2,
860 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
861 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
862 }, {
863 .clk = {
864 .name = "sclk_fimc",
865 .id = 1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900866 .enable = s5pv210_clk_mask1_ctrl,
867 .ctrlbit = (1 << 3),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900868 },
869 .sources = &clkset_group2,
870 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
871 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
872 }, {
873 .clk = {
874 .name = "sclk_fimc",
875 .id = 2,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900876 .enable = s5pv210_clk_mask1_ctrl,
877 .ctrlbit = (1 << 4),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900878 },
879 .sources = &clkset_group2,
880 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
881 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
882 }, {
883 .clk = {
884 .name = "sclk_cam",
885 .id = 0,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900886 .enable = s5pv210_clk_mask0_ctrl,
887 .ctrlbit = (1 << 3),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900888 },
889 .sources = &clkset_group2,
890 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
891 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
892 }, {
893 .clk = {
894 .name = "sclk_cam",
895 .id = 1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900896 .enable = s5pv210_clk_mask0_ctrl,
897 .ctrlbit = (1 << 4),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900898 },
899 .sources = &clkset_group2,
900 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
901 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
902 }, {
903 .clk = {
904 .name = "sclk_fimd",
905 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900906 .enable = s5pv210_clk_mask0_ctrl,
907 .ctrlbit = (1 << 5),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900908 },
909 .sources = &clkset_group2,
910 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
911 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
912 }, {
913 .clk = {
914 .name = "sclk_mmc",
915 .id = 0,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900916 .enable = s5pv210_clk_mask0_ctrl,
917 .ctrlbit = (1 << 8),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900918 },
919 .sources = &clkset_group2,
920 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
921 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
922 }, {
923 .clk = {
924 .name = "sclk_mmc",
925 .id = 1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900926 .enable = s5pv210_clk_mask0_ctrl,
927 .ctrlbit = (1 << 9),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900928 },
929 .sources = &clkset_group2,
930 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
931 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
932 }, {
933 .clk = {
934 .name = "sclk_mmc",
935 .id = 2,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900936 .enable = s5pv210_clk_mask0_ctrl,
937 .ctrlbit = (1 << 10),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900938 },
939 .sources = &clkset_group2,
940 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
941 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
942 }, {
943 .clk = {
944 .name = "sclk_mmc",
945 .id = 3,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900946 .enable = s5pv210_clk_mask0_ctrl,
947 .ctrlbit = (1 << 11),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900948 },
949 .sources = &clkset_group2,
950 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
951 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
952 }, {
953 .clk = {
954 .name = "sclk_mfc",
955 .id = -1,
956 .enable = s5pv210_clk_ip0_ctrl,
957 .ctrlbit = (1 << 16),
958 },
959 .sources = &clkset_group1,
960 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
961 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
962 }, {
963 .clk = {
964 .name = "sclk_g2d",
965 .id = -1,
966 .enable = s5pv210_clk_ip0_ctrl,
967 .ctrlbit = (1 << 12),
968 },
969 .sources = &clkset_group1,
970 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
971 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
972 }, {
973 .clk = {
974 .name = "sclk_g3d",
975 .id = -1,
976 .enable = s5pv210_clk_ip0_ctrl,
977 .ctrlbit = (1 << 8),
978 },
979 .sources = &clkset_group1,
980 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
981 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
982 }, {
983 .clk = {
984 .name = "sclk_csis",
985 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900986 .enable = s5pv210_clk_mask0_ctrl,
987 .ctrlbit = (1 << 6),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900988 },
989 .sources = &clkset_group2,
990 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
991 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
992 }, {
993 .clk = {
994 .name = "sclk_spi",
995 .id = 0,
MyungJoo Ham154d62e2010-06-26 17:21:50 +0900996 .enable = s5pv210_clk_mask0_ctrl,
997 .ctrlbit = (1 << 16),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +0900998 },
999 .sources = &clkset_group2,
1000 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1001 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1002 }, {
1003 .clk = {
1004 .name = "sclk_spi",
1005 .id = 1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +09001006 .enable = s5pv210_clk_mask0_ctrl,
1007 .ctrlbit = (1 << 17),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +09001008 },
1009 .sources = &clkset_group2,
1010 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1011 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1012 }, {
1013 .clk = {
1014 .name = "sclk_pwi",
1015 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +09001016 .enable = s5pv210_clk_mask0_ctrl,
1017 .ctrlbit = (1 << 29),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +09001018 },
1019 .sources = &clkset_group2,
1020 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
1021 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
1022 }, {
1023 .clk = {
1024 .name = "sclk_pwm",
1025 .id = -1,
MyungJoo Ham154d62e2010-06-26 17:21:50 +09001026 .enable = s5pv210_clk_mask0_ctrl,
1027 .ctrlbit = (1 << 19),
Thomas Abrahamf64cacc2010-05-17 09:39:03 +09001028 },
1029 .sources = &clkset_group2,
1030 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
1031 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
Thomas Abraham9e206142010-05-17 09:38:57 +09001032 },
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001033};
1034
1035/* Clock initialisation code */
Thomas Abrahameb1ef1e2010-05-17 09:38:12 +09001036static struct clksrc_clk *sysclks[] = {
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001037 &clk_mout_apll,
1038 &clk_mout_epll,
1039 &clk_mout_mpll,
Thomas Abraham374e0bf2010-05-17 09:38:31 +09001040 &clk_armclk,
Thomas Abrahamaf76a202010-05-17 09:38:34 +09001041 &clk_hclk_msys,
Thomas Abraham0fe967a2010-05-17 09:38:37 +09001042 &clk_sclk_a2m,
1043 &clk_hclk_dsys,
Thomas Abrahamacfa2452010-05-17 09:38:40 +09001044 &clk_hclk_psys,
Thomas Abraham6ed91a22010-05-17 09:38:42 +09001045 &clk_pclk_msys,
Thomas Abraham58772cd2010-05-17 09:38:48 +09001046 &clk_pclk_dsys,
Thomas Abrahamf44cf782010-05-17 09:38:50 +09001047 &clk_pclk_psys,
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001048 &clk_vpllsrc,
1049 &clk_sclk_vpll,
Thomas Abraham9e206142010-05-17 09:38:57 +09001050 &clk_sclk_dac,
1051 &clk_sclk_pixel,
1052 &clk_sclk_hdmi,
Jaecheol Lee08f49d12010-10-12 09:19:30 +09001053 &clk_mout_dmc0,
1054 &clk_sclk_dmc0,
Seungwhan Youn900fa012010-10-14 10:35:24 +09001055 &clk_sclk_audio0,
1056 &clk_sclk_audio1,
1057 &clk_sclk_audio2,
1058 &clk_sclk_spdif,
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001059};
1060
Seungwhan Younc9fa7a02010-10-14 10:39:28 +09001061static u32 epll_div[][6] = {
1062 { 48000000, 0, 48, 3, 3, 0 },
1063 { 96000000, 0, 48, 3, 2, 0 },
1064 { 144000000, 1, 72, 3, 2, 0 },
1065 { 192000000, 0, 48, 3, 1, 0 },
1066 { 288000000, 1, 72, 3, 1, 0 },
1067 { 32750000, 1, 65, 3, 4, 35127 },
1068 { 32768000, 1, 65, 3, 4, 35127 },
1069 { 45158400, 0, 45, 3, 3, 10355 },
1070 { 45000000, 0, 45, 3, 3, 10355 },
1071 { 45158000, 0, 45, 3, 3, 10355 },
1072 { 49125000, 0, 49, 3, 3, 9961 },
1073 { 49152000, 0, 49, 3, 3, 9961 },
1074 { 67737600, 1, 67, 3, 3, 48366 },
1075 { 67738000, 1, 67, 3, 3, 48366 },
1076 { 73800000, 1, 73, 3, 3, 47710 },
1077 { 73728000, 1, 73, 3, 3, 47710 },
1078 { 36000000, 1, 32, 3, 4, 0 },
1079 { 60000000, 1, 60, 3, 3, 0 },
1080 { 72000000, 1, 72, 3, 3, 0 },
1081 { 80000000, 1, 80, 3, 3, 0 },
1082 { 84000000, 0, 42, 3, 2, 0 },
1083 { 50000000, 0, 50, 3, 3, 0 },
1084};
1085
1086static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1087{
1088 unsigned int epll_con, epll_con_k;
1089 unsigned int i;
1090
1091 /* Return if nothing changed */
1092 if (clk->rate == rate)
1093 return 0;
1094
1095 epll_con = __raw_readl(S5P_EPLL_CON);
1096 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1097
1098 epll_con_k &= ~PLL46XX_KDIV_MASK;
1099 epll_con &= ~(1 << 27 |
1100 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1101 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1102 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1103
1104 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1105 if (epll_div[i][0] == rate) {
1106 epll_con_k |= epll_div[i][5] << 0;
1107 epll_con |= (epll_div[i][1] << 27 |
1108 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1109 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1110 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1111 break;
1112 }
1113 }
1114
1115 if (i == ARRAY_SIZE(epll_div)) {
1116 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1117 __func__);
1118 return -EINVAL;
1119 }
1120
1121 __raw_writel(epll_con, S5P_EPLL_CON);
1122 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1123
Seungwhan Youn96166742010-10-14 10:39:33 +09001124 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1125 clk->rate, rate);
1126
Seungwhan Younc9fa7a02010-10-14 10:39:28 +09001127 clk->rate = rate;
1128
1129 return 0;
1130}
1131
1132static struct clk_ops s5pv210_epll_ops = {
1133 .set_rate = s5pv210_epll_set_rate,
1134 .get_rate = s5p_epll_get_rate,
1135};
1136
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001137void __init_or_cpufreq s5pv210_setup_clocks(void)
1138{
1139 struct clk *xtal_clk;
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001140 unsigned long vpllsrc;
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001141 unsigned long armclk;
Thomas Abrahamaf76a202010-05-17 09:38:34 +09001142 unsigned long hclk_msys;
Thomas Abraham0fe967a2010-05-17 09:38:37 +09001143 unsigned long hclk_dsys;
Thomas Abrahamacfa2452010-05-17 09:38:40 +09001144 unsigned long hclk_psys;
Thomas Abraham6ed91a22010-05-17 09:38:42 +09001145 unsigned long pclk_msys;
Thomas Abraham58772cd2010-05-17 09:38:48 +09001146 unsigned long pclk_dsys;
Thomas Abrahamf44cf782010-05-17 09:38:50 +09001147 unsigned long pclk_psys;
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001148 unsigned long apll;
1149 unsigned long mpll;
1150 unsigned long epll;
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001151 unsigned long vpll;
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001152 unsigned int ptr;
1153 u32 clkdiv0, clkdiv1;
1154
Seungwhan Younc9fa7a02010-10-14 10:39:28 +09001155 /* Set functions for clk_fout_epll */
1156 clk_fout_epll.enable = s5p_epll_enable;
1157 clk_fout_epll.ops = &s5pv210_epll_ops;
1158
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001159 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1160
1161 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1162 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1163
1164 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1165 __func__, clkdiv0, clkdiv1);
1166
1167 xtal_clk = clk_get(NULL, "xtal");
1168 BUG_ON(IS_ERR(xtal_clk));
1169
1170 xtal = clk_get_rate(xtal_clk);
1171 clk_put(xtal_clk);
1172
1173 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1174
1175 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1176 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
Seungwhan Youn42a6e202010-10-14 10:39:15 +09001177 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1178 __raw_readl(S5P_EPLL_CON1), pll_4600);
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001179 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1180 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001181
Jaecheol Lee88695842010-10-12 09:19:26 +09001182 clk_fout_apll.ops = &clk_fout_apll_ops;
Thomas Abrahamc62ec6a2010-05-17 09:38:28 +09001183 clk_fout_mpll.rate = mpll;
1184 clk_fout_epll.rate = epll;
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001185 clk_fout_vpll.rate = vpll;
Thomas Abrahamc62ec6a2010-05-17 09:38:28 +09001186
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001187 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1188 apll, mpll, epll, vpll);
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001189
Thomas Abraham374e0bf2010-05-17 09:38:31 +09001190 armclk = clk_get_rate(&clk_armclk.clk);
Thomas Abrahamaf76a202010-05-17 09:38:34 +09001191 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
Thomas Abraham0fe967a2010-05-17 09:38:37 +09001192 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
Thomas Abrahamacfa2452010-05-17 09:38:40 +09001193 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
Thomas Abraham6ed91a22010-05-17 09:38:42 +09001194 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
Thomas Abraham58772cd2010-05-17 09:38:48 +09001195 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
Thomas Abrahamf44cf782010-05-17 09:38:50 +09001196 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001197
Thomas Abrahamacfa2452010-05-17 09:38:40 +09001198 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1199 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1200 armclk, hclk_msys, hclk_dsys, hclk_psys,
Thomas Abrahamf44cf782010-05-17 09:38:50 +09001201 pclk_msys, pclk_dsys, pclk_psys);
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001202
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001203 clk_f.rate = armclk;
Thomas Abrahamacfa2452010-05-17 09:38:40 +09001204 clk_h.rate = hclk_psys;
Thomas Abrahamf44cf782010-05-17 09:38:50 +09001205 clk_p.rate = pclk_psys;
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001206
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001207 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1208 s3c_set_clksrc(&clksrcs[ptr], true);
1209}
1210
1211static struct clk *clks[] __initdata = {
Thomas Abrahamf445dbd2010-05-17 09:38:52 +09001212 &clk_sclk_hdmi27m,
Thomas Abraham2cf4c2e2010-05-17 09:38:55 +09001213 &clk_sclk_hdmiphy,
1214 &clk_sclk_usbphy0,
1215 &clk_sclk_usbphy1,
Thomas Abraham45834872010-05-17 09:39:00 +09001216 &clk_pcmcdclk0,
1217 &clk_pcmcdclk1,
1218 &clk_pcmcdclk2,
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001219};
1220
1221void __init s5pv210_register_clocks(void)
1222{
1223 struct clk *clkp;
1224 int ret;
1225 int ptr;
1226
1227 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1228 if (ret > 0)
1229 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1230
Thomas Abrahameb1ef1e2010-05-17 09:38:12 +09001231 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1232 s3c_register_clksrc(sysclks[ptr], 1);
1233
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001234 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1235 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1236
Kukjin Kim0c1945d2010-02-24 16:40:36 +09001237 clkp = init_clocks_disable;
1238 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1239 ret = s3c24xx_register_clock(clkp);
1240 if (ret < 0) {
1241 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1242 clkp->name, ret);
1243 }
1244 (clkp->enable)(clkp, 0);
1245 }
1246
1247 s3c_pwmclk_init();
1248}