blob: 364b0d1c4566f93f03946071e05bba21884d74c1 [file] [log] [blame]
Alex Deucher97b2e202015-04-20 16:51:00 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
Chunming Zhoud03846a2015-07-28 14:20:03 -040045#include <drm/drmP.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040046#include <drm/drm_gem.h>
Chunming Zhou7e5a5472015-04-24 17:37:30 +080047#include <drm/amdgpu_drm.h>
Alex Deucher97b2e202015-04-20 16:51:00 -040048
yanyang15fc3aee2015-05-22 14:39:35 -040049#include "amd_shared.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040050#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
Alex Deucher1f7371b2015-12-02 17:46:21 -050055#include "amd_powerplay.h"
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -040056#include "amdgpu_acp.h"
Alex Deucher97b2e202015-04-20 16:51:00 -040057
Alex Deucherb80d8472015-08-16 22:55:02 -040058#include "gpu_scheduler.h"
59
Alex Deucher97b2e202015-04-20 16:51:00 -040060/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
Alex Deucher97b2e202015-04-20 16:51:00 -040078extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
Christian Königd9c13152015-09-28 12:31:26 +020083extern int amdgpu_vm_fault_stop;
Christian Königb495bd32015-09-10 14:00:35 +020084extern int amdgpu_vm_debug;
Jammy Zhou1333f722015-07-30 16:36:58 +080085extern int amdgpu_sched_jobs;
Jammy Zhou4afcb302015-07-30 16:44:05 +080086extern int amdgpu_sched_hw_submission;
Alex Deucher1f7371b2015-12-02 17:46:21 -050087extern int amdgpu_powerplay;
Alex Deucher97b2e202015-04-20 16:51:00 -040088
Chunming Zhou4b559c92015-07-21 15:53:04 +080089#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
Alex Deucher97b2e202015-04-20 16:51:00 -040090#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93#define AMDGPU_IB_POOL_SIZE 16
94#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95#define AMDGPUFB_CONN_LIMIT 4
96#define AMDGPU_BIOS_NUM_SCRATCH 8
97
Alex Deucher97b2e202015-04-20 16:51:00 -040098/* max number of rings */
99#define AMDGPU_MAX_RINGS 16
100#define AMDGPU_MAX_GFX_RINGS 1
101#define AMDGPU_MAX_COMPUTE_RINGS 8
102#define AMDGPU_MAX_VCE_RINGS 2
103
Jammy Zhou36f523a2015-09-01 12:54:27 +0800104/* max number of IP instances */
105#define AMDGPU_MAX_SDMA_INSTANCES 2
106
Alex Deucher97b2e202015-04-20 16:51:00 -0400107/* hardcode that limit for now */
108#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
109
110/* hard reset data */
111#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
112
113/* reset flags */
114#define AMDGPU_RESET_GFX (1 << 0)
115#define AMDGPU_RESET_COMPUTE (1 << 1)
116#define AMDGPU_RESET_DMA (1 << 2)
117#define AMDGPU_RESET_CP (1 << 3)
118#define AMDGPU_RESET_GRBM (1 << 4)
119#define AMDGPU_RESET_DMA1 (1 << 5)
120#define AMDGPU_RESET_RLC (1 << 6)
121#define AMDGPU_RESET_SEM (1 << 7)
122#define AMDGPU_RESET_IH (1 << 8)
123#define AMDGPU_RESET_VMC (1 << 9)
124#define AMDGPU_RESET_MC (1 << 10)
125#define AMDGPU_RESET_DISPLAY (1 << 11)
126#define AMDGPU_RESET_UVD (1 << 12)
127#define AMDGPU_RESET_VCE (1 << 13)
128#define AMDGPU_RESET_VCE1 (1 << 14)
129
130/* CG block flags */
131#define AMDGPU_CG_BLOCK_GFX (1 << 0)
132#define AMDGPU_CG_BLOCK_MC (1 << 1)
133#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134#define AMDGPU_CG_BLOCK_UVD (1 << 3)
135#define AMDGPU_CG_BLOCK_VCE (1 << 4)
136#define AMDGPU_CG_BLOCK_HDP (1 << 5)
137#define AMDGPU_CG_BLOCK_BIF (1 << 6)
138
139/* CG flags */
140#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
157
158/* PG flags */
159#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164#define AMDGPU_PG_SUPPORT_CP (1 << 5)
165#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
170
171/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L
174#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
177
178/* max cursor sizes (in pixels) */
179#define CIK_CURSOR_WIDTH 128
180#define CIK_CURSOR_HEIGHT 128
181
182struct amdgpu_device;
183struct amdgpu_fence;
184struct amdgpu_ib;
185struct amdgpu_vm;
186struct amdgpu_ring;
Alex Deucher97b2e202015-04-20 16:51:00 -0400187struct amdgpu_cs_parser;
Chunming Zhoubb977d32015-08-18 15:16:40 +0800188struct amdgpu_job;
Alex Deucher97b2e202015-04-20 16:51:00 -0400189struct amdgpu_irq_src;
Alex Deucher0b492a42015-08-16 22:48:26 -0400190struct amdgpu_fpriv;
Alex Deucher97b2e202015-04-20 16:51:00 -0400191
192enum amdgpu_cp_irq {
193 AMDGPU_CP_IRQ_GFX_EOP = 0,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
202
203 AMDGPU_CP_IRQ_LAST
204};
205
206enum amdgpu_sdma_irq {
207 AMDGPU_SDMA_IRQ_TRAP0 = 0,
208 AMDGPU_SDMA_IRQ_TRAP1,
209
210 AMDGPU_SDMA_IRQ_LAST
211};
212
213enum amdgpu_thermal_irq {
214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
216
217 AMDGPU_THERMAL_IRQ_LAST
218};
219
Alex Deucher97b2e202015-04-20 16:51:00 -0400220int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400221 enum amd_ip_block_type block_type,
222 enum amd_clockgating_state state);
Alex Deucher97b2e202015-04-20 16:51:00 -0400223int amdgpu_set_powergating_state(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400224 enum amd_ip_block_type block_type,
225 enum amd_powergating_state state);
Alex Deucher97b2e202015-04-20 16:51:00 -0400226
227struct amdgpu_ip_block_version {
yanyang15fc3aee2015-05-22 14:39:35 -0400228 enum amd_ip_block_type type;
Alex Deucher97b2e202015-04-20 16:51:00 -0400229 u32 major;
230 u32 minor;
231 u32 rev;
yanyang15fc3aee2015-05-22 14:39:35 -0400232 const struct amd_ip_funcs *funcs;
Alex Deucher97b2e202015-04-20 16:51:00 -0400233};
234
235int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400236 enum amd_ip_block_type type,
Alex Deucher97b2e202015-04-20 16:51:00 -0400237 u32 major, u32 minor);
238
239const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
240 struct amdgpu_device *adev,
yanyang15fc3aee2015-05-22 14:39:35 -0400241 enum amd_ip_block_type type);
Alex Deucher97b2e202015-04-20 16:51:00 -0400242
243/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244struct amdgpu_buffer_funcs {
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes;
247
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw;
250
251 /* used for buffer migration */
Chunming Zhouc7ae72c2015-08-25 17:23:45 +0800252 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400253 /* src addr in bytes */
254 uint64_t src_offset,
255 /* dst addr in bytes */
256 uint64_t dst_offset,
257 /* number of byte to transfer */
258 uint32_t byte_count);
259
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes;
262
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw;
265
266 /* used for buffer clearing */
Chunming Zhou6e7a3842015-08-27 13:46:09 +0800267 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
Alex Deucher97b2e202015-04-20 16:51:00 -0400268 /* value to write to memory */
269 uint32_t src_data,
270 /* dst addr in bytes */
271 uint64_t dst_offset,
272 /* number of byte to fill */
273 uint32_t byte_count);
274};
275
276/* provided by hw blocks that can write ptes, e.g., sdma */
277struct amdgpu_vm_pte_funcs {
278 /* copy pte entries from GART */
279 void (*copy_pte)(struct amdgpu_ib *ib,
280 uint64_t pe, uint64_t src,
281 unsigned count);
282 /* write pte one entry at a time with addr mapping */
283 void (*write_pte)(struct amdgpu_ib *ib,
Christian Königb07c9d22015-11-30 13:26:07 +0100284 const dma_addr_t *pages_addr, uint64_t pe,
Alex Deucher97b2e202015-04-20 16:51:00 -0400285 uint64_t addr, unsigned count,
286 uint32_t incr, uint32_t flags);
287 /* for linear pte/pde updates without addr mapping */
288 void (*set_pte_pde)(struct amdgpu_ib *ib,
289 uint64_t pe,
290 uint64_t addr, unsigned count,
291 uint32_t incr, uint32_t flags);
292 /* pad the indirect buffer to the necessary number of dw */
293 void (*pad_ib)(struct amdgpu_ib *ib);
294};
295
296/* provided by the gmc block */
297struct amdgpu_gart_funcs {
298 /* flush the vm tlb via mmio */
299 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
300 uint32_t vmid);
301 /* write pte/pde updates using the cpu */
302 int (*set_pte_pde)(struct amdgpu_device *adev,
303 void *cpu_pt_addr, /* cpu addr of page table */
304 uint32_t gpu_page_idx, /* pte/pde to update */
305 uint64_t addr, /* addr to write into pte/pde */
306 uint32_t flags); /* access flags */
307};
308
309/* provided by the ih block */
310struct amdgpu_ih_funcs {
311 /* ring read/write ptr handling, called from interrupt context */
312 u32 (*get_wptr)(struct amdgpu_device *adev);
313 void (*decode_iv)(struct amdgpu_device *adev,
314 struct amdgpu_iv_entry *entry);
315 void (*set_rptr)(struct amdgpu_device *adev);
316};
317
318/* provided by hw blocks that expose a ring buffer for commands */
319struct amdgpu_ring_funcs {
320 /* ring read/write ptr handling */
321 u32 (*get_rptr)(struct amdgpu_ring *ring);
322 u32 (*get_wptr)(struct amdgpu_ring *ring);
323 void (*set_wptr)(struct amdgpu_ring *ring);
324 /* validating and patching of IBs */
325 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
326 /* command emit functions */
327 void (*emit_ib)(struct amdgpu_ring *ring,
328 struct amdgpu_ib *ib);
329 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
Chunming Zhou890ee232015-06-01 14:35:03 +0800330 uint64_t seq, unsigned flags);
Alex Deucher97b2e202015-04-20 16:51:00 -0400331 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
332 uint64_t pd_addr);
Christian Königd2edb072015-05-11 14:10:34 +0200333 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
Alex Deucher97b2e202015-04-20 16:51:00 -0400334 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
335 uint32_t gds_base, uint32_t gds_size,
336 uint32_t gws_base, uint32_t gws_size,
337 uint32_t oa_base, uint32_t oa_size);
338 /* testing functions */
339 int (*test_ring)(struct amdgpu_ring *ring);
340 int (*test_ib)(struct amdgpu_ring *ring);
Jammy Zhouedff0e22015-09-01 13:04:08 +0800341 /* insert NOP packets */
342 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
Alex Deucher97b2e202015-04-20 16:51:00 -0400343};
344
345/*
346 * BIOS.
347 */
348bool amdgpu_get_bios(struct amdgpu_device *adev);
349bool amdgpu_read_bios(struct amdgpu_device *adev);
350
351/*
352 * Dummy page
353 */
354struct amdgpu_dummy_page {
355 struct page *page;
356 dma_addr_t addr;
357};
358int amdgpu_dummy_page_init(struct amdgpu_device *adev);
359void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
360
361
362/*
363 * Clocks
364 */
365
366#define AMDGPU_MAX_PPLL 3
367
368struct amdgpu_clock {
369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
370 struct amdgpu_pll spll;
371 struct amdgpu_pll mpll;
372 /* 10 Khz units */
373 uint32_t default_mclk;
374 uint32_t default_sclk;
375 uint32_t default_dispclk;
376 uint32_t current_dispclk;
377 uint32_t dp_extclk;
378 uint32_t max_pixel_clock;
379};
380
381/*
382 * Fences.
383 */
384struct amdgpu_fence_driver {
Alex Deucher97b2e202015-04-20 16:51:00 -0400385 uint64_t gpu_addr;
386 volatile uint32_t *cpu_addr;
387 /* sync_seq is protected by ring emission lock */
Christian König5907a0d2016-01-18 15:16:53 +0100388 uint64_t sync_seq;
Alex Deucher97b2e202015-04-20 16:51:00 -0400389 atomic64_t last_seq;
390 bool initialized;
Alex Deucher97b2e202015-04-20 16:51:00 -0400391 struct amdgpu_irq_src *irq_src;
392 unsigned irq_type;
Christian Königc2776af2015-11-03 13:27:39 +0100393 struct timer_list fallback_timer;
monk.liu7f06c232015-07-30 18:28:12 +0800394 wait_queue_head_t fence_queue;
Alex Deucher97b2e202015-04-20 16:51:00 -0400395};
396
397/* some special values for the owner field */
398#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
399#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
Alex Deucher97b2e202015-04-20 16:51:00 -0400400
Chunming Zhou890ee232015-06-01 14:35:03 +0800401#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
402#define AMDGPU_FENCE_FLAG_INT (1 << 1)
403
Alex Deucher97b2e202015-04-20 16:51:00 -0400404struct amdgpu_fence {
405 struct fence base;
Chunming Zhou4cef9262015-08-05 19:52:14 +0800406
Alex Deucher97b2e202015-04-20 16:51:00 -0400407 /* RB, DMA, etc. */
408 struct amdgpu_ring *ring;
409 uint64_t seq;
410
411 /* filp or special value for fence creator */
412 void *owner;
413
414 wait_queue_t fence_wake;
415};
416
417struct amdgpu_user_fence {
418 /* write-back bo */
419 struct amdgpu_bo *bo;
420 /* write-back address offset to bo start */
421 uint32_t offset;
422};
423
424int amdgpu_fence_driver_init(struct amdgpu_device *adev);
425void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
426void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
427
Christian König4f839a22015-09-08 20:22:31 +0200428int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
Alex Deucher97b2e202015-04-20 16:51:00 -0400429int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
430 struct amdgpu_irq_src *irq_src,
431 unsigned irq_type);
Alex Deucher5ceb54c2015-08-05 12:41:48 -0400432void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
433void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -0400434int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
435 struct amdgpu_fence **fence);
436void amdgpu_fence_process(struct amdgpu_ring *ring);
437int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
438int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
439unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
440
Alex Deucher97b2e202015-04-20 16:51:00 -0400441/*
442 * TTM.
443 */
444struct amdgpu_mman {
445 struct ttm_bo_global_ref bo_global_ref;
446 struct drm_global_reference mem_global_ref;
447 struct ttm_bo_device bdev;
448 bool mem_global_referenced;
449 bool initialized;
450
451#if defined(CONFIG_DEBUG_FS)
452 struct dentry *vram;
453 struct dentry *gtt;
454#endif
455
456 /* buffer handling */
457 const struct amdgpu_buffer_funcs *buffer_funcs;
458 struct amdgpu_ring *buffer_funcs_ring;
459};
460
461int amdgpu_copy_buffer(struct amdgpu_ring *ring,
462 uint64_t src_offset,
463 uint64_t dst_offset,
464 uint32_t byte_count,
465 struct reservation_object *resv,
Chunming Zhouc7ae72c2015-08-25 17:23:45 +0800466 struct fence **fence);
Alex Deucher97b2e202015-04-20 16:51:00 -0400467int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
468
469struct amdgpu_bo_list_entry {
470 struct amdgpu_bo *robj;
471 struct ttm_validate_buffer tv;
472 struct amdgpu_bo_va *bo_va;
Alex Deucher97b2e202015-04-20 16:51:00 -0400473 uint32_t priority;
474};
475
476struct amdgpu_bo_va_mapping {
477 struct list_head list;
478 struct interval_tree_node it;
479 uint64_t offset;
480 uint32_t flags;
481};
482
483/* bo virtual addresses in a specific vm */
484struct amdgpu_bo_va {
Chunming Zhou69b576a2015-11-18 11:17:39 +0800485 struct mutex mutex;
Alex Deucher97b2e202015-04-20 16:51:00 -0400486 /* protected by bo being reserved */
487 struct list_head bo_list;
Chunming Zhoubb1e38a42015-08-03 18:19:38 +0800488 struct fence *last_pt_update;
Alex Deucher97b2e202015-04-20 16:51:00 -0400489 unsigned ref_count;
490
Christian König7fc11952015-07-30 11:53:42 +0200491 /* protected by vm mutex and spinlock */
Alex Deucher97b2e202015-04-20 16:51:00 -0400492 struct list_head vm_status;
493
Christian König7fc11952015-07-30 11:53:42 +0200494 /* mappings for this bo_va */
495 struct list_head invalids;
496 struct list_head valids;
497
Alex Deucher97b2e202015-04-20 16:51:00 -0400498 /* constant after initialization */
499 struct amdgpu_vm *vm;
500 struct amdgpu_bo *bo;
501};
502
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800503#define AMDGPU_GEM_DOMAIN_MAX 0x3
504
Alex Deucher97b2e202015-04-20 16:51:00 -0400505struct amdgpu_bo {
506 /* Protected by gem.mutex */
507 struct list_head list;
508 /* Protected by tbo.reserved */
Christian König1ea863f2015-12-18 22:13:12 +0100509 u32 prefered_domains;
510 u32 allowed_domains;
Chunming Zhou7e5a5472015-04-24 17:37:30 +0800511 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
Alex Deucher97b2e202015-04-20 16:51:00 -0400512 struct ttm_placement placement;
513 struct ttm_buffer_object tbo;
514 struct ttm_bo_kmap_obj kmap;
515 u64 flags;
516 unsigned pin_count;
517 void *kptr;
518 u64 tiling_flags;
519 u64 metadata_flags;
520 void *metadata;
521 u32 metadata_size;
522 /* list of all virtual address to which this bo
523 * is associated to
524 */
525 struct list_head va;
526 /* Constant after initialization */
527 struct amdgpu_device *adev;
528 struct drm_gem_object gem_base;
Christian König82b9c552015-11-27 16:49:00 +0100529 struct amdgpu_bo *parent;
Alex Deucher97b2e202015-04-20 16:51:00 -0400530
531 struct ttm_bo_kmap_obj dma_buf_vmap;
532 pid_t pid;
533 struct amdgpu_mn *mn;
534 struct list_head mn_list;
535};
536#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
537
538void amdgpu_gem_object_free(struct drm_gem_object *obj);
539int amdgpu_gem_object_open(struct drm_gem_object *obj,
540 struct drm_file *file_priv);
541void amdgpu_gem_object_close(struct drm_gem_object *obj,
542 struct drm_file *file_priv);
543unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
544struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
545struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
546 struct dma_buf_attachment *attach,
547 struct sg_table *sg);
548struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
549 struct drm_gem_object *gobj,
550 int flags);
551int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
552void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
553struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
554void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
555void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
556int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
557
558/* sub-allocation manager, it has to be protected by another lock.
559 * By conception this is an helper for other part of the driver
560 * like the indirect buffer or semaphore, which both have their
561 * locking.
562 *
563 * Principe is simple, we keep a list of sub allocation in offset
564 * order (first entry has offset == 0, last entry has the highest
565 * offset).
566 *
567 * When allocating new object we first check if there is room at
568 * the end total_size - (last_object_offset + last_object_size) >=
569 * alloc_size. If so we allocate new object there.
570 *
571 * When there is not enough room at the end, we start waiting for
572 * each sub object until we reach object_offset+object_size >=
573 * alloc_size, this object then become the sub object we return.
574 *
575 * Alignment can't be bigger than page size.
576 *
577 * Hole are not considered for allocation to keep things simple.
578 * Assumption is that there won't be hole (all object on same
579 * alignment).
580 */
581struct amdgpu_sa_manager {
582 wait_queue_head_t wq;
583 struct amdgpu_bo *bo;
584 struct list_head *hole;
585 struct list_head flist[AMDGPU_MAX_RINGS];
586 struct list_head olist;
587 unsigned size;
588 uint64_t gpu_addr;
589 void *cpu_ptr;
590 uint32_t domain;
591 uint32_t align;
592};
593
594struct amdgpu_sa_bo;
595
596/* sub-allocation buffer */
597struct amdgpu_sa_bo {
598 struct list_head olist;
599 struct list_head flist;
600 struct amdgpu_sa_manager *manager;
601 unsigned soffset;
602 unsigned eoffset;
Chunming Zhou4ce98912015-08-19 16:41:19 +0800603 struct fence *fence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400604};
605
606/*
607 * GEM objects.
608 */
609struct amdgpu_gem {
610 struct mutex mutex;
611 struct list_head objects;
612};
613
614int amdgpu_gem_init(struct amdgpu_device *adev);
615void amdgpu_gem_fini(struct amdgpu_device *adev);
616int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
617 int alignment, u32 initial_domain,
618 u64 flags, bool kernel,
619 struct drm_gem_object **obj);
620
621int amdgpu_mode_dumb_create(struct drm_file *file_priv,
622 struct drm_device *dev,
623 struct drm_mode_create_dumb *args);
624int amdgpu_mode_dumb_mmap(struct drm_file *filp,
625 struct drm_device *dev,
626 uint32_t handle, uint64_t *offset_p);
Alex Deucher97b2e202015-04-20 16:51:00 -0400627/*
628 * Synchronization
629 */
630struct amdgpu_sync {
Christian Königf91b3a62015-08-20 14:47:40 +0800631 DECLARE_HASHTABLE(fences, 4);
Chunming Zhou3c623382015-08-20 18:33:59 +0800632 struct fence *last_vm_update;
Alex Deucher97b2e202015-04-20 16:51:00 -0400633};
634
635void amdgpu_sync_create(struct amdgpu_sync *sync);
Christian König91e1a522015-07-06 22:06:40 +0200636int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
637 struct fence *f);
Alex Deucher97b2e202015-04-20 16:51:00 -0400638int amdgpu_sync_resv(struct amdgpu_device *adev,
639 struct amdgpu_sync *sync,
640 struct reservation_object *resv,
641 void *owner);
Christian Könige61235d2015-08-25 11:05:36 +0200642struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
Christian Königf91b3a62015-08-20 14:47:40 +0800643int amdgpu_sync_wait(struct amdgpu_sync *sync);
Christian König8a8f0b42016-02-03 15:11:39 +0100644void amdgpu_sync_free(struct amdgpu_sync *sync);
Alex Deucher97b2e202015-04-20 16:51:00 -0400645
646/*
647 * GART structures, functions & helpers
648 */
649struct amdgpu_mc;
650
651#define AMDGPU_GPU_PAGE_SIZE 4096
652#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
653#define AMDGPU_GPU_PAGE_SHIFT 12
654#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
655
656struct amdgpu_gart {
657 dma_addr_t table_addr;
658 struct amdgpu_bo *robj;
659 void *ptr;
660 unsigned num_gpu_pages;
661 unsigned num_cpu_pages;
662 unsigned table_size;
663 struct page **pages;
664 dma_addr_t *pages_addr;
665 bool ready;
666 const struct amdgpu_gart_funcs *gart_funcs;
667};
668
669int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
670void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
671int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
672void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
673int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
674void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
675int amdgpu_gart_init(struct amdgpu_device *adev);
676void amdgpu_gart_fini(struct amdgpu_device *adev);
677void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
678 int pages);
679int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
680 int pages, struct page **pagelist,
681 dma_addr_t *dma_addr, uint32_t flags);
682
683/*
684 * GPU MC structures, functions & helpers
685 */
686struct amdgpu_mc {
687 resource_size_t aper_size;
688 resource_size_t aper_base;
689 resource_size_t agp_base;
690 /* for some chips with <= 32MB we need to lie
691 * about vram size near mc fb location */
692 u64 mc_vram_size;
693 u64 visible_vram_size;
694 u64 gtt_size;
695 u64 gtt_start;
696 u64 gtt_end;
697 u64 vram_start;
698 u64 vram_end;
699 unsigned vram_width;
700 u64 real_vram_size;
701 int vram_mtrr;
702 u64 gtt_base_align;
703 u64 mc_mask;
704 const struct firmware *fw; /* MC firmware */
705 uint32_t fw_version;
706 struct amdgpu_irq_src vm_fault;
Ken Wang81c59f52015-06-03 21:02:01 +0800707 uint32_t vram_type;
Alex Deucher97b2e202015-04-20 16:51:00 -0400708};
709
710/*
711 * GPU doorbell structures, functions & helpers
712 */
713typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
714{
715 AMDGPU_DOORBELL_KIQ = 0x000,
716 AMDGPU_DOORBELL_HIQ = 0x001,
717 AMDGPU_DOORBELL_DIQ = 0x002,
718 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
719 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
720 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
721 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
722 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
723 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
724 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
725 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
726 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
727 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
728 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
729 AMDGPU_DOORBELL_IH = 0x1E8,
730 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
731 AMDGPU_DOORBELL_INVALID = 0xFFFF
732} AMDGPU_DOORBELL_ASSIGNMENT;
733
734struct amdgpu_doorbell {
735 /* doorbell mmio */
736 resource_size_t base;
737 resource_size_t size;
738 u32 __iomem *ptr;
739 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
740};
741
742void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
743 phys_addr_t *aperture_base,
744 size_t *aperture_size,
745 size_t *start_offset);
746
747/*
748 * IRQS.
749 */
750
751struct amdgpu_flip_work {
752 struct work_struct flip_work;
753 struct work_struct unpin_work;
754 struct amdgpu_device *adev;
755 int crtc_id;
756 uint64_t base;
757 struct drm_pending_vblank_event *event;
758 struct amdgpu_bo *old_rbo;
Christian König1ffd2652015-08-11 17:29:52 +0200759 struct fence *excl;
760 unsigned shared_count;
761 struct fence **shared;
Alex Deucher97b2e202015-04-20 16:51:00 -0400762};
763
764
765/*
766 * CP & rings.
767 */
768
769struct amdgpu_ib {
770 struct amdgpu_sa_bo *sa_bo;
771 uint32_t length_dw;
772 uint64_t gpu_addr;
773 uint32_t *ptr;
774 struct amdgpu_ring *ring;
775 struct amdgpu_fence *fence;
776 struct amdgpu_user_fence *user;
Christian König8d0a7ce2015-11-03 20:58:50 +0100777 bool grabbed_vmid;
Alex Deucher97b2e202015-04-20 16:51:00 -0400778 struct amdgpu_vm *vm;
Christian König3cb485f2015-05-11 15:34:59 +0200779 struct amdgpu_ctx *ctx;
Alex Deucher97b2e202015-04-20 16:51:00 -0400780 struct amdgpu_sync sync;
Alex Deucher97b2e202015-04-20 16:51:00 -0400781 uint32_t gds_base, gds_size;
782 uint32_t gws_base, gws_size;
783 uint32_t oa_base, oa_size;
Jammy Zhoude807f82015-05-11 23:41:41 +0800784 uint32_t flags;
Christian König5430a3f2015-07-21 18:02:21 +0200785 /* resulting sequence number */
786 uint64_t sequence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400787};
788
789enum amdgpu_ring_type {
790 AMDGPU_RING_TYPE_GFX,
791 AMDGPU_RING_TYPE_COMPUTE,
792 AMDGPU_RING_TYPE_SDMA,
793 AMDGPU_RING_TYPE_UVD,
794 AMDGPU_RING_TYPE_VCE
795};
796
Chunming Zhouc1b69ed2015-07-21 13:45:14 +0800797extern struct amd_sched_backend_ops amdgpu_sched_ops;
798
Christian König50838c82016-02-03 13:44:52 +0100799int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
800 struct amdgpu_job **job);
801void amdgpu_job_free(struct amdgpu_job *job);
Chunming Zhou3c704e92015-07-29 10:33:14 +0800802int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
803 struct amdgpu_ring *ring,
804 struct amdgpu_ib *ibs,
805 unsigned num_ibs,
Chunming Zhoubb977d32015-08-18 15:16:40 +0800806 int (*free_job)(struct amdgpu_job *),
Chunming Zhou17635522015-08-03 11:43:19 +0800807 void *owner,
808 struct fence **fence);
Chunming Zhou3c704e92015-07-29 10:33:14 +0800809
Alex Deucher97b2e202015-04-20 16:51:00 -0400810struct amdgpu_ring {
811 struct amdgpu_device *adev;
812 const struct amdgpu_ring_funcs *funcs;
813 struct amdgpu_fence_driver fence_drv;
Christian König4f839a22015-09-08 20:22:31 +0200814 struct amd_gpu_scheduler sched;
Alex Deucher97b2e202015-04-20 16:51:00 -0400815
Chunming Zhou176e1ab2015-07-24 10:49:47 +0800816 spinlock_t fence_lock;
Alex Deucher97b2e202015-04-20 16:51:00 -0400817 struct amdgpu_bo *ring_obj;
818 volatile uint32_t *ring;
819 unsigned rptr_offs;
820 u64 next_rptr_gpu_addr;
821 volatile u32 *next_rptr_cpu_addr;
822 unsigned wptr;
823 unsigned wptr_old;
824 unsigned ring_size;
Christian Königc7e6be22016-01-21 13:06:05 +0100825 unsigned max_dw;
Alex Deucher97b2e202015-04-20 16:51:00 -0400826 int count_dw;
Alex Deucher97b2e202015-04-20 16:51:00 -0400827 uint64_t gpu_addr;
828 uint32_t align_mask;
829 uint32_t ptr_mask;
830 bool ready;
831 u32 nop;
832 u32 idx;
Alex Deucher97b2e202015-04-20 16:51:00 -0400833 u32 me;
834 u32 pipe;
835 u32 queue;
836 struct amdgpu_bo *mqd_obj;
837 u32 doorbell_index;
838 bool use_doorbell;
839 unsigned wptr_offs;
840 unsigned next_rptr_offs;
841 unsigned fence_offs;
Christian König3cb485f2015-05-11 15:34:59 +0200842 struct amdgpu_ctx *current_ctx;
Alex Deucher97b2e202015-04-20 16:51:00 -0400843 enum amdgpu_ring_type type;
844 char name[16];
Chunming Zhou4274f5d2015-07-21 16:04:39 +0800845 bool is_pte_ring;
Alex Deucher97b2e202015-04-20 16:51:00 -0400846};
847
848/*
849 * VM
850 */
851
852/* maximum number of VMIDs */
853#define AMDGPU_NUM_VM 16
854
855/* number of entries in page table */
856#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
857
858/* PTBs (Page Table Blocks) need to be aligned to 32K */
859#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
860#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
861#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
862
863#define AMDGPU_PTE_VALID (1 << 0)
864#define AMDGPU_PTE_SYSTEM (1 << 1)
865#define AMDGPU_PTE_SNOOPED (1 << 2)
866
867/* VI only */
868#define AMDGPU_PTE_EXECUTABLE (1 << 4)
869
870#define AMDGPU_PTE_READABLE (1 << 5)
871#define AMDGPU_PTE_WRITEABLE (1 << 6)
872
873/* PTE (Page Table Entry) fragment field for different page sizes */
874#define AMDGPU_PTE_FRAG_4KB (0 << 7)
875#define AMDGPU_PTE_FRAG_64KB (4 << 7)
876#define AMDGPU_LOG2_PAGES_PER_FRAG 4
877
Christian Königd9c13152015-09-28 12:31:26 +0200878/* How to programm VM fault handling */
879#define AMDGPU_VM_FAULT_STOP_NEVER 0
880#define AMDGPU_VM_FAULT_STOP_FIRST 1
881#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
882
Alex Deucher97b2e202015-04-20 16:51:00 -0400883struct amdgpu_vm_pt {
Christian Königee1782c2015-12-11 21:01:23 +0100884 struct amdgpu_bo_list_entry entry;
885 uint64_t addr;
Alex Deucher97b2e202015-04-20 16:51:00 -0400886};
887
888struct amdgpu_vm_id {
889 unsigned id;
890 uint64_t pd_gpu_addr;
891 /* last flushed PD/PT update */
Chunming Zhou3c623382015-08-20 18:33:59 +0800892 struct fence *flushed_updates;
Alex Deucher97b2e202015-04-20 16:51:00 -0400893};
894
895struct amdgpu_vm {
Christian König25cfc3c2015-12-19 19:42:05 +0100896 /* tree of virtual addresses mapped */
897 spinlock_t it_lock;
Alex Deucher97b2e202015-04-20 16:51:00 -0400898 struct rb_root va;
899
Christian König7fc11952015-07-30 11:53:42 +0200900 /* protecting invalidated */
Alex Deucher97b2e202015-04-20 16:51:00 -0400901 spinlock_t status_lock;
902
903 /* BOs moved, but not yet updated in the PT */
904 struct list_head invalidated;
905
Christian König7fc11952015-07-30 11:53:42 +0200906 /* BOs cleared in the PT because of a move */
907 struct list_head cleared;
908
909 /* BO mappings freed, but not yet updated in the PT */
Alex Deucher97b2e202015-04-20 16:51:00 -0400910 struct list_head freed;
911
912 /* contains the page directory */
913 struct amdgpu_bo *page_directory;
914 unsigned max_pde_used;
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +0200915 struct fence *page_directory_fence;
Alex Deucher97b2e202015-04-20 16:51:00 -0400916
917 /* array of page tables, one for each page directory entry */
918 struct amdgpu_vm_pt *page_tables;
919
920 /* for id and flush management per ring */
921 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
Christian König25cfc3c2015-12-19 19:42:05 +0100922
jimqu81d75a32015-12-04 17:17:00 +0800923 /* protecting freed */
924 spinlock_t freed_lock;
Alex Deucher97b2e202015-04-20 16:51:00 -0400925};
926
Christian Königa9a78b32016-01-21 10:19:11 +0100927struct amdgpu_vm_manager_id {
928 struct list_head list;
929 struct fence *active;
930 atomic_long_t owner;
931};
Christian König8d0a7ce2015-11-03 20:58:50 +0100932
Christian Königa9a78b32016-01-21 10:19:11 +0100933struct amdgpu_vm_manager {
934 /* Handling of VMIDs */
935 struct mutex lock;
936 unsigned num_ids;
937 struct list_head ids_lru;
938 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
Christian König1c16c0a2015-11-14 21:31:40 +0100939
Christian König8b4fb002015-11-15 16:04:16 +0100940 uint32_t max_pfn;
Alex Deucher97b2e202015-04-20 16:51:00 -0400941 /* vram base address for page table entry */
Christian König8b4fb002015-11-15 16:04:16 +0100942 u64 vram_base_offset;
Alex Deucher97b2e202015-04-20 16:51:00 -0400943 /* is vm enabled? */
Christian König8b4fb002015-11-15 16:04:16 +0100944 bool enabled;
Alex Deucher97b2e202015-04-20 16:51:00 -0400945 /* vm pte handling */
946 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
947 struct amdgpu_ring *vm_pte_funcs_ring;
948};
949
Christian Königa9a78b32016-01-21 10:19:11 +0100950void amdgpu_vm_manager_init(struct amdgpu_device *adev);
Christian Königea89f8c2015-11-15 20:52:06 +0100951void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
Christian König8b4fb002015-11-15 16:04:16 +0100952int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
953void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
Christian König56467eb2015-12-11 15:16:32 +0100954void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
955 struct list_head *validated,
956 struct amdgpu_bo_list_entry *entry);
Christian Königee1782c2015-12-11 21:01:23 +0100957void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
Christian Königeceb8a12016-01-11 15:35:21 +0100958void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
959 struct amdgpu_vm *vm);
Christian König8b4fb002015-11-15 16:04:16 +0100960int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
Christian König94dd0a42016-01-18 17:01:42 +0100961 struct amdgpu_sync *sync, struct fence *fence);
Christian König8b4fb002015-11-15 16:04:16 +0100962void amdgpu_vm_flush(struct amdgpu_ring *ring,
963 struct amdgpu_vm *vm,
964 struct fence *updates);
Christian Königb07c9d22015-11-30 13:26:07 +0100965uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
Christian König8b4fb002015-11-15 16:04:16 +0100966int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
967 struct amdgpu_vm *vm);
968int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
969 struct amdgpu_vm *vm);
970int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
971 struct amdgpu_sync *sync);
972int amdgpu_vm_bo_update(struct amdgpu_device *adev,
973 struct amdgpu_bo_va *bo_va,
974 struct ttm_mem_reg *mem);
975void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
976 struct amdgpu_bo *bo);
977struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
978 struct amdgpu_bo *bo);
979struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
980 struct amdgpu_vm *vm,
981 struct amdgpu_bo *bo);
982int amdgpu_vm_bo_map(struct amdgpu_device *adev,
983 struct amdgpu_bo_va *bo_va,
984 uint64_t addr, uint64_t offset,
985 uint64_t size, uint32_t flags);
986int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
987 struct amdgpu_bo_va *bo_va,
988 uint64_t addr);
989void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
990 struct amdgpu_bo_va *bo_va);
991int amdgpu_vm_free_job(struct amdgpu_job *job);
992
Alex Deucher97b2e202015-04-20 16:51:00 -0400993/*
994 * context related structures
995 */
996
Christian König21c16bf2015-07-07 17:24:49 +0200997struct amdgpu_ctx_ring {
Christian König91404fb2015-08-05 18:33:21 +0200998 uint64_t sequence;
Chunming Zhou37cd0ca2015-12-10 15:45:11 +0800999 struct fence **fences;
Christian König91404fb2015-08-05 18:33:21 +02001000 struct amd_sched_entity entity;
Christian König21c16bf2015-07-07 17:24:49 +02001001};
1002
Alex Deucher97b2e202015-04-20 16:51:00 -04001003struct amdgpu_ctx {
Alex Deucher0b492a42015-08-16 22:48:26 -04001004 struct kref refcount;
Chunming Zhou9cb7e5a2015-07-21 13:17:19 +08001005 struct amdgpu_device *adev;
Alex Deucher0b492a42015-08-16 22:48:26 -04001006 unsigned reset_counter;
Christian König21c16bf2015-07-07 17:24:49 +02001007 spinlock_t ring_lock;
Chunming Zhou37cd0ca2015-12-10 15:45:11 +08001008 struct fence **fences;
Christian König21c16bf2015-07-07 17:24:49 +02001009 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
Alex Deucher97b2e202015-04-20 16:51:00 -04001010};
1011
1012struct amdgpu_ctx_mgr {
Alex Deucher0b492a42015-08-16 22:48:26 -04001013 struct amdgpu_device *adev;
1014 struct mutex lock;
1015 /* protected by lock */
1016 struct idr ctx_handles;
Alex Deucher97b2e202015-04-20 16:51:00 -04001017};
1018
Chunming Zhoud033a6d2015-11-05 15:23:09 +08001019int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
Christian König47f38502015-08-04 17:51:05 +02001020 struct amdgpu_ctx *ctx);
1021void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
Alex Deucher0b492a42015-08-16 22:48:26 -04001022
Alex Deucher0b492a42015-08-16 22:48:26 -04001023struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1024int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1025
Christian König21c16bf2015-07-07 17:24:49 +02001026uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
Christian Königce882e62015-08-19 15:00:55 +02001027 struct fence *fence);
Christian König21c16bf2015-07-07 17:24:49 +02001028struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1029 struct amdgpu_ring *ring, uint64_t seq);
1030
Alex Deucher0b492a42015-08-16 22:48:26 -04001031int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1032 struct drm_file *filp);
1033
Christian Königefd4ccb2015-08-04 16:20:31 +02001034void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1035void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
Alex Deucher0b492a42015-08-16 22:48:26 -04001036
Alex Deucher97b2e202015-04-20 16:51:00 -04001037/*
1038 * file private structure
1039 */
1040
1041struct amdgpu_fpriv {
1042 struct amdgpu_vm vm;
1043 struct mutex bo_list_lock;
1044 struct idr bo_list_handles;
Alex Deucher0b492a42015-08-16 22:48:26 -04001045 struct amdgpu_ctx_mgr ctx_mgr;
Alex Deucher97b2e202015-04-20 16:51:00 -04001046};
1047
1048/*
1049 * residency list
1050 */
1051
1052struct amdgpu_bo_list {
1053 struct mutex lock;
1054 struct amdgpu_bo *gds_obj;
1055 struct amdgpu_bo *gws_obj;
1056 struct amdgpu_bo *oa_obj;
1057 bool has_userptr;
1058 unsigned num_entries;
1059 struct amdgpu_bo_list_entry *array;
1060};
1061
1062struct amdgpu_bo_list *
1063amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
Christian König636ce252015-12-18 21:26:47 +01001064void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1065 struct list_head *validated);
Alex Deucher97b2e202015-04-20 16:51:00 -04001066void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1067void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1068
1069/*
1070 * GFX stuff
1071 */
1072#include "clearstate_defs.h"
1073
1074struct amdgpu_rlc {
1075 /* for power gating */
1076 struct amdgpu_bo *save_restore_obj;
1077 uint64_t save_restore_gpu_addr;
1078 volatile uint32_t *sr_ptr;
1079 const u32 *reg_list;
1080 u32 reg_list_size;
1081 /* for clear state */
1082 struct amdgpu_bo *clear_state_obj;
1083 uint64_t clear_state_gpu_addr;
1084 volatile uint32_t *cs_ptr;
1085 const struct cs_section_def *cs_data;
1086 u32 clear_state_size;
1087 /* for cp tables */
1088 struct amdgpu_bo *cp_table_obj;
1089 uint64_t cp_table_gpu_addr;
1090 volatile uint32_t *cp_table_ptr;
1091 u32 cp_table_size;
1092};
1093
1094struct amdgpu_mec {
1095 struct amdgpu_bo *hpd_eop_obj;
1096 u64 hpd_eop_gpu_addr;
1097 u32 num_pipe;
1098 u32 num_mec;
1099 u32 num_queue;
1100};
1101
1102/*
1103 * GPU scratch registers structures, functions & helpers
1104 */
1105struct amdgpu_scratch {
1106 unsigned num_reg;
1107 uint32_t reg_base;
1108 bool free[32];
1109 uint32_t reg[32];
1110};
1111
1112/*
1113 * GFX configurations
1114 */
1115struct amdgpu_gca_config {
1116 unsigned max_shader_engines;
1117 unsigned max_tile_pipes;
1118 unsigned max_cu_per_sh;
1119 unsigned max_sh_per_se;
1120 unsigned max_backends_per_se;
1121 unsigned max_texture_channel_caches;
1122 unsigned max_gprs;
1123 unsigned max_gs_threads;
1124 unsigned max_hw_contexts;
1125 unsigned sc_prim_fifo_size_frontend;
1126 unsigned sc_prim_fifo_size_backend;
1127 unsigned sc_hiz_tile_fifo_size;
1128 unsigned sc_earlyz_tile_fifo_size;
1129
1130 unsigned num_tile_pipes;
1131 unsigned backend_enable_mask;
1132 unsigned mem_max_burst_length_bytes;
1133 unsigned mem_row_size_in_kb;
1134 unsigned shader_engine_tile_size;
1135 unsigned num_gpus;
1136 unsigned multi_gpu_tile_size;
1137 unsigned mc_arb_ramcfg;
1138 unsigned gb_addr_config;
1139
1140 uint32_t tile_mode_array[32];
1141 uint32_t macrotile_mode_array[16];
1142};
1143
1144struct amdgpu_gfx {
1145 struct mutex gpu_clock_mutex;
1146 struct amdgpu_gca_config config;
1147 struct amdgpu_rlc rlc;
1148 struct amdgpu_mec mec;
1149 struct amdgpu_scratch scratch;
1150 const struct firmware *me_fw; /* ME firmware */
1151 uint32_t me_fw_version;
1152 const struct firmware *pfp_fw; /* PFP firmware */
1153 uint32_t pfp_fw_version;
1154 const struct firmware *ce_fw; /* CE firmware */
1155 uint32_t ce_fw_version;
1156 const struct firmware *rlc_fw; /* RLC firmware */
1157 uint32_t rlc_fw_version;
1158 const struct firmware *mec_fw; /* MEC firmware */
1159 uint32_t mec_fw_version;
1160 const struct firmware *mec2_fw; /* MEC2 firmware */
1161 uint32_t mec2_fw_version;
Ken Wang02558a02015-06-03 19:52:06 +08001162 uint32_t me_feature_version;
1163 uint32_t ce_feature_version;
1164 uint32_t pfp_feature_version;
Jammy Zhou351643d2015-08-04 10:43:50 +08001165 uint32_t rlc_feature_version;
1166 uint32_t mec_feature_version;
1167 uint32_t mec2_feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001168 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1169 unsigned num_gfx_rings;
1170 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1171 unsigned num_compute_rings;
1172 struct amdgpu_irq_src eop_irq;
1173 struct amdgpu_irq_src priv_reg_irq;
1174 struct amdgpu_irq_src priv_inst_irq;
1175 /* gfx status */
1176 uint32_t gfx_current_status;
Ken Wanga101a892015-06-03 17:47:54 +08001177 /* ce ram size*/
1178 unsigned ce_ram_size;
Alex Deucher97b2e202015-04-20 16:51:00 -04001179};
1180
1181int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1182 unsigned size, struct amdgpu_ib *ib);
1183void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1184int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1185 struct amdgpu_ib *ib, void *owner);
1186int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1187void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1188int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
Alex Deucher97b2e202015-04-20 16:51:00 -04001189int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
Jammy Zhouedff0e22015-09-01 13:04:08 +08001190void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
Alex Deucher97b2e202015-04-20 16:51:00 -04001191void amdgpu_ring_commit(struct amdgpu_ring *ring);
Alex Deucher97b2e202015-04-20 16:51:00 -04001192void amdgpu_ring_undo(struct amdgpu_ring *ring);
Alex Deucher97b2e202015-04-20 16:51:00 -04001193unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1194 uint32_t **data);
1195int amdgpu_ring_restore(struct amdgpu_ring *ring,
1196 unsigned size, uint32_t *data);
1197int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1198 unsigned ring_size, u32 nop, u32 align_mask,
1199 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1200 enum amdgpu_ring_type ring_type);
1201void amdgpu_ring_fini(struct amdgpu_ring *ring);
Christian König8120b612015-10-22 11:29:33 +02001202struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
Alex Deucher97b2e202015-04-20 16:51:00 -04001203
1204/*
1205 * CS.
1206 */
1207struct amdgpu_cs_chunk {
1208 uint32_t chunk_id;
1209 uint32_t length_dw;
1210 uint32_t *kdata;
Alex Deucher97b2e202015-04-20 16:51:00 -04001211};
1212
1213struct amdgpu_cs_parser {
1214 struct amdgpu_device *adev;
1215 struct drm_file *filp;
Christian König3cb485f2015-05-11 15:34:59 +02001216 struct amdgpu_ctx *ctx;
Christian Königc3cca412015-12-15 14:41:33 +01001217
Alex Deucher97b2e202015-04-20 16:51:00 -04001218 /* chunks */
1219 unsigned nchunks;
1220 struct amdgpu_cs_chunk *chunks;
Alex Deucher97b2e202015-04-20 16:51:00 -04001221
Christian König50838c82016-02-03 13:44:52 +01001222 /* scheduler job object */
1223 struct amdgpu_job *job;
Alex Deucher97b2e202015-04-20 16:51:00 -04001224
Christian Königc3cca412015-12-15 14:41:33 +01001225 /* buffer objects */
1226 struct ww_acquire_ctx ticket;
1227 struct amdgpu_bo_list *bo_list;
1228 struct amdgpu_bo_list_entry vm_pd;
1229 struct list_head validated;
1230 struct fence *fence;
1231 uint64_t bytes_moved_threshold;
1232 uint64_t bytes_moved;
Alex Deucher97b2e202015-04-20 16:51:00 -04001233
1234 /* user fence */
Christian König91acbeb2015-12-14 16:42:31 +01001235 struct amdgpu_bo_list_entry uf_entry;
Alex Deucher97b2e202015-04-20 16:51:00 -04001236};
1237
Chunming Zhoubb977d32015-08-18 15:16:40 +08001238struct amdgpu_job {
1239 struct amd_sched_job base;
1240 struct amdgpu_device *adev;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001241 struct amdgpu_ib *ibs;
1242 uint32_t num_ibs;
Christian Könige2840222015-11-05 19:49:48 +01001243 void *owner;
Chunming Zhoubb977d32015-08-18 15:16:40 +08001244 struct amdgpu_user_fence uf;
Junwei Zhang4c7eb912015-09-09 09:05:55 +08001245 int (*free_job)(struct amdgpu_job *job);
Chunming Zhoubb977d32015-08-18 15:16:40 +08001246};
Junwei Zhanga6db8a32015-09-09 09:21:19 +08001247#define to_amdgpu_job(sched_job) \
1248 container_of((sched_job), struct amdgpu_job, base)
Chunming Zhoubb977d32015-08-18 15:16:40 +08001249
Christian König7270f832016-01-31 11:00:41 +01001250static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1251 uint32_t ib_idx, int idx)
Alex Deucher97b2e202015-04-20 16:51:00 -04001252{
Christian König50838c82016-02-03 13:44:52 +01001253 return p->job->ibs[ib_idx].ptr[idx];
Alex Deucher97b2e202015-04-20 16:51:00 -04001254}
1255
Christian König7270f832016-01-31 11:00:41 +01001256static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1257 uint32_t ib_idx, int idx,
1258 uint32_t value)
1259{
Christian König50838c82016-02-03 13:44:52 +01001260 p->job->ibs[ib_idx].ptr[idx] = value;
Christian König7270f832016-01-31 11:00:41 +01001261}
1262
Alex Deucher97b2e202015-04-20 16:51:00 -04001263/*
1264 * Writeback
1265 */
1266#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1267
1268struct amdgpu_wb {
1269 struct amdgpu_bo *wb_obj;
1270 volatile uint32_t *wb;
1271 uint64_t gpu_addr;
1272 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1273 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1274};
1275
1276int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1277void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1278
Alex Deucher97b2e202015-04-20 16:51:00 -04001279
Alex Deucher97b2e202015-04-20 16:51:00 -04001280
1281enum amdgpu_int_thermal_type {
1282 THERMAL_TYPE_NONE,
1283 THERMAL_TYPE_EXTERNAL,
1284 THERMAL_TYPE_EXTERNAL_GPIO,
1285 THERMAL_TYPE_RV6XX,
1286 THERMAL_TYPE_RV770,
1287 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1288 THERMAL_TYPE_EVERGREEN,
1289 THERMAL_TYPE_SUMO,
1290 THERMAL_TYPE_NI,
1291 THERMAL_TYPE_SI,
1292 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1293 THERMAL_TYPE_CI,
1294 THERMAL_TYPE_KV,
1295};
1296
1297enum amdgpu_dpm_auto_throttle_src {
1298 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1299 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1300};
1301
1302enum amdgpu_dpm_event_src {
1303 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1304 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1305 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1306 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1307 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1308};
1309
1310#define AMDGPU_MAX_VCE_LEVELS 6
1311
1312enum amdgpu_vce_level {
1313 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1314 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1315 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1316 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1317 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1318 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1319};
1320
1321struct amdgpu_ps {
1322 u32 caps; /* vbios flags */
1323 u32 class; /* vbios flags */
1324 u32 class2; /* vbios flags */
1325 /* UVD clocks */
1326 u32 vclk;
1327 u32 dclk;
1328 /* VCE clocks */
1329 u32 evclk;
1330 u32 ecclk;
1331 bool vce_active;
1332 enum amdgpu_vce_level vce_level;
1333 /* asic priv */
1334 void *ps_priv;
1335};
1336
1337struct amdgpu_dpm_thermal {
1338 /* thermal interrupt work */
1339 struct work_struct work;
1340 /* low temperature threshold */
1341 int min_temp;
1342 /* high temperature threshold */
1343 int max_temp;
1344 /* was last interrupt low to high or high to low */
1345 bool high_to_low;
1346 /* interrupt source */
1347 struct amdgpu_irq_src irq;
1348};
1349
1350enum amdgpu_clk_action
1351{
1352 AMDGPU_SCLK_UP = 1,
1353 AMDGPU_SCLK_DOWN
1354};
1355
1356struct amdgpu_blacklist_clocks
1357{
1358 u32 sclk;
1359 u32 mclk;
1360 enum amdgpu_clk_action action;
1361};
1362
1363struct amdgpu_clock_and_voltage_limits {
1364 u32 sclk;
1365 u32 mclk;
1366 u16 vddc;
1367 u16 vddci;
1368};
1369
1370struct amdgpu_clock_array {
1371 u32 count;
1372 u32 *values;
1373};
1374
1375struct amdgpu_clock_voltage_dependency_entry {
1376 u32 clk;
1377 u16 v;
1378};
1379
1380struct amdgpu_clock_voltage_dependency_table {
1381 u32 count;
1382 struct amdgpu_clock_voltage_dependency_entry *entries;
1383};
1384
1385union amdgpu_cac_leakage_entry {
1386 struct {
1387 u16 vddc;
1388 u32 leakage;
1389 };
1390 struct {
1391 u16 vddc1;
1392 u16 vddc2;
1393 u16 vddc3;
1394 };
1395};
1396
1397struct amdgpu_cac_leakage_table {
1398 u32 count;
1399 union amdgpu_cac_leakage_entry *entries;
1400};
1401
1402struct amdgpu_phase_shedding_limits_entry {
1403 u16 voltage;
1404 u32 sclk;
1405 u32 mclk;
1406};
1407
1408struct amdgpu_phase_shedding_limits_table {
1409 u32 count;
1410 struct amdgpu_phase_shedding_limits_entry *entries;
1411};
1412
1413struct amdgpu_uvd_clock_voltage_dependency_entry {
1414 u32 vclk;
1415 u32 dclk;
1416 u16 v;
1417};
1418
1419struct amdgpu_uvd_clock_voltage_dependency_table {
1420 u8 count;
1421 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1422};
1423
1424struct amdgpu_vce_clock_voltage_dependency_entry {
1425 u32 ecclk;
1426 u32 evclk;
1427 u16 v;
1428};
1429
1430struct amdgpu_vce_clock_voltage_dependency_table {
1431 u8 count;
1432 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1433};
1434
1435struct amdgpu_ppm_table {
1436 u8 ppm_design;
1437 u16 cpu_core_number;
1438 u32 platform_tdp;
1439 u32 small_ac_platform_tdp;
1440 u32 platform_tdc;
1441 u32 small_ac_platform_tdc;
1442 u32 apu_tdp;
1443 u32 dgpu_tdp;
1444 u32 dgpu_ulv_power;
1445 u32 tj_max;
1446};
1447
1448struct amdgpu_cac_tdp_table {
1449 u16 tdp;
1450 u16 configurable_tdp;
1451 u16 tdc;
1452 u16 battery_power_limit;
1453 u16 small_power_limit;
1454 u16 low_cac_leakage;
1455 u16 high_cac_leakage;
1456 u16 maximum_power_delivery_limit;
1457};
1458
1459struct amdgpu_dpm_dynamic_state {
1460 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1461 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1463 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1464 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1465 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1466 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1467 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1468 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1469 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1470 struct amdgpu_clock_array valid_sclk_values;
1471 struct amdgpu_clock_array valid_mclk_values;
1472 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1473 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1474 u32 mclk_sclk_ratio;
1475 u32 sclk_mclk_delta;
1476 u16 vddc_vddci_delta;
1477 u16 min_vddc_for_pcie_gen2;
1478 struct amdgpu_cac_leakage_table cac_leakage_table;
1479 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1480 struct amdgpu_ppm_table *ppm_table;
1481 struct amdgpu_cac_tdp_table *cac_tdp_table;
1482};
1483
1484struct amdgpu_dpm_fan {
1485 u16 t_min;
1486 u16 t_med;
1487 u16 t_high;
1488 u16 pwm_min;
1489 u16 pwm_med;
1490 u16 pwm_high;
1491 u8 t_hyst;
1492 u32 cycle_delay;
1493 u16 t_max;
1494 u8 control_mode;
1495 u16 default_max_fan_pwm;
1496 u16 default_fan_output_sensitivity;
1497 u16 fan_output_sensitivity;
1498 bool ucode_fan_control;
1499};
1500
1501enum amdgpu_pcie_gen {
1502 AMDGPU_PCIE_GEN1 = 0,
1503 AMDGPU_PCIE_GEN2 = 1,
1504 AMDGPU_PCIE_GEN3 = 2,
1505 AMDGPU_PCIE_GEN_INVALID = 0xffff
1506};
1507
1508enum amdgpu_dpm_forced_level {
1509 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1510 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1511 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
Eric Huangf3898ea2015-12-11 16:24:34 -05001512 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
Alex Deucher97b2e202015-04-20 16:51:00 -04001513};
1514
1515struct amdgpu_vce_state {
1516 /* vce clocks */
1517 u32 evclk;
1518 u32 ecclk;
1519 /* gpu clocks */
1520 u32 sclk;
1521 u32 mclk;
1522 u8 clk_idx;
1523 u8 pstate;
1524};
1525
1526struct amdgpu_dpm_funcs {
1527 int (*get_temperature)(struct amdgpu_device *adev);
1528 int (*pre_set_power_state)(struct amdgpu_device *adev);
1529 int (*set_power_state)(struct amdgpu_device *adev);
1530 void (*post_set_power_state)(struct amdgpu_device *adev);
1531 void (*display_configuration_changed)(struct amdgpu_device *adev);
1532 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1533 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1534 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1535 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1536 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1537 bool (*vblank_too_short)(struct amdgpu_device *adev);
1538 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
Sonny Jiangb7a07762015-05-28 15:47:53 -04001539 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
Alex Deucher97b2e202015-04-20 16:51:00 -04001540 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1541 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1542 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1543 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1544 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1545};
1546
1547struct amdgpu_dpm {
1548 struct amdgpu_ps *ps;
1549 /* number of valid power states */
1550 int num_ps;
1551 /* current power state that is active */
1552 struct amdgpu_ps *current_ps;
1553 /* requested power state */
1554 struct amdgpu_ps *requested_ps;
1555 /* boot up power state */
1556 struct amdgpu_ps *boot_ps;
1557 /* default uvd power state */
1558 struct amdgpu_ps *uvd_ps;
1559 /* vce requirements */
1560 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1561 enum amdgpu_vce_level vce_level;
Rex Zhu3a2c7882015-08-25 15:57:43 +08001562 enum amd_pm_state_type state;
1563 enum amd_pm_state_type user_state;
Alex Deucher97b2e202015-04-20 16:51:00 -04001564 u32 platform_caps;
1565 u32 voltage_response_time;
1566 u32 backbias_response_time;
1567 void *priv;
1568 u32 new_active_crtcs;
1569 int new_active_crtc_count;
1570 u32 current_active_crtcs;
1571 int current_active_crtc_count;
1572 struct amdgpu_dpm_dynamic_state dyn_state;
1573 struct amdgpu_dpm_fan fan;
1574 u32 tdp_limit;
1575 u32 near_tdp_limit;
1576 u32 near_tdp_limit_adjusted;
1577 u32 sq_ramping_threshold;
1578 u32 cac_leakage;
1579 u16 tdp_od_limit;
1580 u32 tdp_adjustment;
1581 u16 load_line_slope;
1582 bool power_control;
1583 bool ac_power;
1584 /* special states active */
1585 bool thermal_active;
1586 bool uvd_active;
1587 bool vce_active;
1588 /* thermal handling */
1589 struct amdgpu_dpm_thermal thermal;
1590 /* forced levels */
1591 enum amdgpu_dpm_forced_level forced_level;
1592};
1593
1594struct amdgpu_pm {
1595 struct mutex mutex;
Alex Deucher97b2e202015-04-20 16:51:00 -04001596 u32 current_sclk;
1597 u32 current_mclk;
1598 u32 default_sclk;
1599 u32 default_mclk;
1600 struct amdgpu_i2c_chan *i2c_bus;
1601 /* internal thermal controller on rv6xx+ */
1602 enum amdgpu_int_thermal_type int_thermal_type;
1603 struct device *int_hwmon_dev;
1604 /* fan control parameters */
1605 bool no_fan;
1606 u8 fan_pulses_per_revolution;
1607 u8 fan_min_rpm;
1608 u8 fan_max_rpm;
1609 /* dpm */
1610 bool dpm_enabled;
Alex Deucherc86f5ebf2015-10-23 10:45:14 -04001611 bool sysfs_initialized;
Alex Deucher97b2e202015-04-20 16:51:00 -04001612 struct amdgpu_dpm dpm;
1613 const struct firmware *fw; /* SMC firmware */
1614 uint32_t fw_version;
1615 const struct amdgpu_dpm_funcs *funcs;
Alex Deucherd0dd7f02015-11-11 19:45:06 -05001616 uint32_t pcie_gen_mask;
1617 uint32_t pcie_mlw_mask;
Rex Zhu7fb72a12015-11-19 13:35:30 +08001618 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
Alex Deucher97b2e202015-04-20 16:51:00 -04001619};
1620
Alex Deucherd0dd7f02015-11-11 19:45:06 -05001621void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1622
Alex Deucher97b2e202015-04-20 16:51:00 -04001623/*
1624 * UVD
1625 */
1626#define AMDGPU_MAX_UVD_HANDLES 10
1627#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1628#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1629#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1630
1631struct amdgpu_uvd {
1632 struct amdgpu_bo *vcpu_bo;
1633 void *cpu_addr;
1634 uint64_t gpu_addr;
Alex Deucher97b2e202015-04-20 16:51:00 -04001635 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1636 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1637 struct delayed_work idle_work;
1638 const struct firmware *fw; /* UVD firmware */
1639 struct amdgpu_ring ring;
1640 struct amdgpu_irq_src irq;
1641 bool address_64_bit;
1642};
1643
1644/*
1645 * VCE
1646 */
1647#define AMDGPU_MAX_VCE_HANDLES 16
Alex Deucher97b2e202015-04-20 16:51:00 -04001648#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1649
Alex Deucher6a585772015-07-10 14:16:24 -04001650#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1651#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1652
Alex Deucher97b2e202015-04-20 16:51:00 -04001653struct amdgpu_vce {
1654 struct amdgpu_bo *vcpu_bo;
1655 uint64_t gpu_addr;
1656 unsigned fw_version;
1657 unsigned fb_version;
1658 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1659 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
Christian Königf1689ec2015-06-11 20:56:18 +02001660 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
Alex Deucher97b2e202015-04-20 16:51:00 -04001661 struct delayed_work idle_work;
1662 const struct firmware *fw; /* VCE firmware */
1663 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1664 struct amdgpu_irq_src irq;
Alex Deucher6a585772015-07-10 14:16:24 -04001665 unsigned harvest_config;
Alex Deucher97b2e202015-04-20 16:51:00 -04001666};
1667
1668/*
1669 * SDMA
1670 */
Alex Deucherc113ea12015-10-08 16:30:37 -04001671struct amdgpu_sdma_instance {
Alex Deucher97b2e202015-04-20 16:51:00 -04001672 /* SDMA firmware */
1673 const struct firmware *fw;
1674 uint32_t fw_version;
Jammy Zhoucfa21042015-08-04 10:50:47 +08001675 uint32_t feature_version;
Alex Deucher97b2e202015-04-20 16:51:00 -04001676
1677 struct amdgpu_ring ring;
Jammy Zhou18111de2015-08-31 14:06:39 +08001678 bool burst_nop;
Alex Deucher97b2e202015-04-20 16:51:00 -04001679};
1680
Alex Deucherc113ea12015-10-08 16:30:37 -04001681struct amdgpu_sdma {
1682 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1683 struct amdgpu_irq_src trap_irq;
1684 struct amdgpu_irq_src illegal_inst_irq;
1685 int num_instances;
1686};
1687
Alex Deucher97b2e202015-04-20 16:51:00 -04001688/*
1689 * Firmware
1690 */
1691struct amdgpu_firmware {
1692 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1693 bool smu_load;
1694 struct amdgpu_bo *fw_buf;
1695 unsigned int fw_size;
1696};
1697
1698/*
1699 * Benchmarking
1700 */
1701void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1702
1703
1704/*
1705 * Testing
1706 */
1707void amdgpu_test_moves(struct amdgpu_device *adev);
1708void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1709 struct amdgpu_ring *cpA,
1710 struct amdgpu_ring *cpB);
1711void amdgpu_test_syncing(struct amdgpu_device *adev);
1712
1713/*
1714 * MMU Notifier
1715 */
1716#if defined(CONFIG_MMU_NOTIFIER)
1717int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1718void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1719#else
Harry Wentland1d1106b2015-07-15 07:10:41 -04001720static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
Alex Deucher97b2e202015-04-20 16:51:00 -04001721{
1722 return -ENODEV;
1723}
Harry Wentland1d1106b2015-07-15 07:10:41 -04001724static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
Alex Deucher97b2e202015-04-20 16:51:00 -04001725#endif
1726
1727/*
1728 * Debugfs
1729 */
1730struct amdgpu_debugfs {
1731 struct drm_info_list *files;
1732 unsigned num_files;
1733};
1734
1735int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1736 struct drm_info_list *files,
1737 unsigned nfiles);
1738int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1739
1740#if defined(CONFIG_DEBUG_FS)
1741int amdgpu_debugfs_init(struct drm_minor *minor);
1742void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1743#endif
1744
1745/*
1746 * amdgpu smumgr functions
1747 */
1748struct amdgpu_smumgr_funcs {
1749 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1750 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1751 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1752};
1753
1754/*
1755 * amdgpu smumgr
1756 */
1757struct amdgpu_smumgr {
1758 struct amdgpu_bo *toc_buf;
1759 struct amdgpu_bo *smu_buf;
1760 /* asic priv smu data */
1761 void *priv;
1762 spinlock_t smu_lock;
1763 /* smumgr functions */
1764 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1765 /* ucode loading complete flag */
1766 uint32_t fw_flags;
1767};
1768
1769/*
1770 * ASIC specific register table accessible by UMD
1771 */
1772struct amdgpu_allowed_register_entry {
1773 uint32_t reg_offset;
1774 bool untouched;
1775 bool grbm_indexed;
1776};
1777
1778struct amdgpu_cu_info {
1779 uint32_t number; /* total active CU number */
1780 uint32_t ao_cu_mask;
1781 uint32_t bitmap[4][4];
1782};
1783
1784
1785/*
1786 * ASIC specific functions.
1787 */
1788struct amdgpu_asic_funcs {
1789 bool (*read_disabled_bios)(struct amdgpu_device *adev);
Alex Deucher7946b872015-11-24 10:14:28 -05001790 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1791 u8 *bios, u32 length_bytes);
Alex Deucher97b2e202015-04-20 16:51:00 -04001792 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1793 u32 sh_num, u32 reg_offset, u32 *value);
1794 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1795 int (*reset)(struct amdgpu_device *adev);
1796 /* wait for mc_idle */
1797 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1798 /* get the reference clock */
1799 u32 (*get_xclk)(struct amdgpu_device *adev);
1800 /* get the gpu clock counter */
1801 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1802 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1803 /* MM block clocks */
1804 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1805 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1806};
1807
1808/*
1809 * IOCTL.
1810 */
1811int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1812 struct drm_file *filp);
1813int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1814 struct drm_file *filp);
1815
1816int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1817 struct drm_file *filp);
1818int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1819 struct drm_file *filp);
1820int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1825 struct drm_file *filp);
1826int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1827 struct drm_file *filp);
1828int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1829int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1830
1831int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1832 struct drm_file *filp);
1833
1834/* VRAM scratch page for HDP bug, default vram page */
1835struct amdgpu_vram_scratch {
1836 struct amdgpu_bo *robj;
1837 volatile uint32_t *ptr;
1838 u64 gpu_addr;
1839};
1840
1841/*
1842 * ACPI
1843 */
1844struct amdgpu_atif_notification_cfg {
1845 bool enabled;
1846 int command_code;
1847};
1848
1849struct amdgpu_atif_notifications {
1850 bool display_switch;
1851 bool expansion_mode_change;
1852 bool thermal_state;
1853 bool forced_power_state;
1854 bool system_power_state;
1855 bool display_conf_change;
1856 bool px_gfx_switch;
1857 bool brightness_change;
1858 bool dgpu_display_event;
1859};
1860
1861struct amdgpu_atif_functions {
1862 bool system_params;
1863 bool sbios_requests;
1864 bool select_active_disp;
1865 bool lid_state;
1866 bool get_tv_standard;
1867 bool set_tv_standard;
1868 bool get_panel_expansion_mode;
1869 bool set_panel_expansion_mode;
1870 bool temperature_change;
1871 bool graphics_device_types;
1872};
1873
1874struct amdgpu_atif {
1875 struct amdgpu_atif_notifications notifications;
1876 struct amdgpu_atif_functions functions;
1877 struct amdgpu_atif_notification_cfg notification_cfg;
1878 struct amdgpu_encoder *encoder_for_bl;
1879};
1880
1881struct amdgpu_atcs_functions {
1882 bool get_ext_state;
1883 bool pcie_perf_req;
1884 bool pcie_dev_rdy;
1885 bool pcie_bus_width;
1886};
1887
1888struct amdgpu_atcs {
1889 struct amdgpu_atcs_functions functions;
1890};
1891
Alex Deucher97b2e202015-04-20 16:51:00 -04001892/*
Chunming Zhoud03846a2015-07-28 14:20:03 -04001893 * CGS
1894 */
1895void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1896void amdgpu_cgs_destroy_device(void *cgs_device);
1897
1898
1899/*
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001900 * CGS
1901 */
1902void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1903void amdgpu_cgs_destroy_device(void *cgs_device);
1904
1905
Alex Deucher7e471e62016-02-01 11:13:04 -05001906/* GPU virtualization */
1907struct amdgpu_virtualization {
1908 bool supports_sr_iov;
1909};
1910
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001911/*
Alex Deucher97b2e202015-04-20 16:51:00 -04001912 * Core structure, functions and helpers.
1913 */
1914typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1915typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1916
1917typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1918typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1919
Alex Deucher8faf0e02015-07-28 11:50:31 -04001920struct amdgpu_ip_block_status {
1921 bool valid;
1922 bool sw;
1923 bool hw;
1924};
1925
Alex Deucher97b2e202015-04-20 16:51:00 -04001926struct amdgpu_device {
1927 struct device *dev;
1928 struct drm_device *ddev;
1929 struct pci_dev *pdev;
Alex Deucher97b2e202015-04-20 16:51:00 -04001930
Maruthi Bayyavarapua8fe58c2015-09-22 17:05:20 -04001931#ifdef CONFIG_DRM_AMD_ACP
1932 struct amdgpu_acp acp;
1933#endif
1934
Alex Deucher97b2e202015-04-20 16:51:00 -04001935 /* ASIC */
Jammy Zhou2f7d10b2015-07-22 11:29:01 +08001936 enum amd_asic_type asic_type;
Alex Deucher97b2e202015-04-20 16:51:00 -04001937 uint32_t family;
1938 uint32_t rev_id;
1939 uint32_t external_rev_id;
1940 unsigned long flags;
1941 int usec_timeout;
1942 const struct amdgpu_asic_funcs *asic_funcs;
1943 bool shutdown;
1944 bool suspend;
1945 bool need_dma32;
1946 bool accel_working;
Alex Deucher97b2e202015-04-20 16:51:00 -04001947 struct work_struct reset_work;
1948 struct notifier_block acpi_nb;
1949 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1950 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1951 unsigned debugfs_count;
1952#if defined(CONFIG_DEBUG_FS)
1953 struct dentry *debugfs_regs;
1954#endif
1955 struct amdgpu_atif atif;
1956 struct amdgpu_atcs atcs;
1957 struct mutex srbm_mutex;
1958 /* GRBM index mutex. Protects concurrent access to GRBM index */
1959 struct mutex grbm_idx_mutex;
1960 struct dev_pm_domain vga_pm_domain;
1961 bool have_disp_power_ref;
1962
1963 /* BIOS */
1964 uint8_t *bios;
1965 bool is_atom_bios;
1966 uint16_t bios_header_start;
1967 struct amdgpu_bo *stollen_vga_memory;
1968 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1969
1970 /* Register/doorbell mmio */
1971 resource_size_t rmmio_base;
1972 resource_size_t rmmio_size;
1973 void __iomem *rmmio;
1974 /* protects concurrent MM_INDEX/DATA based register access */
1975 spinlock_t mmio_idx_lock;
1976 /* protects concurrent SMC based register access */
1977 spinlock_t smc_idx_lock;
1978 amdgpu_rreg_t smc_rreg;
1979 amdgpu_wreg_t smc_wreg;
1980 /* protects concurrent PCIE register access */
1981 spinlock_t pcie_idx_lock;
1982 amdgpu_rreg_t pcie_rreg;
1983 amdgpu_wreg_t pcie_wreg;
1984 /* protects concurrent UVD register access */
1985 spinlock_t uvd_ctx_idx_lock;
1986 amdgpu_rreg_t uvd_ctx_rreg;
1987 amdgpu_wreg_t uvd_ctx_wreg;
1988 /* protects concurrent DIDT register access */
1989 spinlock_t didt_idx_lock;
1990 amdgpu_rreg_t didt_rreg;
1991 amdgpu_wreg_t didt_wreg;
1992 /* protects concurrent ENDPOINT (audio) register access */
1993 spinlock_t audio_endpt_idx_lock;
1994 amdgpu_block_rreg_t audio_endpt_rreg;
1995 amdgpu_block_wreg_t audio_endpt_wreg;
1996 void __iomem *rio_mem;
1997 resource_size_t rio_mem_size;
1998 struct amdgpu_doorbell doorbell;
1999
2000 /* clock/pll info */
2001 struct amdgpu_clock clock;
2002
2003 /* MC */
2004 struct amdgpu_mc mc;
2005 struct amdgpu_gart gart;
2006 struct amdgpu_dummy_page dummy_page;
2007 struct amdgpu_vm_manager vm_manager;
2008
2009 /* memory management */
2010 struct amdgpu_mman mman;
2011 struct amdgpu_gem gem;
2012 struct amdgpu_vram_scratch vram_scratch;
2013 struct amdgpu_wb wb;
2014 atomic64_t vram_usage;
2015 atomic64_t vram_vis_usage;
2016 atomic64_t gtt_usage;
2017 atomic64_t num_bytes_moved;
Marek Olšákd94aed52015-05-05 21:13:49 +02002018 atomic_t gpu_reset_counter;
Alex Deucher97b2e202015-04-20 16:51:00 -04002019
2020 /* display */
2021 struct amdgpu_mode_info mode_info;
2022 struct work_struct hotplug_work;
2023 struct amdgpu_irq_src crtc_irq;
2024 struct amdgpu_irq_src pageflip_irq;
2025 struct amdgpu_irq_src hpd_irq;
2026
2027 /* rings */
Alex Deucher97b2e202015-04-20 16:51:00 -04002028 unsigned fence_context;
Alex Deucher97b2e202015-04-20 16:51:00 -04002029 unsigned num_rings;
2030 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2031 bool ib_pool_ready;
2032 struct amdgpu_sa_manager ring_tmp_bo;
2033
2034 /* interrupts */
2035 struct amdgpu_irq irq;
2036
Alex Deucher1f7371b2015-12-02 17:46:21 -05002037 /* powerplay */
2038 struct amd_powerplay powerplay;
Jammy Zhoue61710c2015-11-10 18:31:08 -05002039 bool pp_enabled;
Eric Huangf3898ea2015-12-11 16:24:34 -05002040 bool pp_force_state_enabled;
Alex Deucher1f7371b2015-12-02 17:46:21 -05002041
Alex Deucher97b2e202015-04-20 16:51:00 -04002042 /* dpm */
2043 struct amdgpu_pm pm;
2044 u32 cg_flags;
2045 u32 pg_flags;
2046
2047 /* amdgpu smumgr */
2048 struct amdgpu_smumgr smu;
2049
2050 /* gfx */
2051 struct amdgpu_gfx gfx;
2052
2053 /* sdma */
Alex Deucherc113ea12015-10-08 16:30:37 -04002054 struct amdgpu_sdma sdma;
Alex Deucher97b2e202015-04-20 16:51:00 -04002055
2056 /* uvd */
2057 bool has_uvd;
2058 struct amdgpu_uvd uvd;
2059
2060 /* vce */
2061 struct amdgpu_vce vce;
2062
2063 /* firmwares */
2064 struct amdgpu_firmware firmware;
2065
2066 /* GDS */
2067 struct amdgpu_gds gds;
2068
2069 const struct amdgpu_ip_block_version *ip_blocks;
2070 int num_ip_blocks;
Alex Deucher8faf0e02015-07-28 11:50:31 -04002071 struct amdgpu_ip_block_status *ip_block_status;
Alex Deucher97b2e202015-04-20 16:51:00 -04002072 struct mutex mn_lock;
2073 DECLARE_HASHTABLE(mn_hash, 7);
2074
2075 /* tracking pinned memory */
2076 u64 vram_pin_size;
2077 u64 gart_pin_size;
Oded Gabbay130e0372015-06-12 21:35:14 +03002078
2079 /* amdkfd interface */
2080 struct kfd_dev *kfd;
Chunming Zhou23ca0e42015-07-06 13:42:58 +08002081
2082 /* kernel conext for IB submission */
Christian König47f38502015-08-04 17:51:05 +02002083 struct amdgpu_ctx kernel_ctx;
Alex Deucher7e471e62016-02-01 11:13:04 -05002084
2085 struct amdgpu_virtualization virtualization;
Alex Deucher97b2e202015-04-20 16:51:00 -04002086};
2087
2088bool amdgpu_device_is_px(struct drm_device *dev);
2089int amdgpu_device_init(struct amdgpu_device *adev,
2090 struct drm_device *ddev,
2091 struct pci_dev *pdev,
2092 uint32_t flags);
2093void amdgpu_device_fini(struct amdgpu_device *adev);
2094int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2095
2096uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2097 bool always_indirect);
2098void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2099 bool always_indirect);
2100u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2101void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2102
2103u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2104void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2105
2106/*
2107 * Cast helper
2108 */
2109extern const struct fence_ops amdgpu_fence_ops;
2110static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2111{
2112 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2113
2114 if (__f->base.ops == &amdgpu_fence_ops)
2115 return __f;
2116
2117 return NULL;
2118}
2119
2120/*
2121 * Registers read & write functions.
2122 */
2123#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2124#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2125#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2126#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2127#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2128#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2129#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2130#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2131#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2132#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2133#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2134#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2135#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2136#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2137#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2138#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2139#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2140#define WREG32_P(reg, val, mask) \
2141 do { \
2142 uint32_t tmp_ = RREG32(reg); \
2143 tmp_ &= (mask); \
2144 tmp_ |= ((val) & ~(mask)); \
2145 WREG32(reg, tmp_); \
2146 } while (0)
2147#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2148#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2149#define WREG32_PLL_P(reg, val, mask) \
2150 do { \
2151 uint32_t tmp_ = RREG32_PLL(reg); \
2152 tmp_ &= (mask); \
2153 tmp_ |= ((val) & ~(mask)); \
2154 WREG32_PLL(reg, tmp_); \
2155 } while (0)
2156#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2157#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2158#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2159
2160#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2161#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2162
2163#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2164#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2165
2166#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2167 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2168 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2169
2170#define REG_GET_FIELD(value, reg, field) \
2171 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2172
2173/*
2174 * BIOS helpers.
2175 */
2176#define RBIOS8(i) (adev->bios[i])
2177#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2178#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2179
2180/*
2181 * RING helpers.
2182 */
2183static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2184{
2185 if (ring->count_dw <= 0)
Jammy Zhou86c2b792015-05-13 22:52:42 +08002186 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
Alex Deucher97b2e202015-04-20 16:51:00 -04002187 ring->ring[ring->wptr++] = v;
2188 ring->wptr &= ring->ptr_mask;
2189 ring->count_dw--;
Alex Deucher97b2e202015-04-20 16:51:00 -04002190}
2191
Alex Deucherc113ea12015-10-08 16:30:37 -04002192static inline struct amdgpu_sdma_instance *
2193amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08002194{
2195 struct amdgpu_device *adev = ring->adev;
2196 int i;
2197
Alex Deucherc113ea12015-10-08 16:30:37 -04002198 for (i = 0; i < adev->sdma.num_instances; i++)
2199 if (&adev->sdma.instance[i].ring == ring)
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08002200 break;
2201
2202 if (i < AMDGPU_MAX_SDMA_INSTANCES)
Alex Deucherc113ea12015-10-08 16:30:37 -04002203 return &adev->sdma.instance[i];
Jammy Zhou4b2f7e22015-09-01 12:56:17 +08002204 else
2205 return NULL;
2206}
2207
Alex Deucher97b2e202015-04-20 16:51:00 -04002208/*
2209 * ASICs macro.
2210 */
2211#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2212#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2213#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2214#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2215#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2216#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2217#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2218#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
Alex Deucher7946b872015-11-24 10:14:28 -05002219#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
Alex Deucher97b2e202015-04-20 16:51:00 -04002220#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2221#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2222#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2223#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2224#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
Christian Königb07c9d22015-11-30 13:26:07 +01002225#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
Alex Deucher97b2e202015-04-20 16:51:00 -04002226#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2227#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2228#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2229#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2230#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
Alex Deucher97b2e202015-04-20 16:51:00 -04002231#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2232#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2233#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2234#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2235#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
Chunming Zhou890ee232015-06-01 14:35:03 +08002236#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
Alex Deucher97b2e202015-04-20 16:51:00 -04002237#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
Christian Königd2edb072015-05-11 14:10:34 +02002238#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
Alex Deucher97b2e202015-04-20 16:51:00 -04002239#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2240#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2241#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2242#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2243#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2244#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2245#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2246#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2247#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2248#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2249#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2250#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2251#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2252#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2253#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2254#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2255#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2256#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2257#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
Chunming Zhouc7ae72c2015-08-25 17:23:45 +08002258#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
Chunming Zhou6e7a3842015-08-27 13:46:09 +08002259#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
Alex Deucher97b2e202015-04-20 16:51:00 -04002260#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2261#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2262#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2263#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04002264#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
Alex Deucher97b2e202015-04-20 16:51:00 -04002265#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
Alex Deucher97b2e202015-04-20 16:51:00 -04002266#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
Rex Zhu3af76f22015-10-15 17:23:43 +08002267
2268#define amdgpu_dpm_get_temperature(adev) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002269 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002270 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002271 (adev)->pm.funcs->get_temperature((adev)))
Rex Zhu3af76f22015-10-15 17:23:43 +08002272
2273#define amdgpu_dpm_set_fan_control_mode(adev, m) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002274 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002275 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002276 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
Rex Zhu3af76f22015-10-15 17:23:43 +08002277
2278#define amdgpu_dpm_get_fan_control_mode(adev) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002279 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002280 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002281 (adev)->pm.funcs->get_fan_control_mode((adev)))
Rex Zhu3af76f22015-10-15 17:23:43 +08002282
2283#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002284 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002285 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002286 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
Rex Zhu3af76f22015-10-15 17:23:43 +08002287
2288#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002289 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002290 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002291 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
Alex Deucher97b2e202015-04-20 16:51:00 -04002292
Rex Zhu1b5708f2015-11-10 18:25:24 -05002293#define amdgpu_dpm_get_sclk(adev, l) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002294 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002295 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002296 (adev)->pm.funcs->get_sclk((adev), (l)))
Rex Zhu1b5708f2015-11-10 18:25:24 -05002297
2298#define amdgpu_dpm_get_mclk(adev, l) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002299 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002300 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002301 (adev)->pm.funcs->get_mclk((adev), (l)))
Rex Zhu1b5708f2015-11-10 18:25:24 -05002302
2303
2304#define amdgpu_dpm_force_performance_level(adev, l) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002305 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002306 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002307 (adev)->pm.funcs->force_performance_level((adev), (l)))
Rex Zhu1b5708f2015-11-10 18:25:24 -05002308
2309#define amdgpu_dpm_powergate_uvd(adev, g) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002310 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002311 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002312 (adev)->pm.funcs->powergate_uvd((adev), (g)))
Rex Zhu1b5708f2015-11-10 18:25:24 -05002313
2314#define amdgpu_dpm_powergate_vce(adev, g) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002315 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002316 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002317 (adev)->pm.funcs->powergate_vce((adev), (g)))
Rex Zhu1b5708f2015-11-10 18:25:24 -05002318
2319#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
Eric Huang4b5ece22016-01-19 14:28:56 -05002320 ((adev)->pp_enabled ? \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002321 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
Eric Huang4b5ece22016-01-19 14:28:56 -05002322 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
Rex Zhu1b5708f2015-11-10 18:25:24 -05002323
2324#define amdgpu_dpm_get_current_power_state(adev) \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002325 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
Rex Zhu1b5708f2015-11-10 18:25:24 -05002326
2327#define amdgpu_dpm_get_performance_level(adev) \
Jammy Zhoue61710c2015-11-10 18:31:08 -05002328 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
Rex Zhu1b5708f2015-11-10 18:25:24 -05002329
Eric Huangf3898ea2015-12-11 16:24:34 -05002330#define amdgpu_dpm_get_pp_num_states(adev, data) \
2331 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2332
2333#define amdgpu_dpm_get_pp_table(adev, table) \
2334 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2335
2336#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2337 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2338
2339#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2340 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2341
2342#define amdgpu_dpm_force_clock_level(adev, type, level) \
2343 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2344
Jammy Zhoue61710c2015-11-10 18:31:08 -05002345#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
Rex Zhu1b5708f2015-11-10 18:25:24 -05002346 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
Alex Deucher97b2e202015-04-20 16:51:00 -04002347
2348#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2349
2350/* Common functions */
2351int amdgpu_gpu_reset(struct amdgpu_device *adev);
2352void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2353bool amdgpu_card_posted(struct amdgpu_device *adev);
2354void amdgpu_update_display_priority(struct amdgpu_device *adev);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +08002355
Alex Deucher97b2e202015-04-20 16:51:00 -04002356int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2357int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2358 u32 ip_instance, u32 ring,
2359 struct amdgpu_ring **out_ring);
2360void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2361bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2362int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2363 uint32_t flags);
Christian Königcc325d12016-02-08 11:08:35 +01002364struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
Christian Königd7006962016-02-08 10:57:22 +01002365bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2366 unsigned long end);
Alex Deucher97b2e202015-04-20 16:51:00 -04002367bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2368uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2369 struct ttm_mem_reg *mem);
2370void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2371void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2372void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2373void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2374 const u32 *registers,
2375 const u32 array_size);
2376
2377bool amdgpu_device_is_px(struct drm_device *dev);
2378/* atpx handler */
2379#if defined(CONFIG_VGA_SWITCHEROO)
2380void amdgpu_register_atpx_handler(void);
2381void amdgpu_unregister_atpx_handler(void);
2382#else
2383static inline void amdgpu_register_atpx_handler(void) {}
2384static inline void amdgpu_unregister_atpx_handler(void) {}
2385#endif
2386
2387/*
2388 * KMS
2389 */
2390extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2391extern int amdgpu_max_kms_ioctl;
2392
2393int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2394int amdgpu_driver_unload_kms(struct drm_device *dev);
2395void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2396int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2397void amdgpu_driver_postclose_kms(struct drm_device *dev,
2398 struct drm_file *file_priv);
2399void amdgpu_driver_preclose_kms(struct drm_device *dev,
2400 struct drm_file *file_priv);
2401int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2402int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
Thierry Reding88e72712015-09-24 18:35:31 +02002403u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2404int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2405void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2406int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
Alex Deucher97b2e202015-04-20 16:51:00 -04002407 int *max_error,
2408 struct timeval *vblank_time,
2409 unsigned flags);
2410long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2411 unsigned long arg);
2412
2413/*
Alex Deucher97b2e202015-04-20 16:51:00 -04002414 * functions used by amdgpu_encoder.c
2415 */
2416struct amdgpu_afmt_acr {
2417 u32 clock;
2418
2419 int n_32khz;
2420 int cts_32khz;
2421
2422 int n_44_1khz;
2423 int cts_44_1khz;
2424
2425 int n_48khz;
2426 int cts_48khz;
2427
2428};
2429
2430struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2431
2432/* amdgpu_acpi.c */
2433#if defined(CONFIG_ACPI)
2434int amdgpu_acpi_init(struct amdgpu_device *adev);
2435void amdgpu_acpi_fini(struct amdgpu_device *adev);
2436bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2437int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2438 u8 perf_req, bool advertise);
2439int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2440#else
2441static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2442static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2443#endif
2444
2445struct amdgpu_bo_va_mapping *
2446amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2447 uint64_t addr, struct amdgpu_bo **bo);
2448
2449#include "amdgpu_object.h"
2450
2451#endif