jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver |
| 3 | * |
| 4 | * Copyright (c) 2008-2009 USI Co., Ltd. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions, and the following disclaimer, |
| 12 | * without modification. |
| 13 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 14 | * substantially similar to the "NO WARRANTY" disclaimer below |
| 15 | * ("Disclaimer") and any redistribution must be conditioned upon |
| 16 | * including a substantially similar Disclaimer requirement for further |
| 17 | * binary redistribution. |
| 18 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 19 | * of any contributors may be used to endorse or promote products derived |
| 20 | * from this software without specific prior written permission. |
| 21 | * |
| 22 | * Alternatively, this software may be distributed under the terms of the |
| 23 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 24 | * Software Foundation. |
| 25 | * |
| 26 | * NO WARRANTY |
| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
| 30 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 31 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 32 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 33 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 34 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 35 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
| 36 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 37 | * POSSIBILITY OF SUCH DAMAGES. |
| 38 | * |
| 39 | */ |
| 40 | #include "pm8001_sas.h" |
| 41 | #include "pm8001_hwi.h" |
| 42 | #include "pm8001_chips.h" |
| 43 | #include "pm8001_ctl.h" |
| 44 | |
| 45 | /** |
| 46 | * read_main_config_table - read the configure table and save it. |
| 47 | * @pm8001_ha: our hba card information |
| 48 | */ |
| 49 | static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha) |
| 50 | { |
| 51 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; |
| 52 | pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00); |
| 53 | pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04); |
| 54 | pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08); |
| 55 | pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C); |
| 56 | pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10); |
| 57 | pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14); |
| 58 | pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18); |
| 59 | pm8001_ha->main_cfg_tbl.inbound_queue_offset = |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 60 | pm8001_mr32(address, MAIN_IBQ_OFFSET); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 61 | pm8001_ha->main_cfg_tbl.outbound_queue_offset = |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 62 | pm8001_mr32(address, MAIN_OBQ_OFFSET); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 63 | pm8001_ha->main_cfg_tbl.hda_mode_flag = |
| 64 | pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); |
| 65 | |
| 66 | /* read analog Setting offset from the configuration table */ |
| 67 | pm8001_ha->main_cfg_tbl.anolog_setup_table_offset = |
| 68 | pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); |
| 69 | |
| 70 | /* read Error Dump Offset and Length */ |
| 71 | pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 = |
| 72 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); |
| 73 | pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 = |
| 74 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); |
| 75 | pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 = |
| 76 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); |
| 77 | pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 = |
| 78 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); |
| 79 | } |
| 80 | |
| 81 | /** |
| 82 | * read_general_status_table - read the general status table and save it. |
| 83 | * @pm8001_ha: our hba card information |
| 84 | */ |
| 85 | static void __devinit |
| 86 | read_general_status_table(struct pm8001_hba_info *pm8001_ha) |
| 87 | { |
| 88 | void __iomem *address = pm8001_ha->general_stat_tbl_addr; |
| 89 | pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00); |
| 90 | pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04); |
| 91 | pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08); |
| 92 | pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C); |
| 93 | pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10); |
| 94 | pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14); |
| 95 | pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18); |
| 96 | pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C); |
| 97 | pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20); |
| 98 | pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24); |
| 99 | pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28); |
| 100 | pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C); |
| 101 | pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30); |
| 102 | pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34); |
| 103 | pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38); |
| 104 | pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C); |
| 105 | pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40); |
| 106 | pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44); |
| 107 | pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48); |
| 108 | pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C); |
| 109 | pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50); |
| 110 | pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54); |
| 111 | pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58); |
| 112 | pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C); |
| 113 | pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60); |
| 114 | } |
| 115 | |
| 116 | /** |
| 117 | * read_inbnd_queue_table - read the inbound queue table and save it. |
| 118 | * @pm8001_ha: our hba card information |
| 119 | */ |
| 120 | static void __devinit |
| 121 | read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) |
| 122 | { |
| 123 | int inbQ_num = 1; |
| 124 | int i; |
| 125 | void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; |
| 126 | for (i = 0; i < inbQ_num; i++) { |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 127 | u32 offset = i * 0x20; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 128 | pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = |
| 129 | get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); |
| 130 | pm8001_ha->inbnd_q_tbl[i].pi_offset = |
| 131 | pm8001_mr32(address, (offset + 0x18)); |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | /** |
| 136 | * read_outbnd_queue_table - read the outbound queue table and save it. |
| 137 | * @pm8001_ha: our hba card information |
| 138 | */ |
| 139 | static void __devinit |
| 140 | read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) |
| 141 | { |
| 142 | int outbQ_num = 1; |
| 143 | int i; |
| 144 | void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; |
| 145 | for (i = 0; i < outbQ_num; i++) { |
| 146 | u32 offset = i * 0x24; |
| 147 | pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = |
| 148 | get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); |
| 149 | pm8001_ha->outbnd_q_tbl[i].ci_offset = |
| 150 | pm8001_mr32(address, (offset + 0x18)); |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | /** |
| 155 | * init_default_table_values - init the default table. |
| 156 | * @pm8001_ha: our hba card information |
| 157 | */ |
| 158 | static void __devinit |
| 159 | init_default_table_values(struct pm8001_hba_info *pm8001_ha) |
| 160 | { |
| 161 | int qn = 1; |
| 162 | int i; |
| 163 | u32 offsetib, offsetob; |
| 164 | void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; |
| 165 | void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; |
| 166 | |
| 167 | pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0; |
| 168 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0; |
| 169 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0; |
| 170 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0; |
| 171 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0; |
| 172 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0; |
| 173 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0; |
| 174 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0; |
| 175 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0; |
| 176 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0; |
| 177 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0; |
| 178 | |
| 179 | pm8001_ha->main_cfg_tbl.upper_event_log_addr = |
| 180 | pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; |
| 181 | pm8001_ha->main_cfg_tbl.lower_event_log_addr = |
| 182 | pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; |
| 183 | pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE; |
| 184 | pm8001_ha->main_cfg_tbl.event_log_option = 0x01; |
| 185 | pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr = |
| 186 | pm8001_ha->memoryMap.region[IOP].phys_addr_hi; |
| 187 | pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr = |
| 188 | pm8001_ha->memoryMap.region[IOP].phys_addr_lo; |
| 189 | pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE; |
| 190 | pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01; |
| 191 | pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01; |
| 192 | for (i = 0; i < qn; i++) { |
| 193 | pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = |
| 194 | 0x00000100 | (0x00000040 << 16) | (0x00<<30); |
| 195 | pm8001_ha->inbnd_q_tbl[i].upper_base_addr = |
| 196 | pm8001_ha->memoryMap.region[IB].phys_addr_hi; |
| 197 | pm8001_ha->inbnd_q_tbl[i].lower_base_addr = |
| 198 | pm8001_ha->memoryMap.region[IB].phys_addr_lo; |
| 199 | pm8001_ha->inbnd_q_tbl[i].base_virt = |
| 200 | (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr; |
| 201 | pm8001_ha->inbnd_q_tbl[i].total_length = |
| 202 | pm8001_ha->memoryMap.region[IB].total_len; |
| 203 | pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = |
| 204 | pm8001_ha->memoryMap.region[CI].phys_addr_hi; |
| 205 | pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = |
| 206 | pm8001_ha->memoryMap.region[CI].phys_addr_lo; |
| 207 | pm8001_ha->inbnd_q_tbl[i].ci_virt = |
| 208 | pm8001_ha->memoryMap.region[CI].virt_ptr; |
| 209 | offsetib = i * 0x20; |
| 210 | pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = |
| 211 | get_pci_bar_index(pm8001_mr32(addressib, |
| 212 | (offsetib + 0x14))); |
| 213 | pm8001_ha->inbnd_q_tbl[i].pi_offset = |
| 214 | pm8001_mr32(addressib, (offsetib + 0x18)); |
| 215 | pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; |
| 216 | pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; |
| 217 | } |
| 218 | for (i = 0; i < qn; i++) { |
| 219 | pm8001_ha->outbnd_q_tbl[i].element_size_cnt = |
| 220 | 256 | (64 << 16) | (1<<30); |
| 221 | pm8001_ha->outbnd_q_tbl[i].upper_base_addr = |
| 222 | pm8001_ha->memoryMap.region[OB].phys_addr_hi; |
| 223 | pm8001_ha->outbnd_q_tbl[i].lower_base_addr = |
| 224 | pm8001_ha->memoryMap.region[OB].phys_addr_lo; |
| 225 | pm8001_ha->outbnd_q_tbl[i].base_virt = |
| 226 | (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr; |
| 227 | pm8001_ha->outbnd_q_tbl[i].total_length = |
| 228 | pm8001_ha->memoryMap.region[OB].total_len; |
| 229 | pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = |
| 230 | pm8001_ha->memoryMap.region[PI].phys_addr_hi; |
| 231 | pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = |
| 232 | pm8001_ha->memoryMap.region[PI].phys_addr_lo; |
| 233 | pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 234 | 0 | (10 << 16) | (0 << 24); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 235 | pm8001_ha->outbnd_q_tbl[i].pi_virt = |
| 236 | pm8001_ha->memoryMap.region[PI].virt_ptr; |
| 237 | offsetob = i * 0x24; |
| 238 | pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = |
| 239 | get_pci_bar_index(pm8001_mr32(addressob, |
| 240 | offsetob + 0x14)); |
| 241 | pm8001_ha->outbnd_q_tbl[i].ci_offset = |
| 242 | pm8001_mr32(addressob, (offsetob + 0x18)); |
| 243 | pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; |
| 244 | pm8001_ha->outbnd_q_tbl[i].producer_index = 0; |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | /** |
| 249 | * update_main_config_table - update the main default table to the HBA. |
| 250 | * @pm8001_ha: our hba card information |
| 251 | */ |
| 252 | static void __devinit |
| 253 | update_main_config_table(struct pm8001_hba_info *pm8001_ha) |
| 254 | { |
| 255 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; |
| 256 | pm8001_mw32(address, 0x24, |
| 257 | pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd); |
| 258 | pm8001_mw32(address, 0x28, |
| 259 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3); |
| 260 | pm8001_mw32(address, 0x2C, |
| 261 | pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7); |
| 262 | pm8001_mw32(address, 0x30, |
| 263 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3); |
| 264 | pm8001_mw32(address, 0x34, |
| 265 | pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7); |
| 266 | pm8001_mw32(address, 0x38, |
| 267 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3); |
| 268 | pm8001_mw32(address, 0x3C, |
| 269 | pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7); |
| 270 | pm8001_mw32(address, 0x40, |
| 271 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3); |
| 272 | pm8001_mw32(address, 0x44, |
| 273 | pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7); |
| 274 | pm8001_mw32(address, 0x48, |
| 275 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3); |
| 276 | pm8001_mw32(address, 0x4C, |
| 277 | pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7); |
| 278 | pm8001_mw32(address, 0x50, |
| 279 | pm8001_ha->main_cfg_tbl.upper_event_log_addr); |
| 280 | pm8001_mw32(address, 0x54, |
| 281 | pm8001_ha->main_cfg_tbl.lower_event_log_addr); |
| 282 | pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size); |
| 283 | pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option); |
| 284 | pm8001_mw32(address, 0x60, |
| 285 | pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr); |
| 286 | pm8001_mw32(address, 0x64, |
| 287 | pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr); |
| 288 | pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size); |
| 289 | pm8001_mw32(address, 0x6C, |
| 290 | pm8001_ha->main_cfg_tbl.iop_event_log_option); |
| 291 | pm8001_mw32(address, 0x70, |
| 292 | pm8001_ha->main_cfg_tbl.fatal_err_interrupt); |
| 293 | } |
| 294 | |
| 295 | /** |
| 296 | * update_inbnd_queue_table - update the inbound queue table to the HBA. |
| 297 | * @pm8001_ha: our hba card information |
| 298 | */ |
| 299 | static void __devinit |
| 300 | update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number) |
| 301 | { |
| 302 | void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; |
| 303 | u16 offset = number * 0x20; |
| 304 | pm8001_mw32(address, offset + 0x00, |
| 305 | pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); |
| 306 | pm8001_mw32(address, offset + 0x04, |
| 307 | pm8001_ha->inbnd_q_tbl[number].upper_base_addr); |
| 308 | pm8001_mw32(address, offset + 0x08, |
| 309 | pm8001_ha->inbnd_q_tbl[number].lower_base_addr); |
| 310 | pm8001_mw32(address, offset + 0x0C, |
| 311 | pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); |
| 312 | pm8001_mw32(address, offset + 0x10, |
| 313 | pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); |
| 314 | } |
| 315 | |
| 316 | /** |
| 317 | * update_outbnd_queue_table - update the outbound queue table to the HBA. |
| 318 | * @pm8001_ha: our hba card information |
| 319 | */ |
| 320 | static void __devinit |
| 321 | update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number) |
| 322 | { |
| 323 | void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; |
| 324 | u16 offset = number * 0x24; |
| 325 | pm8001_mw32(address, offset + 0x00, |
| 326 | pm8001_ha->outbnd_q_tbl[number].element_size_cnt); |
| 327 | pm8001_mw32(address, offset + 0x04, |
| 328 | pm8001_ha->outbnd_q_tbl[number].upper_base_addr); |
| 329 | pm8001_mw32(address, offset + 0x08, |
| 330 | pm8001_ha->outbnd_q_tbl[number].lower_base_addr); |
| 331 | pm8001_mw32(address, offset + 0x0C, |
| 332 | pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); |
| 333 | pm8001_mw32(address, offset + 0x10, |
| 334 | pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); |
| 335 | pm8001_mw32(address, offset + 0x1C, |
| 336 | pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); |
| 337 | } |
| 338 | |
| 339 | /** |
| 340 | * bar4_shift - function is called to shift BAR base address |
| 341 | * @pm8001_ha : our hba card infomation |
| 342 | * @shiftValue : shifting value in memory bar. |
| 343 | */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 344 | static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 345 | { |
| 346 | u32 regVal; |
| 347 | u32 max_wait_count; |
| 348 | |
| 349 | /* program the inbound AXI translation Lower Address */ |
| 350 | pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); |
| 351 | |
| 352 | /* confirm the setting is written */ |
| 353 | max_wait_count = 1 * 1000 * 1000; /* 1 sec */ |
| 354 | do { |
| 355 | udelay(1); |
| 356 | regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); |
| 357 | } while ((regVal != shiftValue) && (--max_wait_count)); |
| 358 | |
| 359 | if (!max_wait_count) { |
| 360 | PM8001_INIT_DBG(pm8001_ha, |
| 361 | pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" |
| 362 | " = 0x%x\n", regVal)); |
| 363 | return -1; |
| 364 | } |
| 365 | return 0; |
| 366 | } |
| 367 | |
| 368 | /** |
| 369 | * mpi_set_phys_g3_with_ssc |
| 370 | * @pm8001_ha: our hba card information |
| 371 | * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. |
| 372 | */ |
| 373 | static void __devinit |
| 374 | mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit) |
| 375 | { |
| 376 | u32 offset; |
| 377 | u32 value; |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 378 | u32 i, j; |
| 379 | u32 bit_cnt; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 380 | |
| 381 | #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 |
| 382 | #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 |
| 383 | #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 |
| 384 | #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 385 | #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 |
| 386 | #define PHY_G3_WITH_SSC_BIT_SHIFT 13 |
| 387 | #define SNW3_PHY_CAPABILITIES_PARITY 31 |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 388 | |
| 389 | /* |
| 390 | * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) |
| 391 | * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) |
| 392 | */ |
| 393 | if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) |
| 394 | return; |
| 395 | /* set SSC bit of PHY 0 - 3 */ |
| 396 | for (i = 0; i < 4; i++) { |
| 397 | offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; |
| 398 | value = pm8001_cr32(pm8001_ha, 2, offset); |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 399 | if (SSCbit) { |
| 400 | value |= 0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT; |
| 401 | value &= ~(0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT); |
| 402 | } else { |
| 403 | value |= 0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT; |
| 404 | value &= ~(0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT); |
| 405 | } |
| 406 | bit_cnt = 0; |
| 407 | for (j = 0; j < 31; j++) |
| 408 | if ((value >> j) & 0x00000001) |
| 409 | bit_cnt++; |
| 410 | if (bit_cnt % 2) |
| 411 | value &= ~(0x00000001 << SNW3_PHY_CAPABILITIES_PARITY); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 412 | else |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 413 | value |= 0x00000001 << SNW3_PHY_CAPABILITIES_PARITY; |
| 414 | |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 415 | pm8001_cw32(pm8001_ha, 2, offset, value); |
| 416 | } |
| 417 | |
| 418 | /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ |
| 419 | if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) |
| 420 | return; |
| 421 | |
| 422 | /* set SSC bit of PHY 4 - 7 */ |
| 423 | for (i = 4; i < 8; i++) { |
| 424 | offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); |
| 425 | value = pm8001_cr32(pm8001_ha, 2, offset); |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 426 | if (SSCbit) { |
| 427 | value |= 0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT; |
| 428 | value &= ~(0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT); |
| 429 | } else { |
| 430 | value |= 0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT; |
| 431 | value &= ~(0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT); |
| 432 | } |
| 433 | bit_cnt = 0; |
| 434 | for (j = 0; j < 31; j++) |
| 435 | if ((value >> j) & 0x00000001) |
| 436 | bit_cnt++; |
| 437 | if (bit_cnt % 2) |
| 438 | value &= ~(0x00000001 << SNW3_PHY_CAPABILITIES_PARITY); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 439 | else |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 440 | value |= 0x00000001 << SNW3_PHY_CAPABILITIES_PARITY; |
| 441 | |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 442 | pm8001_cw32(pm8001_ha, 2, offset, value); |
| 443 | } |
| 444 | |
| 445 | /*set the shifted destination address to 0x0 to avoid error operation */ |
| 446 | bar4_shift(pm8001_ha, 0x0); |
| 447 | return; |
| 448 | } |
| 449 | |
| 450 | /** |
| 451 | * mpi_set_open_retry_interval_reg |
| 452 | * @pm8001_ha: our hba card information |
| 453 | * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us. |
| 454 | */ |
| 455 | static void __devinit |
| 456 | mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, |
| 457 | u32 interval) |
| 458 | { |
| 459 | u32 offset; |
| 460 | u32 value; |
| 461 | u32 i; |
| 462 | |
| 463 | #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 |
| 464 | #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 |
| 465 | #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 |
| 466 | #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 |
| 467 | #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF |
| 468 | |
| 469 | value = interval & OPEN_RETRY_INTERVAL_REG_MASK; |
| 470 | /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ |
| 471 | if (-1 == bar4_shift(pm8001_ha, |
| 472 | OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) |
| 473 | return; |
| 474 | for (i = 0; i < 4; i++) { |
| 475 | offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; |
| 476 | pm8001_cw32(pm8001_ha, 2, offset, value); |
| 477 | } |
| 478 | |
| 479 | if (-1 == bar4_shift(pm8001_ha, |
| 480 | OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) |
| 481 | return; |
| 482 | for (i = 4; i < 8; i++) { |
| 483 | offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); |
| 484 | pm8001_cw32(pm8001_ha, 2, offset, value); |
| 485 | } |
| 486 | /*set the shifted destination address to 0x0 to avoid error operation */ |
| 487 | bar4_shift(pm8001_ha, 0x0); |
| 488 | return; |
| 489 | } |
| 490 | |
| 491 | /** |
| 492 | * mpi_init_check - check firmware initialization status. |
| 493 | * @pm8001_ha: our hba card information |
| 494 | */ |
| 495 | static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) |
| 496 | { |
| 497 | u32 max_wait_count; |
| 498 | u32 value; |
| 499 | u32 gst_len_mpistate; |
| 500 | /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the |
| 501 | table is updated */ |
| 502 | pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); |
| 503 | /* wait until Inbound DoorBell Clear Register toggled */ |
| 504 | max_wait_count = 1 * 1000 * 1000;/* 1 sec */ |
| 505 | do { |
| 506 | udelay(1); |
| 507 | value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); |
| 508 | value &= SPC_MSGU_CFG_TABLE_UPDATE; |
| 509 | } while ((value != 0) && (--max_wait_count)); |
| 510 | |
| 511 | if (!max_wait_count) |
| 512 | return -1; |
| 513 | /* check the MPI-State for initialization */ |
| 514 | gst_len_mpistate = |
| 515 | pm8001_mr32(pm8001_ha->general_stat_tbl_addr, |
| 516 | GST_GSTLEN_MPIS_OFFSET); |
| 517 | if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) |
| 518 | return -1; |
| 519 | /* check MPI Initialization error */ |
| 520 | gst_len_mpistate = gst_len_mpistate >> 16; |
| 521 | if (0x0000 != gst_len_mpistate) |
| 522 | return -1; |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | /** |
| 527 | * check_fw_ready - The LLDD check if the FW is ready, if not, return error. |
| 528 | * @pm8001_ha: our hba card information |
| 529 | */ |
| 530 | static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) |
| 531 | { |
| 532 | u32 value, value1; |
| 533 | u32 max_wait_count; |
| 534 | /* check error state */ |
| 535 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); |
| 536 | value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); |
| 537 | /* check AAP error */ |
| 538 | if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { |
| 539 | /* error state */ |
| 540 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); |
| 541 | return -1; |
| 542 | } |
| 543 | |
| 544 | /* check IOP error */ |
| 545 | if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { |
| 546 | /* error state */ |
| 547 | value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); |
| 548 | return -1; |
| 549 | } |
| 550 | |
| 551 | /* bit 4-31 of scratch pad1 should be zeros if it is not |
| 552 | in error state*/ |
| 553 | if (value & SCRATCH_PAD1_STATE_MASK) { |
| 554 | /* error case */ |
| 555 | pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); |
| 556 | return -1; |
| 557 | } |
| 558 | |
| 559 | /* bit 2, 4-31 of scratch pad2 should be zeros if it is not |
| 560 | in error state */ |
| 561 | if (value1 & SCRATCH_PAD2_STATE_MASK) { |
| 562 | /* error case */ |
| 563 | return -1; |
| 564 | } |
| 565 | |
| 566 | max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ |
| 567 | |
| 568 | /* wait until scratch pad 1 and 2 registers in ready state */ |
| 569 | do { |
| 570 | udelay(1); |
| 571 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) |
| 572 | & SCRATCH_PAD1_RDY; |
| 573 | value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) |
| 574 | & SCRATCH_PAD2_RDY; |
| 575 | if ((--max_wait_count) == 0) |
| 576 | return -1; |
| 577 | } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); |
| 578 | return 0; |
| 579 | } |
| 580 | |
| 581 | static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) |
| 582 | { |
| 583 | void __iomem *base_addr; |
| 584 | u32 value; |
| 585 | u32 offset; |
| 586 | u32 pcibar; |
| 587 | u32 pcilogic; |
| 588 | |
| 589 | value = pm8001_cr32(pm8001_ha, 0, 0x44); |
| 590 | offset = value & 0x03FFFFFF; |
| 591 | PM8001_INIT_DBG(pm8001_ha, |
| 592 | pm8001_printk("Scratchpad 0 Offset: %x \n", offset)); |
| 593 | pcilogic = (value & 0xFC000000) >> 26; |
| 594 | pcibar = get_pci_bar_index(pcilogic); |
| 595 | PM8001_INIT_DBG(pm8001_ha, |
| 596 | pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar)); |
| 597 | pm8001_ha->main_cfg_tbl_addr = base_addr = |
| 598 | pm8001_ha->io_mem[pcibar].memvirtaddr + offset; |
| 599 | pm8001_ha->general_stat_tbl_addr = |
| 600 | base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); |
| 601 | pm8001_ha->inbnd_q_tbl_addr = |
| 602 | base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); |
| 603 | pm8001_ha->outbnd_q_tbl_addr = |
| 604 | base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); |
| 605 | } |
| 606 | |
| 607 | /** |
| 608 | * pm8001_chip_init - the main init function that initialize whole PM8001 chip. |
| 609 | * @pm8001_ha: our hba card information |
| 610 | */ |
| 611 | static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) |
| 612 | { |
| 613 | /* check the firmware status */ |
| 614 | if (-1 == check_fw_ready(pm8001_ha)) { |
| 615 | PM8001_FAIL_DBG(pm8001_ha, |
| 616 | pm8001_printk("Firmware is not ready!\n")); |
| 617 | return -EBUSY; |
| 618 | } |
| 619 | |
| 620 | /* Initialize pci space address eg: mpi offset */ |
| 621 | init_pci_device_addresses(pm8001_ha); |
| 622 | init_default_table_values(pm8001_ha); |
| 623 | read_main_config_table(pm8001_ha); |
| 624 | read_general_status_table(pm8001_ha); |
| 625 | read_inbnd_queue_table(pm8001_ha); |
| 626 | read_outbnd_queue_table(pm8001_ha); |
| 627 | /* update main config table ,inbound table and outbound table */ |
| 628 | update_main_config_table(pm8001_ha); |
| 629 | update_inbnd_queue_table(pm8001_ha, 0); |
| 630 | update_outbnd_queue_table(pm8001_ha, 0); |
| 631 | mpi_set_phys_g3_with_ssc(pm8001_ha, 0); |
| 632 | mpi_set_open_retry_interval_reg(pm8001_ha, 7); |
| 633 | /* notify firmware update finished and check initialization status */ |
| 634 | if (0 == mpi_init_check(pm8001_ha)) { |
| 635 | PM8001_INIT_DBG(pm8001_ha, |
| 636 | pm8001_printk("MPI initialize successful!\n")); |
| 637 | } else |
| 638 | return -EBUSY; |
| 639 | /*This register is a 16-bit timer with a resolution of 1us. This is the |
| 640 | timer used for interrupt delay/coalescing in the PCIe Application Layer. |
| 641 | Zero is not a valid value. A value of 1 in the register will cause the |
| 642 | interrupts to be normal. A value greater than 1 will cause coalescing |
| 643 | delays.*/ |
| 644 | pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); |
| 645 | pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); |
| 646 | return 0; |
| 647 | } |
| 648 | |
| 649 | static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) |
| 650 | { |
| 651 | u32 max_wait_count; |
| 652 | u32 value; |
| 653 | u32 gst_len_mpistate; |
| 654 | init_pci_device_addresses(pm8001_ha); |
| 655 | /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the |
| 656 | table is stop */ |
| 657 | pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); |
| 658 | |
| 659 | /* wait until Inbound DoorBell Clear Register toggled */ |
| 660 | max_wait_count = 1 * 1000 * 1000;/* 1 sec */ |
| 661 | do { |
| 662 | udelay(1); |
| 663 | value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); |
| 664 | value &= SPC_MSGU_CFG_TABLE_RESET; |
| 665 | } while ((value != 0) && (--max_wait_count)); |
| 666 | |
| 667 | if (!max_wait_count) { |
| 668 | PM8001_FAIL_DBG(pm8001_ha, |
| 669 | pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); |
| 670 | return -1; |
| 671 | } |
| 672 | |
| 673 | /* check the MPI-State for termination in progress */ |
| 674 | /* wait until Inbound DoorBell Clear Register toggled */ |
| 675 | max_wait_count = 1 * 1000 * 1000; /* 1 sec */ |
| 676 | do { |
| 677 | udelay(1); |
| 678 | gst_len_mpistate = |
| 679 | pm8001_mr32(pm8001_ha->general_stat_tbl_addr, |
| 680 | GST_GSTLEN_MPIS_OFFSET); |
| 681 | if (GST_MPI_STATE_UNINIT == |
| 682 | (gst_len_mpistate & GST_MPI_STATE_MASK)) |
| 683 | break; |
| 684 | } while (--max_wait_count); |
| 685 | if (!max_wait_count) { |
| 686 | PM8001_FAIL_DBG(pm8001_ha, |
| 687 | pm8001_printk(" TIME OUT MPI State = 0x%x\n", |
| 688 | gst_len_mpistate & GST_MPI_STATE_MASK)); |
| 689 | return -1; |
| 690 | } |
| 691 | return 0; |
| 692 | } |
| 693 | |
| 694 | /** |
| 695 | * soft_reset_ready_check - Function to check FW is ready for soft reset. |
| 696 | * @pm8001_ha: our hba card information |
| 697 | */ |
| 698 | static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) |
| 699 | { |
| 700 | u32 regVal, regVal1, regVal2; |
| 701 | if (mpi_uninit_check(pm8001_ha) != 0) { |
| 702 | PM8001_FAIL_DBG(pm8001_ha, |
| 703 | pm8001_printk("MPI state is not ready\n")); |
| 704 | return -1; |
| 705 | } |
| 706 | /* read the scratch pad 2 register bit 2 */ |
| 707 | regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) |
| 708 | & SCRATCH_PAD2_FWRDY_RST; |
| 709 | if (regVal == SCRATCH_PAD2_FWRDY_RST) { |
| 710 | PM8001_INIT_DBG(pm8001_ha, |
| 711 | pm8001_printk("Firmware is ready for reset .\n")); |
| 712 | } else { |
| 713 | /* Trigger NMI twice via RB6 */ |
| 714 | if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { |
| 715 | PM8001_FAIL_DBG(pm8001_ha, |
| 716 | pm8001_printk("Shift Bar4 to 0x%x failed\n", |
| 717 | RB6_ACCESS_REG)); |
| 718 | return -1; |
| 719 | } |
| 720 | pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, |
| 721 | RB6_MAGIC_NUMBER_RST); |
| 722 | pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); |
| 723 | /* wait for 100 ms */ |
| 724 | mdelay(100); |
| 725 | regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & |
| 726 | SCRATCH_PAD2_FWRDY_RST; |
| 727 | if (regVal != SCRATCH_PAD2_FWRDY_RST) { |
| 728 | regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); |
| 729 | regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); |
| 730 | PM8001_FAIL_DBG(pm8001_ha, |
| 731 | pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" |
| 732 | "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", |
| 733 | regVal1, regVal2)); |
| 734 | PM8001_FAIL_DBG(pm8001_ha, |
| 735 | pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", |
| 736 | pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); |
| 737 | PM8001_FAIL_DBG(pm8001_ha, |
| 738 | pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", |
| 739 | pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); |
| 740 | return -1; |
| 741 | } |
| 742 | } |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | /** |
| 747 | * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all |
| 748 | * the FW register status to the originated status. |
| 749 | * @pm8001_ha: our hba card information |
| 750 | * @signature: signature in host scratch pad0 register. |
| 751 | */ |
| 752 | static int |
| 753 | pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature) |
| 754 | { |
| 755 | u32 regVal, toggleVal; |
| 756 | u32 max_wait_count; |
| 757 | u32 regVal1, regVal2, regVal3; |
| 758 | |
| 759 | /* step1: Check FW is ready for soft reset */ |
| 760 | if (soft_reset_ready_check(pm8001_ha) != 0) { |
| 761 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); |
| 762 | return -1; |
| 763 | } |
| 764 | |
| 765 | /* step 2: clear NMI status register on AAP1 and IOP, write the same |
| 766 | value to clear */ |
| 767 | /* map 0x60000 to BAR4(0x20), BAR2(win) */ |
| 768 | if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { |
| 769 | PM8001_FAIL_DBG(pm8001_ha, |
| 770 | pm8001_printk("Shift Bar4 to 0x%x failed\n", |
| 771 | MBIC_AAP1_ADDR_BASE)); |
| 772 | return -1; |
| 773 | } |
| 774 | regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); |
| 775 | PM8001_INIT_DBG(pm8001_ha, |
| 776 | pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); |
| 777 | pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); |
| 778 | /* map 0x70000 to BAR4(0x20), BAR2(win) */ |
| 779 | if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { |
| 780 | PM8001_FAIL_DBG(pm8001_ha, |
| 781 | pm8001_printk("Shift Bar4 to 0x%x failed\n", |
| 782 | MBIC_IOP_ADDR_BASE)); |
| 783 | return -1; |
| 784 | } |
| 785 | regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); |
| 786 | PM8001_INIT_DBG(pm8001_ha, |
| 787 | pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); |
| 788 | pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); |
| 789 | |
| 790 | regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); |
| 791 | PM8001_INIT_DBG(pm8001_ha, |
| 792 | pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); |
| 793 | pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); |
| 794 | |
| 795 | regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); |
| 796 | PM8001_INIT_DBG(pm8001_ha, |
| 797 | pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); |
| 798 | pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); |
| 799 | |
| 800 | regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); |
| 801 | PM8001_INIT_DBG(pm8001_ha, |
| 802 | pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); |
| 803 | pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); |
| 804 | |
| 805 | regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); |
| 806 | PM8001_INIT_DBG(pm8001_ha, |
| 807 | pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); |
| 808 | pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); |
| 809 | |
| 810 | /* read the scratch pad 1 register bit 2 */ |
| 811 | regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) |
| 812 | & SCRATCH_PAD1_RST; |
| 813 | toggleVal = regVal ^ SCRATCH_PAD1_RST; |
| 814 | |
| 815 | /* set signature in host scratch pad0 register to tell SPC that the |
| 816 | host performs the soft reset */ |
| 817 | pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); |
| 818 | |
| 819 | /* read required registers for confirmming */ |
| 820 | /* map 0x0700000 to BAR4(0x20), BAR2(win) */ |
| 821 | if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { |
| 822 | PM8001_FAIL_DBG(pm8001_ha, |
| 823 | pm8001_printk("Shift Bar4 to 0x%x failed\n", |
| 824 | GSM_ADDR_BASE)); |
| 825 | return -1; |
| 826 | } |
| 827 | PM8001_INIT_DBG(pm8001_ha, |
| 828 | pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" |
| 829 | " Reset = 0x%x\n", |
| 830 | pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); |
| 831 | |
| 832 | /* step 3: host read GSM Configuration and Reset register */ |
| 833 | regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); |
| 834 | /* Put those bits to low */ |
| 835 | /* GSM XCBI offset = 0x70 0000 |
| 836 | 0x00 Bit 13 COM_SLV_SW_RSTB 1 |
| 837 | 0x00 Bit 12 QSSP_SW_RSTB 1 |
| 838 | 0x00 Bit 11 RAAE_SW_RSTB 1 |
| 839 | 0x00 Bit 9 RB_1_SW_RSTB 1 |
| 840 | 0x00 Bit 8 SM_SW_RSTB 1 |
| 841 | */ |
| 842 | regVal &= ~(0x00003b00); |
| 843 | /* host write GSM Configuration and Reset register */ |
| 844 | pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); |
| 845 | PM8001_INIT_DBG(pm8001_ha, |
| 846 | pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " |
| 847 | "Configuration and Reset is set to = 0x%x\n", |
| 848 | pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); |
| 849 | |
| 850 | /* step 4: */ |
| 851 | /* disable GSM - Read Address Parity Check */ |
| 852 | regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); |
| 853 | PM8001_INIT_DBG(pm8001_ha, |
| 854 | pm8001_printk("GSM 0x700038 - Read Address Parity Check " |
| 855 | "Enable = 0x%x\n", regVal1)); |
| 856 | pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); |
| 857 | PM8001_INIT_DBG(pm8001_ha, |
| 858 | pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" |
| 859 | "is set to = 0x%x\n", |
| 860 | pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); |
| 861 | |
| 862 | /* disable GSM - Write Address Parity Check */ |
| 863 | regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); |
| 864 | PM8001_INIT_DBG(pm8001_ha, |
| 865 | pm8001_printk("GSM 0x700040 - Write Address Parity Check" |
| 866 | " Enable = 0x%x\n", regVal2)); |
| 867 | pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); |
| 868 | PM8001_INIT_DBG(pm8001_ha, |
| 869 | pm8001_printk("GSM 0x700040 - Write Address Parity Check " |
| 870 | "Enable is set to = 0x%x\n", |
| 871 | pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); |
| 872 | |
| 873 | /* disable GSM - Write Data Parity Check */ |
| 874 | regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); |
| 875 | PM8001_INIT_DBG(pm8001_ha, |
| 876 | pm8001_printk("GSM 0x300048 - Write Data Parity Check" |
| 877 | " Enable = 0x%x\n", regVal3)); |
| 878 | pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); |
| 879 | PM8001_INIT_DBG(pm8001_ha, |
| 880 | pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" |
| 881 | "is set to = 0x%x\n", |
| 882 | pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); |
| 883 | |
| 884 | /* step 5: delay 10 usec */ |
| 885 | udelay(10); |
| 886 | /* step 5-b: set GPIO-0 output control to tristate anyway */ |
| 887 | if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { |
| 888 | PM8001_INIT_DBG(pm8001_ha, |
| 889 | pm8001_printk("Shift Bar4 to 0x%x failed\n", |
| 890 | GPIO_ADDR_BASE)); |
| 891 | return -1; |
| 892 | } |
| 893 | regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); |
| 894 | PM8001_INIT_DBG(pm8001_ha, |
| 895 | pm8001_printk("GPIO Output Control Register:" |
| 896 | " = 0x%x\n", regVal)); |
| 897 | /* set GPIO-0 output control to tri-state */ |
| 898 | regVal &= 0xFFFFFFFC; |
| 899 | pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); |
| 900 | |
| 901 | /* Step 6: Reset the IOP and AAP1 */ |
| 902 | /* map 0x00000 to BAR4(0x20), BAR2(win) */ |
| 903 | if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { |
| 904 | PM8001_FAIL_DBG(pm8001_ha, |
| 905 | pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", |
| 906 | SPC_TOP_LEVEL_ADDR_BASE)); |
| 907 | return -1; |
| 908 | } |
| 909 | regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); |
| 910 | PM8001_INIT_DBG(pm8001_ha, |
| 911 | pm8001_printk("Top Register before resetting IOP/AAP1" |
| 912 | ":= 0x%x\n", regVal)); |
| 913 | regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); |
| 914 | pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); |
| 915 | |
| 916 | /* step 7: Reset the BDMA/OSSP */ |
| 917 | regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); |
| 918 | PM8001_INIT_DBG(pm8001_ha, |
| 919 | pm8001_printk("Top Register before resetting BDMA/OSSP" |
| 920 | ": = 0x%x\n", regVal)); |
| 921 | regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); |
| 922 | pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); |
| 923 | |
| 924 | /* step 8: delay 10 usec */ |
| 925 | udelay(10); |
| 926 | |
| 927 | /* step 9: bring the BDMA and OSSP out of reset */ |
| 928 | regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); |
| 929 | PM8001_INIT_DBG(pm8001_ha, |
| 930 | pm8001_printk("Top Register before bringing up BDMA/OSSP" |
| 931 | ":= 0x%x\n", regVal)); |
| 932 | regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); |
| 933 | pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); |
| 934 | |
| 935 | /* step 10: delay 10 usec */ |
| 936 | udelay(10); |
| 937 | |
| 938 | /* step 11: reads and sets the GSM Configuration and Reset Register */ |
| 939 | /* map 0x0700000 to BAR4(0x20), BAR2(win) */ |
| 940 | if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { |
| 941 | PM8001_FAIL_DBG(pm8001_ha, |
| 942 | pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", |
| 943 | GSM_ADDR_BASE)); |
| 944 | return -1; |
| 945 | } |
| 946 | PM8001_INIT_DBG(pm8001_ha, |
| 947 | pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " |
| 948 | "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); |
| 949 | regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); |
| 950 | /* Put those bits to high */ |
| 951 | /* GSM XCBI offset = 0x70 0000 |
| 952 | 0x00 Bit 13 COM_SLV_SW_RSTB 1 |
| 953 | 0x00 Bit 12 QSSP_SW_RSTB 1 |
| 954 | 0x00 Bit 11 RAAE_SW_RSTB 1 |
| 955 | 0x00 Bit 9 RB_1_SW_RSTB 1 |
| 956 | 0x00 Bit 8 SM_SW_RSTB 1 |
| 957 | */ |
| 958 | regVal |= (GSM_CONFIG_RESET_VALUE); |
| 959 | pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); |
| 960 | PM8001_INIT_DBG(pm8001_ha, |
| 961 | pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" |
| 962 | " Configuration and Reset is set to = 0x%x\n", |
| 963 | pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); |
| 964 | |
| 965 | /* step 12: Restore GSM - Read Address Parity Check */ |
| 966 | regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); |
| 967 | /* just for debugging */ |
| 968 | PM8001_INIT_DBG(pm8001_ha, |
| 969 | pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" |
| 970 | " = 0x%x\n", regVal)); |
| 971 | pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); |
| 972 | PM8001_INIT_DBG(pm8001_ha, |
| 973 | pm8001_printk("GSM 0x700038 - Read Address Parity" |
| 974 | " Check Enable is set to = 0x%x\n", |
| 975 | pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); |
| 976 | /* Restore GSM - Write Address Parity Check */ |
| 977 | regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); |
| 978 | pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); |
| 979 | PM8001_INIT_DBG(pm8001_ha, |
| 980 | pm8001_printk("GSM 0x700040 - Write Address Parity Check" |
| 981 | " Enable is set to = 0x%x\n", |
| 982 | pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); |
| 983 | /* Restore GSM - Write Data Parity Check */ |
| 984 | regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); |
| 985 | pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); |
| 986 | PM8001_INIT_DBG(pm8001_ha, |
| 987 | pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" |
| 988 | "is set to = 0x%x\n", |
| 989 | pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); |
| 990 | |
| 991 | /* step 13: bring the IOP and AAP1 out of reset */ |
| 992 | /* map 0x00000 to BAR4(0x20), BAR2(win) */ |
| 993 | if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { |
| 994 | PM8001_FAIL_DBG(pm8001_ha, |
| 995 | pm8001_printk("Shift Bar4 to 0x%x failed\n", |
| 996 | SPC_TOP_LEVEL_ADDR_BASE)); |
| 997 | return -1; |
| 998 | } |
| 999 | regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); |
| 1000 | regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); |
| 1001 | pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); |
| 1002 | |
| 1003 | /* step 14: delay 10 usec - Normal Mode */ |
| 1004 | udelay(10); |
| 1005 | /* check Soft Reset Normal mode or Soft Reset HDA mode */ |
| 1006 | if (signature == SPC_SOFT_RESET_SIGNATURE) { |
| 1007 | /* step 15 (Normal Mode): wait until scratch pad1 register |
| 1008 | bit 2 toggled */ |
| 1009 | max_wait_count = 2 * 1000 * 1000;/* 2 sec */ |
| 1010 | do { |
| 1011 | udelay(1); |
| 1012 | regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & |
| 1013 | SCRATCH_PAD1_RST; |
| 1014 | } while ((regVal != toggleVal) && (--max_wait_count)); |
| 1015 | |
| 1016 | if (!max_wait_count) { |
| 1017 | regVal = pm8001_cr32(pm8001_ha, 0, |
| 1018 | MSGU_SCRATCH_PAD_1); |
| 1019 | PM8001_FAIL_DBG(pm8001_ha, |
| 1020 | pm8001_printk("TIMEOUT : ToggleVal 0x%x," |
| 1021 | "MSGU_SCRATCH_PAD1 = 0x%x\n", |
| 1022 | toggleVal, regVal)); |
| 1023 | PM8001_FAIL_DBG(pm8001_ha, |
| 1024 | pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", |
| 1025 | pm8001_cr32(pm8001_ha, 0, |
| 1026 | MSGU_SCRATCH_PAD_0))); |
| 1027 | PM8001_FAIL_DBG(pm8001_ha, |
| 1028 | pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", |
| 1029 | pm8001_cr32(pm8001_ha, 0, |
| 1030 | MSGU_SCRATCH_PAD_2))); |
| 1031 | PM8001_FAIL_DBG(pm8001_ha, |
| 1032 | pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", |
| 1033 | pm8001_cr32(pm8001_ha, 0, |
| 1034 | MSGU_SCRATCH_PAD_3))); |
| 1035 | return -1; |
| 1036 | } |
| 1037 | |
| 1038 | /* step 16 (Normal) - Clear ODMR and ODCR */ |
| 1039 | pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); |
| 1040 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); |
| 1041 | |
| 1042 | /* step 17 (Normal Mode): wait for the FW and IOP to get |
| 1043 | ready - 1 sec timeout */ |
| 1044 | /* Wait for the SPC Configuration Table to be ready */ |
| 1045 | if (check_fw_ready(pm8001_ha) == -1) { |
| 1046 | regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); |
| 1047 | /* return error if MPI Configuration Table not ready */ |
| 1048 | PM8001_INIT_DBG(pm8001_ha, |
| 1049 | pm8001_printk("FW not ready SCRATCH_PAD1" |
| 1050 | " = 0x%x\n", regVal)); |
| 1051 | regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); |
| 1052 | /* return error if MPI Configuration Table not ready */ |
| 1053 | PM8001_INIT_DBG(pm8001_ha, |
| 1054 | pm8001_printk("FW not ready SCRATCH_PAD2" |
| 1055 | " = 0x%x\n", regVal)); |
| 1056 | PM8001_INIT_DBG(pm8001_ha, |
| 1057 | pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", |
| 1058 | pm8001_cr32(pm8001_ha, 0, |
| 1059 | MSGU_SCRATCH_PAD_0))); |
| 1060 | PM8001_INIT_DBG(pm8001_ha, |
| 1061 | pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", |
| 1062 | pm8001_cr32(pm8001_ha, 0, |
| 1063 | MSGU_SCRATCH_PAD_3))); |
| 1064 | return -1; |
| 1065 | } |
| 1066 | } |
| 1067 | |
| 1068 | PM8001_INIT_DBG(pm8001_ha, |
| 1069 | pm8001_printk("SPC soft reset Complete\n")); |
| 1070 | return 0; |
| 1071 | } |
| 1072 | |
| 1073 | static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) |
| 1074 | { |
| 1075 | u32 i; |
| 1076 | u32 regVal; |
| 1077 | PM8001_INIT_DBG(pm8001_ha, |
| 1078 | pm8001_printk("chip reset start\n")); |
| 1079 | |
| 1080 | /* do SPC chip reset. */ |
| 1081 | regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); |
| 1082 | regVal &= ~(SPC_REG_RESET_DEVICE); |
| 1083 | pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); |
| 1084 | |
| 1085 | /* delay 10 usec */ |
| 1086 | udelay(10); |
| 1087 | |
| 1088 | /* bring chip reset out of reset */ |
| 1089 | regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); |
| 1090 | regVal |= SPC_REG_RESET_DEVICE; |
| 1091 | pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); |
| 1092 | |
| 1093 | /* delay 10 usec */ |
| 1094 | udelay(10); |
| 1095 | |
| 1096 | /* wait for 20 msec until the firmware gets reloaded */ |
| 1097 | i = 20; |
| 1098 | do { |
| 1099 | mdelay(1); |
| 1100 | } while ((--i) != 0); |
| 1101 | |
| 1102 | PM8001_INIT_DBG(pm8001_ha, |
| 1103 | pm8001_printk("chip reset finished\n")); |
| 1104 | } |
| 1105 | |
| 1106 | /** |
| 1107 | * pm8001_chip_iounmap - which maped when initilized. |
| 1108 | * @pm8001_ha: our hba card information |
| 1109 | */ |
| 1110 | static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) |
| 1111 | { |
| 1112 | s8 bar, logical = 0; |
| 1113 | for (bar = 0; bar < 6; bar++) { |
| 1114 | /* |
| 1115 | ** logical BARs for SPC: |
| 1116 | ** bar 0 and 1 - logical BAR0 |
| 1117 | ** bar 2 and 3 - logical BAR1 |
| 1118 | ** bar4 - logical BAR2 |
| 1119 | ** bar5 - logical BAR3 |
| 1120 | ** Skip the appropriate assignments: |
| 1121 | */ |
| 1122 | if ((bar == 1) || (bar == 3)) |
| 1123 | continue; |
| 1124 | if (pm8001_ha->io_mem[logical].memvirtaddr) { |
| 1125 | iounmap(pm8001_ha->io_mem[logical].memvirtaddr); |
| 1126 | logical++; |
| 1127 | } |
| 1128 | } |
| 1129 | } |
| 1130 | |
| 1131 | /** |
| 1132 | * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt |
| 1133 | * @pm8001_ha: our hba card information |
| 1134 | */ |
| 1135 | static void |
| 1136 | pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) |
| 1137 | { |
| 1138 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); |
| 1139 | pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); |
| 1140 | } |
| 1141 | |
| 1142 | /** |
| 1143 | * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt |
| 1144 | * @pm8001_ha: our hba card information |
| 1145 | */ |
| 1146 | static void |
| 1147 | pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) |
| 1148 | { |
| 1149 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); |
| 1150 | } |
| 1151 | |
| 1152 | /** |
| 1153 | * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt |
| 1154 | * @pm8001_ha: our hba card information |
| 1155 | */ |
| 1156 | static void |
| 1157 | pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, |
| 1158 | u32 int_vec_idx) |
| 1159 | { |
| 1160 | u32 msi_index; |
| 1161 | u32 value; |
| 1162 | msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; |
| 1163 | msi_index += MSIX_TABLE_BASE; |
| 1164 | pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); |
| 1165 | value = (1 << int_vec_idx); |
| 1166 | pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); |
| 1167 | |
| 1168 | } |
| 1169 | |
| 1170 | /** |
| 1171 | * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt |
| 1172 | * @pm8001_ha: our hba card information |
| 1173 | */ |
| 1174 | static void |
| 1175 | pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, |
| 1176 | u32 int_vec_idx) |
| 1177 | { |
| 1178 | u32 msi_index; |
| 1179 | msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; |
| 1180 | msi_index += MSIX_TABLE_BASE; |
| 1181 | pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); |
| 1182 | |
| 1183 | } |
| 1184 | /** |
| 1185 | * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt |
| 1186 | * @pm8001_ha: our hba card information |
| 1187 | */ |
| 1188 | static void |
| 1189 | pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha) |
| 1190 | { |
| 1191 | #ifdef PM8001_USE_MSIX |
| 1192 | pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); |
| 1193 | return; |
| 1194 | #endif |
| 1195 | pm8001_chip_intx_interrupt_enable(pm8001_ha); |
| 1196 | |
| 1197 | } |
| 1198 | |
| 1199 | /** |
| 1200 | * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt |
| 1201 | * @pm8001_ha: our hba card information |
| 1202 | */ |
| 1203 | static void |
| 1204 | pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha) |
| 1205 | { |
| 1206 | #ifdef PM8001_USE_MSIX |
| 1207 | pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); |
| 1208 | return; |
| 1209 | #endif |
| 1210 | pm8001_chip_intx_interrupt_disable(pm8001_ha); |
| 1211 | |
| 1212 | } |
| 1213 | |
| 1214 | /** |
| 1215 | * mpi_msg_free_get- get the free message buffer for transfer inbound queue. |
| 1216 | * @circularQ: the inbound queue we want to transfer to HBA. |
| 1217 | * @messageSize: the message size of this transfer, normally it is 64 bytes |
| 1218 | * @messagePtr: the pointer to message. |
| 1219 | */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1220 | static int mpi_msg_free_get(struct inbound_queue_table *circularQ, |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1221 | u16 messageSize, void **messagePtr) |
| 1222 | { |
| 1223 | u32 offset, consumer_index; |
| 1224 | struct mpi_msg_hdr *msgHeader; |
| 1225 | u8 bcCount = 1; /* only support single buffer */ |
| 1226 | |
| 1227 | /* Checks is the requested message size can be allocated in this queue*/ |
| 1228 | if (messageSize > 64) { |
| 1229 | *messagePtr = NULL; |
| 1230 | return -1; |
| 1231 | } |
| 1232 | |
| 1233 | /* Stores the new consumer index */ |
| 1234 | consumer_index = pm8001_read_32(circularQ->ci_virt); |
| 1235 | circularQ->consumer_index = cpu_to_le32(consumer_index); |
| 1236 | if (((circularQ->producer_idx + bcCount) % 256) == |
| 1237 | circularQ->consumer_index) { |
| 1238 | *messagePtr = NULL; |
| 1239 | return -1; |
| 1240 | } |
| 1241 | /* get memory IOMB buffer address */ |
| 1242 | offset = circularQ->producer_idx * 64; |
| 1243 | /* increment to next bcCount element */ |
| 1244 | circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256; |
| 1245 | /* Adds that distance to the base of the region virtual address plus |
| 1246 | the message header size*/ |
| 1247 | msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); |
| 1248 | *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); |
| 1249 | return 0; |
| 1250 | } |
| 1251 | |
| 1252 | /** |
| 1253 | * mpi_build_cmd- build the message queue for transfer, update the PI to FW |
| 1254 | * to tell the fw to get this message from IOMB. |
| 1255 | * @pm8001_ha: our hba card information |
| 1256 | * @circularQ: the inbound queue we want to transfer to HBA. |
| 1257 | * @opCode: the operation code represents commands which LLDD and fw recognized. |
| 1258 | * @payload: the command payload of each operation command. |
| 1259 | */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1260 | static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1261 | struct inbound_queue_table *circularQ, |
| 1262 | u32 opCode, void *payload) |
| 1263 | { |
| 1264 | u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; |
| 1265 | u32 responseQueue = 0; |
| 1266 | void *pMessage; |
| 1267 | |
| 1268 | if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) { |
| 1269 | PM8001_IO_DBG(pm8001_ha, |
| 1270 | pm8001_printk("No free mpi buffer \n")); |
| 1271 | return -1; |
| 1272 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1273 | BUG_ON(!payload); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1274 | /*Copy to the payload*/ |
| 1275 | memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr))); |
| 1276 | |
| 1277 | /*Build the header*/ |
| 1278 | Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) |
| 1279 | | ((responseQueue & 0x3F) << 16) |
| 1280 | | ((category & 0xF) << 12) | (opCode & 0xFFF)); |
| 1281 | |
| 1282 | pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); |
| 1283 | /*Update the PI to the firmware*/ |
| 1284 | pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, |
| 1285 | circularQ->pi_offset, circularQ->producer_idx); |
| 1286 | PM8001_IO_DBG(pm8001_ha, |
| 1287 | pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx, |
| 1288 | circularQ->consumer_index)); |
| 1289 | return 0; |
| 1290 | } |
| 1291 | |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1292 | static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1293 | struct outbound_queue_table *circularQ, u8 bc) |
| 1294 | { |
| 1295 | u32 producer_index; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1296 | struct mpi_msg_hdr *msgHeader; |
| 1297 | struct mpi_msg_hdr *pOutBoundMsgHeader; |
| 1298 | |
| 1299 | msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); |
| 1300 | pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + |
| 1301 | circularQ->consumer_idx * 64); |
| 1302 | if (pOutBoundMsgHeader != msgHeader) { |
| 1303 | PM8001_FAIL_DBG(pm8001_ha, |
| 1304 | pm8001_printk("consumer_idx = %d msgHeader = %p\n", |
| 1305 | circularQ->consumer_idx, msgHeader)); |
| 1306 | |
| 1307 | /* Update the producer index from SPC */ |
| 1308 | producer_index = pm8001_read_32(circularQ->pi_virt); |
| 1309 | circularQ->producer_index = cpu_to_le32(producer_index); |
| 1310 | PM8001_FAIL_DBG(pm8001_ha, |
| 1311 | pm8001_printk("consumer_idx = %d producer_index = %d" |
| 1312 | "msgHeader = %p\n", circularQ->consumer_idx, |
| 1313 | circularQ->producer_index, msgHeader)); |
| 1314 | return 0; |
| 1315 | } |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1316 | /* free the circular queue buffer elements associated with the message*/ |
| 1317 | circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256; |
| 1318 | /* update the CI of outbound queue */ |
| 1319 | pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, |
| 1320 | circularQ->consumer_idx); |
| 1321 | /* Update the producer index from SPC*/ |
| 1322 | producer_index = pm8001_read_32(circularQ->pi_virt); |
| 1323 | circularQ->producer_index = cpu_to_le32(producer_index); |
| 1324 | PM8001_IO_DBG(pm8001_ha, |
| 1325 | pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, |
| 1326 | circularQ->producer_index)); |
| 1327 | return 0; |
| 1328 | } |
| 1329 | |
| 1330 | /** |
| 1331 | * mpi_msg_consume- get the MPI message from outbound queue message table. |
| 1332 | * @pm8001_ha: our hba card information |
| 1333 | * @circularQ: the outbound queue table. |
| 1334 | * @messagePtr1: the message contents of this outbound message. |
| 1335 | * @pBC: the message size. |
| 1336 | */ |
| 1337 | static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, |
| 1338 | struct outbound_queue_table *circularQ, |
| 1339 | void **messagePtr1, u8 *pBC) |
| 1340 | { |
| 1341 | struct mpi_msg_hdr *msgHeader; |
| 1342 | __le32 msgHeader_tmp; |
| 1343 | u32 header_tmp; |
| 1344 | do { |
| 1345 | /* If there are not-yet-delivered messages ... */ |
| 1346 | if (circularQ->producer_index != circularQ->consumer_idx) { |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1347 | /*Get the pointer to the circular queue buffer element*/ |
| 1348 | msgHeader = (struct mpi_msg_hdr *) |
| 1349 | (circularQ->base_virt + |
| 1350 | circularQ->consumer_idx * 64); |
| 1351 | /* read header */ |
| 1352 | header_tmp = pm8001_read_32(msgHeader); |
| 1353 | msgHeader_tmp = cpu_to_le32(header_tmp); |
| 1354 | if (0 != (msgHeader_tmp & 0x80000000)) { |
| 1355 | if (OPC_OUB_SKIP_ENTRY != |
| 1356 | (msgHeader_tmp & 0xfff)) { |
| 1357 | *messagePtr1 = |
| 1358 | ((u8 *)msgHeader) + |
| 1359 | sizeof(struct mpi_msg_hdr); |
| 1360 | *pBC = (u8)((msgHeader_tmp >> 24) & |
| 1361 | 0x1f); |
| 1362 | PM8001_IO_DBG(pm8001_ha, |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1363 | pm8001_printk(": CI=%d PI=%d " |
| 1364 | "msgHeader=%x\n", |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1365 | circularQ->consumer_idx, |
| 1366 | circularQ->producer_index, |
| 1367 | msgHeader_tmp)); |
| 1368 | return MPI_IO_STATUS_SUCCESS; |
| 1369 | } else { |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1370 | circularQ->consumer_idx = |
| 1371 | (circularQ->consumer_idx + |
| 1372 | ((msgHeader_tmp >> 24) & 0x1f)) |
| 1373 | % 256; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1374 | msgHeader_tmp = 0; |
| 1375 | pm8001_write_32(msgHeader, 0, 0); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1376 | /* update the CI of outbound queue */ |
| 1377 | pm8001_cw32(pm8001_ha, |
| 1378 | circularQ->ci_pci_bar, |
| 1379 | circularQ->ci_offset, |
| 1380 | circularQ->consumer_idx); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1381 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1382 | } else { |
| 1383 | circularQ->consumer_idx = |
| 1384 | (circularQ->consumer_idx + |
| 1385 | ((msgHeader_tmp >> 24) & 0x1f)) % 256; |
| 1386 | msgHeader_tmp = 0; |
| 1387 | pm8001_write_32(msgHeader, 0, 0); |
| 1388 | /* update the CI of outbound queue */ |
| 1389 | pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, |
| 1390 | circularQ->ci_offset, |
| 1391 | circularQ->consumer_idx); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1392 | return MPI_IO_STATUS_FAIL; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1393 | } |
| 1394 | } else { |
| 1395 | u32 producer_index; |
| 1396 | void *pi_virt = circularQ->pi_virt; |
| 1397 | /* Update the producer index from SPC */ |
| 1398 | producer_index = pm8001_read_32(pi_virt); |
| 1399 | circularQ->producer_index = cpu_to_le32(producer_index); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1400 | } |
| 1401 | } while (circularQ->producer_index != circularQ->consumer_idx); |
| 1402 | /* while we don't have any more not-yet-delivered message */ |
| 1403 | /* report empty */ |
| 1404 | return MPI_IO_STATUS_BUSY; |
| 1405 | } |
| 1406 | |
| 1407 | static void pm8001_work_queue(struct work_struct *work) |
| 1408 | { |
| 1409 | struct delayed_work *dw = container_of(work, struct delayed_work, work); |
| 1410 | struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q); |
| 1411 | struct pm8001_device *pm8001_dev; |
| 1412 | struct domain_device *dev; |
| 1413 | |
| 1414 | switch (wq->handler) { |
| 1415 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: |
| 1416 | pm8001_dev = wq->data; |
| 1417 | dev = pm8001_dev->sas_device; |
| 1418 | pm8001_I_T_nexus_reset(dev); |
| 1419 | break; |
| 1420 | case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: |
| 1421 | pm8001_dev = wq->data; |
| 1422 | dev = pm8001_dev->sas_device; |
| 1423 | pm8001_I_T_nexus_reset(dev); |
| 1424 | break; |
| 1425 | case IO_DS_IN_ERROR: |
| 1426 | pm8001_dev = wq->data; |
| 1427 | dev = pm8001_dev->sas_device; |
| 1428 | pm8001_I_T_nexus_reset(dev); |
| 1429 | break; |
| 1430 | case IO_DS_NON_OPERATIONAL: |
| 1431 | pm8001_dev = wq->data; |
| 1432 | dev = pm8001_dev->sas_device; |
| 1433 | pm8001_I_T_nexus_reset(dev); |
| 1434 | break; |
| 1435 | } |
| 1436 | list_del(&wq->entry); |
| 1437 | kfree(wq); |
| 1438 | } |
| 1439 | |
| 1440 | static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, |
| 1441 | int handler) |
| 1442 | { |
| 1443 | struct pm8001_wq *wq; |
| 1444 | int ret = 0; |
| 1445 | |
| 1446 | wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC); |
| 1447 | if (wq) { |
| 1448 | wq->pm8001_ha = pm8001_ha; |
| 1449 | wq->data = data; |
| 1450 | wq->handler = handler; |
| 1451 | INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue); |
| 1452 | list_add_tail(&wq->entry, &pm8001_ha->wq_list); |
| 1453 | schedule_delayed_work(&wq->work_q, 0); |
| 1454 | } else |
| 1455 | ret = -ENOMEM; |
| 1456 | |
| 1457 | return ret; |
| 1458 | } |
| 1459 | |
| 1460 | /** |
| 1461 | * mpi_ssp_completion- process the event that FW response to the SSP request. |
| 1462 | * @pm8001_ha: our hba card information |
| 1463 | * @piomb: the message contents of this outbound message. |
| 1464 | * |
| 1465 | * When FW has completed a ssp request for example a IO request, after it has |
| 1466 | * filled the SG data with the data, it will trigger this event represent |
| 1467 | * that he has finished the job,please check the coresponding buffer. |
| 1468 | * So we will tell the caller who maybe waiting the result to tell upper layer |
| 1469 | * that the task has been finished. |
| 1470 | */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1471 | static void |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1472 | mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) |
| 1473 | { |
| 1474 | struct sas_task *t; |
| 1475 | struct pm8001_ccb_info *ccb; |
| 1476 | unsigned long flags; |
| 1477 | u32 status; |
| 1478 | u32 param; |
| 1479 | u32 tag; |
| 1480 | struct ssp_completion_resp *psspPayload; |
| 1481 | struct task_status_struct *ts; |
| 1482 | struct ssp_response_iu *iu; |
| 1483 | struct pm8001_device *pm8001_dev; |
| 1484 | psspPayload = (struct ssp_completion_resp *)(piomb + 4); |
| 1485 | status = le32_to_cpu(psspPayload->status); |
| 1486 | tag = le32_to_cpu(psspPayload->tag); |
| 1487 | ccb = &pm8001_ha->ccb_info[tag]; |
| 1488 | pm8001_dev = ccb->device; |
| 1489 | param = le32_to_cpu(psspPayload->param); |
| 1490 | |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1491 | t = ccb->task; |
| 1492 | |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1493 | if (status && status != IO_UNDERFLOW) |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1494 | PM8001_FAIL_DBG(pm8001_ha, |
| 1495 | pm8001_printk("sas IO status 0x%x\n", status)); |
| 1496 | if (unlikely(!t || !t->lldd_task || !t->dev)) |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1497 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1498 | ts = &t->task_status; |
| 1499 | switch (status) { |
| 1500 | case IO_SUCCESS: |
| 1501 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" |
| 1502 | ",param = %d \n", param)); |
| 1503 | if (param == 0) { |
| 1504 | ts->resp = SAS_TASK_COMPLETE; |
| 1505 | ts->stat = SAM_GOOD; |
| 1506 | } else { |
| 1507 | ts->resp = SAS_TASK_COMPLETE; |
| 1508 | ts->stat = SAS_PROTO_RESPONSE; |
| 1509 | ts->residual = param; |
| 1510 | iu = &psspPayload->ssp_resp_iu; |
| 1511 | sas_ssp_task_response(pm8001_ha->dev, t, iu); |
| 1512 | } |
| 1513 | if (pm8001_dev) |
| 1514 | pm8001_dev->running_req--; |
| 1515 | break; |
| 1516 | case IO_ABORTED: |
| 1517 | PM8001_IO_DBG(pm8001_ha, |
| 1518 | pm8001_printk("IO_ABORTED IOMB Tag \n")); |
| 1519 | ts->resp = SAS_TASK_COMPLETE; |
| 1520 | ts->stat = SAS_ABORTED_TASK; |
| 1521 | break; |
| 1522 | case IO_UNDERFLOW: |
| 1523 | /* SSP Completion with error */ |
| 1524 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" |
| 1525 | ",param = %d \n", param)); |
| 1526 | ts->resp = SAS_TASK_COMPLETE; |
| 1527 | ts->stat = SAS_DATA_UNDERRUN; |
| 1528 | ts->residual = param; |
| 1529 | if (pm8001_dev) |
| 1530 | pm8001_dev->running_req--; |
| 1531 | break; |
| 1532 | case IO_NO_DEVICE: |
| 1533 | PM8001_IO_DBG(pm8001_ha, |
| 1534 | pm8001_printk("IO_NO_DEVICE\n")); |
| 1535 | ts->resp = SAS_TASK_UNDELIVERED; |
| 1536 | ts->stat = SAS_PHY_DOWN; |
| 1537 | break; |
| 1538 | case IO_XFER_ERROR_BREAK: |
| 1539 | PM8001_IO_DBG(pm8001_ha, |
| 1540 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); |
| 1541 | ts->resp = SAS_TASK_COMPLETE; |
| 1542 | ts->stat = SAS_OPEN_REJECT; |
| 1543 | break; |
| 1544 | case IO_XFER_ERROR_PHY_NOT_READY: |
| 1545 | PM8001_IO_DBG(pm8001_ha, |
| 1546 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); |
| 1547 | ts->resp = SAS_TASK_COMPLETE; |
| 1548 | ts->stat = SAS_OPEN_REJECT; |
| 1549 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 1550 | break; |
| 1551 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: |
| 1552 | PM8001_IO_DBG(pm8001_ha, |
| 1553 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); |
| 1554 | ts->resp = SAS_TASK_COMPLETE; |
| 1555 | ts->stat = SAS_OPEN_REJECT; |
| 1556 | ts->open_rej_reason = SAS_OREJ_EPROTO; |
| 1557 | break; |
| 1558 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: |
| 1559 | PM8001_IO_DBG(pm8001_ha, |
| 1560 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); |
| 1561 | ts->resp = SAS_TASK_COMPLETE; |
| 1562 | ts->stat = SAS_OPEN_REJECT; |
| 1563 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 1564 | break; |
| 1565 | case IO_OPEN_CNX_ERROR_BREAK: |
| 1566 | PM8001_IO_DBG(pm8001_ha, |
| 1567 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); |
| 1568 | ts->resp = SAS_TASK_COMPLETE; |
| 1569 | ts->stat = SAS_OPEN_REJECT; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1570 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1571 | break; |
| 1572 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: |
| 1573 | PM8001_IO_DBG(pm8001_ha, |
| 1574 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); |
| 1575 | ts->resp = SAS_TASK_COMPLETE; |
| 1576 | ts->stat = SAS_OPEN_REJECT; |
| 1577 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 1578 | if (!t->uldd_task) |
| 1579 | pm8001_handle_event(pm8001_ha, |
| 1580 | pm8001_dev, |
| 1581 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); |
| 1582 | break; |
| 1583 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: |
| 1584 | PM8001_IO_DBG(pm8001_ha, |
| 1585 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); |
| 1586 | ts->resp = SAS_TASK_COMPLETE; |
| 1587 | ts->stat = SAS_OPEN_REJECT; |
| 1588 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; |
| 1589 | break; |
| 1590 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: |
| 1591 | PM8001_IO_DBG(pm8001_ha, |
| 1592 | pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" |
| 1593 | "NOT_SUPPORTED\n")); |
| 1594 | ts->resp = SAS_TASK_COMPLETE; |
| 1595 | ts->stat = SAS_OPEN_REJECT; |
| 1596 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; |
| 1597 | break; |
| 1598 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: |
| 1599 | PM8001_IO_DBG(pm8001_ha, |
| 1600 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); |
| 1601 | ts->resp = SAS_TASK_UNDELIVERED; |
| 1602 | ts->stat = SAS_OPEN_REJECT; |
| 1603 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; |
| 1604 | break; |
| 1605 | case IO_XFER_ERROR_NAK_RECEIVED: |
| 1606 | PM8001_IO_DBG(pm8001_ha, |
| 1607 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); |
| 1608 | ts->resp = SAS_TASK_COMPLETE; |
| 1609 | ts->stat = SAS_OPEN_REJECT; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1610 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1611 | break; |
| 1612 | case IO_XFER_ERROR_ACK_NAK_TIMEOUT: |
| 1613 | PM8001_IO_DBG(pm8001_ha, |
| 1614 | pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); |
| 1615 | ts->resp = SAS_TASK_COMPLETE; |
| 1616 | ts->stat = SAS_NAK_R_ERR; |
| 1617 | break; |
| 1618 | case IO_XFER_ERROR_DMA: |
| 1619 | PM8001_IO_DBG(pm8001_ha, |
| 1620 | pm8001_printk("IO_XFER_ERROR_DMA\n")); |
| 1621 | ts->resp = SAS_TASK_COMPLETE; |
| 1622 | ts->stat = SAS_OPEN_REJECT; |
| 1623 | break; |
| 1624 | case IO_XFER_OPEN_RETRY_TIMEOUT: |
| 1625 | PM8001_IO_DBG(pm8001_ha, |
| 1626 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); |
| 1627 | ts->resp = SAS_TASK_COMPLETE; |
| 1628 | ts->stat = SAS_OPEN_REJECT; |
| 1629 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 1630 | break; |
| 1631 | case IO_XFER_ERROR_OFFSET_MISMATCH: |
| 1632 | PM8001_IO_DBG(pm8001_ha, |
| 1633 | pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); |
| 1634 | ts->resp = SAS_TASK_COMPLETE; |
| 1635 | ts->stat = SAS_OPEN_REJECT; |
| 1636 | break; |
| 1637 | case IO_PORT_IN_RESET: |
| 1638 | PM8001_IO_DBG(pm8001_ha, |
| 1639 | pm8001_printk("IO_PORT_IN_RESET\n")); |
| 1640 | ts->resp = SAS_TASK_COMPLETE; |
| 1641 | ts->stat = SAS_OPEN_REJECT; |
| 1642 | break; |
| 1643 | case IO_DS_NON_OPERATIONAL: |
| 1644 | PM8001_IO_DBG(pm8001_ha, |
| 1645 | pm8001_printk("IO_DS_NON_OPERATIONAL\n")); |
| 1646 | ts->resp = SAS_TASK_COMPLETE; |
| 1647 | ts->stat = SAS_OPEN_REJECT; |
| 1648 | if (!t->uldd_task) |
| 1649 | pm8001_handle_event(pm8001_ha, |
| 1650 | pm8001_dev, |
| 1651 | IO_DS_NON_OPERATIONAL); |
| 1652 | break; |
| 1653 | case IO_DS_IN_RECOVERY: |
| 1654 | PM8001_IO_DBG(pm8001_ha, |
| 1655 | pm8001_printk("IO_DS_IN_RECOVERY\n")); |
| 1656 | ts->resp = SAS_TASK_COMPLETE; |
| 1657 | ts->stat = SAS_OPEN_REJECT; |
| 1658 | break; |
| 1659 | case IO_TM_TAG_NOT_FOUND: |
| 1660 | PM8001_IO_DBG(pm8001_ha, |
| 1661 | pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); |
| 1662 | ts->resp = SAS_TASK_COMPLETE; |
| 1663 | ts->stat = SAS_OPEN_REJECT; |
| 1664 | break; |
| 1665 | case IO_SSP_EXT_IU_ZERO_LEN_ERROR: |
| 1666 | PM8001_IO_DBG(pm8001_ha, |
| 1667 | pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); |
| 1668 | ts->resp = SAS_TASK_COMPLETE; |
| 1669 | ts->stat = SAS_OPEN_REJECT; |
| 1670 | break; |
| 1671 | case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: |
| 1672 | PM8001_IO_DBG(pm8001_ha, |
| 1673 | pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); |
| 1674 | ts->resp = SAS_TASK_COMPLETE; |
| 1675 | ts->stat = SAS_OPEN_REJECT; |
| 1676 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 1677 | default: |
| 1678 | PM8001_IO_DBG(pm8001_ha, |
| 1679 | pm8001_printk("Unknown status 0x%x\n", status)); |
| 1680 | /* not allowed case. Therefore, return failed status */ |
| 1681 | ts->resp = SAS_TASK_COMPLETE; |
| 1682 | ts->stat = SAS_OPEN_REJECT; |
| 1683 | break; |
| 1684 | } |
| 1685 | PM8001_IO_DBG(pm8001_ha, |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1686 | pm8001_printk("scsi_status = %x \n ", |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1687 | psspPayload->ssp_resp_iu.status)); |
| 1688 | spin_lock_irqsave(&t->task_state_lock, flags); |
| 1689 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
| 1690 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; |
| 1691 | t->task_state_flags |= SAS_TASK_STATE_DONE; |
| 1692 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { |
| 1693 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 1694 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" |
| 1695 | " io_status 0x%x resp 0x%x " |
| 1696 | "stat 0x%x but aborted by upper layer!\n", |
| 1697 | t, status, ts->resp, ts->stat)); |
| 1698 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 1699 | } else { |
| 1700 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 1701 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 1702 | mb();/* in order to force CPU ordering */ |
| 1703 | t->task_done(t); |
| 1704 | } |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1705 | } |
| 1706 | |
| 1707 | /*See the comments for mpi_ssp_completion */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1708 | static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1709 | { |
| 1710 | struct sas_task *t; |
| 1711 | unsigned long flags; |
| 1712 | struct task_status_struct *ts; |
| 1713 | struct pm8001_ccb_info *ccb; |
| 1714 | struct pm8001_device *pm8001_dev; |
| 1715 | struct ssp_event_resp *psspPayload = |
| 1716 | (struct ssp_event_resp *)(piomb + 4); |
| 1717 | u32 event = le32_to_cpu(psspPayload->event); |
| 1718 | u32 tag = le32_to_cpu(psspPayload->tag); |
| 1719 | u32 port_id = le32_to_cpu(psspPayload->port_id); |
| 1720 | u32 dev_id = le32_to_cpu(psspPayload->device_id); |
| 1721 | |
| 1722 | ccb = &pm8001_ha->ccb_info[tag]; |
| 1723 | t = ccb->task; |
| 1724 | pm8001_dev = ccb->device; |
| 1725 | if (event) |
| 1726 | PM8001_FAIL_DBG(pm8001_ha, |
| 1727 | pm8001_printk("sas IO status 0x%x\n", event)); |
| 1728 | if (unlikely(!t || !t->lldd_task || !t->dev)) |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1729 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1730 | ts = &t->task_status; |
| 1731 | PM8001_IO_DBG(pm8001_ha, |
| 1732 | pm8001_printk("port_id = %x,device_id = %x\n", |
| 1733 | port_id, dev_id)); |
| 1734 | switch (event) { |
| 1735 | case IO_OVERFLOW: |
| 1736 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) |
| 1737 | ts->resp = SAS_TASK_COMPLETE; |
| 1738 | ts->stat = SAS_DATA_OVERRUN; |
| 1739 | ts->residual = 0; |
| 1740 | if (pm8001_dev) |
| 1741 | pm8001_dev->running_req--; |
| 1742 | break; |
| 1743 | case IO_XFER_ERROR_BREAK: |
| 1744 | PM8001_IO_DBG(pm8001_ha, |
| 1745 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); |
| 1746 | ts->resp = SAS_TASK_COMPLETE; |
| 1747 | ts->stat = SAS_INTERRUPTED; |
| 1748 | break; |
| 1749 | case IO_XFER_ERROR_PHY_NOT_READY: |
| 1750 | PM8001_IO_DBG(pm8001_ha, |
| 1751 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); |
| 1752 | ts->resp = SAS_TASK_COMPLETE; |
| 1753 | ts->stat = SAS_OPEN_REJECT; |
| 1754 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 1755 | break; |
| 1756 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: |
| 1757 | PM8001_IO_DBG(pm8001_ha, |
| 1758 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" |
| 1759 | "_SUPPORTED\n")); |
| 1760 | ts->resp = SAS_TASK_COMPLETE; |
| 1761 | ts->stat = SAS_OPEN_REJECT; |
| 1762 | ts->open_rej_reason = SAS_OREJ_EPROTO; |
| 1763 | break; |
| 1764 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: |
| 1765 | PM8001_IO_DBG(pm8001_ha, |
| 1766 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); |
| 1767 | ts->resp = SAS_TASK_COMPLETE; |
| 1768 | ts->stat = SAS_OPEN_REJECT; |
| 1769 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 1770 | break; |
| 1771 | case IO_OPEN_CNX_ERROR_BREAK: |
| 1772 | PM8001_IO_DBG(pm8001_ha, |
| 1773 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); |
| 1774 | ts->resp = SAS_TASK_COMPLETE; |
| 1775 | ts->stat = SAS_OPEN_REJECT; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1776 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1777 | break; |
| 1778 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: |
| 1779 | PM8001_IO_DBG(pm8001_ha, |
| 1780 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); |
| 1781 | ts->resp = SAS_TASK_COMPLETE; |
| 1782 | ts->stat = SAS_OPEN_REJECT; |
| 1783 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 1784 | if (!t->uldd_task) |
| 1785 | pm8001_handle_event(pm8001_ha, |
| 1786 | pm8001_dev, |
| 1787 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); |
| 1788 | break; |
| 1789 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: |
| 1790 | PM8001_IO_DBG(pm8001_ha, |
| 1791 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); |
| 1792 | ts->resp = SAS_TASK_COMPLETE; |
| 1793 | ts->stat = SAS_OPEN_REJECT; |
| 1794 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; |
| 1795 | break; |
| 1796 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: |
| 1797 | PM8001_IO_DBG(pm8001_ha, |
| 1798 | pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" |
| 1799 | "NOT_SUPPORTED\n")); |
| 1800 | ts->resp = SAS_TASK_COMPLETE; |
| 1801 | ts->stat = SAS_OPEN_REJECT; |
| 1802 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; |
| 1803 | break; |
| 1804 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: |
| 1805 | PM8001_IO_DBG(pm8001_ha, |
| 1806 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); |
| 1807 | ts->resp = SAS_TASK_COMPLETE; |
| 1808 | ts->stat = SAS_OPEN_REJECT; |
| 1809 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; |
| 1810 | break; |
| 1811 | case IO_XFER_ERROR_NAK_RECEIVED: |
| 1812 | PM8001_IO_DBG(pm8001_ha, |
| 1813 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); |
| 1814 | ts->resp = SAS_TASK_COMPLETE; |
| 1815 | ts->stat = SAS_OPEN_REJECT; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1816 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1817 | break; |
| 1818 | case IO_XFER_ERROR_ACK_NAK_TIMEOUT: |
| 1819 | PM8001_IO_DBG(pm8001_ha, |
| 1820 | pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); |
| 1821 | ts->resp = SAS_TASK_COMPLETE; |
| 1822 | ts->stat = SAS_NAK_R_ERR; |
| 1823 | break; |
| 1824 | case IO_XFER_OPEN_RETRY_TIMEOUT: |
| 1825 | PM8001_IO_DBG(pm8001_ha, |
| 1826 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); |
| 1827 | ts->resp = SAS_TASK_COMPLETE; |
| 1828 | ts->stat = SAS_OPEN_REJECT; |
| 1829 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 1830 | break; |
| 1831 | case IO_XFER_ERROR_UNEXPECTED_PHASE: |
| 1832 | PM8001_IO_DBG(pm8001_ha, |
| 1833 | pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); |
| 1834 | ts->resp = SAS_TASK_COMPLETE; |
| 1835 | ts->stat = SAS_DATA_OVERRUN; |
| 1836 | break; |
| 1837 | case IO_XFER_ERROR_XFER_RDY_OVERRUN: |
| 1838 | PM8001_IO_DBG(pm8001_ha, |
| 1839 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); |
| 1840 | ts->resp = SAS_TASK_COMPLETE; |
| 1841 | ts->stat = SAS_DATA_OVERRUN; |
| 1842 | break; |
| 1843 | case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: |
| 1844 | PM8001_IO_DBG(pm8001_ha, |
| 1845 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); |
| 1846 | ts->resp = SAS_TASK_COMPLETE; |
| 1847 | ts->stat = SAS_DATA_OVERRUN; |
| 1848 | break; |
| 1849 | case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: |
| 1850 | PM8001_IO_DBG(pm8001_ha, |
| 1851 | pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); |
| 1852 | ts->resp = SAS_TASK_COMPLETE; |
| 1853 | ts->stat = SAS_DATA_OVERRUN; |
| 1854 | break; |
| 1855 | case IO_XFER_ERROR_OFFSET_MISMATCH: |
| 1856 | PM8001_IO_DBG(pm8001_ha, |
| 1857 | pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); |
| 1858 | ts->resp = SAS_TASK_COMPLETE; |
| 1859 | ts->stat = SAS_DATA_OVERRUN; |
| 1860 | break; |
| 1861 | case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: |
| 1862 | PM8001_IO_DBG(pm8001_ha, |
| 1863 | pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); |
| 1864 | ts->resp = SAS_TASK_COMPLETE; |
| 1865 | ts->stat = SAS_DATA_OVERRUN; |
| 1866 | break; |
| 1867 | case IO_XFER_CMD_FRAME_ISSUED: |
| 1868 | PM8001_IO_DBG(pm8001_ha, |
| 1869 | pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1870 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1871 | default: |
| 1872 | PM8001_IO_DBG(pm8001_ha, |
| 1873 | pm8001_printk("Unknown status 0x%x\n", event)); |
| 1874 | /* not allowed case. Therefore, return failed status */ |
| 1875 | ts->resp = SAS_TASK_COMPLETE; |
| 1876 | ts->stat = SAS_DATA_OVERRUN; |
| 1877 | break; |
| 1878 | } |
| 1879 | spin_lock_irqsave(&t->task_state_lock, flags); |
| 1880 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
| 1881 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; |
| 1882 | t->task_state_flags |= SAS_TASK_STATE_DONE; |
| 1883 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { |
| 1884 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 1885 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" |
| 1886 | " event 0x%x resp 0x%x " |
| 1887 | "stat 0x%x but aborted by upper layer!\n", |
| 1888 | t, event, ts->resp, ts->stat)); |
| 1889 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 1890 | } else { |
| 1891 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 1892 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 1893 | mb();/* in order to force CPU ordering */ |
| 1894 | t->task_done(t); |
| 1895 | } |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1896 | } |
| 1897 | |
| 1898 | /*See the comments for mpi_ssp_completion */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1899 | static void |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1900 | mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 1901 | { |
| 1902 | struct sas_task *t; |
| 1903 | struct pm8001_ccb_info *ccb; |
| 1904 | unsigned long flags; |
| 1905 | u32 param; |
| 1906 | u32 status; |
| 1907 | u32 tag; |
| 1908 | struct sata_completion_resp *psataPayload; |
| 1909 | struct task_status_struct *ts; |
| 1910 | struct ata_task_resp *resp ; |
| 1911 | u32 *sata_resp; |
| 1912 | struct pm8001_device *pm8001_dev; |
| 1913 | |
| 1914 | psataPayload = (struct sata_completion_resp *)(piomb + 4); |
| 1915 | status = le32_to_cpu(psataPayload->status); |
| 1916 | tag = le32_to_cpu(psataPayload->tag); |
| 1917 | |
| 1918 | ccb = &pm8001_ha->ccb_info[tag]; |
| 1919 | param = le32_to_cpu(psataPayload->param); |
| 1920 | t = ccb->task; |
| 1921 | ts = &t->task_status; |
| 1922 | pm8001_dev = ccb->device; |
| 1923 | if (status) |
| 1924 | PM8001_FAIL_DBG(pm8001_ha, |
| 1925 | pm8001_printk("sata IO status 0x%x\n", status)); |
| 1926 | if (unlikely(!t || !t->lldd_task || !t->dev)) |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 1927 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 1928 | |
| 1929 | switch (status) { |
| 1930 | case IO_SUCCESS: |
| 1931 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); |
| 1932 | if (param == 0) { |
| 1933 | ts->resp = SAS_TASK_COMPLETE; |
| 1934 | ts->stat = SAM_GOOD; |
| 1935 | } else { |
| 1936 | u8 len; |
| 1937 | ts->resp = SAS_TASK_COMPLETE; |
| 1938 | ts->stat = SAS_PROTO_RESPONSE; |
| 1939 | ts->residual = param; |
| 1940 | PM8001_IO_DBG(pm8001_ha, |
| 1941 | pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", |
| 1942 | param)); |
| 1943 | sata_resp = &psataPayload->sata_resp[0]; |
| 1944 | resp = (struct ata_task_resp *)ts->buf; |
| 1945 | if (t->ata_task.dma_xfer == 0 && |
| 1946 | t->data_dir == PCI_DMA_FROMDEVICE) { |
| 1947 | len = sizeof(struct pio_setup_fis); |
| 1948 | PM8001_IO_DBG(pm8001_ha, |
| 1949 | pm8001_printk("PIO read len = %d\n", len)); |
| 1950 | } else if (t->ata_task.use_ncq) { |
| 1951 | len = sizeof(struct set_dev_bits_fis); |
| 1952 | PM8001_IO_DBG(pm8001_ha, |
| 1953 | pm8001_printk("FPDMA len = %d\n", len)); |
| 1954 | } else { |
| 1955 | len = sizeof(struct dev_to_host_fis); |
| 1956 | PM8001_IO_DBG(pm8001_ha, |
| 1957 | pm8001_printk("other len = %d\n", len)); |
| 1958 | } |
| 1959 | if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { |
| 1960 | resp->frame_len = len; |
| 1961 | memcpy(&resp->ending_fis[0], sata_resp, len); |
| 1962 | ts->buf_valid_size = sizeof(*resp); |
| 1963 | } else |
| 1964 | PM8001_IO_DBG(pm8001_ha, |
| 1965 | pm8001_printk("response to large \n")); |
| 1966 | } |
| 1967 | if (pm8001_dev) |
| 1968 | pm8001_dev->running_req--; |
| 1969 | break; |
| 1970 | case IO_ABORTED: |
| 1971 | PM8001_IO_DBG(pm8001_ha, |
| 1972 | pm8001_printk("IO_ABORTED IOMB Tag \n")); |
| 1973 | ts->resp = SAS_TASK_COMPLETE; |
| 1974 | ts->stat = SAS_ABORTED_TASK; |
| 1975 | if (pm8001_dev) |
| 1976 | pm8001_dev->running_req--; |
| 1977 | break; |
| 1978 | /* following cases are to do cases */ |
| 1979 | case IO_UNDERFLOW: |
| 1980 | /* SATA Completion with error */ |
| 1981 | PM8001_IO_DBG(pm8001_ha, |
| 1982 | pm8001_printk("IO_UNDERFLOW param = %d\n", param)); |
| 1983 | ts->resp = SAS_TASK_COMPLETE; |
| 1984 | ts->stat = SAS_DATA_UNDERRUN; |
| 1985 | ts->residual = param; |
| 1986 | if (pm8001_dev) |
| 1987 | pm8001_dev->running_req--; |
| 1988 | break; |
| 1989 | case IO_NO_DEVICE: |
| 1990 | PM8001_IO_DBG(pm8001_ha, |
| 1991 | pm8001_printk("IO_NO_DEVICE\n")); |
| 1992 | ts->resp = SAS_TASK_UNDELIVERED; |
| 1993 | ts->stat = SAS_PHY_DOWN; |
| 1994 | break; |
| 1995 | case IO_XFER_ERROR_BREAK: |
| 1996 | PM8001_IO_DBG(pm8001_ha, |
| 1997 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); |
| 1998 | ts->resp = SAS_TASK_COMPLETE; |
| 1999 | ts->stat = SAS_INTERRUPTED; |
| 2000 | break; |
| 2001 | case IO_XFER_ERROR_PHY_NOT_READY: |
| 2002 | PM8001_IO_DBG(pm8001_ha, |
| 2003 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); |
| 2004 | ts->resp = SAS_TASK_COMPLETE; |
| 2005 | ts->stat = SAS_OPEN_REJECT; |
| 2006 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2007 | break; |
| 2008 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: |
| 2009 | PM8001_IO_DBG(pm8001_ha, |
| 2010 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" |
| 2011 | "_SUPPORTED\n")); |
| 2012 | ts->resp = SAS_TASK_COMPLETE; |
| 2013 | ts->stat = SAS_OPEN_REJECT; |
| 2014 | ts->open_rej_reason = SAS_OREJ_EPROTO; |
| 2015 | break; |
| 2016 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: |
| 2017 | PM8001_IO_DBG(pm8001_ha, |
| 2018 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); |
| 2019 | ts->resp = SAS_TASK_COMPLETE; |
| 2020 | ts->stat = SAS_OPEN_REJECT; |
| 2021 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 2022 | break; |
| 2023 | case IO_OPEN_CNX_ERROR_BREAK: |
| 2024 | PM8001_IO_DBG(pm8001_ha, |
| 2025 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); |
| 2026 | ts->resp = SAS_TASK_COMPLETE; |
| 2027 | ts->stat = SAS_OPEN_REJECT; |
| 2028 | ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; |
| 2029 | break; |
| 2030 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: |
| 2031 | PM8001_IO_DBG(pm8001_ha, |
| 2032 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); |
| 2033 | ts->resp = SAS_TASK_COMPLETE; |
| 2034 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2035 | if (!t->uldd_task) { |
| 2036 | pm8001_handle_event(pm8001_ha, |
| 2037 | pm8001_dev, |
| 2038 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); |
| 2039 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2040 | ts->stat = SAS_QUEUE_FULL; |
| 2041 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2042 | mb();/*in order to force CPU ordering*/ |
| 2043 | t->task_done(t); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2044 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2045 | } |
| 2046 | break; |
| 2047 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: |
| 2048 | PM8001_IO_DBG(pm8001_ha, |
| 2049 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); |
| 2050 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2051 | ts->stat = SAS_OPEN_REJECT; |
| 2052 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; |
| 2053 | if (!t->uldd_task) { |
| 2054 | pm8001_handle_event(pm8001_ha, |
| 2055 | pm8001_dev, |
| 2056 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); |
| 2057 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2058 | ts->stat = SAS_QUEUE_FULL; |
| 2059 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2060 | mb();/*ditto*/ |
| 2061 | t->task_done(t); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2062 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2063 | } |
| 2064 | break; |
| 2065 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: |
| 2066 | PM8001_IO_DBG(pm8001_ha, |
| 2067 | pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" |
| 2068 | "NOT_SUPPORTED\n")); |
| 2069 | ts->resp = SAS_TASK_COMPLETE; |
| 2070 | ts->stat = SAS_OPEN_REJECT; |
| 2071 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; |
| 2072 | break; |
| 2073 | case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: |
| 2074 | PM8001_IO_DBG(pm8001_ha, |
| 2075 | pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" |
| 2076 | "_BUSY\n")); |
| 2077 | ts->resp = SAS_TASK_COMPLETE; |
| 2078 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2079 | if (!t->uldd_task) { |
| 2080 | pm8001_handle_event(pm8001_ha, |
| 2081 | pm8001_dev, |
| 2082 | IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); |
| 2083 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2084 | ts->stat = SAS_QUEUE_FULL; |
| 2085 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2086 | mb();/* ditto*/ |
| 2087 | t->task_done(t); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2088 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2089 | } |
| 2090 | break; |
| 2091 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: |
| 2092 | PM8001_IO_DBG(pm8001_ha, |
| 2093 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); |
| 2094 | ts->resp = SAS_TASK_COMPLETE; |
| 2095 | ts->stat = SAS_OPEN_REJECT; |
| 2096 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; |
| 2097 | break; |
| 2098 | case IO_XFER_ERROR_NAK_RECEIVED: |
| 2099 | PM8001_IO_DBG(pm8001_ha, |
| 2100 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); |
| 2101 | ts->resp = SAS_TASK_COMPLETE; |
| 2102 | ts->stat = SAS_NAK_R_ERR; |
| 2103 | break; |
| 2104 | case IO_XFER_ERROR_ACK_NAK_TIMEOUT: |
| 2105 | PM8001_IO_DBG(pm8001_ha, |
| 2106 | pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); |
| 2107 | ts->resp = SAS_TASK_COMPLETE; |
| 2108 | ts->stat = SAS_NAK_R_ERR; |
| 2109 | break; |
| 2110 | case IO_XFER_ERROR_DMA: |
| 2111 | PM8001_IO_DBG(pm8001_ha, |
| 2112 | pm8001_printk("IO_XFER_ERROR_DMA\n")); |
| 2113 | ts->resp = SAS_TASK_COMPLETE; |
| 2114 | ts->stat = SAS_ABORTED_TASK; |
| 2115 | break; |
| 2116 | case IO_XFER_ERROR_SATA_LINK_TIMEOUT: |
| 2117 | PM8001_IO_DBG(pm8001_ha, |
| 2118 | pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); |
| 2119 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2120 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2121 | break; |
| 2122 | case IO_XFER_ERROR_REJECTED_NCQ_MODE: |
| 2123 | PM8001_IO_DBG(pm8001_ha, |
| 2124 | pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); |
| 2125 | ts->resp = SAS_TASK_COMPLETE; |
| 2126 | ts->stat = SAS_DATA_UNDERRUN; |
| 2127 | break; |
| 2128 | case IO_XFER_OPEN_RETRY_TIMEOUT: |
| 2129 | PM8001_IO_DBG(pm8001_ha, |
| 2130 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); |
| 2131 | ts->resp = SAS_TASK_COMPLETE; |
| 2132 | ts->stat = SAS_OPEN_TO; |
| 2133 | break; |
| 2134 | case IO_PORT_IN_RESET: |
| 2135 | PM8001_IO_DBG(pm8001_ha, |
| 2136 | pm8001_printk("IO_PORT_IN_RESET\n")); |
| 2137 | ts->resp = SAS_TASK_COMPLETE; |
| 2138 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2139 | break; |
| 2140 | case IO_DS_NON_OPERATIONAL: |
| 2141 | PM8001_IO_DBG(pm8001_ha, |
| 2142 | pm8001_printk("IO_DS_NON_OPERATIONAL\n")); |
| 2143 | ts->resp = SAS_TASK_COMPLETE; |
| 2144 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2145 | if (!t->uldd_task) { |
| 2146 | pm8001_handle_event(pm8001_ha, pm8001_dev, |
| 2147 | IO_DS_NON_OPERATIONAL); |
| 2148 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2149 | ts->stat = SAS_QUEUE_FULL; |
| 2150 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2151 | mb();/*ditto*/ |
| 2152 | t->task_done(t); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2153 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2154 | } |
| 2155 | break; |
| 2156 | case IO_DS_IN_RECOVERY: |
| 2157 | PM8001_IO_DBG(pm8001_ha, |
| 2158 | pm8001_printk(" IO_DS_IN_RECOVERY\n")); |
| 2159 | ts->resp = SAS_TASK_COMPLETE; |
| 2160 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2161 | break; |
| 2162 | case IO_DS_IN_ERROR: |
| 2163 | PM8001_IO_DBG(pm8001_ha, |
| 2164 | pm8001_printk("IO_DS_IN_ERROR\n")); |
| 2165 | ts->resp = SAS_TASK_COMPLETE; |
| 2166 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2167 | if (!t->uldd_task) { |
| 2168 | pm8001_handle_event(pm8001_ha, pm8001_dev, |
| 2169 | IO_DS_IN_ERROR); |
| 2170 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2171 | ts->stat = SAS_QUEUE_FULL; |
| 2172 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2173 | mb();/*ditto*/ |
| 2174 | t->task_done(t); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2175 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2176 | } |
| 2177 | break; |
| 2178 | case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: |
| 2179 | PM8001_IO_DBG(pm8001_ha, |
| 2180 | pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); |
| 2181 | ts->resp = SAS_TASK_COMPLETE; |
| 2182 | ts->stat = SAS_OPEN_REJECT; |
| 2183 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2184 | default: |
| 2185 | PM8001_IO_DBG(pm8001_ha, |
| 2186 | pm8001_printk("Unknown status 0x%x\n", status)); |
| 2187 | /* not allowed case. Therefore, return failed status */ |
| 2188 | ts->resp = SAS_TASK_COMPLETE; |
| 2189 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2190 | break; |
| 2191 | } |
| 2192 | spin_lock_irqsave(&t->task_state_lock, flags); |
| 2193 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
| 2194 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; |
| 2195 | t->task_state_flags |= SAS_TASK_STATE_DONE; |
| 2196 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { |
| 2197 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 2198 | PM8001_FAIL_DBG(pm8001_ha, |
| 2199 | pm8001_printk("task 0x%p done with io_status 0x%x" |
| 2200 | " resp 0x%x stat 0x%x but aborted by upper layer!\n", |
| 2201 | t, status, ts->resp, ts->stat)); |
| 2202 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2203 | } else { |
| 2204 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 2205 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2206 | mb();/* ditto */ |
| 2207 | t->task_done(t); |
| 2208 | } |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2209 | } |
| 2210 | |
| 2211 | /*See the comments for mpi_ssp_completion */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2212 | static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2213 | { |
| 2214 | struct sas_task *t; |
| 2215 | unsigned long flags; |
| 2216 | struct task_status_struct *ts; |
| 2217 | struct pm8001_ccb_info *ccb; |
| 2218 | struct pm8001_device *pm8001_dev; |
| 2219 | struct sata_event_resp *psataPayload = |
| 2220 | (struct sata_event_resp *)(piomb + 4); |
| 2221 | u32 event = le32_to_cpu(psataPayload->event); |
| 2222 | u32 tag = le32_to_cpu(psataPayload->tag); |
| 2223 | u32 port_id = le32_to_cpu(psataPayload->port_id); |
| 2224 | u32 dev_id = le32_to_cpu(psataPayload->device_id); |
| 2225 | |
| 2226 | ccb = &pm8001_ha->ccb_info[tag]; |
| 2227 | t = ccb->task; |
| 2228 | pm8001_dev = ccb->device; |
| 2229 | if (event) |
| 2230 | PM8001_FAIL_DBG(pm8001_ha, |
| 2231 | pm8001_printk("sata IO status 0x%x\n", event)); |
| 2232 | if (unlikely(!t || !t->lldd_task || !t->dev)) |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2233 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2234 | ts = &t->task_status; |
| 2235 | PM8001_IO_DBG(pm8001_ha, |
| 2236 | pm8001_printk("port_id = %x,device_id = %x\n", |
| 2237 | port_id, dev_id)); |
| 2238 | switch (event) { |
| 2239 | case IO_OVERFLOW: |
| 2240 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); |
| 2241 | ts->resp = SAS_TASK_COMPLETE; |
| 2242 | ts->stat = SAS_DATA_OVERRUN; |
| 2243 | ts->residual = 0; |
| 2244 | if (pm8001_dev) |
| 2245 | pm8001_dev->running_req--; |
| 2246 | break; |
| 2247 | case IO_XFER_ERROR_BREAK: |
| 2248 | PM8001_IO_DBG(pm8001_ha, |
| 2249 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); |
| 2250 | ts->resp = SAS_TASK_COMPLETE; |
| 2251 | ts->stat = SAS_INTERRUPTED; |
| 2252 | break; |
| 2253 | case IO_XFER_ERROR_PHY_NOT_READY: |
| 2254 | PM8001_IO_DBG(pm8001_ha, |
| 2255 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); |
| 2256 | ts->resp = SAS_TASK_COMPLETE; |
| 2257 | ts->stat = SAS_OPEN_REJECT; |
| 2258 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2259 | break; |
| 2260 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: |
| 2261 | PM8001_IO_DBG(pm8001_ha, |
| 2262 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" |
| 2263 | "_SUPPORTED\n")); |
| 2264 | ts->resp = SAS_TASK_COMPLETE; |
| 2265 | ts->stat = SAS_OPEN_REJECT; |
| 2266 | ts->open_rej_reason = SAS_OREJ_EPROTO; |
| 2267 | break; |
| 2268 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: |
| 2269 | PM8001_IO_DBG(pm8001_ha, |
| 2270 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); |
| 2271 | ts->resp = SAS_TASK_COMPLETE; |
| 2272 | ts->stat = SAS_OPEN_REJECT; |
| 2273 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 2274 | break; |
| 2275 | case IO_OPEN_CNX_ERROR_BREAK: |
| 2276 | PM8001_IO_DBG(pm8001_ha, |
| 2277 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); |
| 2278 | ts->resp = SAS_TASK_COMPLETE; |
| 2279 | ts->stat = SAS_OPEN_REJECT; |
| 2280 | ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; |
| 2281 | break; |
| 2282 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: |
| 2283 | PM8001_IO_DBG(pm8001_ha, |
| 2284 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); |
| 2285 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2286 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2287 | if (!t->uldd_task) { |
| 2288 | pm8001_handle_event(pm8001_ha, |
| 2289 | pm8001_dev, |
| 2290 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); |
| 2291 | ts->resp = SAS_TASK_COMPLETE; |
| 2292 | ts->stat = SAS_QUEUE_FULL; |
| 2293 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2294 | mb();/*ditto*/ |
| 2295 | t->task_done(t); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2296 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2297 | } |
| 2298 | break; |
| 2299 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: |
| 2300 | PM8001_IO_DBG(pm8001_ha, |
| 2301 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); |
| 2302 | ts->resp = SAS_TASK_UNDELIVERED; |
| 2303 | ts->stat = SAS_OPEN_REJECT; |
| 2304 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; |
| 2305 | break; |
| 2306 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: |
| 2307 | PM8001_IO_DBG(pm8001_ha, |
| 2308 | pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" |
| 2309 | "NOT_SUPPORTED\n")); |
| 2310 | ts->resp = SAS_TASK_COMPLETE; |
| 2311 | ts->stat = SAS_OPEN_REJECT; |
| 2312 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; |
| 2313 | break; |
| 2314 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: |
| 2315 | PM8001_IO_DBG(pm8001_ha, |
| 2316 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); |
| 2317 | ts->resp = SAS_TASK_COMPLETE; |
| 2318 | ts->stat = SAS_OPEN_REJECT; |
| 2319 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; |
| 2320 | break; |
| 2321 | case IO_XFER_ERROR_NAK_RECEIVED: |
| 2322 | PM8001_IO_DBG(pm8001_ha, |
| 2323 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); |
| 2324 | ts->resp = SAS_TASK_COMPLETE; |
| 2325 | ts->stat = SAS_NAK_R_ERR; |
| 2326 | break; |
| 2327 | case IO_XFER_ERROR_PEER_ABORTED: |
| 2328 | PM8001_IO_DBG(pm8001_ha, |
| 2329 | pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); |
| 2330 | ts->resp = SAS_TASK_COMPLETE; |
| 2331 | ts->stat = SAS_NAK_R_ERR; |
| 2332 | break; |
| 2333 | case IO_XFER_ERROR_REJECTED_NCQ_MODE: |
| 2334 | PM8001_IO_DBG(pm8001_ha, |
| 2335 | pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); |
| 2336 | ts->resp = SAS_TASK_COMPLETE; |
| 2337 | ts->stat = SAS_DATA_UNDERRUN; |
| 2338 | break; |
| 2339 | case IO_XFER_OPEN_RETRY_TIMEOUT: |
| 2340 | PM8001_IO_DBG(pm8001_ha, |
| 2341 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); |
| 2342 | ts->resp = SAS_TASK_COMPLETE; |
| 2343 | ts->stat = SAS_OPEN_TO; |
| 2344 | break; |
| 2345 | case IO_XFER_ERROR_UNEXPECTED_PHASE: |
| 2346 | PM8001_IO_DBG(pm8001_ha, |
| 2347 | pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); |
| 2348 | ts->resp = SAS_TASK_COMPLETE; |
| 2349 | ts->stat = SAS_OPEN_TO; |
| 2350 | break; |
| 2351 | case IO_XFER_ERROR_XFER_RDY_OVERRUN: |
| 2352 | PM8001_IO_DBG(pm8001_ha, |
| 2353 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); |
| 2354 | ts->resp = SAS_TASK_COMPLETE; |
| 2355 | ts->stat = SAS_OPEN_TO; |
| 2356 | break; |
| 2357 | case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: |
| 2358 | PM8001_IO_DBG(pm8001_ha, |
| 2359 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); |
| 2360 | ts->resp = SAS_TASK_COMPLETE; |
| 2361 | ts->stat = SAS_OPEN_TO; |
| 2362 | break; |
| 2363 | case IO_XFER_ERROR_OFFSET_MISMATCH: |
| 2364 | PM8001_IO_DBG(pm8001_ha, |
| 2365 | pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); |
| 2366 | ts->resp = SAS_TASK_COMPLETE; |
| 2367 | ts->stat = SAS_OPEN_TO; |
| 2368 | break; |
| 2369 | case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: |
| 2370 | PM8001_IO_DBG(pm8001_ha, |
| 2371 | pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); |
| 2372 | ts->resp = SAS_TASK_COMPLETE; |
| 2373 | ts->stat = SAS_OPEN_TO; |
| 2374 | break; |
| 2375 | case IO_XFER_CMD_FRAME_ISSUED: |
| 2376 | PM8001_IO_DBG(pm8001_ha, |
| 2377 | pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); |
| 2378 | break; |
| 2379 | case IO_XFER_PIO_SETUP_ERROR: |
| 2380 | PM8001_IO_DBG(pm8001_ha, |
| 2381 | pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); |
| 2382 | ts->resp = SAS_TASK_COMPLETE; |
| 2383 | ts->stat = SAS_OPEN_TO; |
| 2384 | break; |
| 2385 | default: |
| 2386 | PM8001_IO_DBG(pm8001_ha, |
| 2387 | pm8001_printk("Unknown status 0x%x\n", event)); |
| 2388 | /* not allowed case. Therefore, return failed status */ |
| 2389 | ts->resp = SAS_TASK_COMPLETE; |
| 2390 | ts->stat = SAS_OPEN_TO; |
| 2391 | break; |
| 2392 | } |
| 2393 | spin_lock_irqsave(&t->task_state_lock, flags); |
| 2394 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
| 2395 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; |
| 2396 | t->task_state_flags |= SAS_TASK_STATE_DONE; |
| 2397 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { |
| 2398 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 2399 | PM8001_FAIL_DBG(pm8001_ha, |
| 2400 | pm8001_printk("task 0x%p done with io_status 0x%x" |
| 2401 | " resp 0x%x stat 0x%x but aborted by upper layer!\n", |
| 2402 | t, event, ts->resp, ts->stat)); |
| 2403 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2404 | } else { |
| 2405 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 2406 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2407 | mb();/* in order to force CPU ordering */ |
| 2408 | t->task_done(t); |
| 2409 | } |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2410 | } |
| 2411 | |
| 2412 | /*See the comments for mpi_ssp_completion */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2413 | static void |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2414 | mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2415 | { |
| 2416 | u32 param; |
| 2417 | struct sas_task *t; |
| 2418 | struct pm8001_ccb_info *ccb; |
| 2419 | unsigned long flags; |
| 2420 | u32 status; |
| 2421 | u32 tag; |
| 2422 | struct smp_completion_resp *psmpPayload; |
| 2423 | struct task_status_struct *ts; |
| 2424 | struct pm8001_device *pm8001_dev; |
| 2425 | |
| 2426 | psmpPayload = (struct smp_completion_resp *)(piomb + 4); |
| 2427 | status = le32_to_cpu(psmpPayload->status); |
| 2428 | tag = le32_to_cpu(psmpPayload->tag); |
| 2429 | |
| 2430 | ccb = &pm8001_ha->ccb_info[tag]; |
| 2431 | param = le32_to_cpu(psmpPayload->param); |
| 2432 | t = ccb->task; |
| 2433 | ts = &t->task_status; |
| 2434 | pm8001_dev = ccb->device; |
| 2435 | if (status) |
| 2436 | PM8001_FAIL_DBG(pm8001_ha, |
| 2437 | pm8001_printk("smp IO status 0x%x\n", status)); |
| 2438 | if (unlikely(!t || !t->lldd_task || !t->dev)) |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2439 | return; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2440 | |
| 2441 | switch (status) { |
| 2442 | case IO_SUCCESS: |
| 2443 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); |
| 2444 | ts->resp = SAS_TASK_COMPLETE; |
| 2445 | ts->stat = SAM_GOOD; |
| 2446 | if (pm8001_dev) |
| 2447 | pm8001_dev->running_req--; |
| 2448 | break; |
| 2449 | case IO_ABORTED: |
| 2450 | PM8001_IO_DBG(pm8001_ha, |
| 2451 | pm8001_printk("IO_ABORTED IOMB\n")); |
| 2452 | ts->resp = SAS_TASK_COMPLETE; |
| 2453 | ts->stat = SAS_ABORTED_TASK; |
| 2454 | if (pm8001_dev) |
| 2455 | pm8001_dev->running_req--; |
| 2456 | break; |
| 2457 | case IO_OVERFLOW: |
| 2458 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); |
| 2459 | ts->resp = SAS_TASK_COMPLETE; |
| 2460 | ts->stat = SAS_DATA_OVERRUN; |
| 2461 | ts->residual = 0; |
| 2462 | if (pm8001_dev) |
| 2463 | pm8001_dev->running_req--; |
| 2464 | break; |
| 2465 | case IO_NO_DEVICE: |
| 2466 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); |
| 2467 | ts->resp = SAS_TASK_COMPLETE; |
| 2468 | ts->stat = SAS_PHY_DOWN; |
| 2469 | break; |
| 2470 | case IO_ERROR_HW_TIMEOUT: |
| 2471 | PM8001_IO_DBG(pm8001_ha, |
| 2472 | pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); |
| 2473 | ts->resp = SAS_TASK_COMPLETE; |
| 2474 | ts->stat = SAM_BUSY; |
| 2475 | break; |
| 2476 | case IO_XFER_ERROR_BREAK: |
| 2477 | PM8001_IO_DBG(pm8001_ha, |
| 2478 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); |
| 2479 | ts->resp = SAS_TASK_COMPLETE; |
| 2480 | ts->stat = SAM_BUSY; |
| 2481 | break; |
| 2482 | case IO_XFER_ERROR_PHY_NOT_READY: |
| 2483 | PM8001_IO_DBG(pm8001_ha, |
| 2484 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); |
| 2485 | ts->resp = SAS_TASK_COMPLETE; |
| 2486 | ts->stat = SAM_BUSY; |
| 2487 | break; |
| 2488 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: |
| 2489 | PM8001_IO_DBG(pm8001_ha, |
| 2490 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); |
| 2491 | ts->resp = SAS_TASK_COMPLETE; |
| 2492 | ts->stat = SAS_OPEN_REJECT; |
| 2493 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 2494 | break; |
| 2495 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: |
| 2496 | PM8001_IO_DBG(pm8001_ha, |
| 2497 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); |
| 2498 | ts->resp = SAS_TASK_COMPLETE; |
| 2499 | ts->stat = SAS_OPEN_REJECT; |
| 2500 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 2501 | break; |
| 2502 | case IO_OPEN_CNX_ERROR_BREAK: |
| 2503 | PM8001_IO_DBG(pm8001_ha, |
| 2504 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); |
| 2505 | ts->resp = SAS_TASK_COMPLETE; |
| 2506 | ts->stat = SAS_OPEN_REJECT; |
| 2507 | ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; |
| 2508 | break; |
| 2509 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: |
| 2510 | PM8001_IO_DBG(pm8001_ha, |
| 2511 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); |
| 2512 | ts->resp = SAS_TASK_COMPLETE; |
| 2513 | ts->stat = SAS_OPEN_REJECT; |
| 2514 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; |
| 2515 | pm8001_handle_event(pm8001_ha, |
| 2516 | pm8001_dev, |
| 2517 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); |
| 2518 | break; |
| 2519 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: |
| 2520 | PM8001_IO_DBG(pm8001_ha, |
| 2521 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); |
| 2522 | ts->resp = SAS_TASK_COMPLETE; |
| 2523 | ts->stat = SAS_OPEN_REJECT; |
| 2524 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; |
| 2525 | break; |
| 2526 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: |
| 2527 | PM8001_IO_DBG(pm8001_ha, |
| 2528 | pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" |
| 2529 | "NOT_SUPPORTED\n")); |
| 2530 | ts->resp = SAS_TASK_COMPLETE; |
| 2531 | ts->stat = SAS_OPEN_REJECT; |
| 2532 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; |
| 2533 | break; |
| 2534 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: |
| 2535 | PM8001_IO_DBG(pm8001_ha, |
| 2536 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); |
| 2537 | ts->resp = SAS_TASK_COMPLETE; |
| 2538 | ts->stat = SAS_OPEN_REJECT; |
| 2539 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; |
| 2540 | break; |
| 2541 | case IO_XFER_ERROR_RX_FRAME: |
| 2542 | PM8001_IO_DBG(pm8001_ha, |
| 2543 | pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); |
| 2544 | ts->resp = SAS_TASK_COMPLETE; |
| 2545 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2546 | break; |
| 2547 | case IO_XFER_OPEN_RETRY_TIMEOUT: |
| 2548 | PM8001_IO_DBG(pm8001_ha, |
| 2549 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); |
| 2550 | ts->resp = SAS_TASK_COMPLETE; |
| 2551 | ts->stat = SAS_OPEN_REJECT; |
| 2552 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2553 | break; |
| 2554 | case IO_ERROR_INTERNAL_SMP_RESOURCE: |
| 2555 | PM8001_IO_DBG(pm8001_ha, |
| 2556 | pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); |
| 2557 | ts->resp = SAS_TASK_COMPLETE; |
| 2558 | ts->stat = SAS_QUEUE_FULL; |
| 2559 | break; |
| 2560 | case IO_PORT_IN_RESET: |
| 2561 | PM8001_IO_DBG(pm8001_ha, |
| 2562 | pm8001_printk("IO_PORT_IN_RESET\n")); |
| 2563 | ts->resp = SAS_TASK_COMPLETE; |
| 2564 | ts->stat = SAS_OPEN_REJECT; |
| 2565 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2566 | break; |
| 2567 | case IO_DS_NON_OPERATIONAL: |
| 2568 | PM8001_IO_DBG(pm8001_ha, |
| 2569 | pm8001_printk("IO_DS_NON_OPERATIONAL\n")); |
| 2570 | ts->resp = SAS_TASK_COMPLETE; |
| 2571 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2572 | break; |
| 2573 | case IO_DS_IN_RECOVERY: |
| 2574 | PM8001_IO_DBG(pm8001_ha, |
| 2575 | pm8001_printk("IO_DS_IN_RECOVERY\n")); |
| 2576 | ts->resp = SAS_TASK_COMPLETE; |
| 2577 | ts->stat = SAS_OPEN_REJECT; |
| 2578 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2579 | break; |
| 2580 | case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: |
| 2581 | PM8001_IO_DBG(pm8001_ha, |
| 2582 | pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); |
| 2583 | ts->resp = SAS_TASK_COMPLETE; |
| 2584 | ts->stat = SAS_OPEN_REJECT; |
| 2585 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; |
| 2586 | break; |
| 2587 | default: |
| 2588 | PM8001_IO_DBG(pm8001_ha, |
| 2589 | pm8001_printk("Unknown status 0x%x\n", status)); |
| 2590 | ts->resp = SAS_TASK_COMPLETE; |
| 2591 | ts->stat = SAS_DEV_NO_RESPONSE; |
| 2592 | /* not allowed case. Therefore, return failed status */ |
| 2593 | break; |
| 2594 | } |
| 2595 | spin_lock_irqsave(&t->task_state_lock, flags); |
| 2596 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
| 2597 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; |
| 2598 | t->task_state_flags |= SAS_TASK_STATE_DONE; |
| 2599 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { |
| 2600 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 2601 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" |
| 2602 | " io_status 0x%x resp 0x%x " |
| 2603 | "stat 0x%x but aborted by upper layer!\n", |
| 2604 | t, status, ts->resp, ts->stat)); |
| 2605 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2606 | } else { |
| 2607 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 2608 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); |
| 2609 | mb();/* in order to force CPU ordering */ |
| 2610 | t->task_done(t); |
| 2611 | } |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2612 | } |
| 2613 | |
| 2614 | static void |
| 2615 | mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2616 | { |
| 2617 | struct set_dev_state_resp *pPayload = |
| 2618 | (struct set_dev_state_resp *)(piomb + 4); |
| 2619 | u32 tag = le32_to_cpu(pPayload->tag); |
| 2620 | struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; |
| 2621 | struct pm8001_device *pm8001_dev = ccb->device; |
| 2622 | u32 status = le32_to_cpu(pPayload->status); |
| 2623 | u32 device_id = le32_to_cpu(pPayload->device_id); |
| 2624 | u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS; |
| 2625 | u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS; |
| 2626 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " |
| 2627 | "from 0x%x to 0x%x status = 0x%x!\n", |
| 2628 | device_id, pds, nds, status)); |
| 2629 | complete(pm8001_dev->setds_completion); |
| 2630 | ccb->task = NULL; |
| 2631 | ccb->ccb_tag = 0xFFFFFFFF; |
| 2632 | pm8001_ccb_free(pm8001_ha, tag); |
| 2633 | } |
| 2634 | |
| 2635 | static void |
| 2636 | mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2637 | { |
| 2638 | struct get_nvm_data_resp *pPayload = |
| 2639 | (struct get_nvm_data_resp *)(piomb + 4); |
| 2640 | u32 tag = le32_to_cpu(pPayload->tag); |
| 2641 | struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; |
| 2642 | u32 dlen_status = le32_to_cpu(pPayload->dlen_status); |
| 2643 | complete(pm8001_ha->nvmd_completion); |
| 2644 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); |
| 2645 | if ((dlen_status & NVMD_STAT) != 0) { |
| 2646 | PM8001_FAIL_DBG(pm8001_ha, |
| 2647 | pm8001_printk("Set nvm data error!\n")); |
| 2648 | return; |
| 2649 | } |
| 2650 | ccb->task = NULL; |
| 2651 | ccb->ccb_tag = 0xFFFFFFFF; |
| 2652 | pm8001_ccb_free(pm8001_ha, tag); |
| 2653 | } |
| 2654 | |
| 2655 | static void |
| 2656 | mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2657 | { |
| 2658 | struct fw_control_ex *fw_control_context; |
| 2659 | struct get_nvm_data_resp *pPayload = |
| 2660 | (struct get_nvm_data_resp *)(piomb + 4); |
| 2661 | u32 tag = le32_to_cpu(pPayload->tag); |
| 2662 | struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; |
| 2663 | u32 dlen_status = le32_to_cpu(pPayload->dlen_status); |
| 2664 | u32 ir_tds_bn_dps_das_nvm = |
| 2665 | le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); |
| 2666 | void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; |
| 2667 | fw_control_context = ccb->fw_control_context; |
| 2668 | |
| 2669 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); |
| 2670 | if ((dlen_status & NVMD_STAT) != 0) { |
| 2671 | PM8001_FAIL_DBG(pm8001_ha, |
| 2672 | pm8001_printk("Get nvm data error!\n")); |
| 2673 | complete(pm8001_ha->nvmd_completion); |
| 2674 | return; |
| 2675 | } |
| 2676 | |
| 2677 | if (ir_tds_bn_dps_das_nvm & IPMode) { |
| 2678 | /* indirect mode - IR bit set */ |
| 2679 | PM8001_MSG_DBG(pm8001_ha, |
| 2680 | pm8001_printk("Get NVMD success, IR=1\n")); |
| 2681 | if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { |
| 2682 | if (ir_tds_bn_dps_das_nvm == 0x80a80200) { |
| 2683 | memcpy(pm8001_ha->sas_addr, |
| 2684 | ((u8 *)virt_addr + 4), |
| 2685 | SAS_ADDR_SIZE); |
| 2686 | PM8001_MSG_DBG(pm8001_ha, |
| 2687 | pm8001_printk("Get SAS address" |
| 2688 | " from VPD successfully!\n")); |
| 2689 | } |
| 2690 | } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) |
| 2691 | || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || |
| 2692 | ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { |
| 2693 | ; |
| 2694 | } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) |
| 2695 | || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { |
| 2696 | ; |
| 2697 | } else { |
| 2698 | /* Should not be happened*/ |
| 2699 | PM8001_MSG_DBG(pm8001_ha, |
| 2700 | pm8001_printk("(IR=1)Wrong Device type 0x%x\n", |
| 2701 | ir_tds_bn_dps_das_nvm)); |
| 2702 | } |
| 2703 | } else /* direct mode */{ |
| 2704 | PM8001_MSG_DBG(pm8001_ha, |
| 2705 | pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", |
| 2706 | (dlen_status & NVMD_LEN) >> 24)); |
| 2707 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 2708 | memcpy(fw_control_context->usrAddr, |
| 2709 | pm8001_ha->memoryMap.region[NVMD].virt_ptr, |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 2710 | fw_control_context->len); |
| 2711 | complete(pm8001_ha->nvmd_completion); |
| 2712 | ccb->task = NULL; |
| 2713 | ccb->ccb_tag = 0xFFFFFFFF; |
| 2714 | pm8001_ccb_free(pm8001_ha, tag); |
| 2715 | } |
| 2716 | |
| 2717 | static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2718 | { |
| 2719 | struct local_phy_ctl_resp *pPayload = |
| 2720 | (struct local_phy_ctl_resp *)(piomb + 4); |
| 2721 | u32 status = le32_to_cpu(pPayload->status); |
| 2722 | u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; |
| 2723 | u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; |
| 2724 | if (status != 0) { |
| 2725 | PM8001_MSG_DBG(pm8001_ha, |
| 2726 | pm8001_printk("%x phy execute %x phy op failed! \n", |
| 2727 | phy_id, phy_op)); |
| 2728 | } else |
| 2729 | PM8001_MSG_DBG(pm8001_ha, |
| 2730 | pm8001_printk("%x phy execute %x phy op success! \n", |
| 2731 | phy_id, phy_op)); |
| 2732 | return 0; |
| 2733 | } |
| 2734 | |
| 2735 | /** |
| 2736 | * pm8001_bytes_dmaed - one of the interface function communication with libsas |
| 2737 | * @pm8001_ha: our hba card information |
| 2738 | * @i: which phy that received the event. |
| 2739 | * |
| 2740 | * when HBA driver received the identify done event or initiate FIS received |
| 2741 | * event(for SATA), it will invoke this function to notify the sas layer that |
| 2742 | * the sas toplogy has formed, please discover the the whole sas domain, |
| 2743 | * while receive a broadcast(change) primitive just tell the sas |
| 2744 | * layer to discover the changed domain rather than the whole domain. |
| 2745 | */ |
| 2746 | static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) |
| 2747 | { |
| 2748 | struct pm8001_phy *phy = &pm8001_ha->phy[i]; |
| 2749 | struct asd_sas_phy *sas_phy = &phy->sas_phy; |
| 2750 | struct sas_ha_struct *sas_ha; |
| 2751 | if (!phy->phy_attached) |
| 2752 | return; |
| 2753 | |
| 2754 | sas_ha = pm8001_ha->sas; |
| 2755 | if (sas_phy->phy) { |
| 2756 | struct sas_phy *sphy = sas_phy->phy; |
| 2757 | sphy->negotiated_linkrate = sas_phy->linkrate; |
| 2758 | sphy->minimum_linkrate = phy->minimum_linkrate; |
| 2759 | sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; |
| 2760 | sphy->maximum_linkrate = phy->maximum_linkrate; |
| 2761 | sphy->maximum_linkrate_hw = phy->maximum_linkrate; |
| 2762 | } |
| 2763 | |
| 2764 | if (phy->phy_type & PORT_TYPE_SAS) { |
| 2765 | struct sas_identify_frame *id; |
| 2766 | id = (struct sas_identify_frame *)phy->frame_rcvd; |
| 2767 | id->dev_type = phy->identify.device_type; |
| 2768 | id->initiator_bits = SAS_PROTOCOL_ALL; |
| 2769 | id->target_bits = phy->identify.target_port_protocols; |
| 2770 | } else if (phy->phy_type & PORT_TYPE_SATA) { |
| 2771 | /*Nothing*/ |
| 2772 | } |
| 2773 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); |
| 2774 | |
| 2775 | sas_phy->frame_rcvd_size = phy->frame_rcvd_size; |
| 2776 | pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); |
| 2777 | } |
| 2778 | |
| 2779 | /* Get the link rate speed */ |
| 2780 | static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) |
| 2781 | { |
| 2782 | struct sas_phy *sas_phy = phy->sas_phy.phy; |
| 2783 | |
| 2784 | switch (link_rate) { |
| 2785 | case PHY_SPEED_60: |
| 2786 | phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; |
| 2787 | phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; |
| 2788 | break; |
| 2789 | case PHY_SPEED_30: |
| 2790 | phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; |
| 2791 | phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; |
| 2792 | break; |
| 2793 | case PHY_SPEED_15: |
| 2794 | phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; |
| 2795 | phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; |
| 2796 | break; |
| 2797 | } |
| 2798 | sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; |
| 2799 | sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; |
| 2800 | sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; |
| 2801 | sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; |
| 2802 | sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; |
| 2803 | } |
| 2804 | |
| 2805 | /** |
| 2806 | * asd_get_attached_sas_addr -- extract/generate attached SAS address |
| 2807 | * @phy: pointer to asd_phy |
| 2808 | * @sas_addr: pointer to buffer where the SAS address is to be written |
| 2809 | * |
| 2810 | * This function extracts the SAS address from an IDENTIFY frame |
| 2811 | * received. If OOB is SATA, then a SAS address is generated from the |
| 2812 | * HA tables. |
| 2813 | * |
| 2814 | * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame |
| 2815 | * buffer. |
| 2816 | */ |
| 2817 | static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, |
| 2818 | u8 *sas_addr) |
| 2819 | { |
| 2820 | if (phy->sas_phy.frame_rcvd[0] == 0x34 |
| 2821 | && phy->sas_phy.oob_mode == SATA_OOB_MODE) { |
| 2822 | struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; |
| 2823 | /* FIS device-to-host */ |
| 2824 | u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); |
| 2825 | addr += phy->sas_phy.id; |
| 2826 | *(__be64 *)sas_addr = cpu_to_be64(addr); |
| 2827 | } else { |
| 2828 | struct sas_identify_frame *idframe = |
| 2829 | (void *) phy->sas_phy.frame_rcvd; |
| 2830 | memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); |
| 2831 | } |
| 2832 | } |
| 2833 | |
| 2834 | /** |
| 2835 | * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. |
| 2836 | * @pm8001_ha: our hba card information |
| 2837 | * @Qnum: the outbound queue message number. |
| 2838 | * @SEA: source of event to ack |
| 2839 | * @port_id: port id. |
| 2840 | * @phyId: phy id. |
| 2841 | * @param0: parameter 0. |
| 2842 | * @param1: parameter 1. |
| 2843 | */ |
| 2844 | static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, |
| 2845 | u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) |
| 2846 | { |
| 2847 | struct hw_event_ack_req payload; |
| 2848 | u32 opc = OPC_INB_SAS_HW_EVENT_ACK; |
| 2849 | |
| 2850 | struct inbound_queue_table *circularQ; |
| 2851 | |
| 2852 | memset((u8 *)&payload, 0, sizeof(payload)); |
| 2853 | circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; |
| 2854 | payload.tag = 1; |
| 2855 | payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | |
| 2856 | ((phyId & 0x0F) << 4) | (port_id & 0x0F)); |
| 2857 | payload.param0 = cpu_to_le32(param0); |
| 2858 | payload.param1 = cpu_to_le32(param1); |
| 2859 | mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 2860 | } |
| 2861 | |
| 2862 | static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, |
| 2863 | u32 phyId, u32 phy_op); |
| 2864 | |
| 2865 | /** |
| 2866 | * hw_event_sas_phy_up -FW tells me a SAS phy up event. |
| 2867 | * @pm8001_ha: our hba card information |
| 2868 | * @piomb: IO message buffer |
| 2869 | */ |
| 2870 | static void |
| 2871 | hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2872 | { |
| 2873 | struct hw_event_resp *pPayload = |
| 2874 | (struct hw_event_resp *)(piomb + 4); |
| 2875 | u32 lr_evt_status_phyid_portid = |
| 2876 | le32_to_cpu(pPayload->lr_evt_status_phyid_portid); |
| 2877 | u8 link_rate = |
| 2878 | (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); |
| 2879 | u8 phy_id = |
| 2880 | (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); |
| 2881 | struct sas_ha_struct *sas_ha = pm8001_ha->sas; |
| 2882 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; |
| 2883 | unsigned long flags; |
| 2884 | u8 deviceType = pPayload->sas_identify.dev_type; |
| 2885 | |
| 2886 | PM8001_MSG_DBG(pm8001_ha, |
| 2887 | pm8001_printk("HW_EVENT_SAS_PHY_UP \n")); |
| 2888 | |
| 2889 | switch (deviceType) { |
| 2890 | case SAS_PHY_UNUSED: |
| 2891 | PM8001_MSG_DBG(pm8001_ha, |
| 2892 | pm8001_printk("device type no device.\n")); |
| 2893 | break; |
| 2894 | case SAS_END_DEVICE: |
| 2895 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); |
| 2896 | pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, |
| 2897 | PHY_NOTIFY_ENABLE_SPINUP); |
| 2898 | get_lrate_mode(phy, link_rate); |
| 2899 | break; |
| 2900 | case SAS_EDGE_EXPANDER_DEVICE: |
| 2901 | PM8001_MSG_DBG(pm8001_ha, |
| 2902 | pm8001_printk("expander device.\n")); |
| 2903 | get_lrate_mode(phy, link_rate); |
| 2904 | break; |
| 2905 | case SAS_FANOUT_EXPANDER_DEVICE: |
| 2906 | PM8001_MSG_DBG(pm8001_ha, |
| 2907 | pm8001_printk("fanout expander device.\n")); |
| 2908 | get_lrate_mode(phy, link_rate); |
| 2909 | break; |
| 2910 | default: |
| 2911 | PM8001_MSG_DBG(pm8001_ha, |
| 2912 | pm8001_printk("unkown device type(%x)\n", deviceType)); |
| 2913 | break; |
| 2914 | } |
| 2915 | phy->phy_type |= PORT_TYPE_SAS; |
| 2916 | phy->identify.device_type = deviceType; |
| 2917 | phy->phy_attached = 1; |
| 2918 | if (phy->identify.device_type == SAS_END_DEV) |
| 2919 | phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; |
| 2920 | else if (phy->identify.device_type != NO_DEVICE) |
| 2921 | phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; |
| 2922 | phy->sas_phy.oob_mode = SAS_OOB_MODE; |
| 2923 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); |
| 2924 | spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); |
| 2925 | memcpy(phy->frame_rcvd, &pPayload->sas_identify, |
| 2926 | sizeof(struct sas_identify_frame)-4); |
| 2927 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; |
| 2928 | pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); |
| 2929 | spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); |
| 2930 | if (pm8001_ha->flags == PM8001F_RUN_TIME) |
| 2931 | mdelay(200);/*delay a moment to wait disk to spinup*/ |
| 2932 | pm8001_bytes_dmaed(pm8001_ha, phy_id); |
| 2933 | } |
| 2934 | |
| 2935 | /** |
| 2936 | * hw_event_sata_phy_up -FW tells me a SATA phy up event. |
| 2937 | * @pm8001_ha: our hba card information |
| 2938 | * @piomb: IO message buffer |
| 2939 | */ |
| 2940 | static void |
| 2941 | hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2942 | { |
| 2943 | struct hw_event_resp *pPayload = |
| 2944 | (struct hw_event_resp *)(piomb + 4); |
| 2945 | u32 lr_evt_status_phyid_portid = |
| 2946 | le32_to_cpu(pPayload->lr_evt_status_phyid_portid); |
| 2947 | u8 link_rate = |
| 2948 | (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); |
| 2949 | u8 phy_id = |
| 2950 | (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); |
| 2951 | struct sas_ha_struct *sas_ha = pm8001_ha->sas; |
| 2952 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; |
| 2953 | unsigned long flags; |
| 2954 | get_lrate_mode(phy, link_rate); |
| 2955 | phy->phy_type |= PORT_TYPE_SATA; |
| 2956 | phy->phy_attached = 1; |
| 2957 | phy->sas_phy.oob_mode = SATA_OOB_MODE; |
| 2958 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); |
| 2959 | spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); |
| 2960 | memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), |
| 2961 | sizeof(struct dev_to_host_fis)); |
| 2962 | phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); |
| 2963 | phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; |
| 2964 | phy->identify.device_type = SATA_DEV; |
| 2965 | pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); |
| 2966 | spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); |
| 2967 | pm8001_bytes_dmaed(pm8001_ha, phy_id); |
| 2968 | } |
| 2969 | |
| 2970 | /** |
| 2971 | * hw_event_phy_down -we should notify the libsas the phy is down. |
| 2972 | * @pm8001_ha: our hba card information |
| 2973 | * @piomb: IO message buffer |
| 2974 | */ |
| 2975 | static void |
| 2976 | hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 2977 | { |
| 2978 | struct hw_event_resp *pPayload = |
| 2979 | (struct hw_event_resp *)(piomb + 4); |
| 2980 | u32 lr_evt_status_phyid_portid = |
| 2981 | le32_to_cpu(pPayload->lr_evt_status_phyid_portid); |
| 2982 | u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); |
| 2983 | u8 phy_id = |
| 2984 | (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); |
| 2985 | u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); |
| 2986 | u8 portstate = (u8)(npip_portstate & 0x0000000F); |
| 2987 | |
| 2988 | switch (portstate) { |
| 2989 | case PORT_VALID: |
| 2990 | break; |
| 2991 | case PORT_INVALID: |
| 2992 | PM8001_MSG_DBG(pm8001_ha, |
| 2993 | pm8001_printk(" PortInvalid portID %d \n", port_id)); |
| 2994 | PM8001_MSG_DBG(pm8001_ha, |
| 2995 | pm8001_printk(" Last phy Down and port invalid\n")); |
| 2996 | pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, |
| 2997 | port_id, phy_id, 0, 0); |
| 2998 | break; |
| 2999 | case PORT_IN_RESET: |
| 3000 | PM8001_MSG_DBG(pm8001_ha, |
| 3001 | pm8001_printk(" PortInReset portID %d \n", port_id)); |
| 3002 | break; |
| 3003 | case PORT_NOT_ESTABLISHED: |
| 3004 | PM8001_MSG_DBG(pm8001_ha, |
| 3005 | pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); |
| 3006 | break; |
| 3007 | case PORT_LOSTCOMM: |
| 3008 | PM8001_MSG_DBG(pm8001_ha, |
| 3009 | pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); |
| 3010 | PM8001_MSG_DBG(pm8001_ha, |
| 3011 | pm8001_printk(" Last phy Down and port invalid\n")); |
| 3012 | pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, |
| 3013 | port_id, phy_id, 0, 0); |
| 3014 | break; |
| 3015 | default: |
| 3016 | PM8001_MSG_DBG(pm8001_ha, |
| 3017 | pm8001_printk(" phy Down and(default) = %x\n", |
| 3018 | portstate)); |
| 3019 | break; |
| 3020 | |
| 3021 | } |
| 3022 | } |
| 3023 | |
| 3024 | /** |
| 3025 | * mpi_reg_resp -process register device ID response. |
| 3026 | * @pm8001_ha: our hba card information |
| 3027 | * @piomb: IO message buffer |
| 3028 | * |
| 3029 | * when sas layer find a device it will notify LLDD, then the driver register |
| 3030 | * the domain device to FW, this event is the return device ID which the FW |
| 3031 | * has assigned, from now,inter-communication with FW is no longer using the |
| 3032 | * SAS address, use device ID which FW assigned. |
| 3033 | */ |
| 3034 | static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 3035 | { |
| 3036 | u32 status; |
| 3037 | u32 device_id; |
| 3038 | u32 htag; |
| 3039 | struct pm8001_ccb_info *ccb; |
| 3040 | struct pm8001_device *pm8001_dev; |
| 3041 | struct dev_reg_resp *registerRespPayload = |
| 3042 | (struct dev_reg_resp *)(piomb + 4); |
| 3043 | |
| 3044 | htag = le32_to_cpu(registerRespPayload->tag); |
| 3045 | ccb = &pm8001_ha->ccb_info[registerRespPayload->tag]; |
| 3046 | pm8001_dev = ccb->device; |
| 3047 | status = le32_to_cpu(registerRespPayload->status); |
| 3048 | device_id = le32_to_cpu(registerRespPayload->device_id); |
| 3049 | PM8001_MSG_DBG(pm8001_ha, |
| 3050 | pm8001_printk(" register device is status = %d\n", status)); |
| 3051 | switch (status) { |
| 3052 | case DEVREG_SUCCESS: |
| 3053 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); |
| 3054 | pm8001_dev->device_id = device_id; |
| 3055 | break; |
| 3056 | case DEVREG_FAILURE_OUT_OF_RESOURCE: |
| 3057 | PM8001_MSG_DBG(pm8001_ha, |
| 3058 | pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); |
| 3059 | break; |
| 3060 | case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: |
| 3061 | PM8001_MSG_DBG(pm8001_ha, |
| 3062 | pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); |
| 3063 | break; |
| 3064 | case DEVREG_FAILURE_INVALID_PHY_ID: |
| 3065 | PM8001_MSG_DBG(pm8001_ha, |
| 3066 | pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); |
| 3067 | break; |
| 3068 | case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: |
| 3069 | PM8001_MSG_DBG(pm8001_ha, |
| 3070 | pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); |
| 3071 | break; |
| 3072 | case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: |
| 3073 | PM8001_MSG_DBG(pm8001_ha, |
| 3074 | pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); |
| 3075 | break; |
| 3076 | case DEVREG_FAILURE_PORT_NOT_VALID_STATE: |
| 3077 | PM8001_MSG_DBG(pm8001_ha, |
| 3078 | pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); |
| 3079 | break; |
| 3080 | case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: |
| 3081 | PM8001_MSG_DBG(pm8001_ha, |
| 3082 | pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); |
| 3083 | break; |
| 3084 | default: |
| 3085 | PM8001_MSG_DBG(pm8001_ha, |
| 3086 | pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n")); |
| 3087 | break; |
| 3088 | } |
| 3089 | complete(pm8001_dev->dcompletion); |
| 3090 | ccb->task = NULL; |
| 3091 | ccb->ccb_tag = 0xFFFFFFFF; |
| 3092 | pm8001_ccb_free(pm8001_ha, htag); |
| 3093 | return 0; |
| 3094 | } |
| 3095 | |
| 3096 | static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 3097 | { |
| 3098 | u32 status; |
| 3099 | u32 device_id; |
| 3100 | struct dev_reg_resp *registerRespPayload = |
| 3101 | (struct dev_reg_resp *)(piomb + 4); |
| 3102 | |
| 3103 | status = le32_to_cpu(registerRespPayload->status); |
| 3104 | device_id = le32_to_cpu(registerRespPayload->device_id); |
| 3105 | if (status != 0) |
| 3106 | PM8001_MSG_DBG(pm8001_ha, |
| 3107 | pm8001_printk(" deregister device failed ,status = %x" |
| 3108 | ", device_id = %x\n", status, device_id)); |
| 3109 | return 0; |
| 3110 | } |
| 3111 | |
| 3112 | static int |
| 3113 | mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 3114 | { |
| 3115 | u32 status; |
| 3116 | struct fw_control_ex fw_control_context; |
| 3117 | struct fw_flash_Update_resp *ppayload = |
| 3118 | (struct fw_flash_Update_resp *)(piomb + 4); |
| 3119 | u32 tag = le32_to_cpu(ppayload->tag); |
| 3120 | struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; |
| 3121 | status = le32_to_cpu(ppayload->status); |
| 3122 | memcpy(&fw_control_context, |
| 3123 | ccb->fw_control_context, |
| 3124 | sizeof(fw_control_context)); |
| 3125 | switch (status) { |
| 3126 | case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: |
| 3127 | PM8001_MSG_DBG(pm8001_ha, |
| 3128 | pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); |
| 3129 | break; |
| 3130 | case FLASH_UPDATE_IN_PROGRESS: |
| 3131 | PM8001_MSG_DBG(pm8001_ha, |
| 3132 | pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); |
| 3133 | break; |
| 3134 | case FLASH_UPDATE_HDR_ERR: |
| 3135 | PM8001_MSG_DBG(pm8001_ha, |
| 3136 | pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); |
| 3137 | break; |
| 3138 | case FLASH_UPDATE_OFFSET_ERR: |
| 3139 | PM8001_MSG_DBG(pm8001_ha, |
| 3140 | pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); |
| 3141 | break; |
| 3142 | case FLASH_UPDATE_CRC_ERR: |
| 3143 | PM8001_MSG_DBG(pm8001_ha, |
| 3144 | pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); |
| 3145 | break; |
| 3146 | case FLASH_UPDATE_LENGTH_ERR: |
| 3147 | PM8001_MSG_DBG(pm8001_ha, |
| 3148 | pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); |
| 3149 | break; |
| 3150 | case FLASH_UPDATE_HW_ERR: |
| 3151 | PM8001_MSG_DBG(pm8001_ha, |
| 3152 | pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); |
| 3153 | break; |
| 3154 | case FLASH_UPDATE_DNLD_NOT_SUPPORTED: |
| 3155 | PM8001_MSG_DBG(pm8001_ha, |
| 3156 | pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); |
| 3157 | break; |
| 3158 | case FLASH_UPDATE_DISABLED: |
| 3159 | PM8001_MSG_DBG(pm8001_ha, |
| 3160 | pm8001_printk(": FLASH_UPDATE_DISABLED\n")); |
| 3161 | break; |
| 3162 | default: |
| 3163 | PM8001_MSG_DBG(pm8001_ha, |
| 3164 | pm8001_printk("No matched status = %d\n", status)); |
| 3165 | break; |
| 3166 | } |
| 3167 | ccb->fw_control_context->fw_control->retcode = status; |
| 3168 | pci_free_consistent(pm8001_ha->pdev, |
| 3169 | fw_control_context.len, |
| 3170 | fw_control_context.virtAddr, |
| 3171 | fw_control_context.phys_addr); |
| 3172 | complete(pm8001_ha->nvmd_completion); |
| 3173 | ccb->task = NULL; |
| 3174 | ccb->ccb_tag = 0xFFFFFFFF; |
| 3175 | pm8001_ccb_free(pm8001_ha, tag); |
| 3176 | return 0; |
| 3177 | } |
| 3178 | |
| 3179 | static int |
| 3180 | mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) |
| 3181 | { |
| 3182 | u32 status; |
| 3183 | int i; |
| 3184 | struct general_event_resp *pPayload = |
| 3185 | (struct general_event_resp *)(piomb + 4); |
| 3186 | status = le32_to_cpu(pPayload->status); |
| 3187 | PM8001_MSG_DBG(pm8001_ha, |
| 3188 | pm8001_printk(" status = 0x%x\n", status)); |
| 3189 | for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) |
| 3190 | PM8001_MSG_DBG(pm8001_ha, |
| 3191 | pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i, |
| 3192 | pPayload->inb_IOMB_payload[i])); |
| 3193 | return 0; |
| 3194 | } |
| 3195 | |
| 3196 | static int |
| 3197 | mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 3198 | { |
| 3199 | struct sas_task *t; |
| 3200 | struct pm8001_ccb_info *ccb; |
| 3201 | unsigned long flags; |
| 3202 | u32 status ; |
| 3203 | u32 tag, scp; |
| 3204 | struct task_status_struct *ts; |
| 3205 | |
| 3206 | struct task_abort_resp *pPayload = |
| 3207 | (struct task_abort_resp *)(piomb + 4); |
| 3208 | ccb = &pm8001_ha->ccb_info[pPayload->tag]; |
| 3209 | t = ccb->task; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3210 | |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3211 | |
| 3212 | status = le32_to_cpu(pPayload->status); |
| 3213 | tag = le32_to_cpu(pPayload->tag); |
| 3214 | scp = le32_to_cpu(pPayload->scp); |
| 3215 | PM8001_IO_DBG(pm8001_ha, |
| 3216 | pm8001_printk(" status = 0x%x\n", status)); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3217 | if (t == NULL) |
| 3218 | return -1; |
| 3219 | ts = &t->task_status; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3220 | if (status != 0) |
| 3221 | PM8001_FAIL_DBG(pm8001_ha, |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3222 | pm8001_printk("task abort failed status 0x%x ," |
| 3223 | "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3224 | switch (status) { |
| 3225 | case IO_SUCCESS: |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3226 | PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3227 | ts->resp = SAS_TASK_COMPLETE; |
| 3228 | ts->stat = SAM_GOOD; |
| 3229 | break; |
| 3230 | case IO_NOT_VALID: |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3231 | PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3232 | ts->resp = TMF_RESP_FUNC_FAILED; |
| 3233 | break; |
| 3234 | } |
| 3235 | spin_lock_irqsave(&t->task_state_lock, flags); |
| 3236 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; |
| 3237 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; |
| 3238 | t->task_state_flags |= SAS_TASK_STATE_DONE; |
| 3239 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
| 3240 | pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag); |
| 3241 | mb(); |
| 3242 | t->task_done(t); |
| 3243 | return 0; |
| 3244 | } |
| 3245 | |
| 3246 | /** |
| 3247 | * mpi_hw_event -The hw event has come. |
| 3248 | * @pm8001_ha: our hba card information |
| 3249 | * @piomb: IO message buffer |
| 3250 | */ |
| 3251 | static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) |
| 3252 | { |
| 3253 | unsigned long flags; |
| 3254 | struct hw_event_resp *pPayload = |
| 3255 | (struct hw_event_resp *)(piomb + 4); |
| 3256 | u32 lr_evt_status_phyid_portid = |
| 3257 | le32_to_cpu(pPayload->lr_evt_status_phyid_portid); |
| 3258 | u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); |
| 3259 | u8 phy_id = |
| 3260 | (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); |
| 3261 | u16 eventType = |
| 3262 | (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); |
| 3263 | u8 status = |
| 3264 | (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); |
| 3265 | struct sas_ha_struct *sas_ha = pm8001_ha->sas; |
| 3266 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; |
| 3267 | struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; |
| 3268 | PM8001_MSG_DBG(pm8001_ha, |
| 3269 | pm8001_printk("outbound queue HW event & event type : ")); |
| 3270 | switch (eventType) { |
| 3271 | case HW_EVENT_PHY_START_STATUS: |
| 3272 | PM8001_MSG_DBG(pm8001_ha, |
| 3273 | pm8001_printk("HW_EVENT_PHY_START_STATUS" |
| 3274 | " status = %x\n", status)); |
| 3275 | if (status == 0) { |
| 3276 | phy->phy_state = 1; |
| 3277 | if (pm8001_ha->flags == PM8001F_RUN_TIME) |
| 3278 | complete(phy->enable_completion); |
| 3279 | } |
| 3280 | break; |
| 3281 | case HW_EVENT_SAS_PHY_UP: |
| 3282 | PM8001_MSG_DBG(pm8001_ha, |
| 3283 | pm8001_printk("HW_EVENT_PHY_START_STATUS \n")); |
| 3284 | hw_event_sas_phy_up(pm8001_ha, piomb); |
| 3285 | break; |
| 3286 | case HW_EVENT_SATA_PHY_UP: |
| 3287 | PM8001_MSG_DBG(pm8001_ha, |
| 3288 | pm8001_printk("HW_EVENT_SATA_PHY_UP \n")); |
| 3289 | hw_event_sata_phy_up(pm8001_ha, piomb); |
| 3290 | break; |
| 3291 | case HW_EVENT_PHY_STOP_STATUS: |
| 3292 | PM8001_MSG_DBG(pm8001_ha, |
| 3293 | pm8001_printk("HW_EVENT_PHY_STOP_STATUS " |
| 3294 | "status = %x\n", status)); |
| 3295 | if (status == 0) |
| 3296 | phy->phy_state = 0; |
| 3297 | break; |
| 3298 | case HW_EVENT_SATA_SPINUP_HOLD: |
| 3299 | PM8001_MSG_DBG(pm8001_ha, |
| 3300 | pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n")); |
| 3301 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); |
| 3302 | break; |
| 3303 | case HW_EVENT_PHY_DOWN: |
| 3304 | PM8001_MSG_DBG(pm8001_ha, |
| 3305 | pm8001_printk("HW_EVENT_PHY_DOWN \n")); |
| 3306 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); |
| 3307 | phy->phy_attached = 0; |
| 3308 | phy->phy_state = 0; |
| 3309 | hw_event_phy_down(pm8001_ha, piomb); |
| 3310 | break; |
| 3311 | case HW_EVENT_PORT_INVALID: |
| 3312 | PM8001_MSG_DBG(pm8001_ha, |
| 3313 | pm8001_printk("HW_EVENT_PORT_INVALID\n")); |
| 3314 | sas_phy_disconnected(sas_phy); |
| 3315 | phy->phy_attached = 0; |
| 3316 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3317 | break; |
| 3318 | /* the broadcast change primitive received, tell the LIBSAS this event |
| 3319 | to revalidate the sas domain*/ |
| 3320 | case HW_EVENT_BROADCAST_CHANGE: |
| 3321 | PM8001_MSG_DBG(pm8001_ha, |
| 3322 | pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); |
| 3323 | pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, |
| 3324 | port_id, phy_id, 1, 0); |
| 3325 | spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); |
| 3326 | sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; |
| 3327 | spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); |
| 3328 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
| 3329 | break; |
| 3330 | case HW_EVENT_PHY_ERROR: |
| 3331 | PM8001_MSG_DBG(pm8001_ha, |
| 3332 | pm8001_printk("HW_EVENT_PHY_ERROR\n")); |
| 3333 | sas_phy_disconnected(&phy->sas_phy); |
| 3334 | phy->phy_attached = 0; |
| 3335 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); |
| 3336 | break; |
| 3337 | case HW_EVENT_BROADCAST_EXP: |
| 3338 | PM8001_MSG_DBG(pm8001_ha, |
| 3339 | pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); |
| 3340 | spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); |
| 3341 | sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; |
| 3342 | spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); |
| 3343 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
| 3344 | break; |
| 3345 | case HW_EVENT_LINK_ERR_INVALID_DWORD: |
| 3346 | PM8001_MSG_DBG(pm8001_ha, |
| 3347 | pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); |
| 3348 | pm8001_hw_event_ack_req(pm8001_ha, 0, |
| 3349 | HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); |
| 3350 | sas_phy_disconnected(sas_phy); |
| 3351 | phy->phy_attached = 0; |
| 3352 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3353 | break; |
| 3354 | case HW_EVENT_LINK_ERR_DISPARITY_ERROR: |
| 3355 | PM8001_MSG_DBG(pm8001_ha, |
| 3356 | pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); |
| 3357 | pm8001_hw_event_ack_req(pm8001_ha, 0, |
| 3358 | HW_EVENT_LINK_ERR_DISPARITY_ERROR, |
| 3359 | port_id, phy_id, 0, 0); |
| 3360 | sas_phy_disconnected(sas_phy); |
| 3361 | phy->phy_attached = 0; |
| 3362 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3363 | break; |
| 3364 | case HW_EVENT_LINK_ERR_CODE_VIOLATION: |
| 3365 | PM8001_MSG_DBG(pm8001_ha, |
| 3366 | pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); |
| 3367 | pm8001_hw_event_ack_req(pm8001_ha, 0, |
| 3368 | HW_EVENT_LINK_ERR_CODE_VIOLATION, |
| 3369 | port_id, phy_id, 0, 0); |
| 3370 | sas_phy_disconnected(sas_phy); |
| 3371 | phy->phy_attached = 0; |
| 3372 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3373 | break; |
| 3374 | case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: |
| 3375 | PM8001_MSG_DBG(pm8001_ha, |
| 3376 | pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); |
| 3377 | pm8001_hw_event_ack_req(pm8001_ha, 0, |
| 3378 | HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, |
| 3379 | port_id, phy_id, 0, 0); |
| 3380 | sas_phy_disconnected(sas_phy); |
| 3381 | phy->phy_attached = 0; |
| 3382 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3383 | break; |
| 3384 | case HW_EVENT_MALFUNCTION: |
| 3385 | PM8001_MSG_DBG(pm8001_ha, |
| 3386 | pm8001_printk("HW_EVENT_MALFUNCTION\n")); |
| 3387 | break; |
| 3388 | case HW_EVENT_BROADCAST_SES: |
| 3389 | PM8001_MSG_DBG(pm8001_ha, |
| 3390 | pm8001_printk("HW_EVENT_BROADCAST_SES\n")); |
| 3391 | spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); |
| 3392 | sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; |
| 3393 | spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); |
| 3394 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
| 3395 | break; |
| 3396 | case HW_EVENT_INBOUND_CRC_ERROR: |
| 3397 | PM8001_MSG_DBG(pm8001_ha, |
| 3398 | pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); |
| 3399 | pm8001_hw_event_ack_req(pm8001_ha, 0, |
| 3400 | HW_EVENT_INBOUND_CRC_ERROR, |
| 3401 | port_id, phy_id, 0, 0); |
| 3402 | break; |
| 3403 | case HW_EVENT_HARD_RESET_RECEIVED: |
| 3404 | PM8001_MSG_DBG(pm8001_ha, |
| 3405 | pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); |
| 3406 | sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); |
| 3407 | break; |
| 3408 | case HW_EVENT_ID_FRAME_TIMEOUT: |
| 3409 | PM8001_MSG_DBG(pm8001_ha, |
| 3410 | pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); |
| 3411 | sas_phy_disconnected(sas_phy); |
| 3412 | phy->phy_attached = 0; |
| 3413 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3414 | break; |
| 3415 | case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: |
| 3416 | PM8001_MSG_DBG(pm8001_ha, |
| 3417 | pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n")); |
| 3418 | pm8001_hw_event_ack_req(pm8001_ha, 0, |
| 3419 | HW_EVENT_LINK_ERR_PHY_RESET_FAILED, |
| 3420 | port_id, phy_id, 0, 0); |
| 3421 | sas_phy_disconnected(sas_phy); |
| 3422 | phy->phy_attached = 0; |
| 3423 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3424 | break; |
| 3425 | case HW_EVENT_PORT_RESET_TIMER_TMO: |
| 3426 | PM8001_MSG_DBG(pm8001_ha, |
| 3427 | pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n")); |
| 3428 | sas_phy_disconnected(sas_phy); |
| 3429 | phy->phy_attached = 0; |
| 3430 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3431 | break; |
| 3432 | case HW_EVENT_PORT_RECOVERY_TIMER_TMO: |
| 3433 | PM8001_MSG_DBG(pm8001_ha, |
| 3434 | pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n")); |
| 3435 | sas_phy_disconnected(sas_phy); |
| 3436 | phy->phy_attached = 0; |
| 3437 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); |
| 3438 | break; |
| 3439 | case HW_EVENT_PORT_RECOVER: |
| 3440 | PM8001_MSG_DBG(pm8001_ha, |
| 3441 | pm8001_printk("HW_EVENT_PORT_RECOVER \n")); |
| 3442 | break; |
| 3443 | case HW_EVENT_PORT_RESET_COMPLETE: |
| 3444 | PM8001_MSG_DBG(pm8001_ha, |
| 3445 | pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n")); |
| 3446 | break; |
| 3447 | case EVENT_BROADCAST_ASYNCH_EVENT: |
| 3448 | PM8001_MSG_DBG(pm8001_ha, |
| 3449 | pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); |
| 3450 | break; |
| 3451 | default: |
| 3452 | PM8001_MSG_DBG(pm8001_ha, |
| 3453 | pm8001_printk("Unknown event type = %x\n", eventType)); |
| 3454 | break; |
| 3455 | } |
| 3456 | return 0; |
| 3457 | } |
| 3458 | |
| 3459 | /** |
| 3460 | * process_one_iomb - process one outbound Queue memory block |
| 3461 | * @pm8001_ha: our hba card information |
| 3462 | * @piomb: IO message buffer |
| 3463 | */ |
| 3464 | static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) |
| 3465 | { |
| 3466 | u32 pHeader = (u32)*(u32 *)piomb; |
| 3467 | u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF); |
| 3468 | |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3469 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3470 | |
| 3471 | switch (opc) { |
| 3472 | case OPC_OUB_ECHO: |
| 3473 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n")); |
| 3474 | break; |
| 3475 | case OPC_OUB_HW_EVENT: |
| 3476 | PM8001_MSG_DBG(pm8001_ha, |
| 3477 | pm8001_printk("OPC_OUB_HW_EVENT \n")); |
| 3478 | mpi_hw_event(pm8001_ha, piomb); |
| 3479 | break; |
| 3480 | case OPC_OUB_SSP_COMP: |
| 3481 | PM8001_MSG_DBG(pm8001_ha, |
| 3482 | pm8001_printk("OPC_OUB_SSP_COMP \n")); |
| 3483 | mpi_ssp_completion(pm8001_ha, piomb); |
| 3484 | break; |
| 3485 | case OPC_OUB_SMP_COMP: |
| 3486 | PM8001_MSG_DBG(pm8001_ha, |
| 3487 | pm8001_printk("OPC_OUB_SMP_COMP \n")); |
| 3488 | mpi_smp_completion(pm8001_ha, piomb); |
| 3489 | break; |
| 3490 | case OPC_OUB_LOCAL_PHY_CNTRL: |
| 3491 | PM8001_MSG_DBG(pm8001_ha, |
| 3492 | pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); |
| 3493 | mpi_local_phy_ctl(pm8001_ha, piomb); |
| 3494 | break; |
| 3495 | case OPC_OUB_DEV_REGIST: |
| 3496 | PM8001_MSG_DBG(pm8001_ha, |
| 3497 | pm8001_printk("OPC_OUB_DEV_REGIST \n")); |
| 3498 | mpi_reg_resp(pm8001_ha, piomb); |
| 3499 | break; |
| 3500 | case OPC_OUB_DEREG_DEV: |
| 3501 | PM8001_MSG_DBG(pm8001_ha, |
| 3502 | pm8001_printk("unresgister the deviece \n")); |
| 3503 | mpi_dereg_resp(pm8001_ha, piomb); |
| 3504 | break; |
| 3505 | case OPC_OUB_GET_DEV_HANDLE: |
| 3506 | PM8001_MSG_DBG(pm8001_ha, |
| 3507 | pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n")); |
| 3508 | break; |
| 3509 | case OPC_OUB_SATA_COMP: |
| 3510 | PM8001_MSG_DBG(pm8001_ha, |
| 3511 | pm8001_printk("OPC_OUB_SATA_COMP \n")); |
| 3512 | mpi_sata_completion(pm8001_ha, piomb); |
| 3513 | break; |
| 3514 | case OPC_OUB_SATA_EVENT: |
| 3515 | PM8001_MSG_DBG(pm8001_ha, |
| 3516 | pm8001_printk("OPC_OUB_SATA_EVENT \n")); |
| 3517 | mpi_sata_event(pm8001_ha, piomb); |
| 3518 | break; |
| 3519 | case OPC_OUB_SSP_EVENT: |
| 3520 | PM8001_MSG_DBG(pm8001_ha, |
| 3521 | pm8001_printk("OPC_OUB_SSP_EVENT\n")); |
| 3522 | mpi_ssp_event(pm8001_ha, piomb); |
| 3523 | break; |
| 3524 | case OPC_OUB_DEV_HANDLE_ARRIV: |
| 3525 | PM8001_MSG_DBG(pm8001_ha, |
| 3526 | pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); |
| 3527 | /*This is for target*/ |
| 3528 | break; |
| 3529 | case OPC_OUB_SSP_RECV_EVENT: |
| 3530 | PM8001_MSG_DBG(pm8001_ha, |
| 3531 | pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); |
| 3532 | /*This is for target*/ |
| 3533 | break; |
| 3534 | case OPC_OUB_DEV_INFO: |
| 3535 | PM8001_MSG_DBG(pm8001_ha, |
| 3536 | pm8001_printk("OPC_OUB_DEV_INFO\n")); |
| 3537 | break; |
| 3538 | case OPC_OUB_FW_FLASH_UPDATE: |
| 3539 | PM8001_MSG_DBG(pm8001_ha, |
| 3540 | pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); |
| 3541 | mpi_fw_flash_update_resp(pm8001_ha, piomb); |
| 3542 | break; |
| 3543 | case OPC_OUB_GPIO_RESPONSE: |
| 3544 | PM8001_MSG_DBG(pm8001_ha, |
| 3545 | pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); |
| 3546 | break; |
| 3547 | case OPC_OUB_GPIO_EVENT: |
| 3548 | PM8001_MSG_DBG(pm8001_ha, |
| 3549 | pm8001_printk("OPC_OUB_GPIO_EVENT\n")); |
| 3550 | break; |
| 3551 | case OPC_OUB_GENERAL_EVENT: |
| 3552 | PM8001_MSG_DBG(pm8001_ha, |
| 3553 | pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); |
| 3554 | mpi_general_event(pm8001_ha, piomb); |
| 3555 | break; |
| 3556 | case OPC_OUB_SSP_ABORT_RSP: |
| 3557 | PM8001_MSG_DBG(pm8001_ha, |
| 3558 | pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); |
| 3559 | mpi_task_abort_resp(pm8001_ha, piomb); |
| 3560 | break; |
| 3561 | case OPC_OUB_SATA_ABORT_RSP: |
| 3562 | PM8001_MSG_DBG(pm8001_ha, |
| 3563 | pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); |
| 3564 | mpi_task_abort_resp(pm8001_ha, piomb); |
| 3565 | break; |
| 3566 | case OPC_OUB_SAS_DIAG_MODE_START_END: |
| 3567 | PM8001_MSG_DBG(pm8001_ha, |
| 3568 | pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); |
| 3569 | break; |
| 3570 | case OPC_OUB_SAS_DIAG_EXECUTE: |
| 3571 | PM8001_MSG_DBG(pm8001_ha, |
| 3572 | pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); |
| 3573 | break; |
| 3574 | case OPC_OUB_GET_TIME_STAMP: |
| 3575 | PM8001_MSG_DBG(pm8001_ha, |
| 3576 | pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); |
| 3577 | break; |
| 3578 | case OPC_OUB_SAS_HW_EVENT_ACK: |
| 3579 | PM8001_MSG_DBG(pm8001_ha, |
| 3580 | pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); |
| 3581 | break; |
| 3582 | case OPC_OUB_PORT_CONTROL: |
| 3583 | PM8001_MSG_DBG(pm8001_ha, |
| 3584 | pm8001_printk("OPC_OUB_PORT_CONTROL\n")); |
| 3585 | break; |
| 3586 | case OPC_OUB_SMP_ABORT_RSP: |
| 3587 | PM8001_MSG_DBG(pm8001_ha, |
| 3588 | pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); |
| 3589 | mpi_task_abort_resp(pm8001_ha, piomb); |
| 3590 | break; |
| 3591 | case OPC_OUB_GET_NVMD_DATA: |
| 3592 | PM8001_MSG_DBG(pm8001_ha, |
| 3593 | pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); |
| 3594 | mpi_get_nvmd_resp(pm8001_ha, piomb); |
| 3595 | break; |
| 3596 | case OPC_OUB_SET_NVMD_DATA: |
| 3597 | PM8001_MSG_DBG(pm8001_ha, |
| 3598 | pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); |
| 3599 | mpi_set_nvmd_resp(pm8001_ha, piomb); |
| 3600 | break; |
| 3601 | case OPC_OUB_DEVICE_HANDLE_REMOVAL: |
| 3602 | PM8001_MSG_DBG(pm8001_ha, |
| 3603 | pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); |
| 3604 | break; |
| 3605 | case OPC_OUB_SET_DEVICE_STATE: |
| 3606 | PM8001_MSG_DBG(pm8001_ha, |
| 3607 | pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); |
| 3608 | mpi_set_dev_state_resp(pm8001_ha, piomb); |
| 3609 | break; |
| 3610 | case OPC_OUB_GET_DEVICE_STATE: |
| 3611 | PM8001_MSG_DBG(pm8001_ha, |
| 3612 | pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); |
| 3613 | break; |
| 3614 | case OPC_OUB_SET_DEV_INFO: |
| 3615 | PM8001_MSG_DBG(pm8001_ha, |
| 3616 | pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); |
| 3617 | break; |
| 3618 | case OPC_OUB_SAS_RE_INITIALIZE: |
| 3619 | PM8001_MSG_DBG(pm8001_ha, |
| 3620 | pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); |
| 3621 | break; |
| 3622 | default: |
| 3623 | PM8001_MSG_DBG(pm8001_ha, |
| 3624 | pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", |
| 3625 | opc)); |
| 3626 | break; |
| 3627 | } |
| 3628 | } |
| 3629 | |
| 3630 | static int process_oq(struct pm8001_hba_info *pm8001_ha) |
| 3631 | { |
| 3632 | struct outbound_queue_table *circularQ; |
| 3633 | void *pMsg1 = NULL; |
| 3634 | u8 bc = 0; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3635 | u32 ret = MPI_IO_STATUS_FAIL; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3636 | |
| 3637 | circularQ = &pm8001_ha->outbnd_q_tbl[0]; |
| 3638 | do { |
| 3639 | ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); |
| 3640 | if (MPI_IO_STATUS_SUCCESS == ret) { |
| 3641 | /* process the outbound message */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3642 | process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3643 | /* free the message from the outbound circular buffer */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3644 | mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3645 | } |
| 3646 | if (MPI_IO_STATUS_BUSY == ret) { |
| 3647 | u32 producer_idx; |
| 3648 | /* Update the producer index from SPC */ |
| 3649 | producer_idx = pm8001_read_32(circularQ->pi_virt); |
| 3650 | circularQ->producer_index = cpu_to_le32(producer_idx); |
| 3651 | if (circularQ->producer_index == |
| 3652 | circularQ->consumer_idx) |
| 3653 | /* OQ is empty */ |
| 3654 | break; |
| 3655 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3656 | } while (1); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3657 | return ret; |
| 3658 | } |
| 3659 | |
| 3660 | /* PCI_DMA_... to our direction translation. */ |
| 3661 | static const u8 data_dir_flags[] = { |
| 3662 | [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ |
| 3663 | [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ |
| 3664 | [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ |
| 3665 | [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ |
| 3666 | }; |
| 3667 | static void |
| 3668 | pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) |
| 3669 | { |
| 3670 | int i; |
| 3671 | struct scatterlist *sg; |
| 3672 | struct pm8001_prd *buf_prd = prd; |
| 3673 | |
| 3674 | for_each_sg(scatter, sg, nr, i) { |
| 3675 | buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); |
| 3676 | buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); |
| 3677 | buf_prd->im_len.e = 0; |
| 3678 | buf_prd++; |
| 3679 | } |
| 3680 | } |
| 3681 | |
| 3682 | static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd) |
| 3683 | { |
| 3684 | psmp_cmd->tag = cpu_to_le32(hTag); |
| 3685 | psmp_cmd->device_id = cpu_to_le32(deviceID); |
| 3686 | psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); |
| 3687 | } |
| 3688 | |
| 3689 | /** |
| 3690 | * pm8001_chip_smp_req - send a SMP task to FW |
| 3691 | * @pm8001_ha: our hba card information. |
| 3692 | * @ccb: the ccb information this request used. |
| 3693 | */ |
| 3694 | static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, |
| 3695 | struct pm8001_ccb_info *ccb) |
| 3696 | { |
| 3697 | int elem, rc; |
| 3698 | struct sas_task *task = ccb->task; |
| 3699 | struct domain_device *dev = task->dev; |
| 3700 | struct pm8001_device *pm8001_dev = dev->lldd_dev; |
| 3701 | struct scatterlist *sg_req, *sg_resp; |
| 3702 | u32 req_len, resp_len; |
| 3703 | struct smp_req smp_cmd; |
| 3704 | u32 opc; |
| 3705 | struct inbound_queue_table *circularQ; |
| 3706 | |
| 3707 | memset(&smp_cmd, 0, sizeof(smp_cmd)); |
| 3708 | /* |
| 3709 | * DMA-map SMP request, response buffers |
| 3710 | */ |
| 3711 | sg_req = &task->smp_task.smp_req; |
| 3712 | elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); |
| 3713 | if (!elem) |
| 3714 | return -ENOMEM; |
| 3715 | req_len = sg_dma_len(sg_req); |
| 3716 | |
| 3717 | sg_resp = &task->smp_task.smp_resp; |
| 3718 | elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); |
| 3719 | if (!elem) { |
| 3720 | rc = -ENOMEM; |
| 3721 | goto err_out; |
| 3722 | } |
| 3723 | resp_len = sg_dma_len(sg_resp); |
| 3724 | /* must be in dwords */ |
| 3725 | if ((req_len & 0x3) || (resp_len & 0x3)) { |
| 3726 | rc = -EINVAL; |
| 3727 | goto err_out_2; |
| 3728 | } |
| 3729 | |
| 3730 | opc = OPC_INB_SMP_REQUEST; |
| 3731 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 3732 | smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); |
| 3733 | smp_cmd.long_smp_req.long_req_addr = |
| 3734 | cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); |
| 3735 | smp_cmd.long_smp_req.long_req_size = |
| 3736 | cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); |
| 3737 | smp_cmd.long_smp_req.long_resp_addr = |
| 3738 | cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); |
| 3739 | smp_cmd.long_smp_req.long_resp_size = |
| 3740 | cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); |
| 3741 | build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); |
| 3742 | mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd); |
| 3743 | return 0; |
| 3744 | |
| 3745 | err_out_2: |
| 3746 | dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, |
| 3747 | PCI_DMA_FROMDEVICE); |
| 3748 | err_out: |
| 3749 | dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, |
| 3750 | PCI_DMA_TODEVICE); |
| 3751 | return rc; |
| 3752 | } |
| 3753 | |
| 3754 | /** |
| 3755 | * pm8001_chip_ssp_io_req - send a SSP task to FW |
| 3756 | * @pm8001_ha: our hba card information. |
| 3757 | * @ccb: the ccb information this request used. |
| 3758 | */ |
| 3759 | static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, |
| 3760 | struct pm8001_ccb_info *ccb) |
| 3761 | { |
| 3762 | struct sas_task *task = ccb->task; |
| 3763 | struct domain_device *dev = task->dev; |
| 3764 | struct pm8001_device *pm8001_dev = dev->lldd_dev; |
| 3765 | struct ssp_ini_io_start_req ssp_cmd; |
| 3766 | u32 tag = ccb->ccb_tag; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3767 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3768 | __le64 phys_addr; |
| 3769 | struct inbound_queue_table *circularQ; |
| 3770 | u32 opc = OPC_INB_SSPINIIOSTART; |
| 3771 | memset(&ssp_cmd, 0, sizeof(ssp_cmd)); |
| 3772 | memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); |
| 3773 | ssp_cmd.dir_m_tlr = data_dir_flags[task->data_dir] << 8 | 0x0;/*0 for |
| 3774 | SAS 1.1 compatible TLR*/ |
| 3775 | ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); |
| 3776 | ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); |
| 3777 | ssp_cmd.tag = cpu_to_le32(tag); |
| 3778 | if (task->ssp_task.enable_first_burst) |
| 3779 | ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; |
| 3780 | ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); |
| 3781 | ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); |
| 3782 | memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16); |
| 3783 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 3784 | |
| 3785 | /* fill in PRD (scatter/gather) table, if any */ |
| 3786 | if (task->num_scatter > 1) { |
| 3787 | pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); |
| 3788 | phys_addr = cpu_to_le64(ccb->ccb_dma_handle + |
| 3789 | offsetof(struct pm8001_ccb_info, buf_prd[0])); |
| 3790 | ssp_cmd.addr_low = lower_32_bits(phys_addr); |
| 3791 | ssp_cmd.addr_high = upper_32_bits(phys_addr); |
| 3792 | ssp_cmd.esgl = cpu_to_le32(1<<31); |
| 3793 | } else if (task->num_scatter == 1) { |
| 3794 | __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter)); |
| 3795 | ssp_cmd.addr_low = lower_32_bits(dma_addr); |
| 3796 | ssp_cmd.addr_high = upper_32_bits(dma_addr); |
| 3797 | ssp_cmd.len = cpu_to_le32(task->total_xfer_len); |
| 3798 | ssp_cmd.esgl = 0; |
| 3799 | } else if (task->num_scatter == 0) { |
| 3800 | ssp_cmd.addr_low = 0; |
| 3801 | ssp_cmd.addr_high = 0; |
| 3802 | ssp_cmd.len = cpu_to_le32(task->total_xfer_len); |
| 3803 | ssp_cmd.esgl = 0; |
| 3804 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3805 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd); |
| 3806 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3807 | } |
| 3808 | |
| 3809 | static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, |
| 3810 | struct pm8001_ccb_info *ccb) |
| 3811 | { |
| 3812 | struct sas_task *task = ccb->task; |
| 3813 | struct domain_device *dev = task->dev; |
| 3814 | struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; |
| 3815 | u32 tag = ccb->ccb_tag; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3816 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3817 | struct sata_start_req sata_cmd; |
| 3818 | u32 hdr_tag, ncg_tag = 0; |
| 3819 | __le64 phys_addr; |
| 3820 | u32 ATAP = 0x0; |
| 3821 | u32 dir; |
| 3822 | struct inbound_queue_table *circularQ; |
| 3823 | u32 opc = OPC_INB_SATA_HOST_OPSTART; |
| 3824 | memset(&sata_cmd, 0, sizeof(sata_cmd)); |
| 3825 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 3826 | if (task->data_dir == PCI_DMA_NONE) { |
| 3827 | ATAP = 0x04; /* no data*/ |
| 3828 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n")); |
| 3829 | } else if (likely(!task->ata_task.device_control_reg_update)) { |
| 3830 | if (task->ata_task.dma_xfer) { |
| 3831 | ATAP = 0x06; /* DMA */ |
| 3832 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n")); |
| 3833 | } else { |
| 3834 | ATAP = 0x05; /* PIO*/ |
| 3835 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n")); |
| 3836 | } |
| 3837 | if (task->ata_task.use_ncq && |
| 3838 | dev->sata_dev.command_set != ATAPI_COMMAND_SET) { |
| 3839 | ATAP = 0x07; /* FPDMA */ |
| 3840 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n")); |
| 3841 | } |
| 3842 | } |
| 3843 | if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) |
| 3844 | ncg_tag = cpu_to_le32(hdr_tag); |
| 3845 | dir = data_dir_flags[task->data_dir] << 8; |
| 3846 | sata_cmd.tag = cpu_to_le32(tag); |
| 3847 | sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); |
| 3848 | sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); |
| 3849 | sata_cmd.ncqtag_atap_dir_m = |
| 3850 | cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); |
| 3851 | sata_cmd.sata_fis = task->ata_task.fis; |
| 3852 | if (likely(!task->ata_task.device_control_reg_update)) |
| 3853 | sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ |
| 3854 | sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ |
| 3855 | /* fill in PRD (scatter/gather) table, if any */ |
| 3856 | if (task->num_scatter > 1) { |
| 3857 | pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); |
| 3858 | phys_addr = cpu_to_le64(ccb->ccb_dma_handle + |
| 3859 | offsetof(struct pm8001_ccb_info, buf_prd[0])); |
| 3860 | sata_cmd.addr_low = lower_32_bits(phys_addr); |
| 3861 | sata_cmd.addr_high = upper_32_bits(phys_addr); |
| 3862 | sata_cmd.esgl = cpu_to_le32(1 << 31); |
| 3863 | } else if (task->num_scatter == 1) { |
| 3864 | __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter)); |
| 3865 | sata_cmd.addr_low = lower_32_bits(dma_addr); |
| 3866 | sata_cmd.addr_high = upper_32_bits(dma_addr); |
| 3867 | sata_cmd.len = cpu_to_le32(task->total_xfer_len); |
| 3868 | sata_cmd.esgl = 0; |
| 3869 | } else if (task->num_scatter == 0) { |
| 3870 | sata_cmd.addr_low = 0; |
| 3871 | sata_cmd.addr_high = 0; |
| 3872 | sata_cmd.len = cpu_to_le32(task->total_xfer_len); |
| 3873 | sata_cmd.esgl = 0; |
| 3874 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3875 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd); |
| 3876 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3877 | } |
| 3878 | |
| 3879 | /** |
| 3880 | * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND |
| 3881 | * @pm8001_ha: our hba card information. |
| 3882 | * @num: the inbound queue number |
| 3883 | * @phy_id: the phy id which we wanted to start up. |
| 3884 | */ |
| 3885 | static int |
| 3886 | pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) |
| 3887 | { |
| 3888 | struct phy_start_req payload; |
| 3889 | struct inbound_queue_table *circularQ; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3890 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3891 | u32 tag = 0x01; |
| 3892 | u32 opcode = OPC_INB_PHYSTART; |
| 3893 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 3894 | memset(&payload, 0, sizeof(payload)); |
| 3895 | payload.tag = cpu_to_le32(tag); |
| 3896 | /* |
| 3897 | ** [0:7] PHY Identifier |
| 3898 | ** [8:11] link rate 1.5G, 3G, 6G |
| 3899 | ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both |
| 3900 | ** [14] 0b disable spin up hold; 1b enable spin up hold |
| 3901 | */ |
| 3902 | payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | |
| 3903 | LINKMODE_AUTO | LINKRATE_15 | |
| 3904 | LINKRATE_30 | LINKRATE_60 | phy_id); |
| 3905 | payload.sas_identify.dev_type = SAS_END_DEV; |
| 3906 | payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; |
| 3907 | memcpy(payload.sas_identify.sas_addr, |
| 3908 | pm8001_ha->sas_addr, SAS_ADDR_SIZE); |
| 3909 | payload.sas_identify.phy_id = phy_id; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3910 | ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload); |
| 3911 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3912 | } |
| 3913 | |
| 3914 | /** |
| 3915 | * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND |
| 3916 | * @pm8001_ha: our hba card information. |
| 3917 | * @num: the inbound queue number |
| 3918 | * @phy_id: the phy id which we wanted to start up. |
| 3919 | */ |
| 3920 | static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, |
| 3921 | u8 phy_id) |
| 3922 | { |
| 3923 | struct phy_stop_req payload; |
| 3924 | struct inbound_queue_table *circularQ; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3925 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3926 | u32 tag = 0x01; |
| 3927 | u32 opcode = OPC_INB_PHYSTOP; |
| 3928 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 3929 | memset(&payload, 0, sizeof(payload)); |
| 3930 | payload.tag = cpu_to_le32(tag); |
| 3931 | payload.phy_id = cpu_to_le32(phy_id); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3932 | ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload); |
| 3933 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3934 | } |
| 3935 | |
| 3936 | /** |
| 3937 | * see comments on mpi_reg_resp. |
| 3938 | */ |
| 3939 | static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, |
| 3940 | struct pm8001_device *pm8001_dev, u32 flag) |
| 3941 | { |
| 3942 | struct reg_dev_req payload; |
| 3943 | u32 opc; |
| 3944 | u32 stp_sspsmp_sata = 0x4; |
| 3945 | struct inbound_queue_table *circularQ; |
| 3946 | u32 linkrate, phy_id; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3947 | int rc, tag = 0xdeadbeef; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3948 | struct pm8001_ccb_info *ccb; |
| 3949 | u8 retryFlag = 0x1; |
| 3950 | u16 firstBurstSize = 0; |
| 3951 | u16 ITNT = 2000; |
| 3952 | struct domain_device *dev = pm8001_dev->sas_device; |
| 3953 | struct domain_device *parent_dev = dev->parent; |
| 3954 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 3955 | |
| 3956 | memset(&payload, 0, sizeof(payload)); |
| 3957 | rc = pm8001_tag_alloc(pm8001_ha, &tag); |
| 3958 | if (rc) |
| 3959 | return rc; |
| 3960 | ccb = &pm8001_ha->ccb_info[tag]; |
| 3961 | ccb->device = pm8001_dev; |
| 3962 | ccb->ccb_tag = tag; |
| 3963 | payload.tag = cpu_to_le32(tag); |
| 3964 | if (flag == 1) |
| 3965 | stp_sspsmp_sata = 0x02; /*direct attached sata */ |
| 3966 | else { |
| 3967 | if (pm8001_dev->dev_type == SATA_DEV) |
| 3968 | stp_sspsmp_sata = 0x00; /* stp*/ |
| 3969 | else if (pm8001_dev->dev_type == SAS_END_DEV || |
| 3970 | pm8001_dev->dev_type == EDGE_DEV || |
| 3971 | pm8001_dev->dev_type == FANOUT_DEV) |
| 3972 | stp_sspsmp_sata = 0x01; /*ssp or smp*/ |
| 3973 | } |
| 3974 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) |
| 3975 | phy_id = parent_dev->ex_dev.ex_phy->phy_id; |
| 3976 | else |
| 3977 | phy_id = pm8001_dev->attached_phy; |
| 3978 | opc = OPC_INB_REG_DEV; |
| 3979 | linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? |
| 3980 | pm8001_dev->sas_device->linkrate : dev->port->linkrate; |
| 3981 | payload.phyid_portid = |
| 3982 | cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | |
| 3983 | ((phy_id & 0x0F) << 4)); |
| 3984 | payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | |
| 3985 | ((linkrate & 0x0F) * 0x1000000) | |
| 3986 | ((stp_sspsmp_sata & 0x03) * 0x10000000)); |
| 3987 | payload.firstburstsize_ITNexustimeout = |
| 3988 | cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); |
| 3989 | memcpy(&payload.sas_addr_hi, pm8001_dev->sas_device->sas_addr, |
| 3990 | SAS_ADDR_SIZE); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 3991 | rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 3992 | return rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 3993 | } |
| 3994 | |
| 3995 | /** |
| 3996 | * see comments on mpi_reg_resp. |
| 3997 | */ |
| 3998 | static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, |
| 3999 | u32 device_id) |
| 4000 | { |
| 4001 | struct dereg_dev_req payload; |
| 4002 | u32 opc = OPC_INB_DEREG_DEV_HANDLE; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4003 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4004 | struct inbound_queue_table *circularQ; |
| 4005 | |
| 4006 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4007 | memset(&payload, 0, sizeof(payload)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4008 | payload.tag = 1; |
| 4009 | payload.device_id = cpu_to_le32(device_id); |
| 4010 | PM8001_MSG_DBG(pm8001_ha, |
| 4011 | pm8001_printk("unregister device device_id = %d\n", device_id)); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4012 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 4013 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4014 | } |
| 4015 | |
| 4016 | /** |
| 4017 | * pm8001_chip_phy_ctl_req - support the local phy operation |
| 4018 | * @pm8001_ha: our hba card information. |
| 4019 | * @num: the inbound queue number |
| 4020 | * @phy_id: the phy id which we wanted to operate |
| 4021 | * @phy_op: |
| 4022 | */ |
| 4023 | static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, |
| 4024 | u32 phyId, u32 phy_op) |
| 4025 | { |
| 4026 | struct local_phy_ctl_req payload; |
| 4027 | struct inbound_queue_table *circularQ; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4028 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4029 | u32 opc = OPC_INB_LOCAL_PHY_CONTROL; |
| 4030 | memset((u8 *)&payload, 0, sizeof(payload)); |
| 4031 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4032 | payload.tag = 1; |
| 4033 | payload.phyop_phyid = |
| 4034 | cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4035 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 4036 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4037 | } |
| 4038 | |
| 4039 | static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) |
| 4040 | { |
| 4041 | u32 value; |
| 4042 | #ifdef PM8001_USE_MSIX |
| 4043 | return 1; |
| 4044 | #endif |
| 4045 | value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); |
| 4046 | if (value) |
| 4047 | return 1; |
| 4048 | return 0; |
| 4049 | |
| 4050 | } |
| 4051 | |
| 4052 | /** |
| 4053 | * pm8001_chip_isr - PM8001 isr handler. |
| 4054 | * @pm8001_ha: our hba card information. |
| 4055 | * @irq: irq number. |
| 4056 | * @stat: stat. |
| 4057 | */ |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4058 | static irqreturn_t |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4059 | pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha) |
| 4060 | { |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4061 | unsigned long flags; |
| 4062 | spin_lock_irqsave(&pm8001_ha->lock, flags); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4063 | pm8001_chip_interrupt_disable(pm8001_ha); |
| 4064 | process_oq(pm8001_ha); |
| 4065 | pm8001_chip_interrupt_enable(pm8001_ha); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4066 | spin_unlock_irqrestore(&pm8001_ha->lock, flags); |
| 4067 | return IRQ_HANDLED; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4068 | } |
| 4069 | |
| 4070 | static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, |
| 4071 | u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) |
| 4072 | { |
| 4073 | struct task_abort_req task_abort; |
| 4074 | struct inbound_queue_table *circularQ; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4075 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4076 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4077 | memset(&task_abort, 0, sizeof(task_abort)); |
| 4078 | if (ABORT_SINGLE == (flag & ABORT_MASK)) { |
| 4079 | task_abort.abort_all = 0; |
| 4080 | task_abort.device_id = cpu_to_le32(dev_id); |
| 4081 | task_abort.tag_to_abort = cpu_to_le32(task_tag); |
| 4082 | task_abort.tag = cpu_to_le32(cmd_tag); |
| 4083 | } else if (ABORT_ALL == (flag & ABORT_MASK)) { |
| 4084 | task_abort.abort_all = cpu_to_le32(1); |
| 4085 | task_abort.device_id = cpu_to_le32(dev_id); |
| 4086 | task_abort.tag = cpu_to_le32(cmd_tag); |
| 4087 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4088 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort); |
| 4089 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4090 | } |
| 4091 | |
| 4092 | /** |
| 4093 | * pm8001_chip_abort_task - SAS abort task when error or exception happened. |
| 4094 | * @task: the task we wanted to aborted. |
| 4095 | * @flag: the abort flag. |
| 4096 | */ |
| 4097 | static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, |
| 4098 | struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) |
| 4099 | { |
| 4100 | u32 opc, device_id; |
| 4101 | int rc = TMF_RESP_FUNC_FAILED; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4102 | PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag" |
| 4103 | " = %x", cmd_tag, task_tag)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4104 | if (pm8001_dev->dev_type == SAS_END_DEV) |
| 4105 | opc = OPC_INB_SSP_ABORT; |
| 4106 | else if (pm8001_dev->dev_type == SATA_DEV) |
| 4107 | opc = OPC_INB_SATA_ABORT; |
| 4108 | else |
| 4109 | opc = OPC_INB_SMP_ABORT;/* SMP */ |
| 4110 | device_id = pm8001_dev->device_id; |
| 4111 | rc = send_task_abort(pm8001_ha, opc, device_id, flag, |
| 4112 | task_tag, cmd_tag); |
| 4113 | if (rc != TMF_RESP_FUNC_COMPLETE) |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4114 | PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4115 | return rc; |
| 4116 | } |
| 4117 | |
| 4118 | /** |
| 4119 | * pm8001_chip_ssp_tm_req - built the task managment command. |
| 4120 | * @pm8001_ha: our hba card information. |
| 4121 | * @ccb: the ccb information. |
| 4122 | * @tmf: task management function. |
| 4123 | */ |
| 4124 | static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, |
| 4125 | struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) |
| 4126 | { |
| 4127 | struct sas_task *task = ccb->task; |
| 4128 | struct domain_device *dev = task->dev; |
| 4129 | struct pm8001_device *pm8001_dev = dev->lldd_dev; |
| 4130 | u32 opc = OPC_INB_SSPINITMSTART; |
| 4131 | struct inbound_queue_table *circularQ; |
| 4132 | struct ssp_ini_tm_start_req sspTMCmd; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4133 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4134 | |
| 4135 | memset(&sspTMCmd, 0, sizeof(sspTMCmd)); |
| 4136 | sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); |
| 4137 | sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); |
| 4138 | sspTMCmd.tmf = cpu_to_le32(tmf->tmf); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4139 | memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); |
| 4140 | sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); |
| 4141 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4142 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd); |
| 4143 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4144 | } |
| 4145 | |
| 4146 | static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, |
| 4147 | void *payload) |
| 4148 | { |
| 4149 | u32 opc = OPC_INB_GET_NVMD_DATA; |
| 4150 | u32 nvmd_type; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4151 | int rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4152 | u32 tag; |
| 4153 | struct pm8001_ccb_info *ccb; |
| 4154 | struct inbound_queue_table *circularQ; |
| 4155 | struct get_nvm_data_req nvmd_req; |
| 4156 | struct fw_control_ex *fw_control_context; |
| 4157 | struct pm8001_ioctl_payload *ioctl_payload = payload; |
| 4158 | |
| 4159 | nvmd_type = ioctl_payload->minor_function; |
| 4160 | fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); |
| 4161 | fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0]; |
| 4162 | fw_control_context->len = ioctl_payload->length; |
| 4163 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4164 | memset(&nvmd_req, 0, sizeof(nvmd_req)); |
| 4165 | rc = pm8001_tag_alloc(pm8001_ha, &tag); |
| 4166 | if (rc) |
| 4167 | return rc; |
| 4168 | ccb = &pm8001_ha->ccb_info[tag]; |
| 4169 | ccb->ccb_tag = tag; |
| 4170 | ccb->fw_control_context = fw_control_context; |
| 4171 | nvmd_req.tag = cpu_to_le32(tag); |
| 4172 | |
| 4173 | switch (nvmd_type) { |
| 4174 | case TWI_DEVICE: { |
| 4175 | u32 twi_addr, twi_page_size; |
| 4176 | twi_addr = 0xa8; |
| 4177 | twi_page_size = 2; |
| 4178 | |
| 4179 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | |
| 4180 | twi_page_size << 8 | TWI_DEVICE); |
| 4181 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4182 | nvmd_req.resp_addr_hi = |
| 4183 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4184 | nvmd_req.resp_addr_lo = |
| 4185 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4186 | break; |
| 4187 | } |
| 4188 | case C_SEEPROM: { |
| 4189 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); |
| 4190 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4191 | nvmd_req.resp_addr_hi = |
| 4192 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4193 | nvmd_req.resp_addr_lo = |
| 4194 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4195 | break; |
| 4196 | } |
| 4197 | case VPD_FLASH: { |
| 4198 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); |
| 4199 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4200 | nvmd_req.resp_addr_hi = |
| 4201 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4202 | nvmd_req.resp_addr_lo = |
| 4203 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4204 | break; |
| 4205 | } |
| 4206 | case EXPAN_ROM: { |
| 4207 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); |
| 4208 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4209 | nvmd_req.resp_addr_hi = |
| 4210 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4211 | nvmd_req.resp_addr_lo = |
| 4212 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4213 | break; |
| 4214 | } |
| 4215 | default: |
| 4216 | break; |
| 4217 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4218 | rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req); |
| 4219 | return rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4220 | } |
| 4221 | |
| 4222 | static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, |
| 4223 | void *payload) |
| 4224 | { |
| 4225 | u32 opc = OPC_INB_SET_NVMD_DATA; |
| 4226 | u32 nvmd_type; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4227 | int rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4228 | u32 tag; |
| 4229 | struct pm8001_ccb_info *ccb; |
| 4230 | struct inbound_queue_table *circularQ; |
| 4231 | struct set_nvm_data_req nvmd_req; |
| 4232 | struct fw_control_ex *fw_control_context; |
| 4233 | struct pm8001_ioctl_payload *ioctl_payload = payload; |
| 4234 | |
| 4235 | nvmd_type = ioctl_payload->minor_function; |
| 4236 | fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); |
| 4237 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4238 | memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, |
| 4239 | ioctl_payload->func_specific, |
| 4240 | ioctl_payload->length); |
| 4241 | memset(&nvmd_req, 0, sizeof(nvmd_req)); |
| 4242 | rc = pm8001_tag_alloc(pm8001_ha, &tag); |
| 4243 | if (rc) |
| 4244 | return rc; |
| 4245 | ccb = &pm8001_ha->ccb_info[tag]; |
| 4246 | ccb->fw_control_context = fw_control_context; |
| 4247 | ccb->ccb_tag = tag; |
| 4248 | nvmd_req.tag = cpu_to_le32(tag); |
| 4249 | switch (nvmd_type) { |
| 4250 | case TWI_DEVICE: { |
| 4251 | u32 twi_addr, twi_page_size; |
| 4252 | twi_addr = 0xa8; |
| 4253 | twi_page_size = 2; |
| 4254 | nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); |
| 4255 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | |
| 4256 | twi_page_size << 8 | TWI_DEVICE); |
| 4257 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4258 | nvmd_req.resp_addr_hi = |
| 4259 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4260 | nvmd_req.resp_addr_lo = |
| 4261 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4262 | break; |
| 4263 | } |
| 4264 | case C_SEEPROM: |
| 4265 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); |
| 4266 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4267 | nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); |
| 4268 | nvmd_req.resp_addr_hi = |
| 4269 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4270 | nvmd_req.resp_addr_lo = |
| 4271 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4272 | break; |
| 4273 | case VPD_FLASH: |
| 4274 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); |
| 4275 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4276 | nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); |
| 4277 | nvmd_req.resp_addr_hi = |
| 4278 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4279 | nvmd_req.resp_addr_lo = |
| 4280 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4281 | break; |
| 4282 | case EXPAN_ROM: |
| 4283 | nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); |
| 4284 | nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); |
| 4285 | nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); |
| 4286 | nvmd_req.resp_addr_hi = |
| 4287 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); |
| 4288 | nvmd_req.resp_addr_lo = |
| 4289 | cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); |
| 4290 | break; |
| 4291 | default: |
| 4292 | break; |
| 4293 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4294 | rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req); |
| 4295 | return rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4296 | } |
| 4297 | |
| 4298 | /** |
| 4299 | * pm8001_chip_fw_flash_update_build - support the firmware update operation |
| 4300 | * @pm8001_ha: our hba card information. |
| 4301 | * @fw_flash_updata_info: firmware flash update param |
| 4302 | */ |
| 4303 | static int |
| 4304 | pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, |
| 4305 | void *fw_flash_updata_info, u32 tag) |
| 4306 | { |
| 4307 | struct fw_flash_Update_req payload; |
| 4308 | struct fw_flash_updata_info *info; |
| 4309 | struct inbound_queue_table *circularQ; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4310 | int ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4311 | u32 opc = OPC_INB_FW_FLASH_UPDATE; |
| 4312 | |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4313 | memset(&payload, 0, sizeof(struct fw_flash_Update_req)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4314 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4315 | info = fw_flash_updata_info; |
| 4316 | payload.tag = cpu_to_le32(tag); |
| 4317 | payload.cur_image_len = cpu_to_le32(info->cur_image_len); |
| 4318 | payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); |
| 4319 | payload.total_image_len = cpu_to_le32(info->total_image_len); |
| 4320 | payload.len = info->sgl.im_len.len ; |
| 4321 | payload.sgl_addr_lo = lower_32_bits(info->sgl.addr); |
| 4322 | payload.sgl_addr_hi = upper_32_bits(info->sgl.addr); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4323 | ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 4324 | return ret; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4325 | } |
| 4326 | |
| 4327 | static int |
| 4328 | pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, |
| 4329 | void *payload) |
| 4330 | { |
| 4331 | struct fw_flash_updata_info flash_update_info; |
| 4332 | struct fw_control_info *fw_control; |
| 4333 | struct fw_control_ex *fw_control_context; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4334 | int rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4335 | u32 tag; |
| 4336 | struct pm8001_ccb_info *ccb; |
| 4337 | void *buffer = NULL; |
| 4338 | dma_addr_t phys_addr; |
| 4339 | u32 phys_addr_hi; |
| 4340 | u32 phys_addr_lo; |
| 4341 | struct pm8001_ioctl_payload *ioctl_payload = payload; |
| 4342 | |
| 4343 | fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); |
| 4344 | fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0]; |
| 4345 | if (fw_control->len != 0) { |
| 4346 | if (pm8001_mem_alloc(pm8001_ha->pdev, |
| 4347 | (void **)&buffer, |
| 4348 | &phys_addr, |
| 4349 | &phys_addr_hi, |
| 4350 | &phys_addr_lo, |
| 4351 | fw_control->len, 0) != 0) { |
| 4352 | PM8001_FAIL_DBG(pm8001_ha, |
| 4353 | pm8001_printk("Mem alloc failure\n")); |
| 4354 | return -ENOMEM; |
| 4355 | } |
| 4356 | } |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4357 | memset(buffer, 0, fw_control->len); |
| 4358 | memcpy(buffer, fw_control->buffer, fw_control->len); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4359 | flash_update_info.sgl.addr = cpu_to_le64(phys_addr); |
| 4360 | flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); |
| 4361 | flash_update_info.sgl.im_len.e = 0; |
| 4362 | flash_update_info.cur_image_offset = fw_control->offset; |
| 4363 | flash_update_info.cur_image_len = fw_control->len; |
| 4364 | flash_update_info.total_image_len = fw_control->size; |
| 4365 | fw_control_context->fw_control = fw_control; |
| 4366 | fw_control_context->virtAddr = buffer; |
| 4367 | fw_control_context->len = fw_control->len; |
| 4368 | rc = pm8001_tag_alloc(pm8001_ha, &tag); |
| 4369 | if (rc) |
| 4370 | return rc; |
| 4371 | ccb = &pm8001_ha->ccb_info[tag]; |
| 4372 | ccb->fw_control_context = fw_control_context; |
| 4373 | ccb->ccb_tag = tag; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4374 | rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, |
| 4375 | tag); |
| 4376 | return rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4377 | } |
| 4378 | |
| 4379 | static int |
| 4380 | pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, |
| 4381 | struct pm8001_device *pm8001_dev, u32 state) |
| 4382 | { |
| 4383 | struct set_dev_state_req payload; |
| 4384 | struct inbound_queue_table *circularQ; |
| 4385 | struct pm8001_ccb_info *ccb; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4386 | int rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4387 | u32 tag; |
| 4388 | u32 opc = OPC_INB_SET_DEVICE_STATE; |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4389 | memset(&payload, 0, sizeof(payload)); |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4390 | rc = pm8001_tag_alloc(pm8001_ha, &tag); |
| 4391 | if (rc) |
| 4392 | return -1; |
| 4393 | ccb = &pm8001_ha->ccb_info[tag]; |
| 4394 | ccb->ccb_tag = tag; |
| 4395 | ccb->device = pm8001_dev; |
| 4396 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4397 | payload.tag = cpu_to_le32(tag); |
| 4398 | payload.device_id = cpu_to_le32(pm8001_dev->device_id); |
| 4399 | payload.nds = cpu_to_le32(state); |
jack_wang | 72d0baa | 2009-11-05 22:33:35 +0800 | [diff] [blame] | 4400 | rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 4401 | return rc; |
| 4402 | |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 4403 | } |
| 4404 | |
| 4405 | static int |
| 4406 | pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) |
| 4407 | { |
| 4408 | struct sas_re_initialization_req payload; |
| 4409 | struct inbound_queue_table *circularQ; |
| 4410 | struct pm8001_ccb_info *ccb; |
| 4411 | int rc; |
| 4412 | u32 tag; |
| 4413 | u32 opc = OPC_INB_SAS_RE_INITIALIZE; |
| 4414 | memset(&payload, 0, sizeof(payload)); |
| 4415 | rc = pm8001_tag_alloc(pm8001_ha, &tag); |
| 4416 | if (rc) |
| 4417 | return -1; |
| 4418 | ccb = &pm8001_ha->ccb_info[tag]; |
| 4419 | ccb->ccb_tag = tag; |
| 4420 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; |
| 4421 | payload.tag = cpu_to_le32(tag); |
| 4422 | payload.SSAHOLT = cpu_to_le32(0xd << 25); |
| 4423 | payload.sata_hol_tmo = cpu_to_le32(80); |
| 4424 | payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); |
| 4425 | rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); |
| 4426 | return rc; |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4427 | |
| 4428 | } |
| 4429 | |
| 4430 | const struct pm8001_dispatch pm8001_8001_dispatch = { |
| 4431 | .name = "pmc8001", |
| 4432 | .chip_init = pm8001_chip_init, |
| 4433 | .chip_soft_rst = pm8001_chip_soft_rst, |
| 4434 | .chip_rst = pm8001_hw_chip_rst, |
| 4435 | .chip_iounmap = pm8001_chip_iounmap, |
| 4436 | .isr = pm8001_chip_isr, |
| 4437 | .is_our_interupt = pm8001_chip_is_our_interupt, |
| 4438 | .isr_process_oq = process_oq, |
| 4439 | .interrupt_enable = pm8001_chip_interrupt_enable, |
| 4440 | .interrupt_disable = pm8001_chip_interrupt_disable, |
| 4441 | .make_prd = pm8001_chip_make_sg, |
| 4442 | .smp_req = pm8001_chip_smp_req, |
| 4443 | .ssp_io_req = pm8001_chip_ssp_io_req, |
| 4444 | .sata_req = pm8001_chip_sata_req, |
| 4445 | .phy_start_req = pm8001_chip_phy_start_req, |
| 4446 | .phy_stop_req = pm8001_chip_phy_stop_req, |
| 4447 | .reg_dev_req = pm8001_chip_reg_dev_req, |
| 4448 | .dereg_dev_req = pm8001_chip_dereg_dev_req, |
| 4449 | .phy_ctl_req = pm8001_chip_phy_ctl_req, |
| 4450 | .task_abort = pm8001_chip_abort_task, |
| 4451 | .ssp_tm_req = pm8001_chip_ssp_tm_req, |
| 4452 | .get_nvmd_req = pm8001_chip_get_nvmd_req, |
| 4453 | .set_nvmd_req = pm8001_chip_set_nvmd_req, |
| 4454 | .fw_flash_update_req = pm8001_chip_fw_flash_update_req, |
| 4455 | .set_dev_state_req = pm8001_chip_set_dev_state_req, |
jack_wang | d0b6804 | 2009-11-05 22:32:31 +0800 | [diff] [blame] | 4456 | .sas_re_init_req = pm8001_chip_sas_re_initialization, |
jack wang | dbf9bfe | 2009-10-14 16:19:21 +0800 | [diff] [blame] | 4457 | }; |
| 4458 | |