blob: fd7fb45818491b7fc6c206bb7f1958cc9aa38183 [file] [log] [blame]
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x_reg.h: Broadcom Everest network driver.
2 *
Ariel Elior85b26ea2012-01-26 06:01:54 +00003 * Copyright (c) 2007-2012 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
Eilon Greenstein33471622008-08-13 15:59:08 -07009 * The registers description starts with the register Access type followed
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +000021#ifndef BNX2X_REG_H
22#define BNX2X_REG_H
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020023
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000024#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30/* [RW 1] Initiate the ATC array - reset all the valid bits */
31#define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32/* [R 1] ATC initalization done */
33#define ATC_REG_ATC_INIT_DONE 0x1100bc
34/* [RC 6] Interrupt register #0 read clear */
Vladislav Zolotarov8736c822011-07-21 07:58:36 +000035#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36/* [RW 5] Parity mask register #0 read/write */
37#define ATC_REG_ATC_PRTY_MASK 0x1101d8
38/* [RC 5] Parity register #0 read clear */
39#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000040/* [RW 19] Interrupt mask register #0 read/write */
41#define BRB1_REG_BRB1_INT_MASK 0x60128
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020042/* [R 19] Interrupt register #0 read */
43#define BRB1_REG_BRB1_INT_STS 0x6011c
44/* [RW 4] Parity mask register #0 read/write */
45#define BRB1_REG_BRB1_PRTY_MASK 0x60138
Eliezer Tamirf1410642008-02-28 11:51:50 -080046/* [R 4] Parity register #0 read */
47#define BRB1_REG_BRB1_PRTY_STS 0x6012c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +000048/* [RC 4] Parity register #0 read clear */
49#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020050/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000051 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
52 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
53 * following reset the first rbc access to this reg must be write; there can
54 * be no more rbc writes after the first one; there can be any number of rbc
55 * read following the first write; rbc access not following these rules will
56 * result in hang condition. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020057#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000058/* [RW 10] The number of free blocks below which the full signal to class 0
59 * is asserted */
60#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
Yaniv Rosner9380bb92011-06-14 01:34:07 +000061#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
62/* [RW 11] The number of free blocks above which the full signal to class 0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000063 * is de-asserted */
64#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
Yaniv Rosner9380bb92011-06-14 01:34:07 +000065#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
66/* [RW 11] The number of free blocks below which the full signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000067 * is asserted */
68#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
Yaniv Rosner9380bb92011-06-14 01:34:07 +000069#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
70/* [RW 11] The number of free blocks above which the full signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000071 * is de-asserted */
72#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
Yaniv Rosner9380bb92011-06-14 01:34:07 +000073#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
74/* [RW 11] The number of free blocks below which the full signal to the LB
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000075 * port is asserted */
76#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
77/* [RW 10] The number of free blocks above which the full signal to the LB
78 * port is de-asserted */
79#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
Eilon Greenstein1c063282009-02-12 08:36:43 +000080/* [RW 10] The number of free blocks above which the High_llfc signal to
81 interface #n is de-asserted. */
82#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
83/* [RW 10] The number of free blocks below which the High_llfc signal to
84 interface #n is asserted. */
85#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
Yaniv Rosner9380bb92011-06-14 01:34:07 +000086/* [RW 11] The number of blocks guarantied for the LB port */
87#define BRB1_REG_LB_GUARANTIED 0x601ec
88/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
89 * before signaling XON. */
90#define BRB1_REG_LB_GUARANTIED_HYST 0x60264
91/* [RW 24] LL RAM data. */
92#define BRB1_REG_LL_RAM 0x61000
Eilon Greenstein1c063282009-02-12 08:36:43 +000093/* [RW 10] The number of free blocks above which the Low_llfc signal to
94 interface #n is de-asserted. */
95#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
96/* [RW 10] The number of free blocks below which the Low_llfc signal to
97 interface #n is asserted. */
98#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
Yaniv Rosner9380bb92011-06-14 01:34:07 +000099/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
100 * register is applicable only when per_class_guaranty_mode is set. */
101#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
102/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
103 * 1 before signaling XON. The register is applicable only when
104 * per_class_guaranty_mode is set. */
105#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
106/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
107 * register is applicable only when per_class_guaranty_mode is set. */
108#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
109/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
110 * before signaling XON. The register is applicable only when
111 * per_class_guaranty_mode is set. */
112#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
113/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
114 * is applicable only when per_class_guaranty_mode is set. */
115#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
116/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
117 * 1 before signaling XON. The register is applicable only when
118 * per_class_guaranty_mode is set. */
119#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
120/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
121 * register is applicable only when per_class_guaranty_mode is set. */
122#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
123/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
124 * 1 before signaling XON. The register is applicable only when
125 * per_class_guaranty_mode is set. */
126#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
127/* [RW 11] The number of blocks guarantied for the MAC port. The register is
128 * applicable only when per_class_guaranty_mode is reset. */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000129#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
130#define BRB1_REG_MAC_GUARANTIED_1 0x60240
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200131/* [R 24] The number of full blocks. */
132#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
133/* [ST 32] The number of cycles that the write_full signal towards MAC #0
134 was asserted. */
135#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
136#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200137#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
138/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
139 asserted. */
140#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
141#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000142/* [RW 10] The number of free blocks below which the pause signal to class 0
143 * is asserted */
144#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000145#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
146/* [RW 11] The number of free blocks above which the pause signal to class 0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000147 * is de-asserted */
148#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000149#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
150/* [RW 11] The number of free blocks below which the pause signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000151 * is asserted */
152#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000153#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
154/* [RW 11] The number of free blocks above which the pause signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000155 * is de-asserted */
156#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000157#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000158/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200159#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
160#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
161/* [RW 10] Write client 0: Assert pause threshold. */
162#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
Yaniv Rosner866ceda2011-11-28 00:49:45 +0000163/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
164 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
165 * mode). 1=per-class guaranty mode (new mode). */
166#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268
167/* [R 24] The number of full blocks occpied by port. */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700168#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200169/* [RW 1] Reset the design by software. */
170#define BRB1_REG_SOFT_RESET 0x600dc
171/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
172#define CCM_REG_CAM_OCCUP 0xd0188
173/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
174 acknowledge output is deasserted; all other signals are treated as usual;
175 if 1 - normal activity. */
176#define CCM_REG_CCM_CFC_IFEN 0xd003c
177/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
178 disregarded; valid is deasserted; all other signals are treated as usual;
179 if 1 - normal activity. */
180#define CCM_REG_CCM_CQM_IFEN 0xd000c
181/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
182 Otherwise 0 is inserted. */
183#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
184/* [RW 11] Interrupt mask register #0 read/write */
185#define CCM_REG_CCM_INT_MASK 0xd01e4
186/* [R 11] Interrupt register #0 read */
187#define CCM_REG_CCM_INT_STS 0xd01d8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000188/* [RW 27] Parity mask register #0 read/write */
189#define CCM_REG_CCM_PRTY_MASK 0xd01f4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700190/* [R 27] Parity register #0 read */
191#define CCM_REG_CCM_PRTY_STS 0xd01e8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000192/* [RC 27] Parity register #0 read clear */
193#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200194/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
195 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
196 Is used to determine the number of the AG context REG-pairs written back;
197 when the input message Reg1WbFlg isn't set. */
198#define CCM_REG_CCM_REG0_SZ 0xd00c4
199/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
200 disregarded; valid is deasserted; all other signals are treated as usual;
201 if 1 - normal activity. */
202#define CCM_REG_CCM_STORM0_IFEN 0xd0004
203/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
204 disregarded; valid is deasserted; all other signals are treated as usual;
205 if 1 - normal activity. */
206#define CCM_REG_CCM_STORM1_IFEN 0xd0008
207/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
208 disregarded; valid output is deasserted; all other signals are treated as
209 usual; if 1 - normal activity. */
210#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
211/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
212 are disregarded; all other signals are treated as usual; if 1 - normal
213 activity. */
214#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
215/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
216 disregarded; valid output is deasserted; all other signals are treated as
217 usual; if 1 - normal activity. */
218#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
219/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
220 input is disregarded; all other signals are treated as usual; if 1 -
221 normal activity. */
222#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
223/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
224 the initial credit value; read returns the current value of the credit
225 counter. Must be initialized to 1 at start-up. */
226#define CCM_REG_CFC_INIT_CRD 0xd0204
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300227/* [RW 2] Auxiliary counter flag Q number 1. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200228#define CCM_REG_CNT_AUX1_Q 0xd00c8
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300229/* [RW 2] Auxiliary counter flag Q number 2. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200230#define CCM_REG_CNT_AUX2_Q 0xd00cc
231/* [RW 28] The CM header value for QM request (primary). */
232#define CCM_REG_CQM_CCM_HDR_P 0xd008c
233/* [RW 28] The CM header value for QM request (secondary). */
234#define CCM_REG_CQM_CCM_HDR_S 0xd0090
235/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
236 acknowledge output is deasserted; all other signals are treated as usual;
237 if 1 - normal activity. */
238#define CCM_REG_CQM_CCM_IFEN 0xd0014
239/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
240 the initial credit value; read returns the current value of the credit
241 counter. Must be initialized to 32 at start-up. */
242#define CCM_REG_CQM_INIT_CRD 0xd020c
243/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
244 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
245 prioritised); 2 stands for weight 2; tc. */
246#define CCM_REG_CQM_P_WEIGHT 0xd00b8
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800247/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
249 prioritised); 2 stands for weight 2; tc. */
250#define CCM_REG_CQM_S_WEIGHT 0xd00bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200251/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
252 acknowledge output is deasserted; all other signals are treated as usual;
253 if 1 - normal activity. */
254#define CCM_REG_CSDM_IFEN 0xd0018
255/* [RC 1] Set when the message length mismatch (relative to last indication)
256 at the SDM interface is detected. */
257#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800258/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
259 weight 8 (the most prioritised); 1 stands for weight 1(least
260 prioritised); 2 stands for weight 2; tc. */
261#define CCM_REG_CSDM_WEIGHT 0xd00b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200262/* [RW 28] The CM header for QM formatting in case of an error in the QM
263 inputs. */
264#define CCM_REG_ERR_CCM_HDR 0xd0094
265/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
266#define CCM_REG_ERR_EVNT_ID 0xd0098
267/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
268 writes the initial credit value; read returns the current value of the
269 credit counter. Must be initialized to 64 at start-up. */
270#define CCM_REG_FIC0_INIT_CRD 0xd0210
271/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
272 writes the initial credit value; read returns the current value of the
273 credit counter. Must be initialized to 64 at start-up. */
274#define CCM_REG_FIC1_INIT_CRD 0xd0214
275/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
276 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
277 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
278 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
279 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
280#define CCM_REG_GR_ARB_TYPE 0xd015c
281/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
282 highest priority is 3. It is supposed; that the Store channel priority is
283 the compliment to 4 of the rest priorities - Aggregation channel; Load
284 (FIC0) channel and Load (FIC1). */
285#define CCM_REG_GR_LD0_PR 0xd0164
286/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
287 highest priority is 3. It is supposed; that the Store channel priority is
288 the compliment to 4 of the rest priorities - Aggregation channel; Load
289 (FIC0) channel and Load (FIC1). */
290#define CCM_REG_GR_LD1_PR 0xd0168
291/* [RW 2] General flags index. */
292#define CCM_REG_INV_DONE_Q 0xd0108
293/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
294 context and sent to STORM; for a specific connection type. The double
295 REG-pairs are used in order to align to STORM context row size of 128
296 bits. The offset of these data in the STORM context is always 0. Index
297 _(0..15) stands for the connection type (one of 16). */
298#define CCM_REG_N_SM_CTX_LD_0 0xd004c
299#define CCM_REG_N_SM_CTX_LD_1 0xd0050
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200300#define CCM_REG_N_SM_CTX_LD_2 0xd0054
301#define CCM_REG_N_SM_CTX_LD_3 0xd0058
302#define CCM_REG_N_SM_CTX_LD_4 0xd005c
303/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
304 acknowledge output is deasserted; all other signals are treated as usual;
305 if 1 - normal activity. */
306#define CCM_REG_PBF_IFEN 0xd0028
307/* [RC 1] Set when the message length mismatch (relative to last indication)
308 at the pbf interface is detected. */
309#define CCM_REG_PBF_LENGTH_MIS 0xd0180
310/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
311 weight 8 (the most prioritised); 1 stands for weight 1(least
312 prioritised); 2 stands for weight 2; tc. */
313#define CCM_REG_PBF_WEIGHT 0xd00ac
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200314#define CCM_REG_PHYS_QNUM1_0 0xd0134
315#define CCM_REG_PHYS_QNUM1_1 0xd0138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200316#define CCM_REG_PHYS_QNUM2_0 0xd013c
317#define CCM_REG_PHYS_QNUM2_1 0xd0140
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200318#define CCM_REG_PHYS_QNUM3_0 0xd0144
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700319#define CCM_REG_PHYS_QNUM3_1 0xd0148
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200320#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
321#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200322#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
323#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200324#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700325#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
326#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
327#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200328/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
329 disregarded; acknowledge output is deasserted; all other signals are
330 treated as usual; if 1 - normal activity. */
331#define CCM_REG_STORM_CCM_IFEN 0xd0010
332/* [RC 1] Set when the message length mismatch (relative to last indication)
333 at the STORM interface is detected. */
334#define CCM_REG_STORM_LENGTH_MIS 0xd016c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800335/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
336 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
337 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
338 tc. */
339#define CCM_REG_STORM_WEIGHT 0xd009c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200340/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
341 disregarded; acknowledge output is deasserted; all other signals are
342 treated as usual; if 1 - normal activity. */
343#define CCM_REG_TSEM_IFEN 0xd001c
344/* [RC 1] Set when the message length mismatch (relative to last indication)
345 at the tsem interface is detected. */
346#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
347/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
348 weight 8 (the most prioritised); 1 stands for weight 1(least
349 prioritised); 2 stands for weight 2; tc. */
350#define CCM_REG_TSEM_WEIGHT 0xd00a0
351/* [RW 1] Input usem Interface enable. If 0 - the valid input is
352 disregarded; acknowledge output is deasserted; all other signals are
353 treated as usual; if 1 - normal activity. */
354#define CCM_REG_USEM_IFEN 0xd0024
355/* [RC 1] Set when message length mismatch (relative to last indication) at
356 the usem interface is detected. */
357#define CCM_REG_USEM_LENGTH_MIS 0xd017c
358/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
359 weight 8 (the most prioritised); 1 stands for weight 1(least
360 prioritised); 2 stands for weight 2; tc. */
361#define CCM_REG_USEM_WEIGHT 0xd00a8
362/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
363 disregarded; acknowledge output is deasserted; all other signals are
364 treated as usual; if 1 - normal activity. */
365#define CCM_REG_XSEM_IFEN 0xd0020
366/* [RC 1] Set when the message length mismatch (relative to last indication)
367 at the xsem interface is detected. */
368#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
369/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
370 weight 8 (the most prioritised); 1 stands for weight 1(least
371 prioritised); 2 stands for weight 2; tc. */
372#define CCM_REG_XSEM_WEIGHT 0xd00a4
373/* [RW 19] Indirect access to the descriptor table of the XX protection
374 mechanism. The fields are: [5:0] - message length; [12:6] - message
375 pointer; 18:13] - next pointer. */
376#define CCM_REG_XX_DESCR_TABLE 0xd0300
Vladislav Zolotarov79616892011-07-21 07:58:54 +0000377#define CCM_REG_XX_DESCR_TABLE_SIZE 24
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200378/* [R 7] Used to read the value of XX protection Free counter. */
379#define CCM_REG_XX_FREE 0xd0184
380/* [RW 6] Initial value for the credit counter; responsible for fulfilling
381 of the Input Stage XX protection buffer by the XX protection pending
382 messages. Max credit available - 127. Write writes the initial credit
383 value; read returns the current value of the credit counter. Must be
384 initialized to maximum XX protected message size - 2 at start-up. */
385#define CCM_REG_XX_INIT_CRD 0xd0220
386/* [RW 7] The maximum number of pending messages; which may be stored in XX
387 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
388 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
389 counter. */
390#define CCM_REG_XX_MSG_NUM 0xd0224
391/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
392#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
393/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
394 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
395 header pointer. */
396#define CCM_REG_XX_TABLE 0xd0280
397#define CDU_REG_CDU_CHK_MASK0 0x101000
398#define CDU_REG_CDU_CHK_MASK1 0x101004
399#define CDU_REG_CDU_CONTROL0 0x101008
400#define CDU_REG_CDU_DEBUG 0x101010
401#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
402/* [RW 7] Interrupt mask register #0 read/write */
403#define CDU_REG_CDU_INT_MASK 0x10103c
404/* [R 7] Interrupt register #0 read */
405#define CDU_REG_CDU_INT_STS 0x101030
406/* [RW 5] Parity mask register #0 read/write */
407#define CDU_REG_CDU_PRTY_MASK 0x10104c
Eliezer Tamirf1410642008-02-28 11:51:50 -0800408/* [R 5] Parity register #0 read */
409#define CDU_REG_CDU_PRTY_STS 0x101040
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000410/* [RC 5] Parity register #0 read clear */
411#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200412/* [RC 32] logging of error data in case of a CDU load error:
413 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
414 ype_error; ctual_active; ctual_compressed_context}; */
415#define CDU_REG_ERROR_DATA 0x101014
416/* [WB 216] L1TT ram access. each entry has the following format :
417 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
418 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
419#define CDU_REG_L1TT 0x101800
420/* [WB 24] MATT ram access. each entry has the following
421 format:{RegionLength[11:0]; egionOffset[11:0]} */
422#define CDU_REG_MATT 0x101100
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700423/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
424#define CDU_REG_MF_MODE 0x101050
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200425/* [R 1] indication the initializing the activity counter by the hardware
426 was done. */
427#define CFC_REG_AC_INIT_DONE 0x104078
428/* [RW 13] activity counter ram access */
429#define CFC_REG_ACTIVITY_COUNTER 0x104400
430#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
431/* [R 1] indication the initializing the cams by the hardware was done. */
432#define CFC_REG_CAM_INIT_DONE 0x10407c
433/* [RW 2] Interrupt mask register #0 read/write */
434#define CFC_REG_CFC_INT_MASK 0x104108
435/* [R 2] Interrupt register #0 read */
436#define CFC_REG_CFC_INT_STS 0x1040fc
437/* [RC 2] Interrupt register #0 read clear */
438#define CFC_REG_CFC_INT_STS_CLR 0x104100
439/* [RW 4] Parity mask register #0 read/write */
440#define CFC_REG_CFC_PRTY_MASK 0x104118
Eliezer Tamirf1410642008-02-28 11:51:50 -0800441/* [R 4] Parity register #0 read */
442#define CFC_REG_CFC_PRTY_STS 0x10410c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000443/* [RC 4] Parity register #0 read clear */
444#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200445/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
446#define CFC_REG_CID_CAM 0x104800
447#define CFC_REG_CONTROL0 0x104028
448#define CFC_REG_DEBUG0 0x104050
449/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
450 vector) whether the cfc should be disabled upon it */
451#define CFC_REG_DISABLE_ON_ERROR 0x104044
452/* [RC 14] CFC error vector. when the CFC detects an internal error it will
453 set one of these bits. the bit description can be found in CFC
454 specifications */
455#define CFC_REG_ERROR_VECTOR 0x10403c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800456/* [WB 93] LCID info ram access */
457#define CFC_REG_INFO_RAM 0x105000
458#define CFC_REG_INFO_RAM_SIZE 1024
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200459#define CFC_REG_INIT_REG 0x10404c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800460#define CFC_REG_INTERFACES 0x104058
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200461/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
462 field allows changing the priorities of the weighted-round-robin arbiter
463 which selects which CFC load client should be served next */
464#define CFC_REG_LCREQ_WEIGHTS 0x104084
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700465/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
466#define CFC_REG_LINK_LIST 0x104c00
467#define CFC_REG_LINK_LIST_SIZE 256
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200468/* [R 1] indication the initializing the link list by the hardware was done. */
469#define CFC_REG_LL_INIT_DONE 0x104074
470/* [R 9] Number of allocated LCIDs which are at empty state */
471#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
472/* [R 9] Number of Arriving LCIDs in Link List Block */
473#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300474#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200475/* [R 9] Number of Leaving LCIDs in Link List Block */
476#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000477#define CFC_REG_WEAK_ENABLE_PF 0x104124
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200478/* [RW 8] The event id for aggregated interrupt 0 */
479#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700480#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
481#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
482#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
483#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
484#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
485#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
486#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700487#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700488#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700489#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
Eilon Greensteinca003922009-08-12 22:53:28 -0700490#define CSDM_REG_AGG_INT_EVENT_5 0xc204c
491#define CSDM_REG_AGG_INT_EVENT_6 0xc2050
492#define CSDM_REG_AGG_INT_EVENT_7 0xc2054
493#define CSDM_REG_AGG_INT_EVENT_8 0xc2058
494#define CSDM_REG_AGG_INT_EVENT_9 0xc205c
495/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
496 or auto-mask-mode (1) */
497#define CSDM_REG_AGG_INT_MODE_10 0xc21e0
498#define CSDM_REG_AGG_INT_MODE_11 0xc21e4
499#define CSDM_REG_AGG_INT_MODE_12 0xc21e8
500#define CSDM_REG_AGG_INT_MODE_13 0xc21ec
501#define CSDM_REG_AGG_INT_MODE_14 0xc21f0
502#define CSDM_REG_AGG_INT_MODE_15 0xc21f4
503#define CSDM_REG_AGG_INT_MODE_16 0xc21f8
504#define CSDM_REG_AGG_INT_MODE_6 0xc21d0
505#define CSDM_REG_AGG_INT_MODE_7 0xc21d4
506#define CSDM_REG_AGG_INT_MODE_8 0xc21d8
507#define CSDM_REG_AGG_INT_MODE_9 0xc21dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200508/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
509#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300510/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200511#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300512/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200513#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300514/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200515#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300516/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200517#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
518/* [RW 13] The start address in the internal RAM for the completion
519 counters. */
520#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
521/* [RW 32] Interrupt mask register #0 read/write */
522#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
523#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700524/* [R 32] Interrupt register #0 read */
525#define CSDM_REG_CSDM_INT_STS_0 0xc2290
526#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200527/* [RW 11] Parity mask register #0 read/write */
528#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
Eliezer Tamirf1410642008-02-28 11:51:50 -0800529/* [R 11] Parity register #0 read */
530#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000531/* [RC 11] Parity register #0 read clear */
532#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200533#define CSDM_REG_ENABLE_IN1 0xc2238
534#define CSDM_REG_ENABLE_IN2 0xc223c
535#define CSDM_REG_ENABLE_OUT1 0xc2240
536#define CSDM_REG_ENABLE_OUT2 0xc2244
537/* [RW 4] The initial number of messages that can be sent to the pxp control
538 interface without receiving any ACK. */
539#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
540/* [ST 32] The number of ACK after placement messages received */
541#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
542/* [ST 32] The number of packet end messages received from the parser */
543#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
544/* [ST 32] The number of requests received from the pxp async if */
545#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
546/* [ST 32] The number of commands received in queue 0 */
547#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
548/* [ST 32] The number of commands received in queue 10 */
549#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
550/* [ST 32] The number of commands received in queue 11 */
551#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
552/* [ST 32] The number of commands received in queue 1 */
553#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
554/* [ST 32] The number of commands received in queue 3 */
555#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
556/* [ST 32] The number of commands received in queue 4 */
557#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
558/* [ST 32] The number of commands received in queue 5 */
559#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
560/* [ST 32] The number of commands received in queue 6 */
561#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
562/* [ST 32] The number of commands received in queue 7 */
563#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
564/* [ST 32] The number of commands received in queue 8 */
565#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
566/* [ST 32] The number of commands received in queue 9 */
567#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
568/* [RW 13] The start address in the internal RAM for queue counters */
569#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
570/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
571#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
572/* [R 1] parser fifo empty in sdm_sync block */
573#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
574/* [R 1] parser serial fifo empty in sdm_sync block */
575#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
576/* [RW 32] Tick for timer counter. Applicable only when
577 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
578#define CSDM_REG_TIMER_TICK 0xc2000
579/* [RW 5] The number of time_slots in the arbitration cycle */
580#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
581/* [RW 3] The source that is associated with arbitration element 0. Source
582 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
583 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
584#define CSEM_REG_ARB_ELEMENT0 0x200020
585/* [RW 3] The source that is associated with arbitration element 1. Source
586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
587 sleeping thread with priority 1; 4- sleeping thread with priority 2.
588 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
589#define CSEM_REG_ARB_ELEMENT1 0x200024
590/* [RW 3] The source that is associated with arbitration element 2. Source
591 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
592 sleeping thread with priority 1; 4- sleeping thread with priority 2.
593 Could not be equal to register ~csem_registers_arb_element0.arb_element0
594 and ~csem_registers_arb_element1.arb_element1 */
595#define CSEM_REG_ARB_ELEMENT2 0x200028
596/* [RW 3] The source that is associated with arbitration element 3. Source
597 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
598 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
599 not be equal to register ~csem_registers_arb_element0.arb_element0 and
600 ~csem_registers_arb_element1.arb_element1 and
601 ~csem_registers_arb_element2.arb_element2 */
602#define CSEM_REG_ARB_ELEMENT3 0x20002c
603/* [RW 3] The source that is associated with arbitration element 4. Source
604 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
605 sleeping thread with priority 1; 4- sleeping thread with priority 2.
606 Could not be equal to register ~csem_registers_arb_element0.arb_element0
607 and ~csem_registers_arb_element1.arb_element1 and
608 ~csem_registers_arb_element2.arb_element2 and
609 ~csem_registers_arb_element3.arb_element3 */
610#define CSEM_REG_ARB_ELEMENT4 0x200030
611/* [RW 32] Interrupt mask register #0 read/write */
612#define CSEM_REG_CSEM_INT_MASK_0 0x200110
613#define CSEM_REG_CSEM_INT_MASK_1 0x200120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700614/* [R 32] Interrupt register #0 read */
615#define CSEM_REG_CSEM_INT_STS_0 0x200104
616#define CSEM_REG_CSEM_INT_STS_1 0x200114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200617/* [RW 32] Parity mask register #0 read/write */
618#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
619#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
Eliezer Tamirf1410642008-02-28 11:51:50 -0800620/* [R 32] Parity register #0 read */
621#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
622#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000623/* [RC 32] Parity register #0 read clear */
624#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
625#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200626#define CSEM_REG_ENABLE_IN 0x2000a4
627#define CSEM_REG_ENABLE_OUT 0x2000a8
628/* [RW 32] This address space contains all registers and memories that are
629 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700630 appendix B. In order to access the sem_fast registers the base address
631 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200632#define CSEM_REG_FAST_MEMORY 0x220000
633/* [RW 1] Disables input messages from FIC0 May be updated during run_time
634 by the microcode */
635#define CSEM_REG_FIC0_DISABLE 0x200224
636/* [RW 1] Disables input messages from FIC1 May be updated during run_time
637 by the microcode */
638#define CSEM_REG_FIC1_DISABLE 0x200234
639/* [RW 15] Interrupt table Read and write access to it is not possible in
640 the middle of the work */
641#define CSEM_REG_INT_TABLE 0x200400
642/* [ST 24] Statistics register. The number of messages that entered through
643 FIC0 */
644#define CSEM_REG_MSG_NUM_FIC0 0x200000
645/* [ST 24] Statistics register. The number of messages that entered through
646 FIC1 */
647#define CSEM_REG_MSG_NUM_FIC1 0x200004
648/* [ST 24] Statistics register. The number of messages that were sent to
649 FOC0 */
650#define CSEM_REG_MSG_NUM_FOC0 0x200008
651/* [ST 24] Statistics register. The number of messages that were sent to
652 FOC1 */
653#define CSEM_REG_MSG_NUM_FOC1 0x20000c
654/* [ST 24] Statistics register. The number of messages that were sent to
655 FOC2 */
656#define CSEM_REG_MSG_NUM_FOC2 0x200010
657/* [ST 24] Statistics register. The number of messages that were sent to
658 FOC3 */
659#define CSEM_REG_MSG_NUM_FOC3 0x200014
660/* [RW 1] Disables input messages from the passive buffer May be updated
661 during run_time by the microcode */
662#define CSEM_REG_PAS_DISABLE 0x20024c
663/* [WB 128] Debug only. Passive buffer memory */
664#define CSEM_REG_PASSIVE_BUFFER 0x202000
665/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
666#define CSEM_REG_PRAM 0x240000
667/* [R 16] Valid sleeping threads indication have bit per thread */
668#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
669/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
670#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
671/* [RW 16] List of free threads . There is a bit per thread. */
672#define CSEM_REG_THREADS_LIST 0x2002e4
673/* [RW 3] The arbitration scheme of time_slot 0 */
674#define CSEM_REG_TS_0_AS 0x200038
675/* [RW 3] The arbitration scheme of time_slot 10 */
676#define CSEM_REG_TS_10_AS 0x200060
677/* [RW 3] The arbitration scheme of time_slot 11 */
678#define CSEM_REG_TS_11_AS 0x200064
679/* [RW 3] The arbitration scheme of time_slot 12 */
680#define CSEM_REG_TS_12_AS 0x200068
681/* [RW 3] The arbitration scheme of time_slot 13 */
682#define CSEM_REG_TS_13_AS 0x20006c
683/* [RW 3] The arbitration scheme of time_slot 14 */
684#define CSEM_REG_TS_14_AS 0x200070
685/* [RW 3] The arbitration scheme of time_slot 15 */
686#define CSEM_REG_TS_15_AS 0x200074
687/* [RW 3] The arbitration scheme of time_slot 16 */
688#define CSEM_REG_TS_16_AS 0x200078
689/* [RW 3] The arbitration scheme of time_slot 17 */
690#define CSEM_REG_TS_17_AS 0x20007c
691/* [RW 3] The arbitration scheme of time_slot 18 */
692#define CSEM_REG_TS_18_AS 0x200080
693/* [RW 3] The arbitration scheme of time_slot 1 */
694#define CSEM_REG_TS_1_AS 0x20003c
695/* [RW 3] The arbitration scheme of time_slot 2 */
696#define CSEM_REG_TS_2_AS 0x200040
697/* [RW 3] The arbitration scheme of time_slot 3 */
698#define CSEM_REG_TS_3_AS 0x200044
699/* [RW 3] The arbitration scheme of time_slot 4 */
700#define CSEM_REG_TS_4_AS 0x200048
701/* [RW 3] The arbitration scheme of time_slot 5 */
702#define CSEM_REG_TS_5_AS 0x20004c
703/* [RW 3] The arbitration scheme of time_slot 6 */
704#define CSEM_REG_TS_6_AS 0x200050
705/* [RW 3] The arbitration scheme of time_slot 7 */
706#define CSEM_REG_TS_7_AS 0x200054
707/* [RW 3] The arbitration scheme of time_slot 8 */
708#define CSEM_REG_TS_8_AS 0x200058
709/* [RW 3] The arbitration scheme of time_slot 9 */
710#define CSEM_REG_TS_9_AS 0x20005c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000711/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
712 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
713#define CSEM_REG_VFPF_ERR_NUM 0x200380
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200714/* [RW 1] Parity mask register #0 read/write */
715#define DBG_REG_DBG_PRTY_MASK 0xc0a8
Eliezer Tamirf1410642008-02-28 11:51:50 -0800716/* [R 1] Parity register #0 read */
717#define DBG_REG_DBG_PRTY_STS 0xc09c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000718/* [RC 1] Parity register #0 read clear */
719#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000720/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
721 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
722 * 4.Completion function=0; 5.Error handling=0 */
723#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200724/* [RW 32] Commands memory. The address to command X; row Y is to calculated
725 as 14*X+Y. */
726#define DMAE_REG_CMD_MEM 0x102400
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700727#define DMAE_REG_CMD_MEM_SIZE 224
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200728/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
729 initial value is all ones. */
730#define DMAE_REG_CRC16C_INIT 0x10201c
731/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
732 CRC-16 T10 initial value is all ones. */
733#define DMAE_REG_CRC16T10_INIT 0x102020
734/* [RW 2] Interrupt mask register #0 read/write */
735#define DMAE_REG_DMAE_INT_MASK 0x102054
736/* [RW 4] Parity mask register #0 read/write */
737#define DMAE_REG_DMAE_PRTY_MASK 0x102064
Eliezer Tamirf1410642008-02-28 11:51:50 -0800738/* [R 4] Parity register #0 read */
739#define DMAE_REG_DMAE_PRTY_STS 0x102058
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000740/* [RC 4] Parity register #0 read clear */
741#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200742/* [RW 1] Command 0 go. */
743#define DMAE_REG_GO_C0 0x102080
744/* [RW 1] Command 1 go. */
745#define DMAE_REG_GO_C1 0x102084
746/* [RW 1] Command 10 go. */
747#define DMAE_REG_GO_C10 0x102088
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200748/* [RW 1] Command 11 go. */
749#define DMAE_REG_GO_C11 0x10208c
750/* [RW 1] Command 12 go. */
751#define DMAE_REG_GO_C12 0x102090
752/* [RW 1] Command 13 go. */
753#define DMAE_REG_GO_C13 0x102094
754/* [RW 1] Command 14 go. */
755#define DMAE_REG_GO_C14 0x102098
756/* [RW 1] Command 15 go. */
757#define DMAE_REG_GO_C15 0x10209c
758/* [RW 1] Command 2 go. */
759#define DMAE_REG_GO_C2 0x1020a0
760/* [RW 1] Command 3 go. */
761#define DMAE_REG_GO_C3 0x1020a4
762/* [RW 1] Command 4 go. */
763#define DMAE_REG_GO_C4 0x1020a8
764/* [RW 1] Command 5 go. */
765#define DMAE_REG_GO_C5 0x1020ac
766/* [RW 1] Command 6 go. */
767#define DMAE_REG_GO_C6 0x1020b0
768/* [RW 1] Command 7 go. */
769#define DMAE_REG_GO_C7 0x1020b4
770/* [RW 1] Command 8 go. */
771#define DMAE_REG_GO_C8 0x1020b8
772/* [RW 1] Command 9 go. */
773#define DMAE_REG_GO_C9 0x1020bc
774/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
775 input is disregarded; valid is deasserted; all other signals are treated
776 as usual; if 1 - normal activity. */
777#define DMAE_REG_GRC_IFEN 0x102008
778/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
779 acknowledge input is disregarded; valid is deasserted; full is asserted;
780 all other signals are treated as usual; if 1 - normal activity. */
781#define DMAE_REG_PCI_IFEN 0x102004
782/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
783 initial value to the credit counter; related to the address. Read returns
784 the current value of the counter. */
785#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
786/* [RW 8] Aggregation command. */
787#define DORQ_REG_AGG_CMD0 0x170060
788/* [RW 8] Aggregation command. */
789#define DORQ_REG_AGG_CMD1 0x170064
790/* [RW 8] Aggregation command. */
791#define DORQ_REG_AGG_CMD2 0x170068
792/* [RW 8] Aggregation command. */
793#define DORQ_REG_AGG_CMD3 0x17006c
794/* [RW 28] UCM Header. */
795#define DORQ_REG_CMHEAD_RX 0x170050
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700796/* [RW 32] Doorbell address for RBC doorbells (function 0). */
797#define DORQ_REG_DB_ADDR0 0x17008c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200798/* [RW 5] Interrupt mask register #0 read/write */
799#define DORQ_REG_DORQ_INT_MASK 0x170180
800/* [R 5] Interrupt register #0 read */
801#define DORQ_REG_DORQ_INT_STS 0x170174
802/* [RC 5] Interrupt register #0 read clear */
803#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
804/* [RW 2] Parity mask register #0 read/write */
805#define DORQ_REG_DORQ_PRTY_MASK 0x170190
Eliezer Tamirf1410642008-02-28 11:51:50 -0800806/* [R 2] Parity register #0 read */
807#define DORQ_REG_DORQ_PRTY_STS 0x170184
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000808/* [RC 2] Parity register #0 read clear */
809#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200810/* [RW 8] The address to write the DPM CID to STORM. */
811#define DORQ_REG_DPM_CID_ADDR 0x170044
812/* [RW 5] The DPM mode CID extraction offset. */
813#define DORQ_REG_DPM_CID_OFST 0x170030
814/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
815#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
816/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
817#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
818/* [R 13] Current value of the DQ FIFO fill level according to following
819 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
820 doorbell. */
821#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
822/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
823 equal to full threshold; reset on full clear. */
824#define DORQ_REG_DQ_FULL_ST 0x1700c0
825/* [RW 28] The value sent to CM header in the case of CFC load error. */
826#define DORQ_REG_ERR_CMHEAD 0x170058
827#define DORQ_REG_IF_EN 0x170004
828#define DORQ_REG_MODE_ACT 0x170008
829/* [RW 5] The normal mode CID extraction offset. */
830#define DORQ_REG_NORM_CID_OFST 0x17002c
831/* [RW 28] TCM Header when only TCP context is loaded. */
832#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
833/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
834 Interface. */
835#define DORQ_REG_OUTST_REQ 0x17003c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300836#define DORQ_REG_PF_USAGE_CNT 0x1701d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200837#define DORQ_REG_REGN 0x170038
838/* [R 4] Current value of response A counter credit. Initial credit is
839 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
840 register. */
841#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
842/* [R 4] Current value of response B counter credit. Initial credit is
843 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
844 register. */
845#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
846/* [RW 4] The initial credit at the Doorbell Response Interface. The write
847 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
848 read reads this written value. */
849#define DORQ_REG_RSP_INIT_CRD 0x170048
850/* [RW 4] Initial activity counter value on the load request; when the
851 shortcut is done. */
852#define DORQ_REG_SHRT_ACT_CNT 0x170070
853/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
854#define DORQ_REG_SHRT_CMHEAD 0x170054
855#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000856#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200857#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
Eilon Greenstein8badd272009-02-12 08:36:15 +0000858#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200859#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000860#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
861#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200862#define HC_REG_AGG_INT_0 0x108050
863#define HC_REG_AGG_INT_1 0x108054
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200864#define HC_REG_ATTN_BIT 0x108120
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200865#define HC_REG_ATTN_IDX 0x108100
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200866#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200867#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200868#define HC_REG_ATTN_NUM_P0 0x108038
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200869#define HC_REG_ATTN_NUM_P1 0x10803c
Eilon Greenstein5c862842008-08-13 15:51:48 -0700870#define HC_REG_COMMAND_REG 0x108180
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200871#define HC_REG_CONFIG_0 0x108000
872#define HC_REG_CONFIG_1 0x108004
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700873#define HC_REG_FUNC_NUM_P0 0x1080ac
874#define HC_REG_FUNC_NUM_P1 0x1080b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200875/* [RW 3] Parity mask register #0 read/write */
876#define HC_REG_HC_PRTY_MASK 0x1080a0
Eliezer Tamirf1410642008-02-28 11:51:50 -0800877/* [R 3] Parity register #0 read */
878#define HC_REG_HC_PRTY_STS 0x108094
Vladislav Zolotarovf4a66892010-10-19 05:13:09 +0000879/* [RC 3] Parity register #0 read clear */
880#define HC_REG_HC_PRTY_STS_CLR 0x108098
881#define HC_REG_INT_MASK 0x108108
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200882#define HC_REG_LEADING_EDGE_0 0x108040
883#define HC_REG_LEADING_EDGE_1 0x108048
Vladislav Zolotarovf4a66892010-10-19 05:13:09 +0000884#define HC_REG_MAIN_MEMORY 0x108800
885#define HC_REG_MAIN_MEMORY_SIZE 152
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200886#define HC_REG_P0_PROD_CONS 0x108200
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200887#define HC_REG_P1_PROD_CONS 0x108400
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200888#define HC_REG_PBA_COMMAND 0x108140
889#define HC_REG_PCI_CONFIG_0 0x108010
890#define HC_REG_PCI_CONFIG_1 0x108014
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200891#define HC_REG_STATISTIC_COUNTERS 0x109000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200892#define HC_REG_TRAILING_EDGE_0 0x108044
893#define HC_REG_TRAILING_EDGE_1 0x10804c
894#define HC_REG_UC_RAM_ADDR_0 0x108028
895#define HC_REG_UC_RAM_ADDR_1 0x108030
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200896#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
897#define HC_REG_VQID_0 0x108008
898#define HC_REG_VQID_1 0x10800c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000899#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000900#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000901#define IGU_REG_ATTENTION_ACK_BITS 0x130108
902/* [R 4] Debug: attn_fsm */
903#define IGU_REG_ATTN_FSM 0x130054
904#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
905#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
906/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
907 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300908 * write done didn't receive. */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000909#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
910#define IGU_REG_BLOCK_CONFIGURATION 0x130000
911#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
912#define IGU_REG_COMMAND_REG_CTRL 0x13012c
913/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
914 * is clear. The bits in this registers are set and clear via the producer
915 * command. Data valid only in addresses 0-4. all the rest are zero. */
916#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
917/* [R 5] Debug: ctrl_fsm */
918#define IGU_REG_CTRL_FSM 0x130064
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300919/* [R 1] data available for error memory. If this bit is clear do not red
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000920 * from error_handling_memory. */
921#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000922/* [RW 11] Parity mask register #0 read/write */
923#define IGU_REG_IGU_PRTY_MASK 0x1300a8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000924/* [R 11] Parity register #0 read */
925#define IGU_REG_IGU_PRTY_STS 0x13009c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000926/* [RC 11] Parity register #0 read clear */
927#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000928/* [R 4] Debug: int_handle_fsm */
929#define IGU_REG_INT_HANDLE_FSM 0x130050
930#define IGU_REG_LEADING_EDGE_LATCH 0x130134
931/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
932 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
933 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
934#define IGU_REG_MAPPING_MEMORY 0x131000
935#define IGU_REG_MAPPING_MEMORY_SIZE 136
936#define IGU_REG_PBA_STATUS_LSB 0x130138
937#define IGU_REG_PBA_STATUS_MSB 0x13013c
938#define IGU_REG_PCI_PF_MSI_EN 0x130140
939#define IGU_REG_PCI_PF_MSIX_EN 0x130144
940#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
941/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
942 * pending; 1 = pending. Pendings means interrupt was asserted; and write
943 * done was not received. Data valid only in addresses 0-4. all the rest are
944 * zero. */
945#define IGU_REG_PENDING_BITS_STATUS 0x130300
946#define IGU_REG_PF_CONFIGURATION 0x130154
947/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
948 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
949 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
950 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
951 * - In backward compatible mode; for non default SB; each even line in the
952 * memory holds the U producer and each odd line hold the C producer. The
953 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
954 * last 20 producers are for the DSB for each PF. each PF has five segments
955 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
956 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
957#define IGU_REG_PROD_CONS_MEMORY 0x132000
958/* [R 3] Debug: pxp_arb_fsm */
959#define IGU_REG_PXP_ARB_FSM 0x130068
960/* [RW 6] Write one for each bit will reset the appropriate memory. When the
961 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
962 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
963 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
964#define IGU_REG_RESET_MEMORIES 0x130158
965/* [R 4] Debug: sb_ctrl_fsm */
966#define IGU_REG_SB_CTRL_FSM 0x13004c
967#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
968#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
969#define IGU_REG_SB_MASK_LSB 0x130164
970#define IGU_REG_SB_MASK_MSB 0x130168
971/* [RW 16] Number of command that were dropped without causing an interrupt
972 * due to: read access for WO BAR address; or write access for RO BAR
973 * address or any access for reserved address or PCI function error is set
974 * and address is not MSIX; PBA or cleanup */
975#define IGU_REG_SILENT_DROP 0x13016c
976/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
977 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
978 * PF; 68-71 number of ATTN messages per PF */
979#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
980/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
981 * timer mask command arrives. Value must be bigger than 100. */
982#define IGU_REG_TIMER_MASKING_VALUE 0x13003c
983#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
984#define IGU_REG_VF_CONFIGURATION 0x130170
985/* [WB_R 32] Each bit represent write done pending bits status for that SB
986 * (MSI/MSIX message was sent and write done was not received yet). 0 =
987 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
988#define IGU_REG_WRITE_DONE_PENDING 0x130480
989#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
Dmitry Kravkov7a25cc72011-06-14 01:33:25 +0000990#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
Yaniv Rosner3c9ada22011-06-14 01:34:12 +0000991#define MCP_REG_MCPR_GP_INPUTS 0x800c0
992#define MCP_REG_MCPR_GP_OENABLE 0x800c8
993#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
994#define MCP_REG_MCPR_IMC_COMMAND 0x85900
995#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
996#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
997#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200998#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
999#define MCP_REG_MCPR_NVM_ADDR 0x8640c
1000#define MCP_REG_MCPR_NVM_CFG4 0x8642c
1001#define MCP_REG_MCPR_NVM_COMMAND 0x86400
1002#define MCP_REG_MCPR_NVM_READ 0x86410
1003#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
1004#define MCP_REG_MCPR_NVM_WRITE 0x86408
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001005#define MCP_REG_MCPR_SCRATCH 0xa0000
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00001006#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1007#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001008/* [R 32] read first 32 bit after inversion of function 0. mapped as
1009 follows: [0] NIG attention for function0; [1] NIG attention for
1010 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1011 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1012 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1013 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1014 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1015 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1016 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1017 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1018 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1019 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1020 Parity error; [31] PBF Hw interrupt; */
1021#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1022#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1023/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1024 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1025 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1026 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1027 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1028 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1029 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1030 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1031 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1032 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1033 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1034 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1035 interrupt; */
1036#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1037/* [R 32] read second 32 bit after inversion of function 0. mapped as
1038 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1039 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1040 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1041 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1042 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1043 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1044 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1045 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1046 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1047 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1048 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1049 interrupt; */
1050#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1051#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1052/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1053 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1054 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1055 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1056 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1057 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1058 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1059 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1060 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1061 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1062 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1063 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1064#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1065/* [R 32] read third 32 bit after inversion of function 0. mapped as
1066 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1067 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1068 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1069 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1070 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1071 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1072 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1073 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1074 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1075 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1076 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1077 attn1; */
1078#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1079#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1080/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1081 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1082 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1083 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1084 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1085 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1086 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1087 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1088 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1089 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1090 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1091 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1092#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1093/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1094 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1095 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1096 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1097 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1098 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1099 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1100 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1101 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1102 Latched timeout attention; [27] GRC Latched reserved access attention;
1103 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1104 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1105#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1106#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1107/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1108 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1109 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1110 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1111 General attn13; [12] General attn14; [13] General attn15; [14] General
1112 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1113 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1114 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1115 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1116 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1117 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1118 ump_tx_parity; [31] MCP Latched scpad_parity; */
1119#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001120/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1121 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1122 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1123 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1124#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001125/* [W 14] write to this register results with the clear of the latched
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001126 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1127 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1128 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1129 GRC Latched reserved access attention; one in d7 clears Latched
1130 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001131 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1132 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1133 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1134 from this register return zero */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001135#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1136/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1137 as follows: [0] NIG attention for function0; [1] NIG attention for
1138 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1139 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1140 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1141 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1142 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1143 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1144 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1145 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1146 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1147 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1148 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1149#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1150#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001151#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001152#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001153#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1154#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1155#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001156/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1157 as follows: [0] NIG attention for function0; [1] NIG attention for
1158 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1159 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1160 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1161 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1162 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1163 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1164 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1165 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1166 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1167 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1168 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1169#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1170#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001171#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001172#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001173#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1174#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1175#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1176/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1177 as follows: [0] NIG attention for function0; [1] NIG attention for
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001178 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1179 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1180 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1181 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1182 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1183 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1184 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1185 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1186 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1187 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1188 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1189#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1190#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001191/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1192 as follows: [0] NIG attention for function0; [1] NIG attention for
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001193 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1194 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1195 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1196 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1197 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1198 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1199 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1200 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1201 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1202 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1203 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1204#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1205#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1206/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1207 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1208 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1209 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1210 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1211 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1212 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1213 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1214 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1215 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1216 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1217 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1218 interrupt; */
1219#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1220#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1221/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1222 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1223 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1224 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1225 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1226 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1227 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1228 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1229 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1230 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1231 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1232 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1233 interrupt; */
1234#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1235#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001236/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1237 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1238 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1239 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1240 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1241 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1242 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1243 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1244 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1245 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1246 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1247 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1248 interrupt; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001249#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1250#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001251/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1252 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1253 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1254 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1255 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1256 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1257 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1258 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1259 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1260 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1261 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1262 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1263 interrupt; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001264#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1265#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1266/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1267 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1268 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1269 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1270 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1271 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1272 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1273 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1274 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1275 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1276 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1277 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1278 attn1; */
1279#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1280#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1281/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1282 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1283 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1284 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1285 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1286 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1287 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1288 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1289 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1290 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1291 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1292 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1293 attn1; */
1294#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1295#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001296/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1297 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1298 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1299 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1300 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1301 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1302 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1303 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1304 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1305 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1306 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1307 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1308 attn1; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001309#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1310#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001311/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1312 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1313 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1314 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1315 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1316 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1317 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1318 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1319 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1320 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1321 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1322 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1323 attn1; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001324#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1325#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1326/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1327 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1328 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1329 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1330 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1331 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1332 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1333 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1334 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1335 Latched timeout attention; [27] GRC Latched reserved access attention;
1336 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1337 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1338#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1339#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001340#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1341#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1342#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1343#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001344/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1345 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1346 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1347 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1348 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1349 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1350 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1351 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1352 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1353 Latched timeout attention; [27] GRC Latched reserved access attention;
1354 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1355 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1356#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1357#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001358#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1359#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1360#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1361#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1362/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1363 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1364 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1365 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1366 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1367 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1368 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1369 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1370 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1371 Latched timeout attention; [27] GRC Latched reserved access attention;
1372 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1373 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001374#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1375#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001376/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1377 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1378 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1379 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1380 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1381 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1382 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1383 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1384 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1385 Latched timeout attention; [27] GRC Latched reserved access attention;
1386 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1387 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001388#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1389#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
Dmitry Kravkovf2eaeb52011-09-22 02:33:31 +00001390/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1391 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1392 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1393 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1394 * parity; [31-10] Reserved; */
1395#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
1396/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1397 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1398 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1399 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1400 * parity; [31-10] Reserved; */
1401#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001402/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1403 128 bit vector */
1404#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1405#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1406#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1407#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1408#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001409#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001410#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1411#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1412#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1413#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
Eliezer Tamirf1410642008-02-28 11:51:50 -08001414#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1415#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1416#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001417#define MISC_REG_AEU_GENERAL_MASK 0xa61c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001418/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1419 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1420 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1421 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1422 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1423 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1424 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1425 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1426 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1427 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1428 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1429 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1430 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1431#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1432#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1433/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1434 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1435 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1436 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1437 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1438 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1439 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1440 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1441 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1442 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1443 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1444 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1445 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1446#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1447#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1448/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001449 [9:8] = raserved. Zero = mask; one = unmask */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001450#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1451#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001452/* [RW 1] If set a system kill occurred */
1453#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1454/* [RW 32] Represent the status of the input vector to the AEU when a system
1455 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1456 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1457 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1458 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1459 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1460 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1461 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1462 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1463 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1464 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1465 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1466 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1467 interrupt; */
1468#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1469#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1470#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1471#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001472/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1473 Port. */
1474#define MISC_REG_BOND_ID 0xa400
1475/* [R 8] These bits indicate the metal revision of the chip. This value
1476 starts at 0x00 for each all-layer tape-out and increments by one for each
1477 tape-out. */
1478#define MISC_REG_CHIP_METAL 0xa404
1479/* [R 16] These bits indicate the part number for the chip. */
1480#define MISC_REG_CHIP_NUM 0xa408
1481/* [R 4] These bits indicate the base revision of the chip. This value
1482 starts at 0x0 for the A0 tape-out and increments by one for each
1483 all-layer tape-out. */
1484#define MISC_REG_CHIP_REV 0xa40c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001485/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1486 32 clients. Each client can be controlled by one driver only. One in each
1487 bit represent that this driver control the appropriate client (Ex: bit 5
1488 is set means this driver control client number 5). addr1 = set; addr0 =
1489 clear; read from both addresses will give the same result = status. write
1490 to address 1 will set a request to control all the clients that their
1491 appropriate bit (in the write command) is set. if the client is free (the
1492 appropriate bit in all the other drivers is clear) one will be written to
1493 that driver register; if the client isn't free the bit will remain zero.
1494 if the appropriate bit is set (the driver request to gain control on a
1495 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1496 interrupt will be asserted). write to address 0 will set a request to
1497 free all the clients that their appropriate bit (in the write command) is
1498 set. if the appropriate bit is clear (the driver request to free a client
1499 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1500 be asserted). */
Eliezer Tamirf1410642008-02-28 11:51:50 -08001501#define MISC_REG_DRIVER_CONTROL_1 0xa510
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001502#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001503/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1504 only. */
1505#define MISC_REG_E1HMF_MODE 0xa5f8
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001506/* [R 1] Status of four port mode path swap input pin. */
1507#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1508/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1509 the path_swap output is equal to 4 port mode path swap input pin; if it
1510 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1511 Overwrite value. If bit[0] of this register is 1 this is the value that
1512 receives the path_swap output. Reset on Hard reset. */
1513#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1514/* [R 1] Status of 4 port mode port swap input pin. */
1515#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1516/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1517 the port_swap output is equal to 4 port mode port swap input pin; if it
1518 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1519 Overwrite value. If bit[0] of this register is 1 this is the value that
1520 receives the port_swap output. Reset on Hard reset. */
1521#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
Eilon Greensteinca003922009-08-12 22:53:28 -07001522/* [RW 32] Debug only: spare RW register reset by core reset */
1523#define MISC_REG_GENERIC_CR_0 0xa460
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001524#define MISC_REG_GENERIC_CR_1 0xa464
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00001525/* [RW 32] Debug only: spare RW register reset by por reset */
1526#define MISC_REG_GENERIC_POR_1 0xa474
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001527/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1528 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1529 can not be configured as an output. Each output has its output enable in
1530 the MCP register space; but this bit needs to be set to make use of that.
1531 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1532 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1533 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1534 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1535 spare. Global register. Reset by hard reset. */
1536#define MISC_REG_GEN_PURP_HWG 0xa9a0
Eliezer Tamirf1410642008-02-28 11:51:50 -08001537/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1538 these bits is written as a '1'; the corresponding SPIO bit will turn off
1539 it's drivers and become an input. This is the reset state of all GPIO
1540 pins. The read value of these bits will be a '1' if that last command
1541 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1542 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1543 as a '1'; the corresponding GPIO bit will drive low. The read value of
1544 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1545 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1546 SET When any of these bits is written as a '1'; the corresponding GPIO
1547 bit will drive high (if it has that capability). The read value of these
1548 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1549 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1550 RO; These bits indicate the read value of each of the eight GPIO pins.
1551 This is the result value of the pin; not the drive value. Writing these
1552 bits will have not effect. */
1553#define MISC_REG_GPIO 0xa490
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00001554/* [RW 8] These bits enable the GPIO_INTs to signals event to the
1555 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1556 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1557 [7] p1_gpio_3; */
1558#define MISC_REG_GPIO_EVENT_EN 0xa2bc
1559/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1560 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1561 This will acknowledge an interrupt on the falling edge of corresponding
1562 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1563 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1564 register. This will acknowledge an interrupt on the rising edge of
1565 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1566 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1567 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1568 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1569 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1570 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1571 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1572 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1573 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1574 set when the GPIO input does not match the current value in #OLD_VALUE
1575 (reset value 0). */
1576#define MISC_REG_GPIO_INT 0xa494
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001577/* [R 28] this field hold the last information that caused reserved
1578 attention. bits [19:0] - address; [22:20] function; [23] reserved;
Eilon Greenstein33471622008-08-13 15:59:08 -07001579 [27:24] the master that caused the attention - according to the following
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001580 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1581 dbu; 8 = dmae */
1582#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1583/* [R 28] this field hold the last information that caused timeout
1584 attention. bits [19:0] - address; [22:20] function; [23] reserved;
Eilon Greenstein33471622008-08-13 15:59:08 -07001585 [27:24] the master that caused the attention - according to the following
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001586 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1587 dbu; 8 = dmae */
1588#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001589/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1590 access that does not finish within
1591 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1592 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1593 assert it attention output. */
1594#define MISC_REG_GRC_TIMEOUT_EN 0xa280
1595/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1596 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1597 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1598 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1599 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1600 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1601 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1602 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1603 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1604 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1605 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1606 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1607 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1608 connected to RESET input directly. [15] capRetry_en (reset value 0)
1609 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1610 value 0) bit to continuously monitor vco freq (inverted). [17]
1611 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1612 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1613 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1614 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1615 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1616 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1617 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1618 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1619 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1620 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1621 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1622 register bits. */
1623#define MISC_REG_LCPLL_CTRL_1 0xa2a4
1624#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
Yaniv Rosnerb76070b2011-11-28 00:49:47 +00001625/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1626 * reset. */
1627#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
1628/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1629#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
1630/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1631 * reset. */
1632#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001633/* [RW 4] Interrupt mask register #0 read/write */
1634#define MISC_REG_MISC_INT_MASK 0xa388
1635/* [RW 1] Parity mask register #0 read/write */
1636#define MISC_REG_MISC_PRTY_MASK 0xa398
Eliezer Tamirf1410642008-02-28 11:51:50 -08001637/* [R 1] Parity register #0 read */
1638#define MISC_REG_MISC_PRTY_STS 0xa38c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00001639/* [RC 1] Parity register #0 read clear */
1640#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001641#define MISC_REG_NIG_WOL_P0 0xa270
1642#define MISC_REG_NIG_WOL_P1 0xa274
1643/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1644 assertion */
1645#define MISC_REG_PCIE_HOT_RESET 0xa618
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001646/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1647 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1648 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1649 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1650 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1651 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1652 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1653 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1654 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1655 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1656 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1657 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1658 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1659 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1660 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1661 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1662 testa_en (reset value 0); */
1663#define MISC_REG_PLL_STORM_CTRL_1 0xa294
1664#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1665#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1666#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001667/* [R 1] Status of 4 port mode enable input pin. */
1668#define MISC_REG_PORT4MODE_EN 0xa750
1669/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1670 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1671 * the port4mode_en output is equal to bit[1] of this register; [1] -
1672 * Overwrite value. If bit[0] of this register is 1 this is the value that
1673 * receives the port4mode_en output . */
1674#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001675/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001676 write/read zero = the specific block is in reset; addr 0-wr- the write
1677 value will be written to the register; addr 1-set - one will be written
1678 to all the bits that have the value of one in the data written (bits that
1679 have the value of zero will not be change) ; addr 2-clear - zero will be
1680 written to all the bits that have the value of one in the data written
1681 (bits that have the value of zero will not be change); addr 3-ignore;
1682 read ignore from all addr except addr 00; inside order of the bits is:
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001683 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1684 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1685 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1686 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1687 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1688 rst_pxp_rq_rd_wr; 31:17] reserved */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001689#define MISC_REG_RESET_REG_2 0xa590
1690/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1691 shared with the driver resides */
1692#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
Eliezer Tamirf1410642008-02-28 11:51:50 -08001693/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1694 the corresponding SPIO bit will turn off it's drivers and become an
1695 input. This is the reset state of all SPIO pins. The read value of these
1696 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1697 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1698 is written as a '1'; the corresponding SPIO bit will drive low. The read
1699 value of these bits will be a '1' if that last command (#SET; #CLR; or
1700#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1701 these bits is written as a '1'; the corresponding SPIO bit will drive
1702 high (if it has that capability). The read value of these bits will be a
1703 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1704 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1705 each of the eight SPIO pins. This is the result value of the pin; not the
1706 drive value. Writing these bits will have not effect. Each 8 bits field
1707 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1708 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1709 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1710 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1711 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1712 select VAUX supply. (This is an output pin only; it is not controlled by
1713 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1714 field is not applicable for this pin; only the VALUE fields is relevant -
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001715 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
Eliezer Tamirf1410642008-02-28 11:51:50 -08001716 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1717 device ID select; read by UMP firmware. */
1718#define MISC_REG_SPIO 0xa4fc
1719/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1720 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1721 [7:0] reserved */
1722#define MISC_REG_SPIO_EVENT_EN 0xa2b8
1723/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1724 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1725 interrupt on the falling edge of corresponding SPIO input (reset value
1726 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1727 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1728 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1729 RO; These bits indicate the old value of the SPIO input value. When the
1730 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1731 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1732 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1733 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1734 RO; These bits indicate the current SPIO interrupt state for each SPIO
1735 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1736 command bit is written. This bit is set when the SPIO input does not
1737 match the current value in #OLD_VALUE (reset value 0). */
1738#define MISC_REG_SPIO_INT 0xa500
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08001739/* [RW 32] reload value for counter 4 if reload; the value will be reload if
1740 the counter reached zero and the reload bit
1741 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1742#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1743/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001744 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08001745 timer 8 */
1746#define MISC_REG_SW_TIMER_VAL 0xa5c0
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001747/* [R 1] Status of two port mode path swap input pin. */
1748#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1749/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1750 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1751 - the path_swap output is equal to bit[1] of this register; [1] -
1752 Overwrite value. If bit[0] of this register is 1 this is the value that
1753 receives the path_swap output. Reset on Hard reset. */
1754#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
Eliezer Tamirf1410642008-02-28 11:51:50 -08001755/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1756 loaded; 0-prepare; -unprepare */
1757#define MISC_REG_UNPREPARED 0xa424
Eilon Greenstein581ce432009-07-29 00:20:04 +00001758#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1759#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1760#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1761#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1762#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03001763/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1764 * not it is the recipient of the message on the MDIO interface. The value
1765 * is compared to the value on ctrl_md_devad. Drives output
1766 * misc_xgxs0_phy_addr. Global register. */
1767#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
Yaniv Rosnerb76070b2011-11-28 00:49:47 +00001768#define MISC_REG_WC0_RESET 0xac30
Yaniv Rosner9380bb92011-06-14 01:34:07 +00001769/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1770 side. This should be less than or equal to phy_port_mode; if some of the
1771 ports are not used. This enables reduction of frequency on the core side.
1772 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1773 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1774 input for the XMAC_MP core; and should be changed only while reset is
1775 held low. Reset on Hard reset. */
1776#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1777/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1778 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1779 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1780 XMAC_MP core; and should be changed only while reset is held low. Reset
1781 on Hard reset. */
1782#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03001783/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1784 * Reads from this register will clear bits 31:0. */
1785#define MSTAT_REG_RX_STAT_GR64_LO 0x200
1786/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1787 * 31:0. Reads from this register will clear bits 31:0. */
1788#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
Yaniv Rosner9380bb92011-06-14 01:34:07 +00001789#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1790#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1791#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1792#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1793#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001794#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1795#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001796#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1797#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1798#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1799#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1800/* [RW 1] Input enable for RX_BMAC0 IF */
1801#define NIG_REG_BMAC0_IN_EN 0x100ac
1802/* [RW 1] output enable for TX_BMAC0 IF */
1803#define NIG_REG_BMAC0_OUT_EN 0x100e0
1804/* [RW 1] output enable for TX BMAC pause port 0 IF */
1805#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1806/* [RW 1] output enable for RX_BMAC0_REGS IF */
1807#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1808/* [RW 1] output enable for RX BRB1 port0 IF */
1809#define NIG_REG_BRB0_OUT_EN 0x100f8
1810/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1811#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1812/* [RW 1] output enable for RX BRB1 port1 IF */
1813#define NIG_REG_BRB1_OUT_EN 0x100fc
1814/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1815#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1816/* [RW 1] output enable for RX BRB1 LP IF */
1817#define NIG_REG_BRB_LB_OUT_EN 0x10100
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001818/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1819 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1820 72:73]-vnic_num; 81:74]-sideband_info */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001821#define NIG_REG_DEBUG_PACKET_LB 0x10800
1822/* [RW 1] Input enable for TX Debug packet */
1823#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1824/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1825 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1826 First packet may be deleted from the middle. And last packet will be
1827 always deleted till the end. */
1828#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1829/* [RW 1] Output enable to EMAC0 */
1830#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1831/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1832 to emac for port0; other way to bmac for port0 */
1833#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1834/* [RW 1] Input enable for TX PBF user packet port0 IF */
1835#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1836/* [RW 1] Input enable for TX PBF user packet port1 IF */
1837#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
Eilon Greenstein279abdf2009-07-21 05:47:22 +00001838/* [RW 1] Input enable for TX UMP management packet port0 IF */
1839#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001840/* [RW 1] Input enable for RX_EMAC0 IF */
1841#define NIG_REG_EMAC0_IN_EN 0x100a4
1842/* [RW 1] output enable for TX EMAC pause port 0 IF */
1843#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1844/* [R 1] status from emac0. This bit is set when MDINT from either the
1845 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1846 be cleared in the attached PHY device that is driving the MINT pin. */
1847#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1848/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1849 are described in appendix A. In order to access the BMAC0 registers; the
1850 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1851 added to each BMAC register offset */
1852#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1853/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1854 are described in appendix A. In order to access the BMAC0 registers; the
1855 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1856 added to each BMAC register offset */
1857#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1858/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1859#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1860/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1861 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1862#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
Eilon Greenstein2f904462009-08-12 08:22:16 +00001863/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1864 logic for interrupts must be used. Enable per bit of interrupt of
1865 ~latch_status.latch_status */
1866#define NIG_REG_LATCH_BC_0 0x16210
1867/* [RW 27] Latch for each interrupt from Unicore.b[0]
1868 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1869 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1870 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1871 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1872 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1873 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1874 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1875 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1876 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1877 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1878 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1879 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1880#define NIG_REG_LATCH_STATUS_0 0x18000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001881/* [RW 1] led 10g for port 0 */
1882#define NIG_REG_LED_10G_P0 0x10320
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001883/* [RW 1] led 10g for port 1 */
1884#define NIG_REG_LED_10G_P1 0x10324
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001885/* [RW 1] Port0: This bit is set to enable the use of the
1886 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1887 defined below. If this bit is cleared; then the blink rate will be about
1888 8Hz. */
1889#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1890/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1891 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1892 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1893#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1894/* [RW 1] Port0: If set along with the
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001895 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001896 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1897 bit; the Traffic LED will blink with the blink rate specified in
1898 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1899 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1900 fields. */
1901#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1902/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1903 Traffic LED will then be controlled via bit ~nig_registers_
1904 led_control_traffic_p0.led_control_traffic_p0 and bit
1905 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1906#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1907/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1908 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1909 set; the LED will blink with blink rate specified in
1910 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1911 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1912 fields. */
1913#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1914/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1915 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1916#define NIG_REG_LED_MODE_P0 0x102f0
Eilon Greenstein1c063282009-02-12 08:36:43 +00001917/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1918 tsdm enable; b2- usdm enable */
1919#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
Eilon Greensteinca003922009-08-12 22:53:28 -07001920#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
Eilon Greenstein1c063282009-02-12 08:36:43 +00001921/* [RW 1] SAFC enable for port0. This register may get 1 only when
1922 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1923 port */
1924#define NIG_REG_LLFC_ENABLE_0 0x16208
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001925#define NIG_REG_LLFC_ENABLE_1 0x1620c
Eilon Greenstein1c063282009-02-12 08:36:43 +00001926/* [RW 16] classes are high-priority for port0 */
1927#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001928#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
Eilon Greenstein1c063282009-02-12 08:36:43 +00001929/* [RW 16] classes are low-priority for port0 */
1930#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001931#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
Eilon Greenstein1c063282009-02-12 08:36:43 +00001932/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1933#define NIG_REG_LLFC_OUT_EN_0 0x160c8
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001934#define NIG_REG_LLFC_OUT_EN_1 0x160cc
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001935#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1936#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001937#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001938#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001939/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1940#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001941/* [RW 2] Determine the classification participants. 0: no classification.1:
1942 classification upon VLAN id. 2: classification upon MAC address. 3:
1943 classification upon both VLAN id & MAC addr. */
1944#define NIG_REG_LLH0_CLS_TYPE 0x16080
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001945/* [RW 32] cm header for llh0 */
1946#define NIG_REG_LLH0_CM_HEADER 0x1007c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001947#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1948#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1949/* [RW 16] destination TCP address 1. The LLH will look for this address in
1950 all incoming packets. */
1951#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1952/* [RW 16] destination UDP address 1 The LLH will look for this address in
1953 all incoming packets. */
1954#define NIG_REG_LLH0_DEST_UDP_0 0x10214
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001955#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1956/* [RW 8] event id for llh0 */
1957#define NIG_REG_LLH0_EVENT_ID 0x10084
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001958#define NIG_REG_LLH0_FUNC_EN 0x160fc
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -08001959#define NIG_REG_LLH0_FUNC_MEM 0x16180
1960#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001961#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1962/* [RW 1] Determine the IP version to look for in
1963 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1964#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1965/* [RW 1] t bit for llh0 */
1966#define NIG_REG_LLH0_T_BIT 0x10074
1967/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1968#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001969/* [RW 8] init credit counter for port0 in LLH */
1970#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1971#define NIG_REG_LLH0_XCM_MASK 0x10130
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07001972#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001973/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1974#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001975/* [RW 2] Determine the classification participants. 0: no classification.1:
1976 classification upon VLAN id. 2: classification upon MAC address. 3:
1977 classification upon both VLAN id & MAC addr. */
1978#define NIG_REG_LLH1_CLS_TYPE 0x16084
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001979/* [RW 32] cm header for llh1 */
1980#define NIG_REG_LLH1_CM_HEADER 0x10080
1981#define NIG_REG_LLH1_ERROR_MASK 0x10090
1982/* [RW 8] event id for llh1 */
1983#define NIG_REG_LLH1_EVENT_ID 0x10088
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -08001984#define NIG_REG_LLH1_FUNC_MEM 0x161c0
1985#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1986#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03001987/* [RW 1] When this bit is set; the LLH will classify the packet before
1988 * sending it to the BRB or calculating WoL on it. This bit controls port 1
1989 * only. The legacy llh_multi_function_mode bit controls port 0. */
1990#define NIG_REG_LLH1_MF_MODE 0x18614
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001991/* [RW 8] init credit counter for port1 in LLH */
1992#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1993#define NIG_REG_LLH1_XCM_MASK 0x10134
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001994/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1995 e1hov */
1996#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1997/* [RW 1] When this bit is set; the LLH will classify the packet before
1998 sending it to the BRB or calculating WoL on it. */
1999#define NIG_REG_LLH_MF_MODE 0x16024
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002000#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
2001#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
2002/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
2003#define NIG_REG_NIG_EMAC0_EN 0x1003c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002004/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
2005#define NIG_REG_NIG_EMAC1_EN 0x10040
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002006/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
2007 EMAC0 to strip the CRC from the ingress packets. */
2008#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002009/* [R 32] Interrupt register #0 read */
2010#define NIG_REG_NIG_INT_STS_0 0x103b0
2011#define NIG_REG_NIG_INT_STS_1 0x103c0
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00002012/* [R 32] Legacy E1 and E1H location for parity error mask register. */
2013#define NIG_REG_NIG_PRTY_MASK 0x103dc
2014/* [RW 32] Parity mask register #0 read/write */
2015#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
2016#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002017/* [R 32] Legacy E1 and E1H location for parity error status register. */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002018#define NIG_REG_NIG_PRTY_STS 0x103d0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002019/* [R 32] Parity register #0 read */
2020#define NIG_REG_NIG_PRTY_STS_0 0x183bc
2021#define NIG_REG_NIG_PRTY_STS_1 0x183cc
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00002022/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
2023#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
2024/* [RC 32] Parity register #0 read clear */
2025#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
2026#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00002027#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2028#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2029#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2030#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002031/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2032 * Ethernet header. */
2033#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2034/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2035 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2036 * disabled when this bit is set. */
2037#define NIG_REG_P0_HWPFC_ENABLE 0x18078
2038#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2039#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002040/* [RW 1] Input enable for RX MAC interface. */
2041#define NIG_REG_P0_MAC_IN_EN 0x185ac
2042/* [RW 1] Output enable for TX MAC interface */
2043#define NIG_REG_P0_MAC_OUT_EN 0x185b0
2044/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2045#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002046/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2047 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2048 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2049 * priority field is extracted from the outer-most VLAN in receive packet.
2050 * Only COS 0 and COS 1 are supported in E2. */
2051#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2052/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2053 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2054 * than one bit may be set; allowing multiple priorities to be mapped to one
2055 * COS. */
2056#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2057/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2058 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2059 * than one bit may be set; allowing multiple priorities to be mapped to one
2060 * COS. */
2061#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002062/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2063 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2064 * than one bit may be set; allowing multiple priorities to be mapped to one
2065 * COS. */
2066#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2067/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2068 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2069 * than one bit may be set; allowing multiple priorities to be mapped to one
2070 * COS. */
2071#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2072/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2073 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2074 * than one bit may be set; allowing multiple priorities to be mapped to one
2075 * COS. */
2076#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2077/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2078 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2079 * than one bit may be set; allowing multiple priorities to be mapped to one
2080 * COS. */
2081#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002082/* [R 1] RX FIFO for receiving data from MAC is empty. */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002083/* [RW 15] Specify which of the credit registers the client is to be mapped
2084 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2085 * clients that are not subject to WFQ credit blocking - their
2086 * specifications here are not used. */
2087#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002088/* [RW 32] Specify which of the credit registers the client is to be mapped
2089 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2090 * for client 0; bits [35:32] are for client 8. For clients that are not
2091 * subject to WFQ credit blocking - their specifications here are not used.
2092 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2093 * input clients to ETS arbiter. The reset default is set for management and
2094 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2095 * use credit registers 0-5 respectively (0x543210876). Note that credit
2096 * registers can not be shared between clients. */
2097#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2098/* [RW 4] Specify which of the credit registers the client is to be mapped
2099 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2100 * for client 0; bits [35:32] are for client 8. For clients that are not
2101 * subject to WFQ credit blocking - their specifications here are not used.
2102 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2103 * input clients to ETS arbiter. The reset default is set for management and
2104 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2105 * use credit registers 0-5 respectively (0x543210876). Note that credit
2106 * registers can not be shared between clients. */
2107#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002108/* [RW 5] Specify whether the client competes directly in the strict
2109 * priority arbiter. The bits are mapped according to client ID (client IDs
2110 * are defined in tx_arb_priority_client). Default value is set to enable
2111 * strict priorities for clients 0-2 -- management and debug traffic. */
2112#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2113/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2114 * bits are mapped according to client ID (client IDs are defined in
2115 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2116 * blocking. */
2117#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2118/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2119 * reach. */
2120#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2121#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002122#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2123#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2124#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2125#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2126#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2127#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2128#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002129/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2130 * when it is time to increment. */
2131#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2132#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002133#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2134#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2135#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2136#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2137#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2138#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2139#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002140/* [RW 12] Specify the number of strict priority arbitration slots between
2141 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2142 * no strict priority cycles - the strict priority with anti-starvation
2143 * arbiter becomes a round-robin arbiter. */
2144#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2145/* [RW 15] Specify the client number to be assigned to each priority of the
2146 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2147 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2148 * clients are assigned the following IDs: 0-management; 1-debug traffic
2149 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2150 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2151 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2152 * traffic at priority 3; and COS1 traffic at priority 4. */
2153#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002154/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2155 * Ethernet header. */
2156#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002157#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2158#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002159/* [RW 32] Specify the client number to be assigned to each priority of the
2160 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2161 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2162 * client; bits [35-32] are for priority 8 client. The clients are assigned
2163 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2164 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2165 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2166 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2167 * accommodate the 9 input clients to ETS arbiter. */
2168#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2169/* [RW 4] Specify the client number to be assigned to each priority of the
2170 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2171 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2172 * client; bits [35-32] are for priority 8 client. The clients are assigned
2173 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2174 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2175 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2176 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2177 * accommodate the 9 input clients to ETS arbiter. */
2178#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
Yaniv Rosner127302b2012-01-17 02:33:26 +00002179#define NIG_REG_P1_HWPFC_ENABLE 0x181d0
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002180#define NIG_REG_P1_MAC_IN_EN 0x185c0
2181/* [RW 1] Output enable for TX MAC interface */
2182#define NIG_REG_P1_MAC_OUT_EN 0x185c4
2183/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2184#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002185/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2186 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2187 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2188 * priority field is extracted from the outer-most VLAN in receive packet.
2189 * Only COS 0 and COS 1 are supported in E2. */
2190#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2191/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2192 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2193 * than one bit may be set; allowing multiple priorities to be mapped to one
2194 * COS. */
2195#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2196/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2197 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2198 * than one bit may be set; allowing multiple priorities to be mapped to one
2199 * COS. */
2200#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002201/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2202 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2203 * than one bit may be set; allowing multiple priorities to be mapped to one
2204 * COS. */
2205#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002206/* [R 1] RX FIFO for receiving data from MAC is empty. */
2207#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2208/* [R 1] TLLH FIFO is empty. */
2209#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2210/* [RW 32] Specify which of the credit registers the client is to be mapped
2211 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2212 * for client 0; bits [35:32] are for client 8. For clients that are not
2213 * subject to WFQ credit blocking - their specifications here are not used.
2214 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2215 * input clients to ETS arbiter. The reset default is set for management and
2216 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2217 * use credit registers 0-5 respectively (0x543210876). Note that credit
2218 * registers can not be shared between clients. Note also that there are
2219 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2220 * credit registers 0-5 are valid. This register should be configured
2221 * appropriately before enabling WFQ. */
2222#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2223/* [RW 4] Specify which of the credit registers the client is to be mapped
2224 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2225 * for client 0; bits [35:32] are for client 8. For clients that are not
2226 * subject to WFQ credit blocking - their specifications here are not used.
2227 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2228 * input clients to ETS arbiter. The reset default is set for management and
2229 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2230 * use credit registers 0-5 respectively (0x543210876). Note that credit
2231 * registers can not be shared between clients. Note also that there are
2232 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2233 * credit registers 0-5 are valid. This register should be configured
2234 * appropriately before enabling WFQ. */
2235#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2236/* [RW 9] Specify whether the client competes directly in the strict
2237 * priority arbiter. The bits are mapped according to client ID (client IDs
2238 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2239 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2240 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2241 * Default value is set to enable strict priorities for all clients. */
2242#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2243/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2244 * bits are mapped according to client ID (client IDs are defined in
2245 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2246 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2247 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2248 * 0 for not using WFQ credit blocking. */
2249#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002250#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2251#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2252#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2253#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2254#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2255#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2256/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2257 * when it is time to increment. */
2258#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2259#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2260#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2261#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2262#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2263#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2264/* [RW 12] Specify the number of strict priority arbitration slots between
2265 two round-robin arbitration slots to avoid starvation. A value of 0 means
2266 no strict priority cycles - the strict priority with anti-starvation
2267 arbiter becomes a round-robin arbiter. */
2268#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2269/* [RW 32] Specify the client number to be assigned to each priority of the
2270 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2271 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2272 client; bits [35-32] are for priority 8 client. The clients are assigned
2273 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2274 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2275 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2276 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2277 accommodate the 9 input clients to ETS arbiter. Note that this register
2278 is the same as the one for port 0, except that port 1 only has COS 0-2
2279 traffic. There is no traffic for COS 3-5 of port 1. */
2280#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2281/* [RW 4] Specify the client number to be assigned to each priority of the
2282 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2283 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2284 client; bits [35-32] are for priority 8 client. The clients are assigned
2285 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2286 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2287 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2288 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2289 accommodate the 9 input clients to ETS arbiter. Note that this register
2290 is the same as the one for port 0, except that port 1 only has COS 0-2
2291 traffic. There is no traffic for COS 3-5 of port 1. */
2292#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2293/* [R 1] TX FIFO for transmitting data to MAC is empty. */
2294#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2295/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2296 forwarded to the host. */
2297#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002298/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2299 * reach. */
Eilon Greenstein1c063282009-02-12 08:36:43 +00002300/* [RW 1] Pause enable for port0. This register may get 1 only when
2301 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2302 port */
2303#define NIG_REG_PAUSE_ENABLE_0 0x160c0
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002304#define NIG_REG_PAUSE_ENABLE_1 0x160c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002305/* [RW 1] Input enable for RX PBF LP IF */
2306#define NIG_REG_PBF_LB_IN_EN 0x100b4
Eliezer Tamirf1410642008-02-28 11:51:50 -08002307/* [RW 1] Value of this register will be transmitted to port swap when
2308 ~nig_registers_strap_override.strap_override =1 */
2309#define NIG_REG_PORT_SWAP 0x10394
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002310/* [RW 1] PPP enable for port0. This register may get 1 only when
2311 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2312 * same port */
2313#define NIG_REG_PPP_ENABLE_0 0x160b0
2314#define NIG_REG_PPP_ENABLE_1 0x160b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002315/* [RW 1] output enable for RX parser descriptor IF */
2316#define NIG_REG_PRS_EOP_OUT_EN 0x10104
2317/* [RW 1] Input enable for RX parser request IF */
2318#define NIG_REG_PRS_REQ_IN_EN 0x100b8
Eilon Greensteinc1b73992009-02-12 08:37:07 +00002319/* [RW 5] control to serdes - CL45 DEVAD */
2320#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2321/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2322#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002323/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2324#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2325/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2326#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2327/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2328 for port0 */
2329#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
Yitchak Gertner66e855f2008-08-13 15:49:05 -07002330/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2331 for port0 */
2332#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002333/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2334 between 1024 and 1522 bytes for port0 */
2335#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2336/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2337 between 1523 bytes and above for port0 */
2338#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002339/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2340 for port1 */
2341#define NIG_REG_STAT1_BRB_DISCARD 0x10628
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002342/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2343 between 1024 and 1522 bytes for port1 */
2344#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2345/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2346 between 1523 bytes and above for port1 */
2347#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002348/* [WB_R 64] Rx statistics : User octets received for LP */
2349#define NIG_REG_STAT2_BRB_OCTET 0x107e0
2350#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2351#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
Eliezer Tamirf1410642008-02-28 11:51:50 -08002352/* [RW 1] port swap mux selection. If this register equal to 0 then port
2353 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2354 ort swap is equal to ~nig_registers_port_swap.port_swap */
2355#define NIG_REG_STRAP_OVERRIDE 0x10398
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002356/* [RW 1] output enable for RX_XCM0 IF */
2357#define NIG_REG_XCM0_OUT_EN 0x100f0
2358/* [RW 1] output enable for RX_XCM1 IF */
2359#define NIG_REG_XCM1_OUT_EN 0x100f4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002360/* [RW 1] control to xgxs - remote PHY in-band MDIO */
2361#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002362/* [RW 5] control to xgxs - CL45 DEVAD */
2363#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002364/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2365#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002366/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2367#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2368/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2369#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2370/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2371#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2372/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2373#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2374/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2375#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
Eilon Greenstein2f904462009-08-12 08:22:16 +00002376#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002377#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2378#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2379#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2380#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002381/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2382#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002383/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2384 * of port 0. */
2385#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2386/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2387 * of port 1. */
2388#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002389/* [RW 31] The weight of COS0 in the ETS command arbiter. */
2390#define PBF_REG_COS0_WEIGHT 0x15c054
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002391/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2392#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2393/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2394#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002395/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2396#define PBF_REG_COS1_UPPER_BOUND 0x15c060
2397/* [RW 31] The weight of COS1 in the ETS command arbiter. */
2398#define PBF_REG_COS1_WEIGHT 0x15c058
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002399/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2400#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2401/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2402#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2403/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2404#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2405/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2406#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2407/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2408#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2409/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2410#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2411/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2412#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002413/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2414 * lines. */
2415#define PBF_REG_CREDIT_LB_Q 0x140338
2416/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2417 * lines. */
2418#define PBF_REG_CREDIT_Q0 0x14033c
2419/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2420 * lines. */
2421#define PBF_REG_CREDIT_Q1 0x140340
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002422/* [RW 1] Disable processing further tasks from port 0 (after ending the
2423 current task in process). */
2424#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2425/* [RW 1] Disable processing further tasks from port 1 (after ending the
2426 current task in process). */
2427#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2428/* [RW 1] Disable processing further tasks from port 4 (after ending the
2429 current task in process). */
2430#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002431#define PBF_REG_DISABLE_PF 0x1402e8
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002432/* [RW 18] For port 0: For each client that is subject to WFQ (the
2433 * corresponding bit is 1); indicates to which of the credit registers this
2434 * client is mapped. For clients which are not credit blocked; their mapping
2435 * is dont care. */
2436#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2437/* [RW 9] For port 1: For each client that is subject to WFQ (the
2438 * corresponding bit is 1); indicates to which of the credit registers this
2439 * client is mapped. For clients which are not credit blocked; their mapping
2440 * is dont care. */
2441#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2442/* [RW 6] For port 0: Bit per client to indicate if the client competes in
2443 * the strict priority arbiter directly (corresponding bit = 1); or first
2444 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2445 * lowest priority in the strict-priority arbiter. */
2446#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2447/* [RW 3] For port 1: Bit per client to indicate if the client competes in
2448 * the strict priority arbiter directly (corresponding bit = 1); or first
2449 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2450 * lowest priority in the strict-priority arbiter. */
2451#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2452/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2453 * WFQ credit blocking (corresponding bit = 1). */
2454#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2455/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2456 * WFQ credit blocking (corresponding bit = 1). */
2457#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2458/* [RW 16] For port 0: The number of strict priority arbitration slots
2459 * between 2 RR arbitration slots. A value of 0 means no strict priority
2460 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2461 * arbiter. */
2462#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2463/* [RW 16] For port 1: The number of strict priority arbitration slots
2464 * between 2 RR arbitration slots. A value of 0 means no strict priority
2465 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2466 * arbiter. */
2467#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2468/* [RW 18] For port 0: Indicates which client is connected to each priority
2469 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2470 * priority 5 is the lowest; to which the RR output is connected to (this is
2471 * not configurable). */
2472#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2473/* [RW 9] For port 1: Indicates which client is connected to each priority
2474 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2475 * priority 5 is the lowest; to which the RR output is connected to (this is
2476 * not configurable). */
2477#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002478/* [RW 1] Indicates that ETS is performed between the COSes in the command
2479 * arbiter. If reset strict priority w/ anti-starvation will be performed
2480 * w/o WFQ. */
2481#define PBF_REG_ETS_ENABLED 0x15c050
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002482/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2483 * Ethernet header. */
2484#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002485/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2486#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2487/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2488 * priority in the command arbiter. */
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002489#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002490#define PBF_REG_IF_ENABLE_REG 0x140044
2491/* [RW 1] Init bit. When set the initial credits are copied to the credit
2492 registers (except the port credits). Should be set and then reset after
2493 the configuration of the block has ended. */
2494#define PBF_REG_INIT 0x140000
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002495/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2496 * lines. */
2497#define PBF_REG_INIT_CRD_LB_Q 0x15c248
2498/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2499 * lines. */
2500#define PBF_REG_INIT_CRD_Q0 0x15c230
2501/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2502 * lines. */
2503#define PBF_REG_INIT_CRD_Q1 0x15c234
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002504/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2505 copied to the credit register. Should be set and then reset after the
2506 configuration of the port has ended. */
2507#define PBF_REG_INIT_P0 0x140004
2508/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2509 copied to the credit register. Should be set and then reset after the
2510 configuration of the port has ended. */
2511#define PBF_REG_INIT_P1 0x140008
2512/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2513 copied to the credit register. Should be set and then reset after the
2514 configuration of the port has ended. */
2515#define PBF_REG_INIT_P4 0x14000c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002516/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2517 * the LB queue. Reset upon init. */
2518#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2519/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2520 * queue 0. Reset upon init. */
2521#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2522/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2523 * queue 1. Reset upon init. */
2524#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002525/* [RW 1] Enable for mac interface 0. */
2526#define PBF_REG_MAC_IF0_ENABLE 0x140030
2527/* [RW 1] Enable for mac interface 1. */
2528#define PBF_REG_MAC_IF1_ENABLE 0x140034
2529/* [RW 1] Enable for the loopback interface. */
2530#define PBF_REG_MAC_LB_ENABLE 0x140040
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002531/* [RW 6] Bit-map indicating which headers must appear in the packet */
2532#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002533/* [RW 16] The number of strict priority arbitration slots between 2 RR
2534 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2535 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2536#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002537/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2538 not suppoterd. */
2539#define PBF_REG_P0_ARB_THRSH 0x1400e4
2540/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2541#define PBF_REG_P0_CREDIT 0x140200
2542/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2543 lines. */
2544#define PBF_REG_P0_INIT_CRD 0x1400d0
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002545/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2546 * port 0. Reset upon init. */
2547#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2548/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2549#define PBF_REG_P0_PAUSE_ENABLE 0x140014
2550/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002551#define PBF_REG_P0_TASK_CNT 0x140204
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002552/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2553 * freed from the task queue of port 0. Reset upon init. */
2554#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2555/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2556#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2557/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2558 * buffers in 16 byte lines. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002559#define PBF_REG_P1_CREDIT 0x140208
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002560/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2561 * buffers in 16 byte lines. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002562#define PBF_REG_P1_INIT_CRD 0x1400d4
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002563/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2564 * port 1. Reset upon init. */
2565#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2566/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002567#define PBF_REG_P1_TASK_CNT 0x14020c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002568/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2569 * freed from the task queue of port 1. Reset upon init. */
2570#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2571/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2572#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002573/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2574#define PBF_REG_P4_CREDIT 0x140210
2575/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2576 lines. */
2577#define PBF_REG_P4_INIT_CRD 0x1400e0
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002578/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2579 * port 4. Reset upon init. */
2580#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2581/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002582#define PBF_REG_P4_TASK_CNT 0x140214
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002583/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2584 * freed from the task queue of port 4. Reset upon init. */
2585#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2586/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2587#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002588/* [RW 5] Interrupt mask register #0 read/write */
2589#define PBF_REG_PBF_INT_MASK 0x1401d4
2590/* [R 5] Interrupt register #0 read */
2591#define PBF_REG_PBF_INT_STS 0x1401c8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00002592/* [RW 20] Parity mask register #0 read/write */
2593#define PBF_REG_PBF_PRTY_MASK 0x1401e4
2594/* [RC 20] Parity register #0 read clear */
2595#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002596/* [RW 16] The Ethernet type value for L2 tag 0 */
2597#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2598/* [RW 4] The length of the info field for L2 tag 0. The length is between
2599 * 2B and 14B; in 2B granularity */
2600#define PBF_REG_TAG_LEN_0 0x15c09c
2601/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2602 * queue. Reset upon init. */
2603#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2604/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2605 * queue 0. Reset upon init. */
2606#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2607/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2608 * Reset upon init. */
2609#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2610/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2611 * queue. */
2612#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2613/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2614#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2615/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2616#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002617#define PB_REG_CONTROL 0
2618/* [RW 2] Interrupt mask register #0 read/write */
2619#define PB_REG_PB_INT_MASK 0x28
2620/* [R 2] Interrupt register #0 read */
2621#define PB_REG_PB_INT_STS 0x1c
2622/* [RW 4] Parity mask register #0 read/write */
2623#define PB_REG_PB_PRTY_MASK 0x38
Eliezer Tamirf1410642008-02-28 11:51:50 -08002624/* [R 4] Parity register #0 read */
2625#define PB_REG_PB_PRTY_STS 0x2c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00002626/* [RC 4] Parity register #0 read clear */
2627#define PB_REG_PB_PRTY_STS_CLR 0x30
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002628#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2629#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2630#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2631#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2632#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2633#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2634#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2635#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2636#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2637/* [R 8] Config space A attention dirty bits. Each bit indicates that the
2638 * corresponding PF generates config space A attention. Set by PXP. Reset by
2639 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2640 * from both paths. */
2641#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2642/* [R 8] Config space B attention dirty bits. Each bit indicates that the
2643 * corresponding PF generates config space B attention. Set by PXP. Reset by
2644 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2645 * from both paths. */
2646#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2647/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2648 * - enable. */
2649#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2650/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2651 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2652#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2653/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2654 * - enable. */
2655#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2656/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2657#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2658/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2659#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2660/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2661#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2662/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2663#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2664/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2665 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2666 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2667 * from both paths. */
2668#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2669/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2670 * to a bit in this register in order to clear the corresponding bit in
2671 * flr_request_pf_7_0 register. Note: register contains bits from both
2672 * paths. */
2673#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2674/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2675 * indicates that the FLR register of the corresponding VF was set. Set by
2676 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2677#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2678/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2679 * indicates that the FLR register of the corresponding VF was set. Set by
2680 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2681#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2682/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2683 * indicates that the FLR register of the corresponding VF was set. Set by
2684 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2685#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2686/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2687 * indicates that the FLR register of the corresponding VF was set. Set by
2688 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2689#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2690/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2691 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2692 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2693 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2694 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2695 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2696 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2697 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2698 * and pcie_rx_last not asserted. */
2699#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2700#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2701#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2702#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2703#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2704/* [R 9] Interrupt register #0 read */
2705#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2706/* [RC 9] Interrupt register #0 read clear */
2707#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
Vladislav Zolotarov8736c822011-07-21 07:58:36 +00002708/* [RW 2] Parity mask register #0 read/write */
2709#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002710/* [R 2] Parity register #0 read */
2711#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
Vladislav Zolotarov8736c822011-07-21 07:58:36 +00002712/* [RC 2] Parity register #0 read clear */
2713#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002714/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2715 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2716 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2717 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2718 * if there was a completion error since the last time this register was
2719 * cleared. */
2720#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2721/* [R 18] Details of first ATS Translation Completion request received with
2722 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2723 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2724 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2725 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2726 * completion error since the last time this register was cleared. */
2727#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2728/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2729 * a bit in this register in order to clear the corresponding bit in
2730 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2731 * work-around is needed. Note: register contains bits from both paths. */
2732#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2733/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2734 * VF enable register of the corresponding PF is written to 0 and was
2735 * previously 1. Set by PXP. Reset by MCP writing 1 to
2736 * sr_iov_disabled_request_clr. Note: register contains bits from both
2737 * paths. */
2738#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2739/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2740 * completion did not return yet. 1 - tag is unused. Same functionality as
2741 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2742#define PGLUE_B_REG_TAGS_63_32 0x9244
2743/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2744 * - enable. */
2745#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2746/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2747#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2748/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2749#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2750/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2751#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2752/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2753#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2754/* [R 32] Address [31:0] of first read request not submitted due to error */
2755#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2756/* [R 32] Address [63:32] of first read request not submitted due to error */
2757#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2758/* [R 31] Details of first read request not submitted due to error. [4:0]
2759 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2760 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2761 * VFID. */
2762#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2763/* [R 26] Details of first read request not submitted due to error. [15:0]
2764 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2765 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2766 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2767 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2768 * indicates if there was a request not submitted due to error since the
2769 * last time this register was cleared. */
2770#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2771/* [R 32] Address [31:0] of first write request not submitted due to error */
2772#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2773/* [R 32] Address [63:32] of first write request not submitted due to error */
2774#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2775/* [R 31] Details of first write request not submitted due to error. [4:0]
2776 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2777 * - VFID. */
2778#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2779/* [R 26] Details of first write request not submitted due to error. [15:0]
2780 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2781 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2782 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2783 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2784 * indicates if there was a request not submitted due to error since the
2785 * last time this register was cleared. */
2786#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2787/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2788 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2789 * value (Byte resolution address). */
2790#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2791#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2792#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2793#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2794#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2795#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2796#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2797/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2798 * - enable. */
2799#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2800/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2801 * - enable. */
2802#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2803/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2804 * - enable. */
2805#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2806/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2807#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2808/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2809#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2810/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2811#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2812/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2813#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2814/* [R 26] Details of first target VF request accessing VF GRC space that
2815 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2816 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2817 * request accessing VF GRC space that failed permission check since the
2818 * last time this register was cleared. Permission checks are: function
2819 * permission; R/W permission; address range permission. */
2820#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2821/* [R 31] Details of first target VF request with length violation (too many
2822 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2823 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2824 * valid - indicates if there was a request with length violation since the
2825 * last time this register was cleared. Length violations: length of more
2826 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2827 * length is more than 1 DW. */
2828#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2829/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2830 * that there was a completion with uncorrectable error for the
2831 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2832 * was_error_pf_7_0_clr. */
2833#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2834/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2835 * to a bit in this register in order to clear the corresponding bit in
2836 * flr_request_pf_7_0 register. */
2837#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2838/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2839 * indicates that there was a completion with uncorrectable error for the
2840 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2841 * was_error_vf_127_96_clr. */
2842#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2843/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2844 * writes 1 to a bit in this register in order to clear the corresponding
2845 * bit in was_error_vf_127_96 register. */
2846#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2847/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2848 * indicates that there was a completion with uncorrectable error for the
2849 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2850 * was_error_vf_31_0_clr. */
2851#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2852/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2853 * 1 to a bit in this register in order to clear the corresponding bit in
2854 * was_error_vf_31_0 register. */
2855#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2856/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2857 * indicates that there was a completion with uncorrectable error for the
2858 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2859 * was_error_vf_63_32_clr. */
2860#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2861/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2862 * 1 to a bit in this register in order to clear the corresponding bit in
2863 * was_error_vf_63_32 register. */
2864#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2865/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2866 * indicates that there was a completion with uncorrectable error for the
2867 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2868 * was_error_vf_95_64_clr. */
2869#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2870/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2871 * 1 to a bit in this register in order to clear the corresponding bit in
2872 * was_error_vf_95_64 register. */
2873#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2874/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2875 * - enable. */
2876#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2877/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2878#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2879/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2880#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2881/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2882#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2883/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2884#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002885#define PRS_REG_A_PRSU_20 0x40134
2886/* [R 8] debug only: CFC load request current credit. Transaction based. */
2887#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2888/* [R 8] debug only: CFC search request current credit. Transaction based. */
2889#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2890/* [RW 6] The initial credit for the search message to the CFC interface.
2891 Credit is transaction based. */
2892#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2893/* [RW 24] CID for port 0 if no match */
2894#define PRS_REG_CID_PORT_0 0x400fc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002895/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2896 load response is reset and packet type is 0. Used in packet start message
2897 to TCM. */
2898#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2899#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2900#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2901#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2902#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08002903#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002904/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2905 load response is set and packet type is 0. Used in packet start message
2906 to TCM. */
2907#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2908#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2909#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2910#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2911#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08002912#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002913/* [RW 32] The CM header for a match and packet type 1 for loopback port.
2914 Used in packet start message to TCM. */
2915#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2916#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2917#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2918#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2919/* [RW 32] The CM header for a match and packet type 0. Used in packet start
2920 message to TCM. */
2921#define PRS_REG_CM_HDR_TYPE_0 0x40078
2922#define PRS_REG_CM_HDR_TYPE_1 0x4007c
2923#define PRS_REG_CM_HDR_TYPE_2 0x40080
2924#define PRS_REG_CM_HDR_TYPE_3 0x40084
2925#define PRS_REG_CM_HDR_TYPE_4 0x40088
2926/* [RW 32] The CM header in case there was not a match on the connection */
2927#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002928/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2929#define PRS_REG_E1HOV_MODE 0x401c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002930/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2931 start message to TCM. */
2932#define PRS_REG_EVENT_ID_1 0x40054
2933#define PRS_REG_EVENT_ID_2 0x40058
2934#define PRS_REG_EVENT_ID_3 0x4005c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002935/* [RW 16] The Ethernet type value for FCoE */
2936#define PRS_REG_FCOE_TYPE 0x401d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002937/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2938 load request message. */
2939#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2940#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2941#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2942#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2943#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2944#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2945#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2946#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002947/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2948 * Ethernet header. */
2949#define PRS_REG_HDRS_AFTER_BASIC 0x40238
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002950/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2951 * Ethernet header for port 0 packets. */
2952#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
2953#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
2954/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2955#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
2956/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2957 * port 0 packets */
2958#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
2959#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002960/* [RW 4] The increment value to send in the CFC load request message */
2961#define PRS_REG_INC_VALUE 0x40048
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002962/* [RW 6] Bit-map indicating which headers must appear in the packet */
2963#define PRS_REG_MUST_HAVE_HDRS 0x40254
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002964/* [RW 6] Bit-map indicating which headers must appear in the packet for
2965 * port 0 packets */
2966#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
2967#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002968#define PRS_REG_NIC_MODE 0x40138
2969/* [RW 8] The 8-bit event ID for cases where there is no match on the
2970 connection. Used in packet start message to TCM. */
2971#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2972/* [ST 24] The number of input CFC flush packets */
2973#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2974/* [ST 32] The number of cycles the Parser halted its operation since it
2975 could not allocate the next serial number */
2976#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2977/* [ST 24] The number of input packets */
2978#define PRS_REG_NUM_OF_PACKETS 0x40124
2979/* [ST 24] The number of input transparent flush packets */
2980#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2981/* [RW 8] Context region for received Ethernet packet with a match and
2982 packet type 0. Used in CFC load request message */
2983#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2984#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2985#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2986#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2987#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2988#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2989#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2990#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2991/* [R 2] debug only: Number of pending requests for CAC on port 0. */
2992#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2993/* [R 2] debug only: Number of pending requests for header parsing. */
2994#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2995/* [R 1] Interrupt register #0 read */
2996#define PRS_REG_PRS_INT_STS 0x40188
2997/* [RW 8] Parity mask register #0 read/write */
2998#define PRS_REG_PRS_PRTY_MASK 0x401a4
Eliezer Tamirf1410642008-02-28 11:51:50 -08002999/* [R 8] Parity register #0 read */
3000#define PRS_REG_PRS_PRTY_STS 0x40198
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003001/* [RC 8] Parity register #0 read clear */
3002#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003003/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
3004 request message */
3005#define PRS_REG_PURE_REGIONS 0x40024
3006/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
3007 serail number was released by SDM but cannot be used because a previous
3008 serial number was not released. */
3009#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
3010/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
3011 serail number was released by SDM but cannot be used because a previous
3012 serial number was not released. */
3013#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
3014/* [R 4] debug only: SRC current credit. Transaction based. */
3015#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003016/* [RW 16] The Ethernet type value for L2 tag 0 */
3017#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
3018/* [RW 4] The length of the info field for L2 tag 0. The length is between
3019 * 2B and 14B; in 2B granularity */
3020#define PRS_REG_TAG_LEN_0 0x4022c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003021/* [R 8] debug only: TCM current credit. Cycle based. */
3022#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
3023/* [R 8] debug only: TSDM current credit. Transaction based. */
3024#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003025#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
3026#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
3027#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
3028#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
3029#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
3030#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3031#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003032/* [R 6] Debug only: Number of used entries in the data FIFO */
3033#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3034/* [R 7] Debug only: Number of used entries in the header FIFO */
Dmitry Kravkov9f0096a2011-08-09 03:10:29 +00003035#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
3036#define PXP2_REG_PGL_ADDR_88_F0 0x120534
3037/* [R 32] GRC address for configuration access to PCIE config address 0x88.
3038 * any write to this PCIE address will cause a GRC write access to the
3039 * address that's in t this register */
3040#define PXP2_REG_PGL_ADDR_88_F1 0x120544
3041#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3042/* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3043 * any write to this PCIE address will cause a GRC write access to the
3044 * address that's in t this register */
3045#define PXP2_REG_PGL_ADDR_8C_F1 0x120548
3046#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3047/* [R 32] GRC address for configuration access to PCIE config address 0x90.
3048 * any write to this PCIE address will cause a GRC write access to the
3049 * address that's in t this register */
3050#define PXP2_REG_PGL_ADDR_90_F1 0x12054c
3051#define PXP2_REG_PGL_ADDR_94_F0 0x120540
3052/* [R 32] GRC address for configuration access to PCIE config address 0x94.
3053 * any write to this PCIE address will cause a GRC write access to the
3054 * address that's in t this register */
3055#define PXP2_REG_PGL_ADDR_94_F1 0x120550
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003056#define PXP2_REG_PGL_CONTROL0 0x120490
3057#define PXP2_REG_PGL_CONTROL1 0x120514
Eilon Greensteinca003922009-08-12 22:53:28 -07003058#define PXP2_REG_PGL_DEBUG 0x120520
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003059/* [RW 32] third dword data of expansion rom request. this register is
3060 special. reading from it provides a vector outstanding read requests. if
3061 a bit is zero it means that a read request on the corresponding tag did
3062 not finish yet (not all completions have arrived for it) */
3063#define PXP2_REG_PGL_EXP_ROM2 0x120808
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003064/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3065 its[15:0]-address */
3066#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3067#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3068#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3069#define PXP2_REG_PGL_INT_CSDM_3 0x120500
3070#define PXP2_REG_PGL_INT_CSDM_4 0x120504
3071#define PXP2_REG_PGL_INT_CSDM_5 0x120508
3072#define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3073#define PXP2_REG_PGL_INT_CSDM_7 0x120510
3074/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3075 its[15:0]-address */
3076#define PXP2_REG_PGL_INT_TSDM_0 0x120494
3077#define PXP2_REG_PGL_INT_TSDM_1 0x120498
3078#define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3079#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3080#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3081#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3082#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3083#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3084/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3085 its[15:0]-address */
3086#define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3087#define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3088#define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3089#define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3090#define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3091#define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3092#define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3093#define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3094/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3095 its[15:0]-address */
3096#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3097#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3098#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3099#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3100#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3101#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3102#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3103#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
Eilon Greensteinf1ef27e2009-02-12 08:36:23 +00003104/* [RW 3] this field allows one function to pretend being another function
3105 when accessing any BAR mapped resource within the device. the value of
3106 the field is the number of the function that will be accessed
3107 effectively. after software write to this bit it must read it in order to
3108 know that the new value is updated */
3109#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3110#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3111#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3112#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3113#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3114#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3115#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3116#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003117/* [R 1] this bit indicates that a read request was blocked because of
3118 bus_master_en was deasserted */
3119#define PXP2_REG_PGL_READ_BLOCKED 0x120568
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003120#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003121/* [R 18] debug only */
3122#define PXP2_REG_PGL_TXW_CDTS 0x12052c
3123/* [R 1] this bit indicates that a write request was blocked because of
3124 bus_master_en was deasserted */
3125#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3126#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3127#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3128#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003129#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3130#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003131#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3132#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3133#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3134#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3135#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3136#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3137#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3138#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3139#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003140#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3141#define PXP2_REG_PSWRQ_BW_L28 0x120318
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003142#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3143#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3144#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3145#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3146#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3147#define PXP2_REG_PSWRQ_BW_RD 0x120324
3148#define PXP2_REG_PSWRQ_BW_UB1 0x120238
3149#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3150#define PXP2_REG_PSWRQ_BW_UB11 0x120260
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003151#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3152#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003153#define PXP2_REG_PSWRQ_BW_UB3 0x120240
3154#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3155#define PXP2_REG_PSWRQ_BW_UB7 0x120250
3156#define PXP2_REG_PSWRQ_BW_UB8 0x120254
3157#define PXP2_REG_PSWRQ_BW_UB9 0x120258
3158#define PXP2_REG_PSWRQ_BW_WR 0x120328
3159#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3160#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3161#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3162#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003163#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003164/* [RW 32] Interrupt mask register #0 read/write */
3165#define PXP2_REG_PXP2_INT_MASK_0 0x120578
3166/* [R 32] Interrupt register #0 read */
3167#define PXP2_REG_PXP2_INT_STS_0 0x12056c
3168#define PXP2_REG_PXP2_INT_STS_1 0x120608
3169/* [RC 32] Interrupt register #0 read clear */
3170#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003171/* [RW 32] Parity mask register #0 read/write */
3172#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3173#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
Eliezer Tamirf1410642008-02-28 11:51:50 -08003174/* [R 32] Parity register #0 read */
3175#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3176#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003177/* [RC 32] Parity register #0 read clear */
3178#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3179#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003180/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3181 indication about backpressure) */
3182#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3183/* [R 8] Debug only: The blocks counter - number of unused block ids */
3184#define PXP2_REG_RD_BLK_CNT 0x120418
3185/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3186 Must be bigger than 6. Normally should not be changed. */
3187#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3188/* [RW 2] CDU byte swapping mode configuration for master read requests */
3189#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3190/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3191#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3192/* [R 1] PSWRD internal memories initialization is done */
3193#define PXP2_REG_RD_INIT_DONE 0x120370
3194/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3195 allocated for vq10 */
3196#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3197/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3198 allocated for vq11 */
3199#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3200/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3201 allocated for vq17 */
3202#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3203/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3204 allocated for vq18 */
3205#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3206/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3207 allocated for vq19 */
3208#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3209/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3210 allocated for vq22 */
3211#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3212/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
Eilon Greensteinca003922009-08-12 22:53:28 -07003213 allocated for vq25 */
3214#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3215/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003216 allocated for vq6 */
3217#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3218/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3219 allocated for vq9 */
3220#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3221/* [RW 2] PBF byte swapping mode configuration for master read requests */
3222#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3223/* [R 1] Debug only: Indication if delivery ports are idle */
3224#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3225#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3226/* [RW 2] QM byte swapping mode configuration for master read requests */
3227#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3228/* [R 7] Debug only: The SR counter - number of unused sub request ids */
3229#define PXP2_REG_RD_SR_CNT 0x120414
3230/* [RW 2] SRC byte swapping mode configuration for master read requests */
3231#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3232/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3233 be bigger than 1. Normally should not be changed. */
3234#define PXP2_REG_RD_SR_NUM_CFG 0x120408
3235/* [RW 1] Signals the PSWRD block to start initializing internal memories */
3236#define PXP2_REG_RD_START_INIT 0x12036c
3237/* [RW 2] TM byte swapping mode configuration for master read requests */
3238#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3239/* [RW 10] Bandwidth addition to VQ0 write requests */
3240#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3241/* [RW 10] Bandwidth addition to VQ12 read requests */
3242#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3243/* [RW 10] Bandwidth addition to VQ13 read requests */
3244#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3245/* [RW 10] Bandwidth addition to VQ14 read requests */
3246#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3247/* [RW 10] Bandwidth addition to VQ15 read requests */
3248#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3249/* [RW 10] Bandwidth addition to VQ16 read requests */
3250#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3251/* [RW 10] Bandwidth addition to VQ17 read requests */
3252#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3253/* [RW 10] Bandwidth addition to VQ18 read requests */
3254#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3255/* [RW 10] Bandwidth addition to VQ19 read requests */
3256#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3257/* [RW 10] Bandwidth addition to VQ20 read requests */
3258#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3259/* [RW 10] Bandwidth addition to VQ22 read requests */
3260#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3261/* [RW 10] Bandwidth addition to VQ23 read requests */
3262#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3263/* [RW 10] Bandwidth addition to VQ24 read requests */
3264#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3265/* [RW 10] Bandwidth addition to VQ25 read requests */
3266#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3267/* [RW 10] Bandwidth addition to VQ26 read requests */
3268#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3269/* [RW 10] Bandwidth addition to VQ27 read requests */
3270#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3271/* [RW 10] Bandwidth addition to VQ4 read requests */
3272#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3273/* [RW 10] Bandwidth addition to VQ5 read requests */
3274#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3275/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3276#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3277/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3278#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3279/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3280#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3281/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3282#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3283/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3284#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3285/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3286#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3287/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3288#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3289/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3290#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3291/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3292#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3293/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3294#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3295/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3296#define PXP2_REG_RQ_BW_RD_L22 0x120300
3297/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3298#define PXP2_REG_RQ_BW_RD_L23 0x120304
3299/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3300#define PXP2_REG_RQ_BW_RD_L24 0x120308
3301/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3302#define PXP2_REG_RQ_BW_RD_L25 0x12030c
3303/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3304#define PXP2_REG_RQ_BW_RD_L26 0x120310
3305/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3306#define PXP2_REG_RQ_BW_RD_L27 0x120314
3307/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3308#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3309/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3310#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3311/* [RW 7] Bandwidth upper bound for VQ0 read requests */
3312#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3313/* [RW 7] Bandwidth upper bound for VQ12 read requests */
3314#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3315/* [RW 7] Bandwidth upper bound for VQ13 read requests */
3316#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3317/* [RW 7] Bandwidth upper bound for VQ14 read requests */
3318#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3319/* [RW 7] Bandwidth upper bound for VQ15 read requests */
3320#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3321/* [RW 7] Bandwidth upper bound for VQ16 read requests */
3322#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3323/* [RW 7] Bandwidth upper bound for VQ17 read requests */
3324#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3325/* [RW 7] Bandwidth upper bound for VQ18 read requests */
3326#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3327/* [RW 7] Bandwidth upper bound for VQ19 read requests */
3328#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3329/* [RW 7] Bandwidth upper bound for VQ20 read requests */
3330#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3331/* [RW 7] Bandwidth upper bound for VQ22 read requests */
3332#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3333/* [RW 7] Bandwidth upper bound for VQ23 read requests */
3334#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3335/* [RW 7] Bandwidth upper bound for VQ24 read requests */
3336#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3337/* [RW 7] Bandwidth upper bound for VQ25 read requests */
3338#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3339/* [RW 7] Bandwidth upper bound for VQ26 read requests */
3340#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3341/* [RW 7] Bandwidth upper bound for VQ27 read requests */
3342#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3343/* [RW 7] Bandwidth upper bound for VQ4 read requests */
3344#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3345/* [RW 7] Bandwidth upper bound for VQ5 read requests */
3346#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3347/* [RW 10] Bandwidth addition to VQ29 write requests */
3348#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3349/* [RW 10] Bandwidth addition to VQ30 write requests */
3350#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3351/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3352#define PXP2_REG_RQ_BW_WR_L29 0x12031c
3353/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3354#define PXP2_REG_RQ_BW_WR_L30 0x120320
3355/* [RW 7] Bandwidth upper bound for VQ29 */
3356#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3357/* [RW 7] Bandwidth upper bound for VQ30 */
3358#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003359/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3360#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003361/* [RW 2] Endian mode for cdu */
3362#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003363#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3364#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003365/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3366 -128k */
3367#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3368/* [R 1] 1' indicates that the requester has finished its internal
3369 configuration */
3370#define PXP2_REG_RQ_CFG_DONE 0x1201b4
3371/* [RW 2] Endian mode for debug */
3372#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3373/* [RW 1] When '1'; requests will enter input buffers but wont get out
3374 towards the glue */
3375#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003376/* [RW 4] Determines alignment of write SRs when a request is split into
3377 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3378 * aligned. 4 - 512B aligned. */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003379#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003380/* [RW 4] Determines alignment of read SRs when a request is split into
3381 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3382 * aligned. 4 - 512B aligned. */
3383#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3384/* [RW 1] when set the new alignment method (E2) will be applied; when reset
3385 * the original alignment method (E1 E1H) will be applied */
3386#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003387/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3388 be asserted */
3389#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003390/* [RW 2] Endian mode for hc */
3391#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003392/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3393 compatibility needs; Note that different registers are used per mode */
3394#define PXP2_REG_RQ_ILT_MODE 0x1205b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003395/* [WB 53] Onchip address table */
3396#define PXP2_REG_RQ_ONCHIP_AT 0x122000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003397/* [WB 53] Onchip address table - B0 */
3398#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
Eliezer Tamirf1410642008-02-28 11:51:50 -08003399/* [RW 13] Pending read limiter threshold; in Dwords */
3400#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003401/* [RW 2] Endian mode for qm */
3402#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003403#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3404#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003405/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3406 -128k */
3407#define PXP2_REG_RQ_QM_P_SIZE 0x120050
Eilon Greenstein33471622008-08-13 15:59:08 -07003408/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003409#define PXP2_REG_RQ_RBC_DONE 0x1201b0
3410/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3411 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3412#define PXP2_REG_RQ_RD_MBS0 0x120160
Eliezer Tamirf1410642008-02-28 11:51:50 -08003413/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3414 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3415#define PXP2_REG_RQ_RD_MBS1 0x120168
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003416/* [RW 2] Endian mode for src */
3417#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003418#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3419#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003420/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3421 -128k */
3422#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3423/* [RW 2] Endian mode for tm */
3424#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003425#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3426#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003427/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3428 -128k */
3429#define PXP2_REG_RQ_TM_P_SIZE 0x120034
3430/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3431#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003432/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3433#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003434/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3435#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3436/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3437#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3438/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3439#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3440/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3441#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3442/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3443#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3444/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3445#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3446/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3447#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3448/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3449#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3450/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3451#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3452/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3453#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3454/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3455#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3456/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3457#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3458/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3459#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3460/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3461#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3462/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3463#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3464/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3465#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3466/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3467#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3468/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3469#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3470/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3471#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3472/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3473#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3474/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3475#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3476/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3477#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3478/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3479#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3480/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3481#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3482/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3483#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3484/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3485#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3486/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3487#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3488/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3489#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3490/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3491#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3492/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3493#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3494/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3495#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3496/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3497#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3498/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3499 001:256B; 010: 512B; */
3500#define PXP2_REG_RQ_WR_MBS0 0x12015c
Eliezer Tamirf1410642008-02-28 11:51:50 -08003501/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3502 001:256B; 010: 512B; */
3503#define PXP2_REG_RQ_WR_MBS1 0x120164
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003504/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3505 buffer reaches this number has_payload will be asserted */
3506#define PXP2_REG_WR_CDU_MPS 0x1205f0
3507/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3508 buffer reaches this number has_payload will be asserted */
3509#define PXP2_REG_WR_CSDM_MPS 0x1205d0
3510/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3511 buffer reaches this number has_payload will be asserted */
3512#define PXP2_REG_WR_DBG_MPS 0x1205e8
3513/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3514 buffer reaches this number has_payload will be asserted */
3515#define PXP2_REG_WR_DMAE_MPS 0x1205ec
Eilon Greenstein33471622008-08-13 15:59:08 -07003516/* [RW 10] if Number of entries in dmae fifo will be higher than this
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003517 threshold then has_payload indication will be asserted; the default value
3518 should be equal to &gt; write MBS size! */
3519#define PXP2_REG_WR_DMAE_TH 0x120368
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003520/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3521 buffer reaches this number has_payload will be asserted */
3522#define PXP2_REG_WR_HC_MPS 0x1205c8
3523/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3524 buffer reaches this number has_payload will be asserted */
3525#define PXP2_REG_WR_QM_MPS 0x1205dc
3526/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3527#define PXP2_REG_WR_REV_MODE 0x120670
3528/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3529 buffer reaches this number has_payload will be asserted */
3530#define PXP2_REG_WR_SRC_MPS 0x1205e4
3531/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3532 buffer reaches this number has_payload will be asserted */
3533#define PXP2_REG_WR_TM_MPS 0x1205e0
3534/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3535 buffer reaches this number has_payload will be asserted */
3536#define PXP2_REG_WR_TSDM_MPS 0x1205d4
Eilon Greenstein33471622008-08-13 15:59:08 -07003537/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
Eliezer Tamirf1410642008-02-28 11:51:50 -08003538 threshold then has_payload indication will be asserted; the default value
3539 should be equal to &gt; write MBS size! */
3540#define PXP2_REG_WR_USDMDP_TH 0x120348
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003541/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3542 buffer reaches this number has_payload will be asserted */
3543#define PXP2_REG_WR_USDM_MPS 0x1205cc
3544/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3545 buffer reaches this number has_payload will be asserted */
3546#define PXP2_REG_WR_XSDM_MPS 0x1205d8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003547/* [R 1] debug only: Indication if PSWHST arbiter is idle */
3548#define PXP_REG_HST_ARB_IS_IDLE 0x103004
3549/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3550 this client is waiting for the arbiter. */
3551#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003552/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3553 block. Should be used for close the gates. */
3554#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003555/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
Lucas De Marchi25985ed2011-03-30 22:57:33 -03003556 should update according to 'hst_discard_doorbells' register when the state
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003557 machine is idle */
3558#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003559/* [RW 1] When 1; new internal writes arriving to the block are discarded.
3560 Should be used for close the gates. */
3561#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003562/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3563 means this PSWHST is discarding inputs from this client. Each bit should
Lucas De Marchi25985ed2011-03-30 22:57:33 -03003564 update according to 'hst_discard_internal_writes' register when the state
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003565 machine is idle. */
3566#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003567/* [WB 160] Used for initialization of the inbound interrupts memory */
3568#define PXP_REG_HST_INBOUND_INT 0x103800
3569/* [RW 32] Interrupt mask register #0 read/write */
3570#define PXP_REG_PXP_INT_MASK_0 0x103074
3571#define PXP_REG_PXP_INT_MASK_1 0x103084
3572/* [R 32] Interrupt register #0 read */
3573#define PXP_REG_PXP_INT_STS_0 0x103068
3574#define PXP_REG_PXP_INT_STS_1 0x103078
3575/* [RC 32] Interrupt register #0 read clear */
3576#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003577#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3578/* [RW 27] Parity mask register #0 read/write */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003579#define PXP_REG_PXP_PRTY_MASK 0x103094
Eliezer Tamirf1410642008-02-28 11:51:50 -08003580/* [R 26] Parity register #0 read */
3581#define PXP_REG_PXP_PRTY_STS 0x103088
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003582/* [RC 27] Parity register #0 read clear */
3583#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003584/* [RW 4] The activity counter initial increment value sent in the load
3585 request */
3586#define QM_REG_ACTCTRINITVAL_0 0x168040
3587#define QM_REG_ACTCTRINITVAL_1 0x168044
3588#define QM_REG_ACTCTRINITVAL_2 0x168048
3589#define QM_REG_ACTCTRINITVAL_3 0x16804c
3590/* [RW 32] The base logical address (in bytes) of each physical queue. The
3591 index I represents the physical queue number. The 12 lsbs are ignore and
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003592 considered zero so practically there are only 20 bits in this register;
3593 queues 63-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003594#define QM_REG_BASEADDR 0x168900
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08003595/* [RW 32] The base logical address (in bytes) of each physical queue. The
3596 index I represents the physical queue number. The 12 lsbs are ignore and
3597 considered zero so practically there are only 20 bits in this register;
3598 queues 127-64 */
3599#define QM_REG_BASEADDR_EXT_A 0x16e100
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003600/* [RW 16] The byte credit cost for each task. This value is for both ports */
3601#define QM_REG_BYTECRDCOST 0x168234
3602/* [RW 16] The initial byte credit value for both ports. */
3603#define QM_REG_BYTECRDINITVAL 0x168238
3604/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003605 queue uses port 0 else it uses port 1; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003606#define QM_REG_BYTECRDPORT_LSB 0x168228
3607/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003608 queue uses port 0 else it uses port 1; queues 95-64 */
3609#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3610/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3611 queue uses port 0 else it uses port 1; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003612#define QM_REG_BYTECRDPORT_MSB 0x168224
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003613/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3614 queue uses port 0 else it uses port 1; queues 127-96 */
3615#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003616/* [RW 16] The byte credit value that if above the QM is considered almost
3617 full */
3618#define QM_REG_BYTECREDITAFULLTHR 0x168094
3619/* [RW 4] The initial credit for interface */
3620#define QM_REG_CMINITCRD_0 0x1680cc
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003621#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003622#define QM_REG_CMINITCRD_1 0x1680d0
3623#define QM_REG_CMINITCRD_2 0x1680d4
3624#define QM_REG_CMINITCRD_3 0x1680d8
3625#define QM_REG_CMINITCRD_4 0x1680dc
3626#define QM_REG_CMINITCRD_5 0x1680e0
3627#define QM_REG_CMINITCRD_6 0x1680e4
3628#define QM_REG_CMINITCRD_7 0x1680e8
3629/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3630 is masked */
3631#define QM_REG_CMINTEN 0x1680ec
3632/* [RW 12] A bit vector which indicates which one of the queues are tied to
3633 interface 0 */
3634#define QM_REG_CMINTVOQMASK_0 0x1681f4
3635#define QM_REG_CMINTVOQMASK_1 0x1681f8
3636#define QM_REG_CMINTVOQMASK_2 0x1681fc
3637#define QM_REG_CMINTVOQMASK_3 0x168200
3638#define QM_REG_CMINTVOQMASK_4 0x168204
3639#define QM_REG_CMINTVOQMASK_5 0x168208
3640#define QM_REG_CMINTVOQMASK_6 0x16820c
3641#define QM_REG_CMINTVOQMASK_7 0x168210
3642/* [RW 20] The number of connections divided by 16 which dictates the size
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003643 of each queue which belongs to even function number. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003644#define QM_REG_CONNNUM_0 0x168020
3645/* [R 6] Keep the fill level of the fifo from write client 4 */
3646#define QM_REG_CQM_WRC_FIFOLVL 0x168018
3647/* [RW 8] The context regions sent in the CFC load request */
3648#define QM_REG_CTXREG_0 0x168030
3649#define QM_REG_CTXREG_1 0x168034
3650#define QM_REG_CTXREG_2 0x168038
3651#define QM_REG_CTXREG_3 0x16803c
3652/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3653 bypass enable */
3654#define QM_REG_ENBYPVOQMASK 0x16823c
3655/* [RW 32] A bit mask per each physical queue. If a bit is set then the
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003656 physical queue uses the byte credit; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003657#define QM_REG_ENBYTECRD_LSB 0x168220
3658/* [RW 32] A bit mask per each physical queue. If a bit is set then the
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003659 physical queue uses the byte credit; queues 95-64 */
3660#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3661/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3662 physical queue uses the byte credit; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003663#define QM_REG_ENBYTECRD_MSB 0x16821c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003664/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3665 physical queue uses the byte credit; queues 127-96 */
3666#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003667/* [RW 4] If cleared then the secondary interface will not be served by the
3668 RR arbiter */
3669#define QM_REG_ENSEC 0x1680f0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003670/* [RW 32] NA */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003671#define QM_REG_FUNCNUMSEL_LSB 0x168230
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003672/* [RW 32] NA */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003673#define QM_REG_FUNCNUMSEL_MSB 0x16822c
3674/* [RW 32] A mask register to mask the Almost empty signals which will not
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003675 be use for the almost empty indication to the HW block; queues 31:0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003676#define QM_REG_HWAEMPTYMASK_LSB 0x168218
3677/* [RW 32] A mask register to mask the Almost empty signals which will not
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003678 be use for the almost empty indication to the HW block; queues 95-64 */
3679#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3680/* [RW 32] A mask register to mask the Almost empty signals which will not
3681 be use for the almost empty indication to the HW block; queues 63:32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003682#define QM_REG_HWAEMPTYMASK_MSB 0x168214
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003683/* [RW 32] A mask register to mask the Almost empty signals which will not
3684 be use for the almost empty indication to the HW block; queues 127-96 */
3685#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003686/* [RW 4] The number of outstanding request to CFC */
3687#define QM_REG_OUTLDREQ 0x168804
3688/* [RC 1] A flag to indicate that overflow error occurred in one of the
3689 queues. */
3690#define QM_REG_OVFERROR 0x16805c
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02003691/* [RC 7] the Q where the overflow occurs */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003692#define QM_REG_OVFQNUM 0x168058
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003693/* [R 16] Pause state for physical queues 15-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003694#define QM_REG_PAUSESTATE0 0x168410
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003695/* [R 16] Pause state for physical queues 31-16 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003696#define QM_REG_PAUSESTATE1 0x168414
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003697/* [R 16] Pause state for physical queues 47-32 */
3698#define QM_REG_PAUSESTATE2 0x16e684
3699/* [R 16] Pause state for physical queues 63-48 */
3700#define QM_REG_PAUSESTATE3 0x16e688
3701/* [R 16] Pause state for physical queues 79-64 */
3702#define QM_REG_PAUSESTATE4 0x16e68c
3703/* [R 16] Pause state for physical queues 95-80 */
3704#define QM_REG_PAUSESTATE5 0x16e690
3705/* [R 16] Pause state for physical queues 111-96 */
3706#define QM_REG_PAUSESTATE6 0x16e694
3707/* [R 16] Pause state for physical queues 127-112 */
3708#define QM_REG_PAUSESTATE7 0x16e698
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003709/* [RW 2] The PCI attributes field used in the PCI request. */
3710#define QM_REG_PCIREQAT 0x168054
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003711#define QM_REG_PF_EN 0x16e70c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003712/* [R 24] The number of tasks stored in the QM for the PF. only even
3713 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3714#define QM_REG_PF_USG_CNT_0 0x16e040
3715/* [R 16] NOT USED */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003716#define QM_REG_PORT0BYTECRD 0x168300
3717/* [R 16] The byte credit of port 1 */
3718#define QM_REG_PORT1BYTECRD 0x168304
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003719/* [RW 3] pci function number of queues 15-0 */
3720#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3721#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3722#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3723#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3724#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3725#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3726#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3727#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3728/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3729 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3730 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003731#define QM_REG_PTRTBL 0x168a00
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003732/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3733 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3734 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3735#define QM_REG_PTRTBL_EXT_A 0x16e200
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003736/* [RW 2] Interrupt mask register #0 read/write */
3737#define QM_REG_QM_INT_MASK 0x168444
3738/* [R 2] Interrupt register #0 read */
3739#define QM_REG_QM_INT_STS 0x168438
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003740/* [RW 12] Parity mask register #0 read/write */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003741#define QM_REG_QM_PRTY_MASK 0x168454
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003742/* [R 12] Parity register #0 read */
Eliezer Tamirf1410642008-02-28 11:51:50 -08003743#define QM_REG_QM_PRTY_STS 0x168448
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003744/* [RC 12] Parity register #0 read clear */
3745#define QM_REG_QM_PRTY_STS_CLR 0x16844c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003746/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3747#define QM_REG_QSTATUS_HIGH 0x16802c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003748/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3749#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003750/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3751#define QM_REG_QSTATUS_LOW 0x168028
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003752/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3753#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3754/* [R 24] The number of tasks queued for each queue; queues 63-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003755#define QM_REG_QTASKCTR_0 0x168308
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003756/* [R 24] The number of tasks queued for each queue; queues 127-64 */
3757#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003758/* [RW 4] Queue tied to VOQ */
3759#define QM_REG_QVOQIDX_0 0x1680f4
3760#define QM_REG_QVOQIDX_10 0x16811c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003761#define QM_REG_QVOQIDX_100 0x16e49c
3762#define QM_REG_QVOQIDX_101 0x16e4a0
3763#define QM_REG_QVOQIDX_102 0x16e4a4
3764#define QM_REG_QVOQIDX_103 0x16e4a8
3765#define QM_REG_QVOQIDX_104 0x16e4ac
3766#define QM_REG_QVOQIDX_105 0x16e4b0
3767#define QM_REG_QVOQIDX_106 0x16e4b4
3768#define QM_REG_QVOQIDX_107 0x16e4b8
3769#define QM_REG_QVOQIDX_108 0x16e4bc
3770#define QM_REG_QVOQIDX_109 0x16e4c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003771#define QM_REG_QVOQIDX_11 0x168120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003772#define QM_REG_QVOQIDX_110 0x16e4c4
3773#define QM_REG_QVOQIDX_111 0x16e4c8
3774#define QM_REG_QVOQIDX_112 0x16e4cc
3775#define QM_REG_QVOQIDX_113 0x16e4d0
3776#define QM_REG_QVOQIDX_114 0x16e4d4
3777#define QM_REG_QVOQIDX_115 0x16e4d8
3778#define QM_REG_QVOQIDX_116 0x16e4dc
3779#define QM_REG_QVOQIDX_117 0x16e4e0
3780#define QM_REG_QVOQIDX_118 0x16e4e4
3781#define QM_REG_QVOQIDX_119 0x16e4e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003782#define QM_REG_QVOQIDX_12 0x168124
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003783#define QM_REG_QVOQIDX_120 0x16e4ec
3784#define QM_REG_QVOQIDX_121 0x16e4f0
3785#define QM_REG_QVOQIDX_122 0x16e4f4
3786#define QM_REG_QVOQIDX_123 0x16e4f8
3787#define QM_REG_QVOQIDX_124 0x16e4fc
3788#define QM_REG_QVOQIDX_125 0x16e500
3789#define QM_REG_QVOQIDX_126 0x16e504
3790#define QM_REG_QVOQIDX_127 0x16e508
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003791#define QM_REG_QVOQIDX_13 0x168128
3792#define QM_REG_QVOQIDX_14 0x16812c
3793#define QM_REG_QVOQIDX_15 0x168130
3794#define QM_REG_QVOQIDX_16 0x168134
3795#define QM_REG_QVOQIDX_17 0x168138
3796#define QM_REG_QVOQIDX_21 0x168148
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003797#define QM_REG_QVOQIDX_22 0x16814c
3798#define QM_REG_QVOQIDX_23 0x168150
3799#define QM_REG_QVOQIDX_24 0x168154
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003800#define QM_REG_QVOQIDX_25 0x168158
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003801#define QM_REG_QVOQIDX_26 0x16815c
3802#define QM_REG_QVOQIDX_27 0x168160
3803#define QM_REG_QVOQIDX_28 0x168164
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003804#define QM_REG_QVOQIDX_29 0x168168
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003805#define QM_REG_QVOQIDX_30 0x16816c
3806#define QM_REG_QVOQIDX_31 0x168170
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003807#define QM_REG_QVOQIDX_32 0x168174
3808#define QM_REG_QVOQIDX_33 0x168178
3809#define QM_REG_QVOQIDX_34 0x16817c
3810#define QM_REG_QVOQIDX_35 0x168180
3811#define QM_REG_QVOQIDX_36 0x168184
3812#define QM_REG_QVOQIDX_37 0x168188
3813#define QM_REG_QVOQIDX_38 0x16818c
3814#define QM_REG_QVOQIDX_39 0x168190
3815#define QM_REG_QVOQIDX_40 0x168194
3816#define QM_REG_QVOQIDX_41 0x168198
3817#define QM_REG_QVOQIDX_42 0x16819c
3818#define QM_REG_QVOQIDX_43 0x1681a0
3819#define QM_REG_QVOQIDX_44 0x1681a4
3820#define QM_REG_QVOQIDX_45 0x1681a8
3821#define QM_REG_QVOQIDX_46 0x1681ac
3822#define QM_REG_QVOQIDX_47 0x1681b0
3823#define QM_REG_QVOQIDX_48 0x1681b4
3824#define QM_REG_QVOQIDX_49 0x1681b8
3825#define QM_REG_QVOQIDX_5 0x168108
3826#define QM_REG_QVOQIDX_50 0x1681bc
3827#define QM_REG_QVOQIDX_51 0x1681c0
3828#define QM_REG_QVOQIDX_52 0x1681c4
3829#define QM_REG_QVOQIDX_53 0x1681c8
3830#define QM_REG_QVOQIDX_54 0x1681cc
3831#define QM_REG_QVOQIDX_55 0x1681d0
3832#define QM_REG_QVOQIDX_56 0x1681d4
3833#define QM_REG_QVOQIDX_57 0x1681d8
3834#define QM_REG_QVOQIDX_58 0x1681dc
3835#define QM_REG_QVOQIDX_59 0x1681e0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003836#define QM_REG_QVOQIDX_6 0x16810c
3837#define QM_REG_QVOQIDX_60 0x1681e4
3838#define QM_REG_QVOQIDX_61 0x1681e8
3839#define QM_REG_QVOQIDX_62 0x1681ec
3840#define QM_REG_QVOQIDX_63 0x1681f0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003841#define QM_REG_QVOQIDX_64 0x16e40c
3842#define QM_REG_QVOQIDX_65 0x16e410
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003843#define QM_REG_QVOQIDX_69 0x16e420
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003844#define QM_REG_QVOQIDX_7 0x168110
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003845#define QM_REG_QVOQIDX_70 0x16e424
3846#define QM_REG_QVOQIDX_71 0x16e428
3847#define QM_REG_QVOQIDX_72 0x16e42c
3848#define QM_REG_QVOQIDX_73 0x16e430
3849#define QM_REG_QVOQIDX_74 0x16e434
3850#define QM_REG_QVOQIDX_75 0x16e438
3851#define QM_REG_QVOQIDX_76 0x16e43c
3852#define QM_REG_QVOQIDX_77 0x16e440
3853#define QM_REG_QVOQIDX_78 0x16e444
3854#define QM_REG_QVOQIDX_79 0x16e448
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003855#define QM_REG_QVOQIDX_8 0x168114
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003856#define QM_REG_QVOQIDX_80 0x16e44c
3857#define QM_REG_QVOQIDX_81 0x16e450
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003858#define QM_REG_QVOQIDX_85 0x16e460
3859#define QM_REG_QVOQIDX_86 0x16e464
3860#define QM_REG_QVOQIDX_87 0x16e468
3861#define QM_REG_QVOQIDX_88 0x16e46c
3862#define QM_REG_QVOQIDX_89 0x16e470
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003863#define QM_REG_QVOQIDX_9 0x168118
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003864#define QM_REG_QVOQIDX_90 0x16e474
3865#define QM_REG_QVOQIDX_91 0x16e478
3866#define QM_REG_QVOQIDX_92 0x16e47c
3867#define QM_REG_QVOQIDX_93 0x16e480
3868#define QM_REG_QVOQIDX_94 0x16e484
3869#define QM_REG_QVOQIDX_95 0x16e488
3870#define QM_REG_QVOQIDX_96 0x16e48c
3871#define QM_REG_QVOQIDX_97 0x16e490
3872#define QM_REG_QVOQIDX_98 0x16e494
3873#define QM_REG_QVOQIDX_99 0x16e498
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003874/* [RW 1] Initialization bit command */
3875#define QM_REG_SOFT_RESET 0x168428
3876/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3877#define QM_REG_TASKCRDCOST_0 0x16809c
3878#define QM_REG_TASKCRDCOST_1 0x1680a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003879#define QM_REG_TASKCRDCOST_2 0x1680a4
3880#define QM_REG_TASKCRDCOST_4 0x1680ac
3881#define QM_REG_TASKCRDCOST_5 0x1680b0
3882/* [R 6] Keep the fill level of the fifo from write client 3 */
3883#define QM_REG_TQM_WRC_FIFOLVL 0x168010
3884/* [R 6] Keep the fill level of the fifo from write client 2 */
3885#define QM_REG_UQM_WRC_FIFOLVL 0x168008
3886/* [RC 32] Credit update error register */
3887#define QM_REG_VOQCRDERRREG 0x168408
3888/* [R 16] The credit value for each VOQ */
3889#define QM_REG_VOQCREDIT_0 0x1682d0
3890#define QM_REG_VOQCREDIT_1 0x1682d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003891#define QM_REG_VOQCREDIT_4 0x1682e0
3892/* [RW 16] The credit value that if above the QM is considered almost full */
3893#define QM_REG_VOQCREDITAFULLTHR 0x168090
3894/* [RW 16] The init and maximum credit for each VoQ */
3895#define QM_REG_VOQINITCREDIT_0 0x168060
3896#define QM_REG_VOQINITCREDIT_1 0x168064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003897#define QM_REG_VOQINITCREDIT_2 0x168068
3898#define QM_REG_VOQINITCREDIT_4 0x168070
3899#define QM_REG_VOQINITCREDIT_5 0x168074
3900/* [RW 1] The port of which VOQ belongs */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003901#define QM_REG_VOQPORT_0 0x1682a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003902#define QM_REG_VOQPORT_1 0x1682a4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003903#define QM_REG_VOQPORT_2 0x1682a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003904/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003905#define QM_REG_VOQQMASK_0_LSB 0x168240
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003906/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3907#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3908/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003909#define QM_REG_VOQQMASK_0_MSB 0x168244
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003910/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3911#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3912/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3913#define QM_REG_VOQQMASK_10_LSB 0x168290
3914/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3915#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3916/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3917#define QM_REG_VOQQMASK_10_MSB 0x168294
3918/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3919#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3920/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3921#define QM_REG_VOQQMASK_11_LSB 0x168298
3922/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3923#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3924/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3925#define QM_REG_VOQQMASK_11_MSB 0x16829c
3926/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3927#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3928/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3929#define QM_REG_VOQQMASK_1_LSB 0x168248
3930/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3931#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3932/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003933#define QM_REG_VOQQMASK_1_MSB 0x16824c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003934/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3935#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3936/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003937#define QM_REG_VOQQMASK_2_LSB 0x168250
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003938/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3939#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3940/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003941#define QM_REG_VOQQMASK_2_MSB 0x168254
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003942/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3943#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3944/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003945#define QM_REG_VOQQMASK_3_LSB 0x168258
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003946/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3947#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3948/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3949#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3950/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003951#define QM_REG_VOQQMASK_4_LSB 0x168260
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003952/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3953#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3954/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003955#define QM_REG_VOQQMASK_4_MSB 0x168264
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003956/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3957#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3958/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003959#define QM_REG_VOQQMASK_5_LSB 0x168268
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003960/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3961#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3962/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003963#define QM_REG_VOQQMASK_5_MSB 0x16826c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003964/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3965#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3966/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003967#define QM_REG_VOQQMASK_6_LSB 0x168270
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003968/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3969#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3970/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003971#define QM_REG_VOQQMASK_6_MSB 0x168274
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003972/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3973#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3974/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003975#define QM_REG_VOQQMASK_7_LSB 0x168278
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003976/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3977#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3978/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003979#define QM_REG_VOQQMASK_7_MSB 0x16827c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003980/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3981#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3982/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003983#define QM_REG_VOQQMASK_8_LSB 0x168280
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003984/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3985#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3986/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003987#define QM_REG_VOQQMASK_8_MSB 0x168284
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003988/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3989#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3990/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003991#define QM_REG_VOQQMASK_9_LSB 0x168288
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003992/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3993#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3994/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3995#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003996/* [RW 32] Wrr weights */
3997#define QM_REG_WRRWEIGHTS_0 0x16880c
3998#define QM_REG_WRRWEIGHTS_1 0x168810
3999#define QM_REG_WRRWEIGHTS_10 0x168814
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004000#define QM_REG_WRRWEIGHTS_11 0x168818
4001#define QM_REG_WRRWEIGHTS_12 0x16881c
4002#define QM_REG_WRRWEIGHTS_13 0x168820
4003#define QM_REG_WRRWEIGHTS_14 0x168824
4004#define QM_REG_WRRWEIGHTS_15 0x168828
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004005#define QM_REG_WRRWEIGHTS_16 0x16e000
4006#define QM_REG_WRRWEIGHTS_17 0x16e004
4007#define QM_REG_WRRWEIGHTS_18 0x16e008
4008#define QM_REG_WRRWEIGHTS_19 0x16e00c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004009#define QM_REG_WRRWEIGHTS_2 0x16882c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004010#define QM_REG_WRRWEIGHTS_20 0x16e010
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004011#define QM_REG_WRRWEIGHTS_21 0x16e014
4012#define QM_REG_WRRWEIGHTS_22 0x16e018
4013#define QM_REG_WRRWEIGHTS_23 0x16e01c
4014#define QM_REG_WRRWEIGHTS_24 0x16e020
4015#define QM_REG_WRRWEIGHTS_25 0x16e024
4016#define QM_REG_WRRWEIGHTS_26 0x16e028
4017#define QM_REG_WRRWEIGHTS_27 0x16e02c
4018#define QM_REG_WRRWEIGHTS_28 0x16e030
4019#define QM_REG_WRRWEIGHTS_29 0x16e034
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004020#define QM_REG_WRRWEIGHTS_3 0x168830
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004021#define QM_REG_WRRWEIGHTS_30 0x16e038
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004022#define QM_REG_WRRWEIGHTS_31 0x16e03c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004023#define QM_REG_WRRWEIGHTS_4 0x168834
4024#define QM_REG_WRRWEIGHTS_5 0x168838
4025#define QM_REG_WRRWEIGHTS_6 0x16883c
4026#define QM_REG_WRRWEIGHTS_7 0x168840
4027#define QM_REG_WRRWEIGHTS_8 0x168844
4028#define QM_REG_WRRWEIGHTS_9 0x168848
4029/* [R 6] Keep the fill level of the fifo from write client 1 */
4030#define QM_REG_XQM_WRC_FIFOLVL 0x168000
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004031/* [W 1] reset to parity interrupt */
4032#define SEM_FAST_REG_PARITY_RST 0x18840
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004033#define SRC_REG_COUNTFREE0 0x40500
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004034/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4035 ports. If set the searcher support 8 functions. */
4036#define SRC_REG_E1HMF_ENABLE 0x404cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004037#define SRC_REG_FIRSTFREE0 0x40510
4038#define SRC_REG_KEYRSS0_0 0x40408
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004039#define SRC_REG_KEYRSS0_7 0x40424
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004040#define SRC_REG_KEYRSS1_9 0x40454
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004041#define SRC_REG_KEYSEARCH_0 0x40458
4042#define SRC_REG_KEYSEARCH_1 0x4045c
4043#define SRC_REG_KEYSEARCH_2 0x40460
4044#define SRC_REG_KEYSEARCH_3 0x40464
4045#define SRC_REG_KEYSEARCH_4 0x40468
4046#define SRC_REG_KEYSEARCH_5 0x4046c
4047#define SRC_REG_KEYSEARCH_6 0x40470
4048#define SRC_REG_KEYSEARCH_7 0x40474
4049#define SRC_REG_KEYSEARCH_8 0x40478
4050#define SRC_REG_KEYSEARCH_9 0x4047c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004051#define SRC_REG_LASTFREE0 0x40530
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004052#define SRC_REG_NUMBER_HASH_BITS0 0x40400
4053/* [RW 1] Reset internal state machines. */
4054#define SRC_REG_SOFT_RST 0x4049c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004055/* [R 3] Interrupt register #0 read */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004056#define SRC_REG_SRC_INT_STS 0x404ac
4057/* [RW 3] Parity mask register #0 read/write */
4058#define SRC_REG_SRC_PRTY_MASK 0x404c8
Eliezer Tamirf1410642008-02-28 11:51:50 -08004059/* [R 3] Parity register #0 read */
4060#define SRC_REG_SRC_PRTY_STS 0x404bc
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004061/* [RC 3] Parity register #0 read clear */
4062#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004063/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4064#define TCM_REG_CAM_OCCUP 0x5017c
4065/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4066 disregarded; valid output is deasserted; all other signals are treated as
4067 usual; if 1 - normal activity. */
4068#define TCM_REG_CDU_AG_RD_IFEN 0x50034
4069/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4070 are disregarded; all other signals are treated as usual; if 1 - normal
4071 activity. */
4072#define TCM_REG_CDU_AG_WR_IFEN 0x50030
4073/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4074 disregarded; valid output is deasserted; all other signals are treated as
4075 usual; if 1 - normal activity. */
4076#define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4077/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4078 input is disregarded; all other signals are treated as usual; if 1 -
4079 normal activity. */
4080#define TCM_REG_CDU_SM_WR_IFEN 0x50038
4081/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4082 the initial credit value; read returns the current value of the credit
4083 counter. Must be initialized to 1 at start-up. */
4084#define TCM_REG_CFC_INIT_CRD 0x50204
4085/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4086 weight 8 (the most prioritised); 1 stands for weight 1(least
4087 prioritised); 2 stands for weight 2; tc. */
4088#define TCM_REG_CP_WEIGHT 0x500c0
4089/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4090 disregarded; acknowledge output is deasserted; all other signals are
4091 treated as usual; if 1 - normal activity. */
4092#define TCM_REG_CSEM_IFEN 0x5002c
4093/* [RC 1] Message length mismatch (relative to last indication) at the In#9
4094 interface. */
4095#define TCM_REG_CSEM_LENGTH_MIS 0x50174
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004096/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4097 weight 8 (the most prioritised); 1 stands for weight 1(least
4098 prioritised); 2 stands for weight 2; tc. */
4099#define TCM_REG_CSEM_WEIGHT 0x500bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004100/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4101#define TCM_REG_ERR_EVNT_ID 0x500a0
4102/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4103#define TCM_REG_ERR_TCM_HDR 0x5009c
4104/* [RW 8] The Event ID for Timers expiration. */
4105#define TCM_REG_EXPR_EVNT_ID 0x500a4
4106/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4107 writes the initial credit value; read returns the current value of the
4108 credit counter. Must be initialized to 64 at start-up. */
4109#define TCM_REG_FIC0_INIT_CRD 0x5020c
4110/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4111 writes the initial credit value; read returns the current value of the
4112 credit counter. Must be initialized to 64 at start-up. */
4113#define TCM_REG_FIC1_INIT_CRD 0x50210
4114/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4115 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4116 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4117 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4118#define TCM_REG_GR_ARB_TYPE 0x50114
4119/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4120 highest priority is 3. It is supposed that the Store channel is the
4121 compliment of the other 3 groups. */
4122#define TCM_REG_GR_LD0_PR 0x5011c
4123/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4124 highest priority is 3. It is supposed that the Store channel is the
4125 compliment of the other 3 groups. */
4126#define TCM_REG_GR_LD1_PR 0x50120
4127/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4128 sent to STORM; for a specific connection type. The double REG-pairs are
4129 used to align to STORM context row size of 128 bits. The offset of these
4130 data in the STORM context is always 0. Index _i stands for the connection
4131 type (one of 16). */
4132#define TCM_REG_N_SM_CTX_LD_0 0x50050
4133#define TCM_REG_N_SM_CTX_LD_1 0x50054
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004134#define TCM_REG_N_SM_CTX_LD_2 0x50058
4135#define TCM_REG_N_SM_CTX_LD_3 0x5005c
4136#define TCM_REG_N_SM_CTX_LD_4 0x50060
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004137#define TCM_REG_N_SM_CTX_LD_5 0x50064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004138/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4139 acknowledge output is deasserted; all other signals are treated as usual;
4140 if 1 - normal activity. */
4141#define TCM_REG_PBF_IFEN 0x50024
4142/* [RC 1] Message length mismatch (relative to last indication) at the In#7
4143 interface. */
4144#define TCM_REG_PBF_LENGTH_MIS 0x5016c
4145/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4146 weight 8 (the most prioritised); 1 stands for weight 1(least
4147 prioritised); 2 stands for weight 2; tc. */
4148#define TCM_REG_PBF_WEIGHT 0x500b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004149#define TCM_REG_PHYS_QNUM0_0 0x500e0
4150#define TCM_REG_PHYS_QNUM0_1 0x500e4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004151#define TCM_REG_PHYS_QNUM1_0 0x500e8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004152#define TCM_REG_PHYS_QNUM1_1 0x500ec
4153#define TCM_REG_PHYS_QNUM2_0 0x500f0
4154#define TCM_REG_PHYS_QNUM2_1 0x500f4
4155#define TCM_REG_PHYS_QNUM3_0 0x500f8
4156#define TCM_REG_PHYS_QNUM3_1 0x500fc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004157/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4158 acknowledge output is deasserted; all other signals are treated as usual;
4159 if 1 - normal activity. */
4160#define TCM_REG_PRS_IFEN 0x50020
4161/* [RC 1] Message length mismatch (relative to last indication) at the In#6
4162 interface. */
4163#define TCM_REG_PRS_LENGTH_MIS 0x50168
4164/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4165 weight 8 (the most prioritised); 1 stands for weight 1(least
4166 prioritised); 2 stands for weight 2; tc. */
4167#define TCM_REG_PRS_WEIGHT 0x500b0
4168/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4169#define TCM_REG_STOP_EVNT_ID 0x500a8
4170/* [RC 1] Message length mismatch (relative to last indication) at the STORM
4171 interface. */
4172#define TCM_REG_STORM_LENGTH_MIS 0x50160
4173/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4174 disregarded; acknowledge output is deasserted; all other signals are
4175 treated as usual; if 1 - normal activity. */
4176#define TCM_REG_STORM_TCM_IFEN 0x50010
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004177/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4178 weight 8 (the most prioritised); 1 stands for weight 1(least
4179 prioritised); 2 stands for weight 2; tc. */
4180#define TCM_REG_STORM_WEIGHT 0x500ac
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004181/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4182 acknowledge output is deasserted; all other signals are treated as usual;
4183 if 1 - normal activity. */
4184#define TCM_REG_TCM_CFC_IFEN 0x50040
4185/* [RW 11] Interrupt mask register #0 read/write */
4186#define TCM_REG_TCM_INT_MASK 0x501dc
4187/* [R 11] Interrupt register #0 read */
4188#define TCM_REG_TCM_INT_STS 0x501d0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004189/* [RW 27] Parity mask register #0 read/write */
4190#define TCM_REG_TCM_PRTY_MASK 0x501ec
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004191/* [R 27] Parity register #0 read */
4192#define TCM_REG_TCM_PRTY_STS 0x501e0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004193/* [RC 27] Parity register #0 read clear */
4194#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004195/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4196 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4197 Is used to determine the number of the AG context REG-pairs written back;
4198 when the input message Reg1WbFlg isn't set. */
4199#define TCM_REG_TCM_REG0_SZ 0x500d8
4200/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4201 disregarded; valid is deasserted; all other signals are treated as usual;
4202 if 1 - normal activity. */
4203#define TCM_REG_TCM_STORM0_IFEN 0x50004
4204/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4205 disregarded; valid is deasserted; all other signals are treated as usual;
4206 if 1 - normal activity. */
4207#define TCM_REG_TCM_STORM1_IFEN 0x50008
4208/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4209 disregarded; valid is deasserted; all other signals are treated as usual;
4210 if 1 - normal activity. */
4211#define TCM_REG_TCM_TQM_IFEN 0x5000c
4212/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4213#define TCM_REG_TCM_TQM_USE_Q 0x500d4
4214/* [RW 28] The CM header for Timers expiration command. */
4215#define TCM_REG_TM_TCM_HDR 0x50098
4216/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4217 disregarded; acknowledge output is deasserted; all other signals are
4218 treated as usual; if 1 - normal activity. */
4219#define TCM_REG_TM_TCM_IFEN 0x5001c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004220/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4221 weight 8 (the most prioritised); 1 stands for weight 1(least
4222 prioritised); 2 stands for weight 2; tc. */
4223#define TCM_REG_TM_WEIGHT 0x500d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004224/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4225 the initial credit value; read returns the current value of the credit
4226 counter. Must be initialized to 32 at start-up. */
4227#define TCM_REG_TQM_INIT_CRD 0x5021c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004228/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4229 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4230 prioritised); 2 stands for weight 2; tc. */
4231#define TCM_REG_TQM_P_WEIGHT 0x500c8
4232/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4233 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4234 prioritised); 2 stands for weight 2; tc. */
4235#define TCM_REG_TQM_S_WEIGHT 0x500cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004236/* [RW 28] The CM header value for QM request (primary). */
4237#define TCM_REG_TQM_TCM_HDR_P 0x50090
4238/* [RW 28] The CM header value for QM request (secondary). */
4239#define TCM_REG_TQM_TCM_HDR_S 0x50094
4240/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4241 acknowledge output is deasserted; all other signals are treated as usual;
4242 if 1 - normal activity. */
4243#define TCM_REG_TQM_TCM_IFEN 0x50014
4244/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4245 acknowledge output is deasserted; all other signals are treated as usual;
4246 if 1 - normal activity. */
4247#define TCM_REG_TSDM_IFEN 0x50018
4248/* [RC 1] Message length mismatch (relative to last indication) at the SDM
4249 interface. */
4250#define TCM_REG_TSDM_LENGTH_MIS 0x50164
4251/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4252 weight 8 (the most prioritised); 1 stands for weight 1(least
4253 prioritised); 2 stands for weight 2; tc. */
4254#define TCM_REG_TSDM_WEIGHT 0x500c4
4255/* [RW 1] Input usem Interface enable. If 0 - the valid input is
4256 disregarded; acknowledge output is deasserted; all other signals are
4257 treated as usual; if 1 - normal activity. */
4258#define TCM_REG_USEM_IFEN 0x50028
4259/* [RC 1] Message length mismatch (relative to last indication) at the In#8
4260 interface. */
4261#define TCM_REG_USEM_LENGTH_MIS 0x50170
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004262/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4263 weight 8 (the most prioritised); 1 stands for weight 1(least
4264 prioritised); 2 stands for weight 2; tc. */
4265#define TCM_REG_USEM_WEIGHT 0x500b8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004266/* [RW 21] Indirect access to the descriptor table of the XX protection
4267 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4268 pointer; 20:16] - next pointer. */
4269#define TCM_REG_XX_DESCR_TABLE 0x50280
Vladislav Zolotarov79616892011-07-21 07:58:54 +00004270#define TCM_REG_XX_DESCR_TABLE_SIZE 29
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004271/* [R 6] Use to read the value of XX protection Free counter. */
4272#define TCM_REG_XX_FREE 0x50178
4273/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4274 of the Input Stage XX protection buffer by the XX protection pending
4275 messages. Max credit available - 127.Write writes the initial credit
4276 value; read returns the current value of the credit counter. Must be
4277 initialized to 19 at start-up. */
4278#define TCM_REG_XX_INIT_CRD 0x50220
4279/* [RW 6] Maximum link list size (messages locked) per connection in the XX
4280 protection. */
4281#define TCM_REG_XX_MAX_LL_SZ 0x50044
4282/* [RW 6] The maximum number of pending messages; which may be stored in XX
4283 protection. ~tcm_registers_xx_free.xx_free is read on read. */
4284#define TCM_REG_XX_MSG_NUM 0x50224
4285/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4286#define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4287/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4288 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4289 header pointer. */
4290#define TCM_REG_XX_TABLE 0x50240
Anand Gadiyar411c9402009-07-07 15:24:23 +05304291/* [RW 4] Load value for cfc ac credit cnt. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004292#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4293/* [RW 4] Load value for cfc cld credit cnt. */
4294#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4295/* [RW 8] Client0 context region. */
4296#define TM_REG_CL0_CONT_REGION 0x164030
4297/* [RW 8] Client1 context region. */
4298#define TM_REG_CL1_CONT_REGION 0x164034
4299/* [RW 8] Client2 context region. */
4300#define TM_REG_CL2_CONT_REGION 0x164038
4301/* [RW 2] Client in High priority client number. */
4302#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4303/* [RW 4] Load value for clout0 cred cnt. */
4304#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4305/* [RW 4] Load value for clout1 cred cnt. */
4306#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4307/* [RW 4] Load value for clout2 cred cnt. */
4308#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4309/* [RW 1] Enable client0 input. */
4310#define TM_REG_EN_CL0_INPUT 0x164008
4311/* [RW 1] Enable client1 input. */
4312#define TM_REG_EN_CL1_INPUT 0x16400c
4313/* [RW 1] Enable client2 input. */
4314#define TM_REG_EN_CL2_INPUT 0x164010
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004315#define TM_REG_EN_LINEAR0_TIMER 0x164014
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004316/* [RW 1] Enable real time counter. */
4317#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4318/* [RW 1] Enable for Timers state machines. */
4319#define TM_REG_EN_TIMERS 0x164000
4320/* [RW 4] Load value for expiration credit cnt. CFC max number of
4321 outstanding load requests for timers (expiration) context loading. */
4322#define TM_REG_EXP_CRDCNT_VAL 0x164238
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004323/* [RW 32] Linear0 logic address. */
4324#define TM_REG_LIN0_LOGIC_ADDR 0x164240
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004325/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004326#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03004327/* [ST 16] Linear0 Number of scans counter. */
4328#define TM_REG_LIN0_NUM_SCANS 0x1640a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004329/* [WB 64] Linear0 phy address. */
4330#define TM_REG_LIN0_PHY_ADDR 0x164270
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004331/* [RW 1] Linear0 physical address valid. */
4332#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
Eilon Greensteinca003922009-08-12 22:53:28 -07004333#define TM_REG_LIN0_SCAN_ON 0x1640d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004334/* [RW 24] Linear0 array scan timeout. */
4335#define TM_REG_LIN0_SCAN_TIME 0x16403c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03004336#define TM_REG_LIN0_VNIC_UC 0x164128
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004337/* [RW 32] Linear1 logic address. */
4338#define TM_REG_LIN1_LOGIC_ADDR 0x164250
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004339/* [WB 64] Linear1 phy address. */
4340#define TM_REG_LIN1_PHY_ADDR 0x164280
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004341/* [RW 1] Linear1 physical address valid. */
4342#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004343/* [RW 6] Linear timer set_clear fifo threshold. */
4344#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4345/* [RW 2] Load value for pci arbiter credit cnt. */
4346#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004347/* [RW 20] The amount of hardware cycles for each timer tick. */
4348#define TM_REG_TIMER_TICK_SIZE 0x16401c
4349/* [RW 8] Timers Context region. */
4350#define TM_REG_TM_CONTEXT_REGION 0x164044
4351/* [RW 1] Interrupt mask register #0 read/write */
4352#define TM_REG_TM_INT_MASK 0x1640fc
4353/* [R 1] Interrupt register #0 read */
4354#define TM_REG_TM_INT_STS 0x1640f0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004355/* [RW 7] Parity mask register #0 read/write */
4356#define TM_REG_TM_PRTY_MASK 0x16410c
4357/* [RC 7] Parity register #0 read clear */
4358#define TM_REG_TM_PRTY_STS_CLR 0x164104
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004359/* [RW 8] The event id for aggregated interrupt 0 */
4360#define TSDM_REG_AGG_INT_EVENT_0 0x42038
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004361#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004362#define TSDM_REG_AGG_INT_EVENT_2 0x42040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004363#define TSDM_REG_AGG_INT_EVENT_3 0x42044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004364#define TSDM_REG_AGG_INT_EVENT_4 0x42048
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004365/* [RW 1] The T bit for aggregated interrupt 0 */
4366#define TSDM_REG_AGG_INT_T_0 0x420b8
4367#define TSDM_REG_AGG_INT_T_1 0x420bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004368/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4369#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004370/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004371#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004372/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004373#define TSDM_REG_CMP_COUNTER_MAX1 0x42020
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004374/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004375#define TSDM_REG_CMP_COUNTER_MAX2 0x42024
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004376/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004377#define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4378/* [RW 13] The start address in the internal RAM for the completion
4379 counters. */
4380#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4381#define TSDM_REG_ENABLE_IN1 0x42238
4382#define TSDM_REG_ENABLE_IN2 0x4223c
4383#define TSDM_REG_ENABLE_OUT1 0x42240
4384#define TSDM_REG_ENABLE_OUT2 0x42244
4385/* [RW 4] The initial number of messages that can be sent to the pxp control
4386 interface without receiving any ACK. */
4387#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4388/* [ST 32] The number of ACK after placement messages received */
4389#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4390/* [ST 32] The number of packet end messages received from the parser */
4391#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4392/* [ST 32] The number of requests received from the pxp async if */
4393#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4394/* [ST 32] The number of commands received in queue 0 */
4395#define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4396/* [ST 32] The number of commands received in queue 10 */
4397#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4398/* [ST 32] The number of commands received in queue 11 */
4399#define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4400/* [ST 32] The number of commands received in queue 1 */
4401#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4402/* [ST 32] The number of commands received in queue 3 */
4403#define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4404/* [ST 32] The number of commands received in queue 4 */
4405#define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4406/* [ST 32] The number of commands received in queue 5 */
4407#define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4408/* [ST 32] The number of commands received in queue 6 */
4409#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4410/* [ST 32] The number of commands received in queue 7 */
4411#define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4412/* [ST 32] The number of commands received in queue 8 */
4413#define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4414/* [ST 32] The number of commands received in queue 9 */
4415#define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4416/* [RW 13] The start address in the internal RAM for the packet end message */
4417#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4418/* [RW 13] The start address in the internal RAM for queue counters */
4419#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4420/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4421#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4422/* [R 1] parser fifo empty in sdm_sync block */
4423#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4424/* [R 1] parser serial fifo empty in sdm_sync block */
4425#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4426/* [RW 32] Tick for timer counter. Applicable only when
4427 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4428#define TSDM_REG_TIMER_TICK 0x42000
4429/* [RW 32] Interrupt mask register #0 read/write */
4430#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4431#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004432/* [R 32] Interrupt register #0 read */
4433#define TSDM_REG_TSDM_INT_STS_0 0x42290
4434#define TSDM_REG_TSDM_INT_STS_1 0x422a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004435/* [RW 11] Parity mask register #0 read/write */
4436#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
Eliezer Tamirf1410642008-02-28 11:51:50 -08004437/* [R 11] Parity register #0 read */
4438#define TSDM_REG_TSDM_PRTY_STS 0x422b0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004439/* [RC 11] Parity register #0 read clear */
4440#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004441/* [RW 5] The number of time_slots in the arbitration cycle */
4442#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4443/* [RW 3] The source that is associated with arbitration element 0. Source
4444 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4445 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4446#define TSEM_REG_ARB_ELEMENT0 0x180020
4447/* [RW 3] The source that is associated with arbitration element 1. Source
4448 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4449 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4450 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4451#define TSEM_REG_ARB_ELEMENT1 0x180024
4452/* [RW 3] The source that is associated with arbitration element 2. Source
4453 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4454 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4455 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4456 and ~tsem_registers_arb_element1.arb_element1 */
4457#define TSEM_REG_ARB_ELEMENT2 0x180028
4458/* [RW 3] The source that is associated with arbitration element 3. Source
4459 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4460 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4461 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4462 ~tsem_registers_arb_element1.arb_element1 and
4463 ~tsem_registers_arb_element2.arb_element2 */
4464#define TSEM_REG_ARB_ELEMENT3 0x18002c
4465/* [RW 3] The source that is associated with arbitration element 4. Source
4466 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4467 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4468 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4469 and ~tsem_registers_arb_element1.arb_element1 and
4470 ~tsem_registers_arb_element2.arb_element2 and
4471 ~tsem_registers_arb_element3.arb_element3 */
4472#define TSEM_REG_ARB_ELEMENT4 0x180030
4473#define TSEM_REG_ENABLE_IN 0x1800a4
4474#define TSEM_REG_ENABLE_OUT 0x1800a8
4475/* [RW 32] This address space contains all registers and memories that are
4476 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004477 appendix B. In order to access the sem_fast registers the base address
4478 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004479#define TSEM_REG_FAST_MEMORY 0x1a0000
4480/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4481 by the microcode */
4482#define TSEM_REG_FIC0_DISABLE 0x180224
4483/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4484 by the microcode */
4485#define TSEM_REG_FIC1_DISABLE 0x180234
4486/* [RW 15] Interrupt table Read and write access to it is not possible in
4487 the middle of the work */
4488#define TSEM_REG_INT_TABLE 0x180400
4489/* [ST 24] Statistics register. The number of messages that entered through
4490 FIC0 */
4491#define TSEM_REG_MSG_NUM_FIC0 0x180000
4492/* [ST 24] Statistics register. The number of messages that entered through
4493 FIC1 */
4494#define TSEM_REG_MSG_NUM_FIC1 0x180004
4495/* [ST 24] Statistics register. The number of messages that were sent to
4496 FOC0 */
4497#define TSEM_REG_MSG_NUM_FOC0 0x180008
4498/* [ST 24] Statistics register. The number of messages that were sent to
4499 FOC1 */
4500#define TSEM_REG_MSG_NUM_FOC1 0x18000c
4501/* [ST 24] Statistics register. The number of messages that were sent to
4502 FOC2 */
4503#define TSEM_REG_MSG_NUM_FOC2 0x180010
4504/* [ST 24] Statistics register. The number of messages that were sent to
4505 FOC3 */
4506#define TSEM_REG_MSG_NUM_FOC3 0x180014
4507/* [RW 1] Disables input messages from the passive buffer May be updated
4508 during run_time by the microcode */
4509#define TSEM_REG_PAS_DISABLE 0x18024c
4510/* [WB 128] Debug only. Passive buffer memory */
4511#define TSEM_REG_PASSIVE_BUFFER 0x181000
4512/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4513#define TSEM_REG_PRAM 0x1c0000
4514/* [R 8] Valid sleeping threads indication have bit per thread */
4515#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4516/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4517#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4518/* [RW 8] List of free threads . There is a bit per thread. */
4519#define TSEM_REG_THREADS_LIST 0x1802e4
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004520/* [RC 32] Parity register #0 read clear */
4521#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4522#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004523/* [RW 3] The arbitration scheme of time_slot 0 */
4524#define TSEM_REG_TS_0_AS 0x180038
4525/* [RW 3] The arbitration scheme of time_slot 10 */
4526#define TSEM_REG_TS_10_AS 0x180060
4527/* [RW 3] The arbitration scheme of time_slot 11 */
4528#define TSEM_REG_TS_11_AS 0x180064
4529/* [RW 3] The arbitration scheme of time_slot 12 */
4530#define TSEM_REG_TS_12_AS 0x180068
4531/* [RW 3] The arbitration scheme of time_slot 13 */
4532#define TSEM_REG_TS_13_AS 0x18006c
4533/* [RW 3] The arbitration scheme of time_slot 14 */
4534#define TSEM_REG_TS_14_AS 0x180070
4535/* [RW 3] The arbitration scheme of time_slot 15 */
4536#define TSEM_REG_TS_15_AS 0x180074
4537/* [RW 3] The arbitration scheme of time_slot 16 */
4538#define TSEM_REG_TS_16_AS 0x180078
4539/* [RW 3] The arbitration scheme of time_slot 17 */
4540#define TSEM_REG_TS_17_AS 0x18007c
4541/* [RW 3] The arbitration scheme of time_slot 18 */
4542#define TSEM_REG_TS_18_AS 0x180080
4543/* [RW 3] The arbitration scheme of time_slot 1 */
4544#define TSEM_REG_TS_1_AS 0x18003c
4545/* [RW 3] The arbitration scheme of time_slot 2 */
4546#define TSEM_REG_TS_2_AS 0x180040
4547/* [RW 3] The arbitration scheme of time_slot 3 */
4548#define TSEM_REG_TS_3_AS 0x180044
4549/* [RW 3] The arbitration scheme of time_slot 4 */
4550#define TSEM_REG_TS_4_AS 0x180048
4551/* [RW 3] The arbitration scheme of time_slot 5 */
4552#define TSEM_REG_TS_5_AS 0x18004c
4553/* [RW 3] The arbitration scheme of time_slot 6 */
4554#define TSEM_REG_TS_6_AS 0x180050
4555/* [RW 3] The arbitration scheme of time_slot 7 */
4556#define TSEM_REG_TS_7_AS 0x180054
4557/* [RW 3] The arbitration scheme of time_slot 8 */
4558#define TSEM_REG_TS_8_AS 0x180058
4559/* [RW 3] The arbitration scheme of time_slot 9 */
4560#define TSEM_REG_TS_9_AS 0x18005c
4561/* [RW 32] Interrupt mask register #0 read/write */
4562#define TSEM_REG_TSEM_INT_MASK_0 0x180100
4563#define TSEM_REG_TSEM_INT_MASK_1 0x180110
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004564/* [R 32] Interrupt register #0 read */
4565#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4566#define TSEM_REG_TSEM_INT_STS_1 0x180104
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004567/* [RW 32] Parity mask register #0 read/write */
4568#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4569#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
Eliezer Tamirf1410642008-02-28 11:51:50 -08004570/* [R 32] Parity register #0 read */
4571#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4572#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00004573/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4574 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4575#define TSEM_REG_VFPF_ERR_NUM 0x180380
4576/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4577 * [10:8] of the address should be the offset within the accessed LCID
4578 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4579 * LCID100. The RBC address should be 12'ha64. */
4580#define UCM_REG_AG_CTX 0xe2000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004581/* [R 5] Used to read the XX protection CAM occupancy counter. */
4582#define UCM_REG_CAM_OCCUP 0xe0170
4583/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4584 disregarded; valid output is deasserted; all other signals are treated as
4585 usual; if 1 - normal activity. */
4586#define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4587/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4588 are disregarded; all other signals are treated as usual; if 1 - normal
4589 activity. */
4590#define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4591/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4592 disregarded; valid output is deasserted; all other signals are treated as
4593 usual; if 1 - normal activity. */
4594#define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4595/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4596 input is disregarded; all other signals are treated as usual; if 1 -
4597 normal activity. */
4598#define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4599/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4600 the initial credit value; read returns the current value of the credit
4601 counter. Must be initialized to 1 at start-up. */
4602#define UCM_REG_CFC_INIT_CRD 0xe0204
4603/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4604 weight 8 (the most prioritised); 1 stands for weight 1(least
4605 prioritised); 2 stands for weight 2; tc. */
4606#define UCM_REG_CP_WEIGHT 0xe00c4
4607/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4608 disregarded; acknowledge output is deasserted; all other signals are
4609 treated as usual; if 1 - normal activity. */
4610#define UCM_REG_CSEM_IFEN 0xe0028
4611/* [RC 1] Set when the message length mismatch (relative to last indication)
4612 at the csem interface is detected. */
4613#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4614/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4615 weight 8 (the most prioritised); 1 stands for weight 1(least
4616 prioritised); 2 stands for weight 2; tc. */
4617#define UCM_REG_CSEM_WEIGHT 0xe00b8
4618/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4619 disregarded; acknowledge output is deasserted; all other signals are
4620 treated as usual; if 1 - normal activity. */
4621#define UCM_REG_DORQ_IFEN 0xe0030
4622/* [RC 1] Set when the message length mismatch (relative to last indication)
4623 at the dorq interface is detected. */
4624#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004625/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4626 weight 8 (the most prioritised); 1 stands for weight 1(least
4627 prioritised); 2 stands for weight 2; tc. */
4628#define UCM_REG_DORQ_WEIGHT 0xe00c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004629/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4630#define UCM_REG_ERR_EVNT_ID 0xe00a4
4631/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4632#define UCM_REG_ERR_UCM_HDR 0xe00a0
4633/* [RW 8] The Event ID for Timers expiration. */
4634#define UCM_REG_EXPR_EVNT_ID 0xe00a8
4635/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4636 writes the initial credit value; read returns the current value of the
4637 credit counter. Must be initialized to 64 at start-up. */
4638#define UCM_REG_FIC0_INIT_CRD 0xe020c
4639/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4640 writes the initial credit value; read returns the current value of the
4641 credit counter. Must be initialized to 64 at start-up. */
4642#define UCM_REG_FIC1_INIT_CRD 0xe0210
4643/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4644 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4645 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4646 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4647#define UCM_REG_GR_ARB_TYPE 0xe0144
4648/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4649 highest priority is 3. It is supposed that the Store channel group is
4650 compliment to the others. */
4651#define UCM_REG_GR_LD0_PR 0xe014c
4652/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4653 highest priority is 3. It is supposed that the Store channel group is
4654 compliment to the others. */
4655#define UCM_REG_GR_LD1_PR 0xe0150
4656/* [RW 2] The queue index for invalidate counter flag decision. */
4657#define UCM_REG_INV_CFLG_Q 0xe00e4
4658/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4659 sent to STORM; for a specific connection type. the double REG-pairs are
4660 used in order to align to STORM context row size of 128 bits. The offset
4661 of these data in the STORM context is always 0. Index _i stands for the
4662 connection type (one of 16). */
4663#define UCM_REG_N_SM_CTX_LD_0 0xe0054
4664#define UCM_REG_N_SM_CTX_LD_1 0xe0058
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004665#define UCM_REG_N_SM_CTX_LD_2 0xe005c
4666#define UCM_REG_N_SM_CTX_LD_3 0xe0060
4667#define UCM_REG_N_SM_CTX_LD_4 0xe0064
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004668#define UCM_REG_N_SM_CTX_LD_5 0xe0068
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004669#define UCM_REG_PHYS_QNUM0_0 0xe0110
4670#define UCM_REG_PHYS_QNUM0_1 0xe0114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004671#define UCM_REG_PHYS_QNUM1_0 0xe0118
4672#define UCM_REG_PHYS_QNUM1_1 0xe011c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004673#define UCM_REG_PHYS_QNUM2_0 0xe0120
4674#define UCM_REG_PHYS_QNUM2_1 0xe0124
4675#define UCM_REG_PHYS_QNUM3_0 0xe0128
4676#define UCM_REG_PHYS_QNUM3_1 0xe012c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004677/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4678#define UCM_REG_STOP_EVNT_ID 0xe00ac
4679/* [RC 1] Set when the message length mismatch (relative to last indication)
4680 at the STORM interface is detected. */
4681#define UCM_REG_STORM_LENGTH_MIS 0xe0154
4682/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4683 disregarded; acknowledge output is deasserted; all other signals are
4684 treated as usual; if 1 - normal activity. */
4685#define UCM_REG_STORM_UCM_IFEN 0xe0010
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004686/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4687 weight 8 (the most prioritised); 1 stands for weight 1(least
4688 prioritised); 2 stands for weight 2; tc. */
4689#define UCM_REG_STORM_WEIGHT 0xe00b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004690/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4691 writes the initial credit value; read returns the current value of the
4692 credit counter. Must be initialized to 4 at start-up. */
4693#define UCM_REG_TM_INIT_CRD 0xe021c
4694/* [RW 28] The CM header for Timers expiration command. */
4695#define UCM_REG_TM_UCM_HDR 0xe009c
4696/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4697 disregarded; acknowledge output is deasserted; all other signals are
4698 treated as usual; if 1 - normal activity. */
4699#define UCM_REG_TM_UCM_IFEN 0xe001c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004700/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4701 weight 8 (the most prioritised); 1 stands for weight 1(least
4702 prioritised); 2 stands for weight 2; tc. */
4703#define UCM_REG_TM_WEIGHT 0xe00d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004704/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4705 disregarded; acknowledge output is deasserted; all other signals are
4706 treated as usual; if 1 - normal activity. */
4707#define UCM_REG_TSEM_IFEN 0xe0024
4708/* [RC 1] Set when the message length mismatch (relative to last indication)
4709 at the tsem interface is detected. */
4710#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4711/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4712 weight 8 (the most prioritised); 1 stands for weight 1(least
4713 prioritised); 2 stands for weight 2; tc. */
4714#define UCM_REG_TSEM_WEIGHT 0xe00b4
4715/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4716 acknowledge output is deasserted; all other signals are treated as usual;
4717 if 1 - normal activity. */
4718#define UCM_REG_UCM_CFC_IFEN 0xe0044
4719/* [RW 11] Interrupt mask register #0 read/write */
4720#define UCM_REG_UCM_INT_MASK 0xe01d4
4721/* [R 11] Interrupt register #0 read */
4722#define UCM_REG_UCM_INT_STS 0xe01c8
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00004723/* [RW 27] Parity mask register #0 read/write */
4724#define UCM_REG_UCM_PRTY_MASK 0xe01e4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004725/* [R 27] Parity register #0 read */
4726#define UCM_REG_UCM_PRTY_STS 0xe01d8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004727/* [RC 27] Parity register #0 read clear */
4728#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004729/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4730 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4731 Is used to determine the number of the AG context REG-pairs written back;
4732 when the Reg1WbFlg isn't set. */
4733#define UCM_REG_UCM_REG0_SZ 0xe00dc
4734/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4735 disregarded; valid is deasserted; all other signals are treated as usual;
4736 if 1 - normal activity. */
4737#define UCM_REG_UCM_STORM0_IFEN 0xe0004
4738/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4739 disregarded; valid is deasserted; all other signals are treated as usual;
4740 if 1 - normal activity. */
4741#define UCM_REG_UCM_STORM1_IFEN 0xe0008
4742/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4743 disregarded; acknowledge output is deasserted; all other signals are
4744 treated as usual; if 1 - normal activity. */
4745#define UCM_REG_UCM_TM_IFEN 0xe0020
4746/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4747 disregarded; valid is deasserted; all other signals are treated as usual;
4748 if 1 - normal activity. */
4749#define UCM_REG_UCM_UQM_IFEN 0xe000c
4750/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4751#define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4752/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4753 the initial credit value; read returns the current value of the credit
4754 counter. Must be initialized to 32 at start-up. */
4755#define UCM_REG_UQM_INIT_CRD 0xe0220
4756/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4757 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4758 prioritised); 2 stands for weight 2; tc. */
4759#define UCM_REG_UQM_P_WEIGHT 0xe00cc
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004760/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4761 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4762 prioritised); 2 stands for weight 2; tc. */
4763#define UCM_REG_UQM_S_WEIGHT 0xe00d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004764/* [RW 28] The CM header value for QM request (primary). */
4765#define UCM_REG_UQM_UCM_HDR_P 0xe0094
4766/* [RW 28] The CM header value for QM request (secondary). */
4767#define UCM_REG_UQM_UCM_HDR_S 0xe0098
4768/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4769 acknowledge output is deasserted; all other signals are treated as usual;
4770 if 1 - normal activity. */
4771#define UCM_REG_UQM_UCM_IFEN 0xe0014
4772/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4773 acknowledge output is deasserted; all other signals are treated as usual;
4774 if 1 - normal activity. */
4775#define UCM_REG_USDM_IFEN 0xe0018
4776/* [RC 1] Set when the message length mismatch (relative to last indication)
4777 at the SDM interface is detected. */
4778#define UCM_REG_USDM_LENGTH_MIS 0xe0158
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004779/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4780 weight 8 (the most prioritised); 1 stands for weight 1(least
4781 prioritised); 2 stands for weight 2; tc. */
4782#define UCM_REG_USDM_WEIGHT 0xe00c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004783/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4784 disregarded; acknowledge output is deasserted; all other signals are
4785 treated as usual; if 1 - normal activity. */
4786#define UCM_REG_XSEM_IFEN 0xe002c
4787/* [RC 1] Set when the message length mismatch (relative to last indication)
4788 at the xsem interface isdetected. */
4789#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004790/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4791 weight 8 (the most prioritised); 1 stands for weight 1(least
4792 prioritised); 2 stands for weight 2; tc. */
4793#define UCM_REG_XSEM_WEIGHT 0xe00bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004794/* [RW 20] Indirect access to the descriptor table of the XX protection
4795 mechanism. The fields are:[5:0] - message length; 14:6] - message
4796 pointer; 19:15] - next pointer. */
4797#define UCM_REG_XX_DESCR_TABLE 0xe0280
Vladislav Zolotarov79616892011-07-21 07:58:54 +00004798#define UCM_REG_XX_DESCR_TABLE_SIZE 27
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004799/* [R 6] Use to read the XX protection Free counter. */
4800#define UCM_REG_XX_FREE 0xe016c
4801/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4802 of the Input Stage XX protection buffer by the XX protection pending
4803 messages. Write writes the initial credit value; read returns the current
4804 value of the credit counter. Must be initialized to 12 at start-up. */
4805#define UCM_REG_XX_INIT_CRD 0xe0224
4806/* [RW 6] The maximum number of pending messages; which may be stored in XX
4807 protection. ~ucm_registers_xx_free.xx_free read on read. */
4808#define UCM_REG_XX_MSG_NUM 0xe0228
4809/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4810#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4811/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4812 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4813 header pointer. */
4814#define UCM_REG_XX_TABLE 0xe0300
Mintz Yuvale18c56b2012-02-15 02:10:23 +00004815#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
Yaniv Rosner9d5b36b2011-08-02 22:59:10 +00004816#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
Yaniv Rosner9380bb92011-06-14 01:34:07 +00004817#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4818#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4819#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
Yaniv Rosner9d5b36b2011-08-02 22:59:10 +00004820#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
Yaniv Rosner9380bb92011-06-14 01:34:07 +00004821#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4822#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4823#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4824#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4825#define UMAC_REG_COMMAND_CONFIG 0x8
Yaniv Rosnerb8d6d082011-07-05 01:06:27 +00004826/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
4827 * to bit 17 of the MAC address etc. */
4828#define UMAC_REG_MAC_ADDR0 0xc
4829/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
4830 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
4831#define UMAC_REG_MAC_ADDR1 0x10
Yaniv Rosner9380bb92011-06-14 01:34:07 +00004832/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4833 * logic to check frames. */
4834#define UMAC_REG_MAXFR 0x14
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004835/* [RW 8] The event id for aggregated interrupt 0 */
4836#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4837#define USDM_REG_AGG_INT_EVENT_1 0xc403c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004838#define USDM_REG_AGG_INT_EVENT_2 0xc4040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004839#define USDM_REG_AGG_INT_EVENT_4 0xc4048
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004840#define USDM_REG_AGG_INT_EVENT_5 0xc404c
Eilon Greensteinca003922009-08-12 22:53:28 -07004841#define USDM_REG_AGG_INT_EVENT_6 0xc4050
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004842/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4843 or auto-mask-mode (1) */
4844#define USDM_REG_AGG_INT_MODE_0 0xc41b8
4845#define USDM_REG_AGG_INT_MODE_1 0xc41bc
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004846#define USDM_REG_AGG_INT_MODE_4 0xc41c8
4847#define USDM_REG_AGG_INT_MODE_5 0xc41cc
Eilon Greensteinca003922009-08-12 22:53:28 -07004848#define USDM_REG_AGG_INT_MODE_6 0xc41d0
4849/* [RW 1] The T bit for aggregated interrupt 5 */
4850#define USDM_REG_AGG_INT_T_5 0xc40cc
4851#define USDM_REG_AGG_INT_T_6 0xc40d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004852/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4853#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004854/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004855#define USDM_REG_CMP_COUNTER_MAX0 0xc401c
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004856/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004857#define USDM_REG_CMP_COUNTER_MAX1 0xc4020
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004858/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004859#define USDM_REG_CMP_COUNTER_MAX2 0xc4024
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004860/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004861#define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4862/* [RW 13] The start address in the internal RAM for the completion
4863 counters. */
4864#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4865#define USDM_REG_ENABLE_IN1 0xc4238
4866#define USDM_REG_ENABLE_IN2 0xc423c
4867#define USDM_REG_ENABLE_OUT1 0xc4240
4868#define USDM_REG_ENABLE_OUT2 0xc4244
4869/* [RW 4] The initial number of messages that can be sent to the pxp control
4870 interface without receiving any ACK. */
4871#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4872/* [ST 32] The number of ACK after placement messages received */
4873#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4874/* [ST 32] The number of packet end messages received from the parser */
4875#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4876/* [ST 32] The number of requests received from the pxp async if */
4877#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4878/* [ST 32] The number of commands received in queue 0 */
4879#define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4880/* [ST 32] The number of commands received in queue 10 */
4881#define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4882/* [ST 32] The number of commands received in queue 11 */
4883#define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4884/* [ST 32] The number of commands received in queue 1 */
4885#define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4886/* [ST 32] The number of commands received in queue 2 */
4887#define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4888/* [ST 32] The number of commands received in queue 3 */
4889#define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4890/* [ST 32] The number of commands received in queue 4 */
4891#define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4892/* [ST 32] The number of commands received in queue 5 */
4893#define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4894/* [ST 32] The number of commands received in queue 6 */
4895#define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4896/* [ST 32] The number of commands received in queue 7 */
4897#define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4898/* [ST 32] The number of commands received in queue 8 */
4899#define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4900/* [ST 32] The number of commands received in queue 9 */
4901#define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4902/* [RW 13] The start address in the internal RAM for the packet end message */
4903#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4904/* [RW 13] The start address in the internal RAM for queue counters */
4905#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4906/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4907#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4908/* [R 1] parser fifo empty in sdm_sync block */
4909#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4910/* [R 1] parser serial fifo empty in sdm_sync block */
4911#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4912/* [RW 32] Tick for timer counter. Applicable only when
4913 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4914#define USDM_REG_TIMER_TICK 0xc4000
4915/* [RW 32] Interrupt mask register #0 read/write */
4916#define USDM_REG_USDM_INT_MASK_0 0xc42a0
4917#define USDM_REG_USDM_INT_MASK_1 0xc42b0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004918/* [R 32] Interrupt register #0 read */
4919#define USDM_REG_USDM_INT_STS_0 0xc4294
4920#define USDM_REG_USDM_INT_STS_1 0xc42a4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004921/* [RW 11] Parity mask register #0 read/write */
4922#define USDM_REG_USDM_PRTY_MASK 0xc42c0
Eliezer Tamirf1410642008-02-28 11:51:50 -08004923/* [R 11] Parity register #0 read */
4924#define USDM_REG_USDM_PRTY_STS 0xc42b4
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004925/* [RC 11] Parity register #0 read clear */
4926#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004927/* [RW 5] The number of time_slots in the arbitration cycle */
4928#define USEM_REG_ARB_CYCLE_SIZE 0x300034
4929/* [RW 3] The source that is associated with arbitration element 0. Source
4930 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4931 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4932#define USEM_REG_ARB_ELEMENT0 0x300020
4933/* [RW 3] The source that is associated with arbitration element 1. Source
4934 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4935 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4936 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4937#define USEM_REG_ARB_ELEMENT1 0x300024
4938/* [RW 3] The source that is associated with arbitration element 2. Source
4939 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4940 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4941 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4942 and ~usem_registers_arb_element1.arb_element1 */
4943#define USEM_REG_ARB_ELEMENT2 0x300028
4944/* [RW 3] The source that is associated with arbitration element 3. Source
4945 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4946 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4947 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4948 ~usem_registers_arb_element1.arb_element1 and
4949 ~usem_registers_arb_element2.arb_element2 */
4950#define USEM_REG_ARB_ELEMENT3 0x30002c
4951/* [RW 3] The source that is associated with arbitration element 4. Source
4952 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4953 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4954 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4955 and ~usem_registers_arb_element1.arb_element1 and
4956 ~usem_registers_arb_element2.arb_element2 and
4957 ~usem_registers_arb_element3.arb_element3 */
4958#define USEM_REG_ARB_ELEMENT4 0x300030
4959#define USEM_REG_ENABLE_IN 0x3000a4
4960#define USEM_REG_ENABLE_OUT 0x3000a8
4961/* [RW 32] This address space contains all registers and memories that are
4962 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004963 appendix B. In order to access the sem_fast registers the base address
4964 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004965#define USEM_REG_FAST_MEMORY 0x320000
4966/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4967 by the microcode */
4968#define USEM_REG_FIC0_DISABLE 0x300224
4969/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4970 by the microcode */
4971#define USEM_REG_FIC1_DISABLE 0x300234
4972/* [RW 15] Interrupt table Read and write access to it is not possible in
4973 the middle of the work */
4974#define USEM_REG_INT_TABLE 0x300400
4975/* [ST 24] Statistics register. The number of messages that entered through
4976 FIC0 */
4977#define USEM_REG_MSG_NUM_FIC0 0x300000
4978/* [ST 24] Statistics register. The number of messages that entered through
4979 FIC1 */
4980#define USEM_REG_MSG_NUM_FIC1 0x300004
4981/* [ST 24] Statistics register. The number of messages that were sent to
4982 FOC0 */
4983#define USEM_REG_MSG_NUM_FOC0 0x300008
4984/* [ST 24] Statistics register. The number of messages that were sent to
4985 FOC1 */
4986#define USEM_REG_MSG_NUM_FOC1 0x30000c
4987/* [ST 24] Statistics register. The number of messages that were sent to
4988 FOC2 */
4989#define USEM_REG_MSG_NUM_FOC2 0x300010
4990/* [ST 24] Statistics register. The number of messages that were sent to
4991 FOC3 */
4992#define USEM_REG_MSG_NUM_FOC3 0x300014
4993/* [RW 1] Disables input messages from the passive buffer May be updated
4994 during run_time by the microcode */
4995#define USEM_REG_PAS_DISABLE 0x30024c
4996/* [WB 128] Debug only. Passive buffer memory */
4997#define USEM_REG_PASSIVE_BUFFER 0x302000
4998/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4999#define USEM_REG_PRAM 0x340000
5000/* [R 16] Valid sleeping threads indication have bit per thread */
5001#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
5002/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5003#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
5004/* [RW 16] List of free threads . There is a bit per thread. */
5005#define USEM_REG_THREADS_LIST 0x3002e4
5006/* [RW 3] The arbitration scheme of time_slot 0 */
5007#define USEM_REG_TS_0_AS 0x300038
5008/* [RW 3] The arbitration scheme of time_slot 10 */
5009#define USEM_REG_TS_10_AS 0x300060
5010/* [RW 3] The arbitration scheme of time_slot 11 */
5011#define USEM_REG_TS_11_AS 0x300064
5012/* [RW 3] The arbitration scheme of time_slot 12 */
5013#define USEM_REG_TS_12_AS 0x300068
5014/* [RW 3] The arbitration scheme of time_slot 13 */
5015#define USEM_REG_TS_13_AS 0x30006c
5016/* [RW 3] The arbitration scheme of time_slot 14 */
5017#define USEM_REG_TS_14_AS 0x300070
5018/* [RW 3] The arbitration scheme of time_slot 15 */
5019#define USEM_REG_TS_15_AS 0x300074
5020/* [RW 3] The arbitration scheme of time_slot 16 */
5021#define USEM_REG_TS_16_AS 0x300078
5022/* [RW 3] The arbitration scheme of time_slot 17 */
5023#define USEM_REG_TS_17_AS 0x30007c
5024/* [RW 3] The arbitration scheme of time_slot 18 */
5025#define USEM_REG_TS_18_AS 0x300080
5026/* [RW 3] The arbitration scheme of time_slot 1 */
5027#define USEM_REG_TS_1_AS 0x30003c
5028/* [RW 3] The arbitration scheme of time_slot 2 */
5029#define USEM_REG_TS_2_AS 0x300040
5030/* [RW 3] The arbitration scheme of time_slot 3 */
5031#define USEM_REG_TS_3_AS 0x300044
5032/* [RW 3] The arbitration scheme of time_slot 4 */
5033#define USEM_REG_TS_4_AS 0x300048
5034/* [RW 3] The arbitration scheme of time_slot 5 */
5035#define USEM_REG_TS_5_AS 0x30004c
5036/* [RW 3] The arbitration scheme of time_slot 6 */
5037#define USEM_REG_TS_6_AS 0x300050
5038/* [RW 3] The arbitration scheme of time_slot 7 */
5039#define USEM_REG_TS_7_AS 0x300054
5040/* [RW 3] The arbitration scheme of time_slot 8 */
5041#define USEM_REG_TS_8_AS 0x300058
5042/* [RW 3] The arbitration scheme of time_slot 9 */
5043#define USEM_REG_TS_9_AS 0x30005c
5044/* [RW 32] Interrupt mask register #0 read/write */
5045#define USEM_REG_USEM_INT_MASK_0 0x300110
5046#define USEM_REG_USEM_INT_MASK_1 0x300120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005047/* [R 32] Interrupt register #0 read */
5048#define USEM_REG_USEM_INT_STS_0 0x300104
5049#define USEM_REG_USEM_INT_STS_1 0x300114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005050/* [RW 32] Parity mask register #0 read/write */
5051#define USEM_REG_USEM_PRTY_MASK_0 0x300130
5052#define USEM_REG_USEM_PRTY_MASK_1 0x300140
Eliezer Tamirf1410642008-02-28 11:51:50 -08005053/* [R 32] Parity register #0 read */
5054#define USEM_REG_USEM_PRTY_STS_0 0x300124
5055#define USEM_REG_USEM_PRTY_STS_1 0x300134
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00005056/* [RC 32] Parity register #0 read clear */
5057#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
5058#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005059/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5060 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5061#define USEM_REG_VFPF_ERR_NUM 0x300380
5062#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
5063#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
5064#define VFC_REG_MEMORIES_RST 0x1943c
5065/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5066 * [12:8] of the address should be the offset within the accessed LCID
5067 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5068 * LCID100. The RBC address should be 13'ha64. */
5069#define XCM_REG_AG_CTX 0x28000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005070/* [RW 2] The queue index for registration on Aux1 counter flag. */
5071#define XCM_REG_AUX1_Q 0x20134
5072/* [RW 2] Per each decision rule the queue index to register to. */
5073#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
5074/* [R 5] Used to read the XX protection CAM occupancy counter. */
5075#define XCM_REG_CAM_OCCUP 0x20244
5076/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5077 disregarded; valid output is deasserted; all other signals are treated as
5078 usual; if 1 - normal activity. */
5079#define XCM_REG_CDU_AG_RD_IFEN 0x20044
5080/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5081 are disregarded; all other signals are treated as usual; if 1 - normal
5082 activity. */
5083#define XCM_REG_CDU_AG_WR_IFEN 0x20040
5084/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5085 disregarded; valid output is deasserted; all other signals are treated as
5086 usual; if 1 - normal activity. */
5087#define XCM_REG_CDU_SM_RD_IFEN 0x2004c
5088/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5089 input is disregarded; all other signals are treated as usual; if 1 -
5090 normal activity. */
5091#define XCM_REG_CDU_SM_WR_IFEN 0x20048
5092/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5093 the initial credit value; read returns the current value of the credit
5094 counter. Must be initialized to 1 at start-up. */
5095#define XCM_REG_CFC_INIT_CRD 0x20404
5096/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5097 weight 8 (the most prioritised); 1 stands for weight 1(least
5098 prioritised); 2 stands for weight 2; tc. */
5099#define XCM_REG_CP_WEIGHT 0x200dc
5100/* [RW 1] Input csem Interface enable. If 0 - the valid input is
5101 disregarded; acknowledge output is deasserted; all other signals are
5102 treated as usual; if 1 - normal activity. */
5103#define XCM_REG_CSEM_IFEN 0x20028
5104/* [RC 1] Set at message length mismatch (relative to last indication) at
5105 the csem interface. */
5106#define XCM_REG_CSEM_LENGTH_MIS 0x20228
5107/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5108 weight 8 (the most prioritised); 1 stands for weight 1(least
5109 prioritised); 2 stands for weight 2; tc. */
5110#define XCM_REG_CSEM_WEIGHT 0x200c4
5111/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5112 disregarded; acknowledge output is deasserted; all other signals are
5113 treated as usual; if 1 - normal activity. */
5114#define XCM_REG_DORQ_IFEN 0x20030
5115/* [RC 1] Set at message length mismatch (relative to last indication) at
5116 the dorq interface. */
5117#define XCM_REG_DORQ_LENGTH_MIS 0x20230
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005118/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5119 weight 8 (the most prioritised); 1 stands for weight 1(least
5120 prioritised); 2 stands for weight 2; tc. */
5121#define XCM_REG_DORQ_WEIGHT 0x200cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005122/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5123#define XCM_REG_ERR_EVNT_ID 0x200b0
5124/* [RW 28] The CM erroneous header for QM and Timers formatting. */
5125#define XCM_REG_ERR_XCM_HDR 0x200ac
5126/* [RW 8] The Event ID for Timers expiration. */
5127#define XCM_REG_EXPR_EVNT_ID 0x200b4
5128/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5129 writes the initial credit value; read returns the current value of the
5130 credit counter. Must be initialized to 64 at start-up. */
5131#define XCM_REG_FIC0_INIT_CRD 0x2040c
5132/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5133 writes the initial credit value; read returns the current value of the
5134 credit counter. Must be initialized to 64 at start-up. */
5135#define XCM_REG_FIC1_INIT_CRD 0x20410
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005136#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
5137#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005138#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
5139#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
5140/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5141 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5142 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
5143 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
5144#define XCM_REG_GR_ARB_TYPE 0x2020c
5145/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5146 highest priority is 3. It is supposed that the Channel group is the
5147 compliment of the other 3 groups. */
5148#define XCM_REG_GR_LD0_PR 0x20214
5149/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5150 highest priority is 3. It is supposed that the Channel group is the
5151 compliment of the other 3 groups. */
5152#define XCM_REG_GR_LD1_PR 0x20218
5153/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5154 disregarded; acknowledge output is deasserted; all other signals are
5155 treated as usual; if 1 - normal activity. */
5156#define XCM_REG_NIG0_IFEN 0x20038
5157/* [RC 1] Set at message length mismatch (relative to last indication) at
5158 the nig0 interface. */
5159#define XCM_REG_NIG0_LENGTH_MIS 0x20238
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005160/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5161 weight 8 (the most prioritised); 1 stands for weight 1(least
5162 prioritised); 2 stands for weight 2; tc. */
5163#define XCM_REG_NIG0_WEIGHT 0x200d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005164/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5165 disregarded; acknowledge output is deasserted; all other signals are
5166 treated as usual; if 1 - normal activity. */
5167#define XCM_REG_NIG1_IFEN 0x2003c
5168/* [RC 1] Set at message length mismatch (relative to last indication) at
5169 the nig1 interface. */
5170#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005171/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5172 sent to STORM; for a specific connection type. The double REG-pairs are
5173 used in order to align to STORM context row size of 128 bits. The offset
5174 of these data in the STORM context is always 0. Index _i stands for the
5175 connection type (one of 16). */
5176#define XCM_REG_N_SM_CTX_LD_0 0x20060
5177#define XCM_REG_N_SM_CTX_LD_1 0x20064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005178#define XCM_REG_N_SM_CTX_LD_2 0x20068
5179#define XCM_REG_N_SM_CTX_LD_3 0x2006c
5180#define XCM_REG_N_SM_CTX_LD_4 0x20070
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005181#define XCM_REG_N_SM_CTX_LD_5 0x20074
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005182/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5183 acknowledge output is deasserted; all other signals are treated as usual;
5184 if 1 - normal activity. */
5185#define XCM_REG_PBF_IFEN 0x20034
5186/* [RC 1] Set at message length mismatch (relative to last indication) at
5187 the pbf interface. */
5188#define XCM_REG_PBF_LENGTH_MIS 0x20234
5189/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5190 weight 8 (the most prioritised); 1 stands for weight 1(least
5191 prioritised); 2 stands for weight 2; tc. */
5192#define XCM_REG_PBF_WEIGHT 0x200d0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005193#define XCM_REG_PHYS_QNUM3_0 0x20100
5194#define XCM_REG_PHYS_QNUM3_1 0x20104
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005195/* [RW 8] The Event ID for Timers formatting in case of stop done. */
5196#define XCM_REG_STOP_EVNT_ID 0x200b8
5197/* [RC 1] Set at message length mismatch (relative to last indication) at
5198 the STORM interface. */
5199#define XCM_REG_STORM_LENGTH_MIS 0x2021c
5200/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5201 weight 8 (the most prioritised); 1 stands for weight 1(least
5202 prioritised); 2 stands for weight 2; tc. */
5203#define XCM_REG_STORM_WEIGHT 0x200bc
5204/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5205 disregarded; acknowledge output is deasserted; all other signals are
5206 treated as usual; if 1 - normal activity. */
5207#define XCM_REG_STORM_XCM_IFEN 0x20010
5208/* [RW 4] Timers output initial credit. Max credit available - 15.Write
5209 writes the initial credit value; read returns the current value of the
5210 credit counter. Must be initialized to 4 at start-up. */
5211#define XCM_REG_TM_INIT_CRD 0x2041c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005212/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5213 weight 8 (the most prioritised); 1 stands for weight 1(least
5214 prioritised); 2 stands for weight 2; tc. */
5215#define XCM_REG_TM_WEIGHT 0x200ec
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005216/* [RW 28] The CM header for Timers expiration command. */
5217#define XCM_REG_TM_XCM_HDR 0x200a8
5218/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5219 disregarded; acknowledge output is deasserted; all other signals are
5220 treated as usual; if 1 - normal activity. */
5221#define XCM_REG_TM_XCM_IFEN 0x2001c
5222/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5223 disregarded; acknowledge output is deasserted; all other signals are
5224 treated as usual; if 1 - normal activity. */
5225#define XCM_REG_TSEM_IFEN 0x20024
5226/* [RC 1] Set at message length mismatch (relative to last indication) at
5227 the tsem interface. */
5228#define XCM_REG_TSEM_LENGTH_MIS 0x20224
5229/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5230 weight 8 (the most prioritised); 1 stands for weight 1(least
5231 prioritised); 2 stands for weight 2; tc. */
5232#define XCM_REG_TSEM_WEIGHT 0x200c0
5233/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5234#define XCM_REG_UNA_GT_NXT_Q 0x20120
5235/* [RW 1] Input usem Interface enable. If 0 - the valid input is
5236 disregarded; acknowledge output is deasserted; all other signals are
5237 treated as usual; if 1 - normal activity. */
5238#define XCM_REG_USEM_IFEN 0x2002c
5239/* [RC 1] Message length mismatch (relative to last indication) at the usem
5240 interface. */
5241#define XCM_REG_USEM_LENGTH_MIS 0x2022c
5242/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5243 weight 8 (the most prioritised); 1 stands for weight 1(least
5244 prioritised); 2 stands for weight 2; tc. */
5245#define XCM_REG_USEM_WEIGHT 0x200c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005246#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005247#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005248#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005249#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005250#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005251#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005252#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005253#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005254#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005255#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005256#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005257#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5258/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5259 acknowledge output is deasserted; all other signals are treated as usual;
5260 if 1 - normal activity. */
5261#define XCM_REG_XCM_CFC_IFEN 0x20050
5262/* [RW 14] Interrupt mask register #0 read/write */
5263#define XCM_REG_XCM_INT_MASK 0x202b4
5264/* [R 14] Interrupt register #0 read */
5265#define XCM_REG_XCM_INT_STS 0x202a8
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005266/* [RW 30] Parity mask register #0 read/write */
5267#define XCM_REG_XCM_PRTY_MASK 0x202c4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005268/* [R 30] Parity register #0 read */
5269#define XCM_REG_XCM_PRTY_STS 0x202b8
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005270/* [RC 30] Parity register #0 read clear */
5271#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5272
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005273/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5274 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5275 Is used to determine the number of the AG context REG-pairs written back;
5276 when the Reg1WbFlg isn't set. */
5277#define XCM_REG_XCM_REG0_SZ 0x200f4
5278/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5279 disregarded; valid is deasserted; all other signals are treated as usual;
5280 if 1 - normal activity. */
5281#define XCM_REG_XCM_STORM0_IFEN 0x20004
5282/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5283 disregarded; valid is deasserted; all other signals are treated as usual;
5284 if 1 - normal activity. */
5285#define XCM_REG_XCM_STORM1_IFEN 0x20008
5286/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5287 disregarded; acknowledge output is deasserted; all other signals are
5288 treated as usual; if 1 - normal activity. */
5289#define XCM_REG_XCM_TM_IFEN 0x20020
5290/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5291 disregarded; valid is deasserted; all other signals are treated as usual;
5292 if 1 - normal activity. */
5293#define XCM_REG_XCM_XQM_IFEN 0x2000c
5294/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5295#define XCM_REG_XCM_XQM_USE_Q 0x200f0
5296/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5297#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5298/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5299 the initial credit value; read returns the current value of the credit
5300 counter. Must be initialized to 32 at start-up. */
5301#define XCM_REG_XQM_INIT_CRD 0x20420
5302/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5303 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5304 prioritised); 2 stands for weight 2; tc. */
5305#define XCM_REG_XQM_P_WEIGHT 0x200e4
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005306/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5307 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5308 prioritised); 2 stands for weight 2; tc. */
5309#define XCM_REG_XQM_S_WEIGHT 0x200e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005310/* [RW 28] The CM header value for QM request (primary). */
5311#define XCM_REG_XQM_XCM_HDR_P 0x200a0
5312/* [RW 28] The CM header value for QM request (secondary). */
5313#define XCM_REG_XQM_XCM_HDR_S 0x200a4
5314/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5315 acknowledge output is deasserted; all other signals are treated as usual;
5316 if 1 - normal activity. */
5317#define XCM_REG_XQM_XCM_IFEN 0x20014
5318/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5319 acknowledge output is deasserted; all other signals are treated as usual;
5320 if 1 - normal activity. */
5321#define XCM_REG_XSDM_IFEN 0x20018
5322/* [RC 1] Set at message length mismatch (relative to last indication) at
5323 the SDM interface. */
5324#define XCM_REG_XSDM_LENGTH_MIS 0x20220
5325/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5326 weight 8 (the most prioritised); 1 stands for weight 1(least
5327 prioritised); 2 stands for weight 2; tc. */
5328#define XCM_REG_XSDM_WEIGHT 0x200e0
5329/* [RW 17] Indirect access to the descriptor table of the XX protection
5330 mechanism. The fields are: [5:0] - message length; 11:6] - message
5331 pointer; 16:12] - next pointer. */
5332#define XCM_REG_XX_DESCR_TABLE 0x20480
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005333#define XCM_REG_XX_DESCR_TABLE_SIZE 32
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005334/* [R 6] Used to read the XX protection Free counter. */
5335#define XCM_REG_XX_FREE 0x20240
5336/* [RW 6] Initial value for the credit counter; responsible for fulfilling
5337 of the Input Stage XX protection buffer by the XX protection pending
5338 messages. Max credit available - 3.Write writes the initial credit value;
5339 read returns the current value of the credit counter. Must be initialized
5340 to 2 at start-up. */
5341#define XCM_REG_XX_INIT_CRD 0x20424
5342/* [RW 6] The maximum number of pending messages; which may be stored in XX
5343 protection. ~xcm_registers_xx_free.xx_free read on read. */
5344#define XCM_REG_XX_MSG_NUM 0x20428
5345/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5346#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005347#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5348#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
Yaniv Rosner4d7e25d2011-09-07 00:48:03 +00005349#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005350#define XMAC_CTRL_REG_RX_EN (0x1<<1)
5351#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5352#define XMAC_CTRL_REG_TX_EN (0x1<<0)
5353#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5354#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5355#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5356#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5357#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5358#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5359#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5360#define XMAC_REG_CTRL 0
Yaniv Rosnerb8d6d082011-07-05 01:06:27 +00005361/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5362 * packets transmitted by the MAC */
5363#define XMAC_REG_CTRL_SA_HI 0x2c
5364/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5365 * packets transmitted by the MAC */
5366#define XMAC_REG_CTRL_SA_LO 0x28
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005367#define XMAC_REG_PAUSE_CTRL 0x68
5368#define XMAC_REG_PFC_CTRL 0x70
5369#define XMAC_REG_PFC_CTRL_HI 0x74
5370#define XMAC_REG_RX_LSS_STATUS 0x58
5371/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5372 * CRC in strip mode */
5373#define XMAC_REG_RX_MAX_SIZE 0x40
5374#define XMAC_REG_TX_CTRL 0x20
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005375/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005376 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5377 header pointer. */
5378#define XCM_REG_XX_TABLE 0x20500
5379/* [RW 8] The event id for aggregated interrupt 0 */
5380#define XSDM_REG_AGG_INT_EVENT_0 0x166038
5381#define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5382#define XSDM_REG_AGG_INT_EVENT_10 0x166060
5383#define XSDM_REG_AGG_INT_EVENT_11 0x166064
5384#define XSDM_REG_AGG_INT_EVENT_12 0x166068
5385#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5386#define XSDM_REG_AGG_INT_EVENT_14 0x166070
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005387#define XSDM_REG_AGG_INT_EVENT_2 0x166040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005388#define XSDM_REG_AGG_INT_EVENT_3 0x166044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005389#define XSDM_REG_AGG_INT_EVENT_4 0x166048
5390#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5391#define XSDM_REG_AGG_INT_EVENT_6 0x166050
5392#define XSDM_REG_AGG_INT_EVENT_7 0x166054
5393#define XSDM_REG_AGG_INT_EVENT_8 0x166058
5394#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005395/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5396 or auto-mask-mode (1) */
5397#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5398#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005399/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5400#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005401/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005402#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005403/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005404#define XSDM_REG_CMP_COUNTER_MAX1 0x166020
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005405/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005406#define XSDM_REG_CMP_COUNTER_MAX2 0x166024
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005407/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005408#define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5409/* [RW 13] The start address in the internal RAM for the completion
5410 counters. */
5411#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5412#define XSDM_REG_ENABLE_IN1 0x166238
5413#define XSDM_REG_ENABLE_IN2 0x16623c
5414#define XSDM_REG_ENABLE_OUT1 0x166240
5415#define XSDM_REG_ENABLE_OUT2 0x166244
5416/* [RW 4] The initial number of messages that can be sent to the pxp control
5417 interface without receiving any ACK. */
5418#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5419/* [ST 32] The number of ACK after placement messages received */
5420#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5421/* [ST 32] The number of packet end messages received from the parser */
5422#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5423/* [ST 32] The number of requests received from the pxp async if */
5424#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5425/* [ST 32] The number of commands received in queue 0 */
5426#define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5427/* [ST 32] The number of commands received in queue 10 */
5428#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5429/* [ST 32] The number of commands received in queue 11 */
5430#define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5431/* [ST 32] The number of commands received in queue 1 */
5432#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5433/* [ST 32] The number of commands received in queue 3 */
5434#define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5435/* [ST 32] The number of commands received in queue 4 */
5436#define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5437/* [ST 32] The number of commands received in queue 5 */
5438#define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5439/* [ST 32] The number of commands received in queue 6 */
5440#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5441/* [ST 32] The number of commands received in queue 7 */
5442#define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5443/* [ST 32] The number of commands received in queue 8 */
5444#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5445/* [ST 32] The number of commands received in queue 9 */
5446#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005447/* [RW 13] The start address in the internal RAM for queue counters */
5448#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005449/* [W 17] Generate an operation after completion; bit-16 is
5450 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5451 * bits 4:0 are the T124Param[4:0] */
5452#define XSDM_REG_OPERATION_GEN 0x1664c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005453/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5454#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5455/* [R 1] parser fifo empty in sdm_sync block */
5456#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5457/* [R 1] parser serial fifo empty in sdm_sync block */
5458#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5459/* [RW 32] Tick for timer counter. Applicable only when
5460 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5461#define XSDM_REG_TIMER_TICK 0x166000
5462/* [RW 32] Interrupt mask register #0 read/write */
5463#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5464#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005465/* [R 32] Interrupt register #0 read */
5466#define XSDM_REG_XSDM_INT_STS_0 0x166290
5467#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005468/* [RW 11] Parity mask register #0 read/write */
5469#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
Eliezer Tamirf1410642008-02-28 11:51:50 -08005470/* [R 11] Parity register #0 read */
5471#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00005472/* [RC 11] Parity register #0 read clear */
5473#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005474/* [RW 5] The number of time_slots in the arbitration cycle */
5475#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5476/* [RW 3] The source that is associated with arbitration element 0. Source
5477 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5478 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5479#define XSEM_REG_ARB_ELEMENT0 0x280020
5480/* [RW 3] The source that is associated with arbitration element 1. Source
5481 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5482 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5483 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5484#define XSEM_REG_ARB_ELEMENT1 0x280024
5485/* [RW 3] The source that is associated with arbitration element 2. Source
5486 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5487 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5488 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5489 and ~xsem_registers_arb_element1.arb_element1 */
5490#define XSEM_REG_ARB_ELEMENT2 0x280028
5491/* [RW 3] The source that is associated with arbitration element 3. Source
5492 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5493 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5494 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5495 ~xsem_registers_arb_element1.arb_element1 and
5496 ~xsem_registers_arb_element2.arb_element2 */
5497#define XSEM_REG_ARB_ELEMENT3 0x28002c
5498/* [RW 3] The source that is associated with arbitration element 4. Source
5499 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5500 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5501 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5502 and ~xsem_registers_arb_element1.arb_element1 and
5503 ~xsem_registers_arb_element2.arb_element2 and
5504 ~xsem_registers_arb_element3.arb_element3 */
5505#define XSEM_REG_ARB_ELEMENT4 0x280030
5506#define XSEM_REG_ENABLE_IN 0x2800a4
5507#define XSEM_REG_ENABLE_OUT 0x2800a8
5508/* [RW 32] This address space contains all registers and memories that are
5509 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005510 appendix B. In order to access the sem_fast registers the base address
5511 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005512#define XSEM_REG_FAST_MEMORY 0x2a0000
5513/* [RW 1] Disables input messages from FIC0 May be updated during run_time
5514 by the microcode */
5515#define XSEM_REG_FIC0_DISABLE 0x280224
5516/* [RW 1] Disables input messages from FIC1 May be updated during run_time
5517 by the microcode */
5518#define XSEM_REG_FIC1_DISABLE 0x280234
5519/* [RW 15] Interrupt table Read and write access to it is not possible in
5520 the middle of the work */
5521#define XSEM_REG_INT_TABLE 0x280400
5522/* [ST 24] Statistics register. The number of messages that entered through
5523 FIC0 */
5524#define XSEM_REG_MSG_NUM_FIC0 0x280000
5525/* [ST 24] Statistics register. The number of messages that entered through
5526 FIC1 */
5527#define XSEM_REG_MSG_NUM_FIC1 0x280004
5528/* [ST 24] Statistics register. The number of messages that were sent to
5529 FOC0 */
5530#define XSEM_REG_MSG_NUM_FOC0 0x280008
5531/* [ST 24] Statistics register. The number of messages that were sent to
5532 FOC1 */
5533#define XSEM_REG_MSG_NUM_FOC1 0x28000c
5534/* [ST 24] Statistics register. The number of messages that were sent to
5535 FOC2 */
5536#define XSEM_REG_MSG_NUM_FOC2 0x280010
5537/* [ST 24] Statistics register. The number of messages that were sent to
5538 FOC3 */
5539#define XSEM_REG_MSG_NUM_FOC3 0x280014
5540/* [RW 1] Disables input messages from the passive buffer May be updated
5541 during run_time by the microcode */
5542#define XSEM_REG_PAS_DISABLE 0x28024c
5543/* [WB 128] Debug only. Passive buffer memory */
5544#define XSEM_REG_PASSIVE_BUFFER 0x282000
5545/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5546#define XSEM_REG_PRAM 0x2c0000
5547/* [R 16] Valid sleeping threads indication have bit per thread */
5548#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5549/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5550#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5551/* [RW 16] List of free threads . There is a bit per thread. */
5552#define XSEM_REG_THREADS_LIST 0x2802e4
5553/* [RW 3] The arbitration scheme of time_slot 0 */
5554#define XSEM_REG_TS_0_AS 0x280038
5555/* [RW 3] The arbitration scheme of time_slot 10 */
5556#define XSEM_REG_TS_10_AS 0x280060
5557/* [RW 3] The arbitration scheme of time_slot 11 */
5558#define XSEM_REG_TS_11_AS 0x280064
5559/* [RW 3] The arbitration scheme of time_slot 12 */
5560#define XSEM_REG_TS_12_AS 0x280068
5561/* [RW 3] The arbitration scheme of time_slot 13 */
5562#define XSEM_REG_TS_13_AS 0x28006c
5563/* [RW 3] The arbitration scheme of time_slot 14 */
5564#define XSEM_REG_TS_14_AS 0x280070
5565/* [RW 3] The arbitration scheme of time_slot 15 */
5566#define XSEM_REG_TS_15_AS 0x280074
5567/* [RW 3] The arbitration scheme of time_slot 16 */
5568#define XSEM_REG_TS_16_AS 0x280078
5569/* [RW 3] The arbitration scheme of time_slot 17 */
5570#define XSEM_REG_TS_17_AS 0x28007c
5571/* [RW 3] The arbitration scheme of time_slot 18 */
5572#define XSEM_REG_TS_18_AS 0x280080
5573/* [RW 3] The arbitration scheme of time_slot 1 */
5574#define XSEM_REG_TS_1_AS 0x28003c
5575/* [RW 3] The arbitration scheme of time_slot 2 */
5576#define XSEM_REG_TS_2_AS 0x280040
5577/* [RW 3] The arbitration scheme of time_slot 3 */
5578#define XSEM_REG_TS_3_AS 0x280044
5579/* [RW 3] The arbitration scheme of time_slot 4 */
5580#define XSEM_REG_TS_4_AS 0x280048
5581/* [RW 3] The arbitration scheme of time_slot 5 */
5582#define XSEM_REG_TS_5_AS 0x28004c
5583/* [RW 3] The arbitration scheme of time_slot 6 */
5584#define XSEM_REG_TS_6_AS 0x280050
5585/* [RW 3] The arbitration scheme of time_slot 7 */
5586#define XSEM_REG_TS_7_AS 0x280054
5587/* [RW 3] The arbitration scheme of time_slot 8 */
5588#define XSEM_REG_TS_8_AS 0x280058
5589/* [RW 3] The arbitration scheme of time_slot 9 */
5590#define XSEM_REG_TS_9_AS 0x28005c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005591/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5592 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5593#define XSEM_REG_VFPF_ERR_NUM 0x280380
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005594/* [RW 32] Interrupt mask register #0 read/write */
5595#define XSEM_REG_XSEM_INT_MASK_0 0x280110
5596#define XSEM_REG_XSEM_INT_MASK_1 0x280120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005597/* [R 32] Interrupt register #0 read */
5598#define XSEM_REG_XSEM_INT_STS_0 0x280104
5599#define XSEM_REG_XSEM_INT_STS_1 0x280114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005600/* [RW 32] Parity mask register #0 read/write */
5601#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5602#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
Eliezer Tamirf1410642008-02-28 11:51:50 -08005603/* [R 32] Parity register #0 read */
5604#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5605#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00005606/* [RC 32] Parity register #0 read clear */
5607#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5608#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005609#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5610#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5611#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5612#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5613#define MCPR_NVM_COMMAND_DOIT (1L<<4)
5614#define MCPR_NVM_COMMAND_DONE (1L<<3)
5615#define MCPR_NVM_COMMAND_FIRST (1L<<7)
5616#define MCPR_NVM_COMMAND_LAST (1L<<8)
5617#define MCPR_NVM_COMMAND_WR (1L<<5)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005618#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5619#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5620#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5621#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5622#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5623#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5624#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5625#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
Yaniv Rosner3deb8162011-06-14 01:34:33 +00005626#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005627#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5628#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5629#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5630#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5631#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5632#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5633#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5634#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5635#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005636#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5637#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5638#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5639#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5640#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5641#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
Yaniv Rosner3deb8162011-06-14 01:34:33 +00005642#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005643#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5644#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5645#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5646#define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5647#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5648#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5649#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5650#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5651#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5652#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5653#define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005654#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5655#define EMAC_LED_100MB_OVERRIDE (1L<<2)
5656#define EMAC_LED_10MB_OVERRIDE (1L<<3)
5657#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5658#define EMAC_LED_OVERRIDE (1L<<0)
5659#define EMAC_LED_TRAFFIC (1L<<6)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005660#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
Yaniv Rosner6583e332011-06-14 01:34:17 +00005661#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005662#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
Yaniv Rosner6583e332011-06-14 01:34:17 +00005663#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005664#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5665#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5666#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5667#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5668#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
Yaniv Rosner157fa282011-08-02 22:59:32 +00005669#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
Eliezer Tamirf1410642008-02-28 11:51:50 -08005670#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
Yaniv Rosner157fa282011-08-02 22:59:32 +00005671#define EMAC_MDIO_STATUS_10MB (1L<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005672#define EMAC_MODE_25G_MODE (1L<<5)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005673#define EMAC_MODE_HALF_DUPLEX (1L<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005674#define EMAC_MODE_PORT_GMII (2L<<2)
5675#define EMAC_MODE_PORT_MII (1L<<2)
5676#define EMAC_MODE_PORT_MII_10M (3L<<2)
5677#define EMAC_MODE_RESET (1L<<0)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005678#define EMAC_REG_EMAC_LED 0xc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005679#define EMAC_REG_EMAC_MAC_MATCH 0x10
5680#define EMAC_REG_EMAC_MDIO_COMM 0xac
5681#define EMAC_REG_EMAC_MDIO_MODE 0xb4
Yaniv Rosner157fa282011-08-02 22:59:32 +00005682#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005683#define EMAC_REG_EMAC_MODE 0x0
5684#define EMAC_REG_EMAC_RX_MODE 0xc8
5685#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5686#define EMAC_REG_EMAC_RX_STAT_AC 0x180
5687#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5688#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5689#define EMAC_REG_EMAC_TX_MODE 0xbc
5690#define EMAC_REG_EMAC_TX_STAT_AC 0x280
5691#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00005692#define EMAC_REG_RX_PFC_MODE 0x320
5693#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5694#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5695#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5696#define EMAC_REG_RX_PFC_PARAM 0x324
5697#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5698#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5699#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5700#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5701#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5702#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5703#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5704#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5705#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5706#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005707#define EMAC_RX_MODE_FLOW_EN (1L<<2)
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00005708#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005709#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5710#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
Eilon Greenstein811a2f22009-02-12 08:37:04 +00005711#define EMAC_RX_MODE_RESET (1L<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005712#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5713#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07005714#define EMAC_TX_MODE_FLOW_EN (1L<<4)
Eilon Greenstein811a2f22009-02-12 08:37:04 +00005715#define EMAC_TX_MODE_RESET (1L<<0)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005716#define MISC_REGISTERS_GPIO_0 0
Eliezer Tamirf1410642008-02-28 11:51:50 -08005717#define MISC_REGISTERS_GPIO_1 1
5718#define MISC_REGISTERS_GPIO_2 2
5719#define MISC_REGISTERS_GPIO_3 3
5720#define MISC_REGISTERS_GPIO_CLR_POS 16
5721#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5722#define MISC_REGISTERS_GPIO_FLOAT_POS 24
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005723#define MISC_REGISTERS_GPIO_HIGH 1
Eliezer Tamirf1410642008-02-28 11:51:50 -08005724#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00005725#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5726#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5727#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5728#define MISC_REGISTERS_GPIO_INT_SET_POS 16
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005729#define MISC_REGISTERS_GPIO_LOW 0
Eliezer Tamirf1410642008-02-28 11:51:50 -08005730#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5731#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5732#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5733#define MISC_REGISTERS_GPIO_SET_POS 8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005734#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
Ariel Eliorf16da432012-01-26 06:01:50 +00005735#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005736#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07005737#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005738#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5739#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005740#define MISC_REGISTERS_RESET_REG_1_SET 0x584
5741#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005742#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5743#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
Vladislav Zolotarov8736c822011-07-21 07:58:36 +00005744#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
5745#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005746#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
Vladislav Zolotarov8736c822011-07-21 07:58:36 +00005747#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
5748#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005749#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
Vladislav Zolotarov8736c822011-07-21 07:58:36 +00005750#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005751#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5752#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5753#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005754#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5755#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005756#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5757#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5758#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005759#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005760#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005761#define MISC_REGISTERS_RESET_REG_2_SET 0x594
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005762#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
Vladislav Zolotarov8736c822011-07-21 07:58:36 +00005763#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005764#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5765#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005766#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5767#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5768#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5769#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5770#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5771#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5772#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5773#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5774#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5775#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5776#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
Eliezer Tamirf1410642008-02-28 11:51:50 -08005777#define MISC_REGISTERS_SPIO_4 4
5778#define MISC_REGISTERS_SPIO_5 5
5779#define MISC_REGISTERS_SPIO_7 7
5780#define MISC_REGISTERS_SPIO_CLR_POS 16
5781#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
Eliezer Tamirf1410642008-02-28 11:51:50 -08005782#define MISC_REGISTERS_SPIO_FLOAT_POS 24
5783#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5784#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5785#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5786#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5787#define MISC_REGISTERS_SPIO_SET_POS 8
5788#define HW_LOCK_MAX_RESOURCE_VALUE 31
Ariel Eliorf16da432012-01-26 06:01:50 +00005789#define HW_LOCK_RESOURCE_DRV_FLAGS 10
Eliezer Tamirf1410642008-02-28 11:51:50 -08005790#define HW_LOCK_RESOURCE_GPIO 1
Eilon Greenstein46c6a672009-02-12 08:36:58 +00005791#define HW_LOCK_RESOURCE_MDIO 0
Ariel Eliorf16da432012-01-26 06:01:50 +00005792#define HW_LOCK_RESOURCE_NVRAM 12
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005793#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5794#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5795#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
Ariel Eliorf16da432012-01-26 06:01:50 +00005796#define HW_LOCK_RESOURCE_RECOVERY_REG 11
Dmitry Kravkov7a06a122011-08-30 00:08:43 +00005797#define HW_LOCK_RESOURCE_RESET 5
Ariel Eliorf16da432012-01-26 06:01:50 +00005798#define HW_LOCK_RESOURCE_SPIO 2
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005799#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5800#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5801#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5802#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5803#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5804#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5805#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5806#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5807#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5808#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5809#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
5810#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
5811#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
5812#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
5813#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
5814#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
5815#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
5816#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
5817#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
5818#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
5819#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
5820#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
5821#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
5822#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
5823#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
5824#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
5825#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
5826#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
5827#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
5828#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
5829#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
5830#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5831#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5832#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
5833#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
5834#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
5835#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
5836#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
5837#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
5838#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
5839#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
5840#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
5841#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
5842#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
5843#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
5844#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
5845#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
5846#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
5847#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
5848#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
5849#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
5850#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
5851#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
5852#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
5853#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
5854#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
5855#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
5856#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
5857#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
5858#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
5859#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
5860#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
5861#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
5862#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
5863
5864#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
5865#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
5866
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005867#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5868
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005869#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005870#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5871
5872#define RESERVED_GENERAL_ATTENTION_BIT_6 6
5873#define RESERVED_GENERAL_ATTENTION_BIT_7 7
5874#define RESERVED_GENERAL_ATTENTION_BIT_8 8
5875#define RESERVED_GENERAL_ATTENTION_BIT_9 9
5876#define RESERVED_GENERAL_ATTENTION_BIT_10 10
5877#define RESERVED_GENERAL_ATTENTION_BIT_11 11
5878#define RESERVED_GENERAL_ATTENTION_BIT_12 12
5879#define RESERVED_GENERAL_ATTENTION_BIT_13 13
5880#define RESERVED_GENERAL_ATTENTION_BIT_14 14
5881#define RESERVED_GENERAL_ATTENTION_BIT_15 15
5882#define RESERVED_GENERAL_ATTENTION_BIT_16 16
5883#define RESERVED_GENERAL_ATTENTION_BIT_17 17
5884#define RESERVED_GENERAL_ATTENTION_BIT_18 18
5885#define RESERVED_GENERAL_ATTENTION_BIT_19 19
5886#define RESERVED_GENERAL_ATTENTION_BIT_20 20
5887#define RESERVED_GENERAL_ATTENTION_BIT_21 21
5888
5889/* storm asserts attention bits */
5890#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5891#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5892#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5893#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5894
5895/* mcp error attention bit */
5896#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5897
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005898/*E1H NIG status sync attention mapped to group 4-7*/
5899#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5900#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5901#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5902#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5903#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5904#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5905#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5906#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5907
5908
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005909#define LATCHED_ATTN_RBCR 23
5910#define LATCHED_ATTN_RBCT 24
5911#define LATCHED_ATTN_RBCN 25
5912#define LATCHED_ATTN_RBCU 26
5913#define LATCHED_ATTN_RBCP 27
5914#define LATCHED_ATTN_TIMEOUT_GRC 28
5915#define LATCHED_ATTN_RSVD_GRC 29
5916#define LATCHED_ATTN_ROM_PARITY_MCP 30
5917#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5918#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5919#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5920
5921#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00005922#define GENERAL_ATTEN_OFFSET(atten_name)\
5923 (1UL << ((94 + atten_name) % 32))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005924/*
5925 * This file defines GRC base address for every block.
5926 * This file is included by chipsim, asm microcode and cpp microcode.
5927 * These values are used in Design.xml on regBase attribute
5928 * Use the base with the generated offsets of specific registers.
5929 */
5930
5931#define GRCBASE_PXPCS 0x000000
5932#define GRCBASE_PCICONFIG 0x002000
5933#define GRCBASE_PCIREG 0x002400
5934#define GRCBASE_EMAC0 0x008000
5935#define GRCBASE_EMAC1 0x008400
5936#define GRCBASE_DBU 0x008800
5937#define GRCBASE_MISC 0x00A000
5938#define GRCBASE_DBG 0x00C000
5939#define GRCBASE_NIG 0x010000
5940#define GRCBASE_XCM 0x020000
5941#define GRCBASE_PRS 0x040000
5942#define GRCBASE_SRCH 0x040400
5943#define GRCBASE_TSDM 0x042000
5944#define GRCBASE_TCM 0x050000
5945#define GRCBASE_BRB1 0x060000
5946#define GRCBASE_MCP 0x080000
5947#define GRCBASE_UPB 0x0C1000
5948#define GRCBASE_CSDM 0x0C2000
5949#define GRCBASE_USDM 0x0C4000
5950#define GRCBASE_CCM 0x0D0000
5951#define GRCBASE_UCM 0x0E0000
5952#define GRCBASE_CDU 0x101000
5953#define GRCBASE_DMAE 0x102000
5954#define GRCBASE_PXP 0x103000
5955#define GRCBASE_CFC 0x104000
5956#define GRCBASE_HC 0x108000
5957#define GRCBASE_PXP2 0x120000
5958#define GRCBASE_PBF 0x140000
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005959#define GRCBASE_UMAC0 0x160000
5960#define GRCBASE_UMAC1 0x160400
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005961#define GRCBASE_XPB 0x161000
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005962#define GRCBASE_MSTAT0 0x162000
5963#define GRCBASE_MSTAT1 0x162800
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005964#define GRCBASE_XMAC0 0x163000
5965#define GRCBASE_XMAC1 0x163800
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005966#define GRCBASE_TIMERS 0x164000
5967#define GRCBASE_XSDM 0x166000
5968#define GRCBASE_QM 0x168000
5969#define GRCBASE_DQ 0x170000
5970#define GRCBASE_TSEM 0x180000
5971#define GRCBASE_CSEM 0x200000
5972#define GRCBASE_XSEM 0x280000
5973#define GRCBASE_USEM 0x300000
5974#define GRCBASE_MISC_AEU GRCBASE_MISC
5975
5976
Eilon Greenstein5c862842008-08-13 15:51:48 -07005977/* offset of configuration space in the pci core register */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005978#define PCICFG_OFFSET 0x2000
5979#define PCICFG_VENDOR_ID_OFFSET 0x00
5980#define PCICFG_DEVICE_ID_OFFSET 0x02
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005981#define PCICFG_COMMAND_OFFSET 0x04
Eilon Greenstein5c862842008-08-13 15:51:48 -07005982#define PCICFG_COMMAND_IO_SPACE (1<<0)
5983#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5984#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5985#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5986#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5987#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5988#define PCICFG_COMMAND_PERR_ENA (1<<6)
5989#define PCICFG_COMMAND_STEPPING (1<<7)
5990#define PCICFG_COMMAND_SERR_ENA (1<<8)
5991#define PCICFG_COMMAND_FAST_B2B (1<<9)
5992#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5993#define PCICFG_COMMAND_RESERVED (0x1f<<11)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005994#define PCICFG_STATUS_OFFSET 0x06
Eilon Greenstein0d1a8d22009-03-02 07:59:20 +00005995#define PCICFG_REVESION_ID_OFFSET 0x08
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005996#define PCICFG_CACHE_LINE_SIZE 0x0c
5997#define PCICFG_LATENCY_TIMER 0x0d
Eilon Greenstein5c862842008-08-13 15:51:48 -07005998#define PCICFG_BAR_1_LOW 0x10
5999#define PCICFG_BAR_1_HIGH 0x14
6000#define PCICFG_BAR_2_LOW 0x18
6001#define PCICFG_BAR_2_HIGH 0x1c
6002#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006003#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
Eilon Greenstein5c862842008-08-13 15:51:48 -07006004#define PCICFG_INT_LINE 0x3c
6005#define PCICFG_INT_PIN 0x3d
6006#define PCICFG_PM_CAPABILITY 0x48
6007#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
6008#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
6009#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
6010#define PCICFG_PM_CAPABILITY_DSI (1<<21)
6011#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
6012#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
6013#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
6014#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
6015#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
6016#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
6017#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
6018#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
6019#define PCICFG_PM_CSR_OFFSET 0x4c
6020#define PCICFG_PM_CSR_STATE (0x3<<0)
6021#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
6022#define PCICFG_PM_CSR_PME_STATUS (1<<15)
Eilon Greenstein0d1a8d22009-03-02 07:59:20 +00006023#define PCICFG_MSI_CAP_ID_OFFSET 0x58
Eilon Greenstein8badd272009-02-12 08:36:15 +00006024#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
6025#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
6026#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
6027#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
6028#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
Eilon Greenstein5c862842008-08-13 15:51:48 -07006029#define PCICFG_GRC_ADDRESS 0x78
Ariel Eliorc22610d02012-01-26 06:01:47 +00006030#define PCICFG_GRC_DATA 0x80
6031#define PCICFG_ME_REGISTER 0x98
Eilon Greenstein0d1a8d22009-03-02 07:59:20 +00006032#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
Eilon Greenstein8badd272009-02-12 08:36:15 +00006033#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
6034#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
6035#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
6036#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
6037
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006038#define PCICFG_DEVICE_CONTROL 0xb4
Eilon Greenstein8badd272009-02-12 08:36:15 +00006039#define PCICFG_DEVICE_STATUS 0xb6
6040#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
6041#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
6042#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
6043#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
6044#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
6045#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006046#define PCICFG_LINK_CONTROL 0xbc
6047
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006048
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006049#define BAR_USTRORM_INTMEM 0x400000
6050#define BAR_CSTRORM_INTMEM 0x410000
6051#define BAR_XSTRORM_INTMEM 0x420000
6052#define BAR_TSTRORM_INTMEM 0x430000
6053
Eilon Greenstein5c862842008-08-13 15:51:48 -07006054/* for accessing the IGU in case of status block ACK */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006055#define BAR_IGU_INTMEM 0x440000
6056
6057#define BAR_DOORBELL_OFFSET 0x800000
6058
6059#define BAR_ME_REGISTER 0x450000
6060
Eilon Greenstein5c862842008-08-13 15:51:48 -07006061/* config_2 offset */
6062#define GRC_CONFIG_2_SIZE_REG 0x408
6063#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006064#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
6065#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
6066#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
6067#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6068#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
6069#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
6070#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
6071#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
6072#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
6073#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
6074#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
6075#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
6076#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
6077#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
6078#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
6079#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
Eilon Greenstein5c862842008-08-13 15:51:48 -07006080#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
6081#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
6082#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
6083#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
6084#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006085#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
6086#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
6087#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
6088#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
6089#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
6090#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
6091#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
6092#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
6093#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
6094#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
6095#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
6096#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
6097#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
6098#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
6099#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
6100#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
Eilon Greenstein5c862842008-08-13 15:51:48 -07006101#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
6102#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006103
6104/* config_3 offset */
Eilon Greenstein5c862842008-08-13 15:51:48 -07006105#define GRC_CONFIG_3_SIZE_REG 0x40c
6106#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
6107#define PCI_CONFIG_3_FORCE_PME (1L<<24)
6108#define PCI_CONFIG_3_PME_STATUS (1L<<25)
6109#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
6110#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
6111#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
6112#define PCI_CONFIG_3_PCI_POWER (1L<<31)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006113
6114#define GRC_BAR2_CONFIG 0x4e0
Eilon Greenstein5c862842008-08-13 15:51:48 -07006115#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
6116#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
6117#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
6118#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
6119#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6120#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
6121#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
6122#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
6123#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
6124#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
6125#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
6126#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
6127#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
6128#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
6129#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
6130#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
6131#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
6132#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006133
Eilon Greenstein5c862842008-08-13 15:51:48 -07006134#define PCI_PM_DATA_A 0x410
6135#define PCI_PM_DATA_B 0x414
6136#define PCI_ID_VAL1 0x434
6137#define PCI_ID_VAL2 0x438
6138
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00006139#define PXPCS_TL_CONTROL_5 0x814
6140#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
6141#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
6142#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
6143#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
6144#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
6145#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
6146#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
6147#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
6148#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
6149#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
6150#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
6151#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
6152#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
6153#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
6154#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
6155#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
6156#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
6157#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
6158#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
6159#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
6160#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
6161#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
6162#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
6163#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
6164#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
6165#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
6166#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
6167#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
6168#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
6169#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
6170
6171
6172#define PXPCS_TL_FUNC345_STAT 0x854
6173#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
6174#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
6175 (1 << 28) /* Unsupported Request Error Status in function4, if \
6176 set, generate pcie_err_attn output when this error is seen. WC */
6177#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
6178 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
6179 generate pcie_err_attn output when this error is seen.. WC */
6180#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
6181 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
6182 generate pcie_err_attn output when this error is seen.. WC */
6183#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
6184 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
6185 set, generate pcie_err_attn output when this error is seen.. WC \
6186 */
6187#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
6188 (1 << 24) /* Unexpected Completion Status Status in function 4, \
6189 if set, generate pcie_err_attn output when this error is seen. WC \
6190 */
6191#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
6192 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
6193 pcie_err_attn output when this error is seen. WC */
6194#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
6195 (1 << 22) /* Completer Timeout Status Status in function 4, if \
6196 set, generate pcie_err_attn output when this error is seen. WC */
6197#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
6198 (1 << 21) /* Flow Control Protocol Error Status Status in \
6199 function 4, if set, generate pcie_err_attn output when this error \
6200 is seen. WC */
6201#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
6202 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
6203 generate pcie_err_attn output when this error is seen.. WC */
6204#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
6205#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
6206 (1 << 18) /* Unsupported Request Error Status in function3, if \
6207 set, generate pcie_err_attn output when this error is seen. WC */
6208#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
6209 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6210 generate pcie_err_attn output when this error is seen.. WC */
6211#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
6212 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6213 generate pcie_err_attn output when this error is seen.. WC */
6214#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
6215 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6216 set, generate pcie_err_attn output when this error is seen.. WC \
6217 */
6218#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
6219 (1 << 14) /* Unexpected Completion Status Status in function 3, \
6220 if set, generate pcie_err_attn output when this error is seen. WC \
6221 */
6222#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
6223 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6224 pcie_err_attn output when this error is seen. WC */
6225#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
6226 (1 << 12) /* Completer Timeout Status Status in function 3, if \
6227 set, generate pcie_err_attn output when this error is seen. WC */
6228#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
6229 (1 << 11) /* Flow Control Protocol Error Status Status in \
6230 function 3, if set, generate pcie_err_attn output when this error \
6231 is seen. WC */
6232#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
6233 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6234 generate pcie_err_attn output when this error is seen.. WC */
6235#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
6236#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
6237 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
6238 set, generate pcie_err_attn output when this error is seen. WC */
6239#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
6240 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
6241 generate pcie_err_attn output when this error is seen.. WC */
6242#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
6243 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
6244 generate pcie_err_attn output when this error is seen.. WC */
6245#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
6246 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
6247 set, generate pcie_err_attn output when this error is seen.. WC \
6248 */
6249#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6250 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6251 if set, generate pcie_err_attn output when this error is seen. WC \
6252 */
6253#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6254 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6255 pcie_err_attn output when this error is seen. WC */
6256#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6257 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6258 set, generate pcie_err_attn output when this error is seen. WC */
6259#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6260 (1 << 1) /* Flow Control Protocol Error Status Status for \
6261 Function 2, if set, generate pcie_err_attn output when this error \
6262 is seen. WC */
6263#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6264 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6265 generate pcie_err_attn output when this error is seen.. WC */
6266
6267
6268#define PXPCS_TL_FUNC678_STAT 0x85C
6269#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
6270#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6271 (1 << 28) /* Unsupported Request Error Status in function7, if \
6272 set, generate pcie_err_attn output when this error is seen. WC */
6273#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6274 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6275 generate pcie_err_attn output when this error is seen.. WC */
6276#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6277 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6278 generate pcie_err_attn output when this error is seen.. WC */
6279#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6280 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6281 set, generate pcie_err_attn output when this error is seen.. WC \
6282 */
6283#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6284 (1 << 24) /* Unexpected Completion Status Status in function 7, \
6285 if set, generate pcie_err_attn output when this error is seen. WC \
6286 */
6287#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6288 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6289 pcie_err_attn output when this error is seen. WC */
6290#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6291 (1 << 22) /* Completer Timeout Status Status in function 7, if \
6292 set, generate pcie_err_attn output when this error is seen. WC */
6293#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6294 (1 << 21) /* Flow Control Protocol Error Status Status in \
6295 function 7, if set, generate pcie_err_attn output when this error \
6296 is seen. WC */
6297#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6298 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6299 generate pcie_err_attn output when this error is seen.. WC */
6300#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
6301#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6302 (1 << 18) /* Unsupported Request Error Status in function6, if \
6303 set, generate pcie_err_attn output when this error is seen. WC */
6304#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6305 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6306 generate pcie_err_attn output when this error is seen.. WC */
6307#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6308 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6309 generate pcie_err_attn output when this error is seen.. WC */
6310#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6311 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6312 set, generate pcie_err_attn output when this error is seen.. WC \
6313 */
6314#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6315 (1 << 14) /* Unexpected Completion Status Status in function 6, \
6316 if set, generate pcie_err_attn output when this error is seen. WC \
6317 */
6318#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6319 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6320 pcie_err_attn output when this error is seen. WC */
6321#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6322 (1 << 12) /* Completer Timeout Status Status in function 6, if \
6323 set, generate pcie_err_attn output when this error is seen. WC */
6324#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6325 (1 << 11) /* Flow Control Protocol Error Status Status in \
6326 function 6, if set, generate pcie_err_attn output when this error \
6327 is seen. WC */
6328#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6329 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6330 generate pcie_err_attn output when this error is seen.. WC */
6331#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
6332#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6333 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6334 set, generate pcie_err_attn output when this error is seen. WC */
6335#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6336 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6337 generate pcie_err_attn output when this error is seen.. WC */
6338#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6339 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6340 generate pcie_err_attn output when this error is seen.. WC */
6341#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6342 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6343 set, generate pcie_err_attn output when this error is seen.. WC \
6344 */
6345#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6346 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6347 if set, generate pcie_err_attn output when this error is seen. WC \
6348 */
6349#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6350 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6351 pcie_err_attn output when this error is seen. WC */
6352#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6353 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6354 set, generate pcie_err_attn output when this error is seen. WC */
6355#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6356 (1 << 1) /* Flow Control Protocol Error Status Status for \
6357 Function 5, if set, generate pcie_err_attn output when this error \
6358 is seen. WC */
6359#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6360 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6361 generate pcie_err_attn output when this error is seen.. WC */
6362
6363
6364#define BAR_USTRORM_INTMEM 0x400000
6365#define BAR_CSTRORM_INTMEM 0x410000
6366#define BAR_XSTRORM_INTMEM 0x420000
6367#define BAR_TSTRORM_INTMEM 0x430000
6368
6369/* for accessing the IGU in case of status block ACK */
6370#define BAR_IGU_INTMEM 0x440000
6371
6372#define BAR_DOORBELL_OFFSET 0x800000
6373
6374#define BAR_ME_REGISTER 0x450000
6375#define ME_REG_PF_NUM_SHIFT 0
6376#define ME_REG_PF_NUM\
6377 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6378#define ME_REG_VF_VALID (1<<8)
6379#define ME_REG_VF_NUM_SHIFT 9
6380#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6381#define ME_REG_VF_ERR (0x1<<3)
6382#define ME_REG_ABS_PF_NUM_SHIFT 16
6383#define ME_REG_ABS_PF_NUM\
6384 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6385
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006386
Yaniv Rosner7846e472009-11-05 19:18:07 +02006387#define MDIO_REG_BANK_CL73_IEEEB0 0x0
6388#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006389#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6390#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6391#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6392
Yaniv Rosner7846e472009-11-05 19:18:07 +02006393#define MDIO_REG_BANK_CL73_IEEEB1 0x10
6394#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6395#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6396#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6397#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6398#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6399#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006400#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6401#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6402#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6403#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
Yaniv Rosner7846e472009-11-05 19:18:07 +02006404#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6405#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6406#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6407#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6408#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
Mintz Yuval9e7e8392012-02-15 02:10:24 +00006409#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006410
6411#define MDIO_REG_BANK_RX0 0x80b0
Eilon Greenstein239d6862009-08-12 08:23:04 +00006412#define MDIO_RX0_RX_STATUS 0x10
6413#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6414#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006415#define MDIO_RX0_RX_EQ_BOOST 0x1c
6416#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6417#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6418
6419#define MDIO_REG_BANK_RX1 0x80c0
6420#define MDIO_RX1_RX_EQ_BOOST 0x1c
6421#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6422#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6423
6424#define MDIO_REG_BANK_RX2 0x80d0
6425#define MDIO_RX2_RX_EQ_BOOST 0x1c
6426#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6427#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6428
6429#define MDIO_REG_BANK_RX3 0x80e0
6430#define MDIO_RX3_RX_EQ_BOOST 0x1c
6431#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6432#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6433
6434#define MDIO_REG_BANK_RX_ALL 0x80f0
6435#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6436#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006437#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006438
6439#define MDIO_REG_BANK_TX0 0x8060
6440#define MDIO_TX0_TX_DRIVER 0x17
6441#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6442#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6443#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6444#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6445#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6446#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6447#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6448#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6449#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6450
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00006451#define MDIO_REG_BANK_TX1 0x8070
6452#define MDIO_TX1_TX_DRIVER 0x17
6453#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6454#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6455#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6456#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6457#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6458#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6459#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6460#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6461#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6462
6463#define MDIO_REG_BANK_TX2 0x8080
6464#define MDIO_TX2_TX_DRIVER 0x17
6465#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6466#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6467#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6468#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6469#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6470#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6471#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6472#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6473#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6474
6475#define MDIO_REG_BANK_TX3 0x8090
6476#define MDIO_TX3_TX_DRIVER 0x17
6477#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6478#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6479#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6480#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6481#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6482#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6483#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6484#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6485#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6486
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006487#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6488#define MDIO_BLOCK0_XGXS_CONTROL 0x10
6489
6490#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6491#define MDIO_BLOCK1_LANE_CTRL0 0x15
6492#define MDIO_BLOCK1_LANE_CTRL1 0x16
6493#define MDIO_BLOCK1_LANE_CTRL2 0x17
6494#define MDIO_BLOCK1_LANE_PRBS 0x19
6495
6496#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6497#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6498#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6499#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006500#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006501#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006502#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
Eliezer Tamirf1410642008-02-28 11:51:50 -08006503#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6504#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006505#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006506
6507#define MDIO_REG_BANK_GP_STATUS 0x8120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006508#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6509#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6510#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6511#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6512#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6513#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6514#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6515#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6516#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6517#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6518#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6519#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6520#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6521#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6522#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6523#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6524#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6525#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6526#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6527#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6528#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6529#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6530#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6531#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6532#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006533#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6534#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6535#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6536#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006537
6538
6539#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02006540#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6541#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006542#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6543#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6544#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6545#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006546
6547#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006548#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6549#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6550#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6551#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6552#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6553#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6554#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6555#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6556#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6557#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6558#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006559#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6560#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006561#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6562#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
6563#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
6564#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
6565#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
6566#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
6567#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02006568#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
6569#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006570#define MDIO_SERDES_DIGITAL_MISC1 0x18
6571#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
6572#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
6573#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
6574#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
6575#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
6576#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
6577#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
6578#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
6579#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
6580#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
6581#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
6582#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
6583#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
6584#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
6585#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
6586#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
6587#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
6588#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006589
6590#define MDIO_REG_BANK_OVER_1G 0x8320
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006591#define MDIO_OVER_1G_DIGCTL_3_4 0x14
6592#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
6593#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
6594#define MDIO_OVER_1G_UP1 0x19
6595#define MDIO_OVER_1G_UP1_2_5G 0x0001
6596#define MDIO_OVER_1G_UP1_5G 0x0002
6597#define MDIO_OVER_1G_UP1_6G 0x0004
6598#define MDIO_OVER_1G_UP1_10G 0x0010
6599#define MDIO_OVER_1G_UP1_10GH 0x0008
6600#define MDIO_OVER_1G_UP1_12G 0x0020
6601#define MDIO_OVER_1G_UP1_12_5G 0x0040
6602#define MDIO_OVER_1G_UP1_13G 0x0080
6603#define MDIO_OVER_1G_UP1_15G 0x0100
6604#define MDIO_OVER_1G_UP1_16G 0x0200
6605#define MDIO_OVER_1G_UP2 0x1A
6606#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
6607#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
6608#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
6609#define MDIO_OVER_1G_UP3 0x1B
6610#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
6611#define MDIO_OVER_1G_LP_UP1 0x1C
6612#define MDIO_OVER_1G_LP_UP2 0x1D
6613#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
6614#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
6615#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
6616#define MDIO_OVER_1G_LP_UP3 0x1E
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006617
Eilon Greenstein239d6862009-08-12 08:23:04 +00006618#define MDIO_REG_BANK_REMOTE_PHY 0x8330
6619#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
6620#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
6621#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
6622
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006623#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006624#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
6625#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
6626#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006627
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006628#define MDIO_REG_BANK_CL73_USERB0 0x8370
Eilon Greenstein239d6862009-08-12 08:23:04 +00006629#define MDIO_CL73_USERB0_CL73_UCTRL 0x10
6630#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
6631#define MDIO_CL73_USERB0_CL73_USTAT1 0x11
6632#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
6633#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006634#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
6635#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
6636#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
6637#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
6638#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
6639#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006640
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006641#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
6642#define MDIO_AER_BLOCK_AER_REG 0x1E
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006643
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006644#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
6645#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
6646#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
6647#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
6648#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
6649#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
6650#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6651#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6652#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6653#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6654#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6655#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6656#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6657#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6658#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6659#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6660#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6661#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6662#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6663#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6664#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6665#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6666#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6667#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6668#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6669#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6670#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6671#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6672#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6673#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6674#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6675/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6676bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6677Theotherbitsarereservedandshouldbezero*/
6678#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006679
6680
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006681#define MDIO_PMA_DEVAD 0x1
6682/*ieee*/
6683#define MDIO_PMA_REG_CTRL 0x0
6684#define MDIO_PMA_REG_STATUS 0x1
6685#define MDIO_PMA_REG_10G_CTRL2 0x7
Yaniv Rosner85242ee2011-07-05 01:06:53 +00006686#define MDIO_PMA_REG_TX_DISABLE 0x0009
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006687#define MDIO_PMA_REG_RX_SD 0xa
6688/*bcm*/
6689#define MDIO_PMA_REG_BCM_CTRL 0x0096
6690#define MDIO_PMA_REG_FEC_CTRL 0x00ab
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006691#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6692#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6693#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6694#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6695#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6696#define MDIO_PMA_REG_MISC_CTRL 0xca0a
6697#define MDIO_PMA_REG_GEN_CTRL 0xca10
6698#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6699#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
Yaniv Rosner57963ed2008-08-13 15:55:28 -07006700#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6701#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006702#define MDIO_PMA_REG_ROM_VER1 0xca19
6703#define MDIO_PMA_REG_ROM_VER2 0xca1a
6704#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6705#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006706#define MDIO_PMA_REG_PLL_CTRL 0xca1e
Eilon Greenstein589abe32009-02-12 08:36:55 +00006707#define MDIO_PMA_REG_MISC_CTRL0 0xca23
6708#define MDIO_PMA_REG_LRM_MODE 0xca3f
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006709#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6710#define MDIO_PMA_REG_MISC_CTRL1 0xca85
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006711
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006712#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6713#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6714#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6715#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6716#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6717#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6718#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6719#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
Eilon Greenstein589abe32009-02-12 08:36:55 +00006720#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6721#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6722#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6723#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6724
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006725#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6726#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6727#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006728#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6729#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6730#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6731#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006732#define MDIO_PMA_REG_8727_PCS_GP 0xc842
Yaniv Rosnera8db5b42011-01-31 04:22:28 +00006733#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006734
6735#define MDIO_AN_REG_8727_MISC_CTRL 0x8309
Eilon Greenstein589abe32009-02-12 08:36:55 +00006736
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006737#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6738#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6739#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006740#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006741
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006742#define MDIO_PMA_REG_7101_RESET 0xc000
6743#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006744#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006745#define MDIO_PMA_REG_7101_VER1 0xc026
6746#define MDIO_PMA_REG_7101_VER2 0xc027
Eliezer Tamirf1410642008-02-28 11:51:50 -08006747
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006748#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6749#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6750#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6751#define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6752#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6753#define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6754#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6755#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6756#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6757#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
Eilon Greenstein2f904462009-08-12 08:22:16 +00006758
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006759
6760#define MDIO_WIS_DEVAD 0x2
6761/*bcm*/
6762#define MDIO_WIS_REG_LASI_CNTL 0x9002
6763#define MDIO_WIS_REG_LASI_STATUS 0x9005
6764
6765#define MDIO_PCS_DEVAD 0x3
6766#define MDIO_PCS_REG_STATUS 0x0020
6767#define MDIO_PCS_REG_LASI_STATUS 0x9005
6768#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6769#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6770#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6771#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6772#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6773#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6774#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6775#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6776#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6777
6778
6779#define MDIO_XS_DEVAD 0x4
6780#define MDIO_XS_PLL_SEQUENCER 0x8000
6781#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6782
Eilon Greenstein589abe32009-02-12 08:36:55 +00006783#define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6784#define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6785#define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6786#define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6787#define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6788
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006789#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6790
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006791#define MDIO_AN_DEVAD 0x7
6792/*ieee*/
6793#define MDIO_AN_REG_CTRL 0x0000
6794#define MDIO_AN_REG_STATUS 0x0001
6795#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6796#define MDIO_AN_REG_ADV_PAUSE 0x0010
6797#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6798#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6799#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6800#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6801#define MDIO_AN_REG_ADV 0x0011
6802#define MDIO_AN_REG_ADV2 0x0012
Mintz Yuval9e7e8392012-02-15 02:10:24 +00006803#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6804#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006805#define MDIO_AN_REG_MASTER_STATUS 0x0021
6806/*bcm*/
6807#define MDIO_AN_REG_LINK_STATUS 0x8304
6808#define MDIO_AN_REG_CL37_CL73 0x8370
6809#define MDIO_AN_REG_CL37_AN 0xffe0
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07006810#define MDIO_AN_REG_CL37_FC_LD 0xffe4
Mintz Yuval9e7e8392012-02-15 02:10:24 +00006811#define MDIO_AN_REG_CL37_FC_LP 0xffe5
6812#define MDIO_AN_REG_1000T_STATUS 0xffea
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006813
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006814#define MDIO_AN_REG_8073_2_5G 0x8329
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006815#define MDIO_AN_REG_8073_BAM 0x8350
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006816
Yaniv Rosnerac4d9442010-09-01 09:51:25 +00006817#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
Eilon Greenstein2f904462009-08-12 08:22:16 +00006818#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006819#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
Eilon Greenstein2f904462009-08-12 08:22:16 +00006820#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006821#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
Eilon Greenstein2f904462009-08-12 08:22:16 +00006822#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6823#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6824#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
Yaniv Rosnerac4d9442010-09-01 09:51:25 +00006825#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
Eilon Greenstein2f904462009-08-12 08:22:16 +00006826#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006827
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006828/* BCM84823 only */
6829#define MDIO_CTL_DEVAD 0x1e
6830#define MDIO_CTL_REG_84823_MEDIA 0x401a
6831#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6832 /* These pins configure the BCM84823 interface to MAC after reset. */
6833#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6834#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6835 /* These pins configure the BCM84823 interface to Line after reset. */
6836#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6837#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6838#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6839 /* When this pin is active high during reset, 10GBASE-T core is power
6840 * down, When it is active low the 10GBASE-T is power up
6841 */
6842#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6843#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6844#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6845#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6846#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
Yaniv Rosner521683d2011-11-28 00:49:48 +00006847#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6848#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
6849#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
6850#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
6851#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6852#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
6853#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006854
Yaniv Rosnerbac27bd2011-05-31 21:28:10 +00006855/* BCM84833 only */
6856#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
6857#define MDIO_84833_SUPER_ISOLATE 0x8000
6858/* These are mailbox register set used by 84833. */
6859#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
6860#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
6861#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
6862#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
6863#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
Yaniv Rosner521683d2011-11-28 00:49:48 +00006864#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
6865#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
6866#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
6867#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
6868#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
6869#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
6870#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
6871#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
6872#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
6873#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
6874#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
6875#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
6876#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
Yaniv Rosnerbac27bd2011-05-31 21:28:10 +00006877
6878/* Mailbox command set used by 84833. */
Yaniv Rosner521683d2011-11-28 00:49:48 +00006879#define PHY84833_CMD_SET_PAIR_SWAP 0x8001
6880#define PHY84833_CMD_GET_EEE_MODE 0x8008
6881#define PHY84833_CMD_SET_EEE_MODE 0x8009
Yaniv Rosnerbac27bd2011-05-31 21:28:10 +00006882/* Mailbox status set used by 84833. */
Yaniv Rosner521683d2011-11-28 00:49:48 +00006883#define PHY84833_STATUS_CMD_RECEIVED 0x0001
6884#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
6885#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
6886#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
6887#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
6888#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
6889#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
6890#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
6891#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
Yaniv Rosnerbac27bd2011-05-31 21:28:10 +00006892
Yaniv Rosnera89a1d42011-07-05 01:07:05 +00006893
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006894/* Warpcore clause 45 addressing */
6895#define MDIO_WC_DEVAD 0x3
6896#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
6897#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
6898#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
6899#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
Yaniv Rosner6b1f3902011-09-07 00:47:54 +00006900#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
6901#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
6902#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006903#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96
6904#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
6905#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
6906#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
6907#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
6908#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
6909#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
6910#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
6911#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
6912#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
6913#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
6914#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
6915#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
6916#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
6917#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
6918#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6919#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
6920#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
6921#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
6922#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
6923#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
6924#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
6925#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
6926#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
6927#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
6928#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
6929#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
6930#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
6931#define MDIO_WC_REG_XGXS_STATUS3 0x8129
6932#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
6933#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
6934#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
6935#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
6936#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
6937#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
6938#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
6939#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
6940#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
6941#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
6942#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
6943#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
6944#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
6945#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
6946#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
6947#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
6948#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
6949#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
6950#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
6951#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
6952#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
6953#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
6954#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
6955#define MDIO_WC_REG_DSC_SMC 0x8213
6956#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
6957#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
6958#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
6959#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
6960#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
6961#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
6962#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
6963#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
6964#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
6965#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
6966#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
6967#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
6968#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
6969#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
6970#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
6971#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
6972#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
6973#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
6974#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
6975#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
6976#define MDIO_WC_REG_DIGITAL3_UP1 0x8329
Mintz Yuval9e7e8392012-02-15 02:10:24 +00006977#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006978#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
6979#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
6980#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
6981#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
Yaniv Rosnera34bc962011-07-05 01:06:41 +00006982#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006983#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
6984#define MDIO_WC_REG_TX66_CONTROL 0x83b0
6985#define MDIO_WC_REG_RX66_CONTROL 0x83c0
6986#define MDIO_WC_REG_RX66_SCW0 0x83c2
6987#define MDIO_WC_REG_RX66_SCW1 0x83c3
6988#define MDIO_WC_REG_RX66_SCW2 0x83c4
6989#define MDIO_WC_REG_RX66_SCW3 0x83c5
6990#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
6991#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
6992#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
6993#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
6994#define MDIO_WC_REG_FX100_CTRL1 0x8400
6995#define MDIO_WC_REG_FX100_CTRL3 0x8402
6996
6997#define MDIO_WC_REG_MICROBLK_CMD 0xffc2
6998#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
6999#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
7000
7001#define MDIO_WC_REG_AERBLK_AER 0xffde
7002#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
7003#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
7004
7005#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
7006#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
7007#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
7008
7009#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
7010
7011#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
7012
Yaniv Rosner52c4d6c2011-07-05 01:06:34 +00007013/* 54618se */
7014#define MDIO_REG_GPHY_PHYID_LSB 0x3
7015#define MDIO_REG_GPHY_ID_54618SE 0x5cd5
7016#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
7017#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
7018#define MDIO_REG_GPHY_EEE_ADV 0x3c
7019#define MDIO_REG_GPHY_EEE_1G (0x1 << 2)
7020#define MDIO_REG_GPHY_EEE_100 (0x1 << 1)
7021#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
Yaniv Rosner6583e332011-06-14 01:34:17 +00007022#define MDIO_REG_INTR_STATUS 0x1a
7023#define MDIO_REG_INTR_MASK 0x1b
7024#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
7025#define MDIO_REG_GPHY_SHADOW 0x1c
Yaniv Rosner1d125bd2011-11-23 03:54:08 +00007026#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
Yaniv Rosner6583e332011-06-14 01:34:17 +00007027#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
7028#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
7029#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
7030#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
7031
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07007032#define IGU_FUNC_BASE 0x0400
7033
7034#define IGU_ADDR_MSIX 0x0000
7035#define IGU_ADDR_INT_ACK 0x0200
7036#define IGU_ADDR_PROD_UPD 0x0201
7037#define IGU_ADDR_ATTN_BITS_UPD 0x0202
7038#define IGU_ADDR_ATTN_BITS_SET 0x0203
7039#define IGU_ADDR_ATTN_BITS_CLR 0x0204
7040#define IGU_ADDR_COALESCE_NOW 0x0205
7041#define IGU_ADDR_SIMD_MASK 0x0206
7042#define IGU_ADDR_SIMD_NOMASK 0x0207
7043#define IGU_ADDR_MSI_CTL 0x0210
7044#define IGU_ADDR_MSI_ADDR_LO 0x0211
7045#define IGU_ADDR_MSI_ADDR_HI 0x0212
7046#define IGU_ADDR_MSI_DATA 0x0213
7047
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007048#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
7049#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
7050#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
7051#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
7052
Eilon Greenstein5c862842008-08-13 15:51:48 -07007053#define COMMAND_REG_INT_ACK 0x0
7054#define COMMAND_REG_PROD_UPD 0x4
7055#define COMMAND_REG_ATTN_BITS_UPD 0x8
7056#define COMMAND_REG_ATTN_BITS_SET 0xc
7057#define COMMAND_REG_ATTN_BITS_CLR 0x10
7058#define COMMAND_REG_COALESCE_NOW 0x14
7059#define COMMAND_REG_SIMD_MASK 0x18
7060#define COMMAND_REG_SIMD_NOMASK 0x1c
7061
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02007062
Eilon Greenstein573f2032009-08-12 08:24:14 +00007063#define IGU_MEM_BASE 0x0000
7064
7065#define IGU_MEM_MSIX_BASE 0x0000
7066#define IGU_MEM_MSIX_UPPER 0x007f
7067#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
7068
7069#define IGU_MEM_PBA_MSIX_BASE 0x0200
7070#define IGU_MEM_PBA_MSIX_UPPER 0x0200
7071
7072#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
7073#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
7074
7075#define IGU_CMD_INT_ACK_BASE 0x0400
7076#define IGU_CMD_INT_ACK_UPPER\
7077 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7078#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
7079
7080#define IGU_CMD_E2_PROD_UPD_BASE 0x0500
7081#define IGU_CMD_E2_PROD_UPD_UPPER\
7082 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7083#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
7084
7085#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
7086#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
7087#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
7088
7089#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
7090#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
7091#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
7092#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
7093
7094#define IGU_REG_RESERVED_UPPER 0x05ff
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007095/* Fields of IGU PF CONFIGRATION REGISTER */
7096#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
7097#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7098#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
7099#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7100#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7101#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
7102
7103/* Fields of IGU VF CONFIGRATION REGISTER */
7104#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
7105#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7106#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
7107#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
7108#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7109
7110
7111#define IGU_BC_DSB_NUM_SEGS 5
7112#define IGU_BC_NDSB_NUM_SEGS 2
7113#define IGU_NORM_DSB_NUM_SEGS 2
7114#define IGU_NORM_NDSB_NUM_SEGS 1
7115#define IGU_BC_BASE_DSB_PROD 128
7116#define IGU_NORM_BASE_DSB_PROD 136
7117
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007118 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7119 [5:2] = 0; [1:0] = PF number) */
7120#define IGU_FID_ENCODE_IS_PF (0x1<<6)
7121#define IGU_FID_ENCODE_IS_PF_SHIFT 6
7122#define IGU_FID_VF_NUM_MASK (0x3f)
7123#define IGU_FID_PF_NUM_MASK (0x7)
7124
7125#define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
7126#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
7127#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
7128#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7129#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
Eilon Greenstein573f2032009-08-12 08:24:14 +00007130
7131
7132#define CDU_REGION_NUMBER_XCM_AG 2
7133#define CDU_REGION_NUMBER_UCM_AG 4
7134
7135
7136/**
7137 * String-to-compress [31:8] = CID (all 24 bits)
7138 * String-to-compress [7:4] = Region
7139 * String-to-compress [3:0] = Type
7140 */
7141#define CDU_VALID_DATA(_cid, _region, _type)\
7142 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7143#define CDU_CRC8(_cid, _region, _type)\
7144 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7145#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
7146 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7147#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
7148 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7149#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7150
7151/******************************************************************************
7152 * Description:
7153 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7154 * Code was translated from Verilog.
7155 * Return:
7156 *****************************************************************************/
7157static inline u8 calc_crc8(u32 data, u8 crc)
7158{
7159 u8 D[32];
7160 u8 NewCRC[8];
7161 u8 C[8];
7162 u8 crc_res;
7163 u8 i;
7164
7165 /* split the data into 31 bits */
7166 for (i = 0; i < 32; i++) {
7167 D[i] = (u8)(data & 1);
7168 data = data >> 1;
7169 }
7170
7171 /* split the crc into 8 bits */
7172 for (i = 0; i < 8; i++) {
7173 C[i] = crc & 1;
7174 crc = crc >> 1;
7175 }
7176
7177 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
7178 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
7179 C[6] ^ C[7];
7180 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
7181 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
7182 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
7183 C[6];
7184 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
7185 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
7186 C[0] ^ C[1] ^ C[4] ^ C[5];
7187 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
7188 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
7189 C[1] ^ C[2] ^ C[5] ^ C[6];
7190 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
7191 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
7192 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
7193 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
7194 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
7195 C[3] ^ C[4] ^ C[7];
7196 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
7197 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
7198 C[5];
7199 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
7200 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
7201 C[6];
7202
7203 crc_res = 0;
7204 for (i = 0; i < 8; i++)
7205 crc_res |= (NewCRC[i] << i);
7206
7207 return crc_res;
7208}
7209
7210
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00007211#endif /* BNX2X_REG_H */