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Benoit Cousson208106a2013-05-29 12:38:07 -04001/*
2 * OMAP54XX SCRM registers and bitfields
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * This file is automatically generated from the OMAP hardware databases.
9 * We respectfully ask that any modifications to this file be coordinated
10 * with the public linux-omap@vger.kernel.org mailing list and the
11 * authors above to ensure that the autogeneration scripts are kept
12 * up-to-date with the file contents.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
20#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
21
22#define OMAP5_SCRM_BASE 0x4ae0a000
23
24#define OMAP54XX_SCRM_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
26
27/* SCRM */
28
29/* SCRM.SCRM register offsets */
30#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
31#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
32#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
33#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
34#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
35#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
36#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
37#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
38#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
39#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
40#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
41#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
42#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
43#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
44#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
45#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
46#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
47#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
48#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
49#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
50#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
51#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
52#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
53#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
54#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
55#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
56#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
57#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
58#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
59#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
60#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
61#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
62#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
63#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
64#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
65#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
66#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
67#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
68#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
69#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
70#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
71#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
72#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
73#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
74#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
75#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
76#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
77#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
78#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
79#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
80#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
81#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
82#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
83#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
84#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
85#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
86#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
87#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
88#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
89#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
90
91/*
92 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
93 * AUXCLKREQ5, D2DCLKREQ
94 */
95#define OMAP5_ACCURACY_SHIFT 1
96#define OMAP5_ACCURACY_WIDTH 0x1
97#define OMAP5_ACCURACY_MASK (1 << 1)
98
99/* Used by APEWARMRSTST */
100#define OMAP5_APEWARMRSTST_SHIFT 1
101#define OMAP5_APEWARMRSTST_WIDTH 0x1
102#define OMAP5_APEWARMRSTST_MASK (1 << 1)
103
104/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
105#define OMAP5_CLKDIV_SHIFT 16
106#define OMAP5_CLKDIV_WIDTH 0x4
107#define OMAP5_CLKDIV_MASK (0xf << 16)
108
109/* Used by D2DCLKM, MODEMCLKM */
110#define OMAP5_CLK_32KHZ_SHIFT 0
111#define OMAP5_CLK_32KHZ_WIDTH 0x1
112#define OMAP5_CLK_32KHZ_MASK (1 << 0)
113
114/* Used by D2DRSTCTRL, MODEMRSTCTRL */
115#define OMAP5_COLDRST_SHIFT 0
116#define OMAP5_COLDRST_WIDTH 0x1
117#define OMAP5_COLDRST_MASK (1 << 0)
118
119/* Used by D2DWARMRSTST */
120#define OMAP5_D2DWARMRSTST_SHIFT 3
121#define OMAP5_D2DWARMRSTST_WIDTH 0x1
122#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
123
124/* Used by AUXCLK0 */
125#define OMAP5_DISABLECLK_SHIFT 9
126#define OMAP5_DISABLECLK_WIDTH 0x1
127#define OMAP5_DISABLECLK_MASK (1 << 9)
128
129/* Used by CLKSETUPTIME */
130#define OMAP5_DOWNTIME_SHIFT 16
131#define OMAP5_DOWNTIME_WIDTH 0x6
132#define OMAP5_DOWNTIME_MASK (0x3f << 16)
133
134/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
135#define OMAP5_ENABLE_SHIFT 8
136#define OMAP5_ENABLE_WIDTH 0x1
137#define OMAP5_ENABLE_MASK (1 << 8)
138
139/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
140#define OMAP5_ENABLE_0_0_SHIFT 0
141#define OMAP5_ENABLE_0_0_WIDTH 0x1
142#define OMAP5_ENABLE_0_0_MASK (1 << 0)
143
144/* Used by ALTCLKSRC */
145#define OMAP5_ENABLE_EXT_SHIFT 3
146#define OMAP5_ENABLE_EXT_WIDTH 0x1
147#define OMAP5_ENABLE_EXT_MASK (1 << 3)
148
149/* Used by ALTCLKSRC */
150#define OMAP5_ENABLE_INT_SHIFT 2
151#define OMAP5_ENABLE_INT_WIDTH 0x1
152#define OMAP5_ENABLE_INT_MASK (1 << 2)
153
154/* Used by EXTWARMRSTST */
155#define OMAP5_EXTWARMRSTST_SHIFT 0
156#define OMAP5_EXTWARMRSTST_WIDTH 0x1
157#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
158
159/*
160 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
161 * AUXCLKREQ5
162 */
163#define OMAP5_MAPPING_SHIFT 2
164#define OMAP5_MAPPING_WIDTH 0x3
165#define OMAP5_MAPPING_MASK (0x7 << 2)
166
167/* Used by ALTCLKSRC */
168#define OMAP5_MODE_SHIFT 0
169#define OMAP5_MODE_WIDTH 0x2
170#define OMAP5_MODE_MASK (0x3 << 0)
171
172/* Used by MODEMWARMRSTST */
173#define OMAP5_MODEMWARMRSTST_SHIFT 2
174#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
175#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
176
177/*
178 * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
179 * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
180 * D2DCLKREQ, EXTCLKREQ, PWRREQ
181 */
182#define OMAP5_POLARITY_SHIFT 0
183#define OMAP5_POLARITY_WIDTH 0x1
184#define OMAP5_POLARITY_MASK (1 << 0)
185
186/* Used by EXTPWRONRSTCTRL */
187#define OMAP5_PWRONRST_SHIFT 1
188#define OMAP5_PWRONRST_WIDTH 0x1
189#define OMAP5_PWRONRST_MASK (1 << 1)
190
191/* Used by REVISION_SCRM */
192#define OMAP5_REV_SHIFT 0
193#define OMAP5_REV_WIDTH 0x8
194#define OMAP5_REV_MASK (0xff << 0)
195
196/* Used by RSTTIME */
197#define OMAP5_RSTTIME_SHIFT 0
198#define OMAP5_RSTTIME_WIDTH 0x4
199#define OMAP5_RSTTIME_MASK (0xf << 0)
200
201/* Used by CLKSETUPTIME */
202#define OMAP5_SETUPTIME_SHIFT 0
203#define OMAP5_SETUPTIME_WIDTH 0xc
204#define OMAP5_SETUPTIME_MASK (0xfff << 0)
205
206/* Used by PMICSETUPTIME */
207#define OMAP5_SLEEPTIME_SHIFT 0
208#define OMAP5_SLEEPTIME_WIDTH 0x6
209#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
210
211/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
212#define OMAP5_SRCSELECT_SHIFT 1
213#define OMAP5_SRCSELECT_WIDTH 0x2
214#define OMAP5_SRCSELECT_MASK (0x3 << 1)
215
216/* Used by D2DCLKM */
217#define OMAP5_SYSCLK_SHIFT 1
218#define OMAP5_SYSCLK_WIDTH 0x1
219#define OMAP5_SYSCLK_MASK (1 << 1)
220
221/* Used by PMICSETUPTIME */
222#define OMAP5_WAKEUPTIME_SHIFT 16
223#define OMAP5_WAKEUPTIME_WIDTH 0x6
224#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
225
226/* Used by D2DRSTCTRL, MODEMRSTCTRL */
227#define OMAP5_WARMRST_SHIFT 1
228#define OMAP5_WARMRST_WIDTH 0x1
229#define OMAP5_WARMRST_MASK (1 << 1)
230
231#endif