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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __LINUX_UHCI_HCD_H
2#define __LINUX_UHCI_HCD_H
3
4#include <linux/list.h>
5#include <linux/usb.h>
6
7#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8#define PIPE_DEVEP_MASK 0x0007ff00
9
Alan Stern8b262bd2005-09-26 16:31:15 -040010
Linus Torvalds1da177e2005-04-16 15:20:36 -070011/*
12 * Universal Host Controller Interface data structures and defines
13 */
14
15/* Command register */
16#define USBCMD 0
17#define USBCMD_RS 0x0001 /* Run/Stop */
18#define USBCMD_HCRESET 0x0002 /* Host reset */
19#define USBCMD_GRESET 0x0004 /* Global reset */
20#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
21#define USBCMD_FGR 0x0010 /* Force Global Resume */
22#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
23#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
24#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
25
26/* Status register */
27#define USBSTS 2
28#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
29#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
30#define USBSTS_RD 0x0004 /* Resume Detect */
Alan Sterndccf4a42005-12-17 17:58:46 -050031#define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
32#define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
33 * the schedule is buggy */
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#define USBSTS_HCH 0x0020 /* HC Halted */
35
36/* Interrupt enable register */
37#define USBINTR 4
38#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
39#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
40#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
41#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
42
43#define USBFRNUM 6
44#define USBFLBASEADD 8
45#define USBSOF 12
Alan Sterna8bed8b2005-04-09 17:29:00 -040046#define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48/* USB port status and control registers */
49#define USBPORTSC1 16
50#define USBPORTSC2 18
Alan Sterndccf4a42005-12-17 17:58:46 -050051#define USBPORTSC_CCS 0x0001 /* Current Connect Status
52 * ("device present") */
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
54#define USBPORTSC_PE 0x0004 /* Port Enable */
55#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
56#define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
57#define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
58#define USBPORTSC_RD 0x0040 /* Resume Detect */
59#define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
60#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
61#define USBPORTSC_PR 0x0200 /* Port Reset */
62/* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
63#define USBPORTSC_OC 0x0400 /* Over Current condition */
64#define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
65#define USBPORTSC_SUSP 0x1000 /* Suspend */
66#define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
67#define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
68#define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
69
Alan Stern0d436b42010-06-25 14:02:49 -040070/* PCI legacy support register */
Linus Torvalds1da177e2005-04-16 15:20:36 -070071#define USBLEGSUP 0xc0
72#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
Alan Sterna8bed8b2005-04-09 17:29:00 -040073#define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
74#define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
Alan Stern0d436b42010-06-25 14:02:49 -040076/* PCI Intel-specific resume-enable register */
77#define USBRES_INTEL 0xc4
78#define USBPORT1EN 0x01
79#define USBPORT2EN 0x02
80
Jan Andersson51e2f622011-05-18 10:44:51 +020081#define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F)
82#define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001)
83#define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002)
84#define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004)
85#define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000)
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
87#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
88#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
Alan Sterndccf4a42005-12-17 17:58:46 -050089#define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames
90 * can be scheduled */
Alan Stern3ca2a322007-01-16 11:56:32 -050091#define MAX_PHASE 32 /* Periodic scheduling length */
Linus Torvalds1da177e2005-04-16 15:20:36 -070092
Alan Stern84afddd2006-05-12 11:35:45 -040093/* When no queues need Full-Speed Bandwidth Reclamation,
94 * delay this long before turning FSBR off */
Alan Sternc5e3b742006-06-05 12:28:57 -040095#define FSBR_OFF_DELAY msecs_to_jiffies(10)
Alan Stern84afddd2006-05-12 11:35:45 -040096
97/* If a queue hasn't advanced after this much time, assume it is stuck */
98#define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
99
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
Alan Stern8b262bd2005-09-26 16:31:15 -0400101/*
Jan Andersson51e2f622011-05-18 10:44:51 +0200102 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
103 * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on
104 * the host controller implementation.
105 *
106 * To facilitate the strongest possible byte-order checking from "sparse"
107 * and so on, we use __leXX unless that's not practical.
108 */
109#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
110typedef __u32 __bitwise __hc32;
111typedef __u16 __bitwise __hc16;
112#else
113#define __hc32 __le32
114#define __hc16 __le16
115#endif
116
117/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400118 * Queue Headers
119 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
121/*
Alan Sterndccf4a42005-12-17 17:58:46 -0500122 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes
123 * with each endpoint, and qh->element (updated by the HC) is either:
124 * - the next unprocessed TD in the endpoint's queue, or
125 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126 *
127 * The other role of a QH is to serve as a "skeleton" framelist entry, so we
128 * can easily splice a QH for some endpoint into the schedule at the right
129 * place. Then qh->element is UHCI_PTR_TERM.
130 *
Alan Sterndccf4a42005-12-17 17:58:46 -0500131 * In the schedule, qh->link maintains a list of QHs seen by the HC:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
Alan Sterndccf4a42005-12-17 17:58:46 -0500133 *
134 * qh->node is the software equivalent of qh->link. The differences
135 * are that the software list is doubly-linked and QHs in the UNLINKING
136 * state are on the software list but not the hardware schedule.
137 *
138 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
139 * but they never get added to the hardware schedule.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 */
Alan Sterndccf4a42005-12-17 17:58:46 -0500141#define QH_STATE_IDLE 1 /* QH is not being used */
142#define QH_STATE_UNLINKING 2 /* QH has been removed from the
143 * schedule but the hardware may
144 * still be using it */
145#define QH_STATE_ACTIVE 3 /* QH is on the schedule */
146
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147struct uhci_qh {
148 /* Hardware fields */
Jan Andersson51e2f622011-05-18 10:44:51 +0200149 __hc32 link; /* Next QH in the schedule */
150 __hc32 element; /* Queue element (TD) pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151
152 /* Software fields */
Alan Stern28b93252007-02-19 15:51:51 -0500153 dma_addr_t dma_handle;
154
Alan Sterndccf4a42005-12-17 17:58:46 -0500155 struct list_head node; /* Node in the list of QHs */
156 struct usb_host_endpoint *hep; /* Endpoint information */
157 struct usb_device *udev;
158 struct list_head queue; /* Queue of urbps for this QH */
Alan Sternaf0bb592005-12-17 18:00:12 -0500159 struct uhci_td *dummy_td; /* Dummy TD to end the queue */
Alan Stern59e29ed2006-05-12 11:19:19 -0400160 struct uhci_td *post_td; /* Last TD completed */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
Alan Sternc8155cc2006-05-19 16:52:35 -0400162 struct usb_iso_packet_descriptor *iso_packet_desc;
163 /* Next urb->iso_frame_desc entry */
Alan Stern84afddd2006-05-12 11:35:45 -0400164 unsigned long advance_jiffies; /* Time of last queue advance */
Alan Sterndccf4a42005-12-17 17:58:46 -0500165 unsigned int unlink_frame; /* When the QH was unlinked */
Alan Sterncaf38272006-05-19 16:44:55 -0400166 unsigned int period; /* For Interrupt and Isochronous QHs */
Alan Stern3ca2a322007-01-16 11:56:32 -0500167 short phase; /* Between 0 and period-1 */
168 short load; /* Periodic time requirement, in us */
Alan Sternc8155cc2006-05-19 16:52:35 -0400169 unsigned int iso_frame; /* Frame # for iso_packet_desc */
Alan Sterncaf38272006-05-19 16:44:55 -0400170
Alan Sterndccf4a42005-12-17 17:58:46 -0500171 int state; /* QH_STATE_xxx; see above */
Alan Stern4de7d2c2006-05-05 16:26:58 -0400172 int type; /* Queue type (control, bulk, etc) */
Alan Stern17230ac2007-02-19 15:52:45 -0500173 int skel; /* Skeleton queue number */
Alan Stern0ed8fee2005-12-17 18:02:38 -0500174
175 unsigned int initial_toggle:1; /* Endpoint's current toggle value */
176 unsigned int needs_fixup:1; /* Must fix the TD toggle values */
Alan Stern59e29ed2006-05-12 11:19:19 -0400177 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */
Alan Stern84afddd2006-05-12 11:35:45 -0400178 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */
Alan Stern3ca2a322007-01-16 11:56:32 -0500179 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has
180 * been allocated */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181} __attribute__((aligned(16)));
182
183/*
184 * We need a special accessor for the element pointer because it is
Alan Stern8b262bd2005-09-26 16:31:15 -0400185 * subject to asynchronous updates by the controller.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 */
Alan Sternbab1ff12011-05-18 10:44:50 +0200187#define qh_element(qh) ACCESS_ONCE((qh)->element)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
Jan Andersson51e2f622011-05-18 10:44:51 +0200189#define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \
190 cpu_to_hc32((uhci), (qh)->dma_handle))
Alan Stern28b93252007-02-19 15:51:51 -0500191
Alan Stern8b262bd2005-09-26 16:31:15 -0400192
193/*
194 * Transfer Descriptors
195 */
196
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197/*
198 * for TD <status>:
199 */
200#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
201#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
202#define TD_CTRL_C_ERR_SHIFT 27
203#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
204#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
205#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
206#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
207#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
208#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
209#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
210#define TD_CTRL_NAK (1 << 19) /* NAK Received */
211#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
212#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
213#define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
214
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
216#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
Alan Sterndccf4a42005-12-17 17:58:46 -0500217#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
218 TD_CTRL_ACTLEN_MASK) /* 1-based */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219
220/*
221 * for TD <info>: (a.k.a. Token)
222 */
Jan Andersson51e2f622011-05-18 10:44:51 +0200223#define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224#define TD_TOKEN_DEVADDR_SHIFT 8
225#define TD_TOKEN_TOGGLE_SHIFT 19
226#define TD_TOKEN_TOGGLE (1 << 19)
227#define TD_TOKEN_EXPLEN_SHIFT 21
Alan Sterndccf4a42005-12-17 17:58:46 -0500228#define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229#define TD_TOKEN_PID_MASK 0xFF
230
Alan Sternfa346562005-11-30 11:57:51 -0500231#define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
232 TD_TOKEN_EXPLEN_SHIFT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233
Alan Sternfa346562005-11-30 11:57:51 -0500234#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
235 1) & TD_TOKEN_EXPLEN_MASK)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
237#define uhci_endpoint(token) (((token) >> 15) & 0xf)
238#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
239#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
240#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
241#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
242#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
243
244/*
245 * The documentation says "4 words for hardware, 4 words for software".
246 *
247 * That's silly, the hardware doesn't care. The hardware only cares that
248 * the hardware words are 16-byte aligned, and we can have any amount of
Alan Stern8b262bd2005-09-26 16:31:15 -0400249 * sw space after the TD entry.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250 *
251 * td->link points to either another TD (not necessarily for the same urb or
Alan Sterndccf4a42005-12-17 17:58:46 -0500252 * even the same endpoint), or nothing (PTR_TERM), or a QH.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 */
254struct uhci_td {
255 /* Hardware fields */
Jan Andersson51e2f622011-05-18 10:44:51 +0200256 __hc32 link;
257 __hc32 status;
258 __hc32 token;
259 __hc32 buffer;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260
261 /* Software fields */
262 dma_addr_t dma_handle;
263
Alan Stern8b262bd2005-09-26 16:31:15 -0400264 struct list_head list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
266 int frame; /* for iso: what frame? */
Alan Stern8b262bd2005-09-26 16:31:15 -0400267 struct list_head fl_list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268} __attribute__((aligned(16)));
269
270/*
271 * We need a special accessor for the control/status word because it is
Alan Stern8b262bd2005-09-26 16:31:15 -0400272 * subject to asynchronous updates by the controller.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 */
Jan Andersson51e2f622011-05-18 10:44:51 +0200274#define td_status(uhci, td) hc32_to_cpu((uhci), \
275 ACCESS_ONCE((td)->status))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276
Jan Andersson51e2f622011-05-18 10:44:51 +0200277#define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle))
Alan Stern28b93252007-02-19 15:51:51 -0500278
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279
280/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400281 * Skeleton Queue Headers
282 */
283
284/*
Alan Sterndccf4a42005-12-17 17:58:46 -0500285 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
286 * automatic queuing. To make it easy to insert entries into the schedule,
Alan Stern17230ac2007-02-19 15:52:45 -0500287 * we have a skeleton of QHs for each predefined Interrupt latency.
288 * Asynchronous QHs (low-speed control, full-speed control, and bulk)
289 * go onto the period-1 interrupt list, since they all get accessed on
290 * every frame.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 *
Alan Stern17230ac2007-02-19 15:52:45 -0500292 * When we want to add a new QH, we add it to the list starting from the
293 * appropriate skeleton QH. For instance, the schedule can look like this:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 *
295 * skel int128 QH
296 * dev 1 interrupt QH
297 * dev 5 interrupt QH
298 * skel int64 QH
299 * skel int32 QH
300 * ...
Alan Stern17230ac2007-02-19 15:52:45 -0500301 * skel int1 + async QH
302 * dev 5 low-speed control QH
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 * dev 1 bulk QH
304 * dev 2 bulk QH
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 *
Alan Stern17230ac2007-02-19 15:52:45 -0500306 * There is a special terminating QH used to keep full-speed bandwidth
307 * reclamation active when no full-speed control or bulk QHs are linked
308 * into the schedule. It has an inactive TD (to work around a PIIX bug,
309 * see the Intel errata) and it points back to itself.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 *
Alan Stern17230ac2007-02-19 15:52:45 -0500311 * There's a special skeleton QH for Isochronous QHs which never appears
312 * on the schedule. Isochronous TDs go on the schedule before the
Alan Sterndccf4a42005-12-17 17:58:46 -0500313 * the skeleton QHs. The hardware accesses them directly rather than
314 * through their QH, which is used only for bookkeeping purposes.
315 * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
316 * it doesn't use them either. And the spec says that queues never
317 * advance on an error completion status, which makes them totally
318 * unsuitable for Isochronous transfers.
Alan Stern17230ac2007-02-19 15:52:45 -0500319 *
320 * There's also a special skeleton QH used for QHs which are in the process
321 * of unlinking and so may still be in use by the hardware. It too never
322 * appears on the schedule.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 */
324
Alan Stern17230ac2007-02-19 15:52:45 -0500325#define UHCI_NUM_SKELQH 11
326#define SKEL_UNLINK 0
327#define skel_unlink_qh skelqh[SKEL_UNLINK]
328#define SKEL_ISO 1
329#define skel_iso_qh skelqh[SKEL_ISO]
330 /* int128, int64, ..., int1 = 2, 3, ..., 9 */
331#define SKEL_INDEX(exponent) (9 - exponent)
332#define SKEL_ASYNC 9
333#define skel_async_qh skelqh[SKEL_ASYNC]
334#define SKEL_TERM 10
335#define skel_term_qh skelqh[SKEL_TERM]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
Alan Stern17230ac2007-02-19 15:52:45 -0500337/* The following entries refer to sublists of skel_async_qh */
338#define SKEL_LS_CONTROL 20
339#define SKEL_FS_CONTROL 21
340#define SKEL_FSBR SKEL_FS_CONTROL
341#define SKEL_BULK 22
Alan Stern8b262bd2005-09-26 16:31:15 -0400342
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400344 * The UHCI controller and root hub
345 */
346
347/*
348 * States for the root hub:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 *
350 * To prevent "bouncing" in the presence of electrical noise,
Alan Sternc8f4fe42005-04-09 17:27:32 -0400351 * when there are no devices attached we delay for 1 second in the
352 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
353 *
354 * (Note that the AUTO_STOPPED state won't be necessary once the hub
355 * driver learns to autosuspend.)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 */
Alan Sternc8f4fe42005-04-09 17:27:32 -0400357enum uhci_rh_state {
Alan Stern6c1b4452005-04-21 16:04:58 -0400358 /* In the following states the HC must be halted.
Alan Stern8b262bd2005-09-26 16:31:15 -0400359 * These two must come first. */
Alan Stern6c1b4452005-04-21 16:04:58 -0400360 UHCI_RH_RESET,
Alan Sternc8f4fe42005-04-09 17:27:32 -0400361 UHCI_RH_SUSPENDED,
Alan Sterna8bed8b2005-04-09 17:29:00 -0400362
Alan Sternc8f4fe42005-04-09 17:27:32 -0400363 UHCI_RH_AUTO_STOPPED,
364 UHCI_RH_RESUMING,
365
Alan Stern6c1b4452005-04-21 16:04:58 -0400366 /* In this state the HC changes from running to halted,
367 * so it can legally appear either way. */
Alan Sternc8f4fe42005-04-09 17:27:32 -0400368 UHCI_RH_SUSPENDING,
369
Alan Stern6c1b4452005-04-21 16:04:58 -0400370 /* In the following states it's an error if the HC is halted.
Alan Stern8b262bd2005-09-26 16:31:15 -0400371 * These two must come last. */
Alan Sternc8f4fe42005-04-09 17:27:32 -0400372 UHCI_RH_RUNNING, /* The normal state */
373 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374};
375
376/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400377 * The full UHCI controller information:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 */
379struct uhci_hcd {
380
381 /* debugfs */
382 struct dentry *dentry;
383
384 /* Grabbed from PCI */
385 unsigned long io_addr;
386
Jan Anderssond3219d12011-05-06 12:00:17 +0200387 /* Used when registers are memory mapped */
388 void __iomem *regs;
389
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390 struct dma_pool *qh_pool;
391 struct dma_pool *td_pool;
392
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
Alan Stern687f5f32005-11-30 17:16:19 -0500394 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */
Alan Stern0ed8fee2005-12-17 18:02:38 -0500395 struct uhci_qh *next_qh; /* Next QH to scan */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396
397 spinlock_t lock;
Alan Sterna1d59ce2005-09-16 14:22:51 -0400398
Alan Sterndccf4a42005-12-17 17:58:46 -0500399 dma_addr_t frame_dma_handle; /* Hardware frame list */
Jan Andersson51e2f622011-05-18 10:44:51 +0200400 __hc32 *frame;
Alan Sterndccf4a42005-12-17 17:58:46 -0500401 void **frame_cpu; /* CPU's frame list */
Alan Sterna1d59ce2005-09-16 14:22:51 -0400402
Alan Sternc8f4fe42005-04-09 17:27:32 -0400403 enum uhci_rh_state rh_state;
404 unsigned long auto_stop_time; /* When to AUTO_STOP */
405
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406 unsigned int frame_number; /* As of last check */
407 unsigned int is_stopped;
408#define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
Alan Sternc8155cc2006-05-19 16:52:35 -0400409 unsigned int last_iso_frame; /* Frame of last scan */
410 unsigned int cur_iso_frame; /* Frame for current scan */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411
412 unsigned int scan_in_progress:1; /* Schedule scan is running */
413 unsigned int need_rescan:1; /* Redo the schedule scan */
Alan Sterne323de42006-06-05 12:21:30 -0400414 unsigned int dead:1; /* Controller has died */
Alan Sternd8f12ab2008-04-22 10:49:15 -0400415 unsigned int RD_enable:1; /* Suspended root hub with
416 Resume-Detect interrupts
417 enabled */
Alan Stern8d402e12005-12-17 18:03:37 -0500418 unsigned int is_initialized:1; /* Data structure is usable */
Alan Stern84afddd2006-05-12 11:35:45 -0400419 unsigned int fsbr_is_on:1; /* FSBR is turned on */
Alan Sternc5e3b742006-06-05 12:28:57 -0400420 unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */
421 unsigned int fsbr_expiring:1; /* FSBR is timing out */
422
423 struct timer_list fsbr_timer; /* For turning off FBSR */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424
Jan Anderssondfeca7a2011-05-06 12:00:12 +0200425 /* Silicon quirks */
426 unsigned int oc_low:1; /* OverCurrent bit active low */
427 unsigned int wait_for_hp:1; /* Wait for HP port reset */
Jan Andersson8452c672011-05-18 10:44:49 +0200428 unsigned int big_endian_mmio:1; /* Big endian registers */
Jan Andersson51e2f622011-05-18 10:44:51 +0200429 unsigned int big_endian_desc:1; /* Big endian descriptors */
Jan Anderssondfeca7a2011-05-06 12:00:12 +0200430
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 /* Support for port suspend/resume/reset */
432 unsigned long port_c_suspend; /* Bit-arrays of ports */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 unsigned long resuming_ports;
434 unsigned long ports_timeout; /* Time to stop signalling */
435
Alan Sterndccf4a42005-12-17 17:58:46 -0500436 struct list_head idle_qh_list; /* Where the idle QHs live */
437
Alan Stern1f09df82005-09-05 13:59:51 -0400438 int rh_numports; /* Number of root-hub ports */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439
440 wait_queue_head_t waitqh; /* endpoint_disable waiters */
Alan Sterndccf4a42005-12-17 17:58:46 -0500441 int num_waiting; /* Number of waiters */
Alan Stern3ca2a322007-01-16 11:56:32 -0500442
443 int total_load; /* Sum of array values */
444 short load[MAX_PHASE]; /* Periodic allocations */
Jan Anderssone7652e12011-05-06 12:00:13 +0200445
446 /* Reset host controller */
447 void (*reset_hc) (struct uhci_hcd *uhci);
448 int (*check_and_reset_hc) (struct uhci_hcd *uhci);
449 /* configure_hc should perform arch specific settings, if needed */
450 void (*configure_hc) (struct uhci_hcd *uhci);
451 /* Check for broken resume detect interrupts */
452 int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
453 /* Check for broken global suspend */
454 int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455};
456
457/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
458static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
459{
460 return (struct uhci_hcd *) (hcd->hcd_priv);
461}
462static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
463{
464 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
465}
466
467#define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
468
Alan Sternc4334722006-05-19 16:34:57 -0400469/* Utility macro for comparing frame numbers */
470#define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
471
Alan Stern8b262bd2005-09-26 16:31:15 -0400472
473/*
474 * Private per-URB data
475 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476struct urb_priv {
Alan Sterndccf4a42005-12-17 17:58:46 -0500477 struct list_head node; /* Node in the QH's urbp list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478
479 struct urb *urb;
480
481 struct uhci_qh *qh; /* QH for this URB */
Alan Stern8b262bd2005-09-26 16:31:15 -0400482 struct list_head td_list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
Alan Stern84afddd2006-05-12 11:35:45 -0400484 unsigned fsbr:1; /* URB wants FSBR */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485};
486
Alan Stern8b262bd2005-09-26 16:31:15 -0400487
Alan Sternc8f4fe42005-04-09 17:27:32 -0400488/* Some special IDs */
489
490#define PCI_VENDOR_ID_GENESYS 0x17a0
491#define PCI_DEVICE_ID_GL880S_UHCI 0x8083
Alan Sternc8f4fe42005-04-09 17:27:32 -0400492
Jan Anderssond3219d12011-05-06 12:00:17 +0200493/*
494 * Functions used to access controller registers. The UCHI spec says that host
495 * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
496 * we use memory mapped registers.
497 */
498
Jan Andersson8452c672011-05-18 10:44:49 +0200499#ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
Jan Anderssond3219d12011-05-06 12:00:17 +0200500/* Support PCI only */
Jan Andersson8452c672011-05-18 10:44:49 +0200501static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
Jan Andersson9faa0912011-05-06 12:00:16 +0200502{
503 return inl(uhci->io_addr + reg);
504}
505
Jan Andersson8452c672011-05-18 10:44:49 +0200506static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
Jan Andersson9faa0912011-05-06 12:00:16 +0200507{
508 outl(val, uhci->io_addr + reg);
509}
510
Jan Andersson8452c672011-05-18 10:44:49 +0200511static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
Jan Andersson9faa0912011-05-06 12:00:16 +0200512{
513 return inw(uhci->io_addr + reg);
514}
515
Jan Andersson8452c672011-05-18 10:44:49 +0200516static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
Jan Andersson9faa0912011-05-06 12:00:16 +0200517{
518 outw(val, uhci->io_addr + reg);
519}
520
Jan Andersson8452c672011-05-18 10:44:49 +0200521static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
Jan Andersson9faa0912011-05-06 12:00:16 +0200522{
523 return inb(uhci->io_addr + reg);
524}
525
Jan Andersson8452c672011-05-18 10:44:49 +0200526static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
Jan Andersson9faa0912011-05-06 12:00:16 +0200527{
528 outb(val, uhci->io_addr + reg);
529}
530
Jan Anderssond3219d12011-05-06 12:00:17 +0200531#else
Jan Andersson8452c672011-05-18 10:44:49 +0200532/* Support non-PCI host controllers */
533#ifdef CONFIG_PCI
Jan Anderssond3219d12011-05-06 12:00:17 +0200534/* Support PCI and non-PCI host controllers */
Jan Anderssond3219d12011-05-06 12:00:17 +0200535#define uhci_has_pci_registers(u) ((u)->io_addr != 0)
Jan Andersson8452c672011-05-18 10:44:49 +0200536#else
537/* Support non-PCI host controllers only */
538#define uhci_has_pci_registers(u) 0
539#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200540
Jan Andersson8452c672011-05-18 10:44:49 +0200541#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
542/* Support (non-PCI) big endian host controllers */
543#define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
544#else
545#define uhci_big_endian_mmio(u) 0
546#endif
547
548static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
Jan Anderssond3219d12011-05-06 12:00:17 +0200549{
550 if (uhci_has_pci_registers(uhci))
551 return inl(uhci->io_addr + reg);
Jan Andersson8452c672011-05-18 10:44:49 +0200552#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
553 else if (uhci_big_endian_mmio(uhci))
554 return readl_be(uhci->regs + reg);
555#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200556 else
557 return readl(uhci->regs + reg);
558}
559
Jan Andersson8452c672011-05-18 10:44:49 +0200560static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
Jan Anderssond3219d12011-05-06 12:00:17 +0200561{
562 if (uhci_has_pci_registers(uhci))
563 outl(val, uhci->io_addr + reg);
Jan Andersson8452c672011-05-18 10:44:49 +0200564#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
565 else if (uhci_big_endian_mmio(uhci))
566 writel_be(val, uhci->regs + reg);
567#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200568 else
569 writel(val, uhci->regs + reg);
570}
571
Jan Andersson8452c672011-05-18 10:44:49 +0200572static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
Jan Anderssond3219d12011-05-06 12:00:17 +0200573{
574 if (uhci_has_pci_registers(uhci))
575 return inw(uhci->io_addr + reg);
Jan Andersson8452c672011-05-18 10:44:49 +0200576#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
577 else if (uhci_big_endian_mmio(uhci))
578 return readw_be(uhci->regs + reg);
579#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200580 else
581 return readw(uhci->regs + reg);
582}
583
Jan Andersson8452c672011-05-18 10:44:49 +0200584static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
Jan Anderssond3219d12011-05-06 12:00:17 +0200585{
586 if (uhci_has_pci_registers(uhci))
587 outw(val, uhci->io_addr + reg);
Jan Andersson8452c672011-05-18 10:44:49 +0200588#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
589 else if (uhci_big_endian_mmio(uhci))
590 writew_be(val, uhci->regs + reg);
591#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200592 else
593 writew(val, uhci->regs + reg);
594}
595
Jan Andersson8452c672011-05-18 10:44:49 +0200596static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
Jan Anderssond3219d12011-05-06 12:00:17 +0200597{
598 if (uhci_has_pci_registers(uhci))
599 return inb(uhci->io_addr + reg);
Jan Andersson8452c672011-05-18 10:44:49 +0200600#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
601 else if (uhci_big_endian_mmio(uhci))
602 return readb_be(uhci->regs + reg);
603#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200604 else
605 return readb(uhci->regs + reg);
606}
607
Jan Andersson8452c672011-05-18 10:44:49 +0200608static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
Jan Anderssond3219d12011-05-06 12:00:17 +0200609{
610 if (uhci_has_pci_registers(uhci))
611 outb(val, uhci->io_addr + reg);
Jan Andersson8452c672011-05-18 10:44:49 +0200612#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
613 else if (uhci_big_endian_mmio(uhci))
614 writeb_be(val, uhci->regs + reg);
615#endif
Jan Anderssond3219d12011-05-06 12:00:17 +0200616 else
617 writeb(val, uhci->regs + reg);
618}
Jan Andersson8452c672011-05-18 10:44:49 +0200619#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
Jan Anderssond3219d12011-05-06 12:00:17 +0200620
Jan Andersson51e2f622011-05-18 10:44:51 +0200621/*
622 * The GRLIB GRUSBHC controller can use big endian format for its descriptors.
623 *
624 * UHCI controllers accessed through PCI work normally (little-endian
625 * everywhere), so we don't bother supporting a BE-only mode.
626 */
627#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
628#define uhci_big_endian_desc(u) ((u)->big_endian_desc)
629
630/* cpu to uhci */
631static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
632{
633 return uhci_big_endian_desc(uhci)
634 ? (__force __hc32)cpu_to_be32(x)
635 : (__force __hc32)cpu_to_le32(x);
636}
637
638/* uhci to cpu */
639static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
640{
641 return uhci_big_endian_desc(uhci)
642 ? be32_to_cpu((__force __be32)x)
643 : le32_to_cpu((__force __le32)x);
644}
645
646#else
647/* cpu to uhci */
648static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
649{
650 return cpu_to_le32(x);
651}
652
653/* uhci to cpu */
654static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
655{
656 return le32_to_cpu(x);
657}
658#endif
659
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660#endif