blob: bbed3a13f9a4952214112992eecd22034a170f70 [file] [log] [blame]
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001/*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +020030#include <linux/semaphore.h>
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +020031#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +020034#include <linux/wait.h>
Tomi Valkeinen18946f62010-01-12 14:16:41 +020035#include <linux/workqueue.h>
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +020036
37#include <plat/display.h>
38#include <plat/clock.h>
39
40#include "dss.h"
41
42/*#define VERBOSE_IRQ*/
43#define DSI_CATCH_MISSING_TE
44
45#define DSI_BASE 0x4804FC00
46
47struct dsi_reg { u16 idx; };
48
49#define DSI_REG(idx) ((const struct dsi_reg) { idx })
50
51#define DSI_SZ_REGS SZ_1K
52/* DSI Protocol Engine */
53
54#define DSI_REVISION DSI_REG(0x0000)
55#define DSI_SYSCONFIG DSI_REG(0x0010)
56#define DSI_SYSSTATUS DSI_REG(0x0014)
57#define DSI_IRQSTATUS DSI_REG(0x0018)
58#define DSI_IRQENABLE DSI_REG(0x001C)
59#define DSI_CTRL DSI_REG(0x0040)
60#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63#define DSI_CLK_CTRL DSI_REG(0x0054)
64#define DSI_TIMING1 DSI_REG(0x0058)
65#define DSI_TIMING2 DSI_REG(0x005C)
66#define DSI_VM_TIMING1 DSI_REG(0x0060)
67#define DSI_VM_TIMING2 DSI_REG(0x0064)
68#define DSI_VM_TIMING3 DSI_REG(0x0068)
69#define DSI_CLK_TIMING DSI_REG(0x006C)
70#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74#define DSI_VM_TIMING4 DSI_REG(0x0080)
75#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76#define DSI_VM_TIMING5 DSI_REG(0x0088)
77#define DSI_VM_TIMING6 DSI_REG(0x008C)
78#define DSI_VM_TIMING7 DSI_REG(0x0090)
79#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
87
88/* DSIPHY_SCP */
89
90#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94
95/* DSI_PLL_CTRL_SCP */
96
97#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
98#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
99#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
100#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
101#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102
103#define REG_GET(idx, start, end) \
104 FLD_GET(dsi_read_reg(idx), start, end)
105
106#define REG_FLD_MOD(idx, val, start, end) \
107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108
109/* Global interrupts */
110#define DSI_IRQ_VC0 (1 << 0)
111#define DSI_IRQ_VC1 (1 << 1)
112#define DSI_IRQ_VC2 (1 << 2)
113#define DSI_IRQ_VC3 (1 << 3)
114#define DSI_IRQ_WAKEUP (1 << 4)
115#define DSI_IRQ_RESYNC (1 << 5)
116#define DSI_IRQ_PLL_LOCK (1 << 7)
117#define DSI_IRQ_PLL_UNLOCK (1 << 8)
118#define DSI_IRQ_PLL_RECALL (1 << 9)
119#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
120#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
121#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
122#define DSI_IRQ_TE_TRIGGER (1 << 16)
123#define DSI_IRQ_ACK_TRIGGER (1 << 17)
124#define DSI_IRQ_SYNC_LOST (1 << 18)
125#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
126#define DSI_IRQ_TA_TIMEOUT (1 << 20)
127#define DSI_IRQ_ERROR_MASK \
128 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 DSI_IRQ_TA_TIMEOUT)
130#define DSI_IRQ_CHANNEL_MASK 0xf
131
132/* Virtual channel interrupts */
133#define DSI_VC_IRQ_CS (1 << 0)
134#define DSI_VC_IRQ_ECC_CORR (1 << 1)
135#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
136#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
137#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
138#define DSI_VC_IRQ_BTA (1 << 5)
139#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
140#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
141#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
142#define DSI_VC_IRQ_ERROR_MASK \
143 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
144 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
145 DSI_VC_IRQ_FIFO_TX_UDF)
146
147/* ComplexIO interrupts */
148#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
149#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
150#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
151#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
152#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
153#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
154#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
155#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
156#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
157#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
158#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
159#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
160#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
161#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
162#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
163#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
164#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
165#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
166#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
167#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
168
169#define DSI_DT_DCS_SHORT_WRITE_0 0x05
170#define DSI_DT_DCS_SHORT_WRITE_1 0x15
171#define DSI_DT_DCS_READ 0x06
172#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
173#define DSI_DT_NULL_PACKET 0x09
174#define DSI_DT_DCS_LONG_WRITE 0x39
175
176#define DSI_DT_RX_ACK_WITH_ERR 0x02
177#define DSI_DT_RX_DCS_LONG_READ 0x1c
178#define DSI_DT_RX_SHORT_READ_1 0x21
179#define DSI_DT_RX_SHORT_READ_2 0x22
180
181#define FINT_MAX 2100000
182#define FINT_MIN 750000
183#define REGN_MAX (1 << 7)
184#define REGM_MAX ((1 << 11) - 1)
185#define REGM3_MAX (1 << 4)
186#define REGM4_MAX (1 << 4)
187#define LP_DIV_MAX ((1 << 13) - 1)
188
189enum fifo_size {
190 DSI_FIFO_SIZE_0 = 0,
191 DSI_FIFO_SIZE_32 = 1,
192 DSI_FIFO_SIZE_64 = 2,
193 DSI_FIFO_SIZE_96 = 3,
194 DSI_FIFO_SIZE_128 = 4,
195};
196
197enum dsi_vc_mode {
198 DSI_VC_MODE_L4 = 0,
199 DSI_VC_MODE_VP,
200};
201
202struct dsi_update_region {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200203 u16 x, y, w, h;
204 struct omap_dss_device *device;
205};
206
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200207struct dsi_irq_stats {
208 unsigned long last_reset;
209 unsigned irq_count;
210 unsigned dsi_irqs[32];
211 unsigned vc_irqs[4][32];
212 unsigned cio_irqs[32];
213};
214
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200215static struct
216{
217 void __iomem *base;
218
219 struct dsi_clock_info current_cinfo;
220
221 struct regulator *vdds_dsi_reg;
222
223 struct {
224 enum dsi_vc_mode mode;
225 struct omap_dss_device *dssdev;
226 enum fifo_size fifo_size;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200227 } vc[4];
228
229 struct mutex lock;
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200230 struct semaphore bus_lock;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200231
232 unsigned pll_locked;
233
234 struct completion bta_completion;
235
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200236 int update_channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200237 struct dsi_update_region update_region;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200238
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200239 bool te_enabled;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200240
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +0300241 struct workqueue_struct *workqueue;
242
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200243 struct work_struct framedone_work;
244 void (*framedone_callback)(int, void *);
245 void *framedone_data;
246
247 struct delayed_work framedone_timeout_work;
248
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200249#ifdef DSI_CATCH_MISSING_TE
250 struct timer_list te_timer;
251#endif
252
253 unsigned long cache_req_pck;
254 unsigned long cache_clk_freq;
255 struct dsi_clock_info cache_cinfo;
256
257 u32 errors;
258 spinlock_t errors_lock;
259#ifdef DEBUG
260 ktime_t perf_setup_time;
261 ktime_t perf_start_time;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200262#endif
263 int debug_read;
264 int debug_write;
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200265
266#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
267 spinlock_t irq_stats_lock;
268 struct dsi_irq_stats irq_stats;
269#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200270} dsi;
271
272#ifdef DEBUG
273static unsigned int dsi_perf;
274module_param_named(dsi_perf, dsi_perf, bool, 0644);
275#endif
276
277static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
278{
279 __raw_writel(val, dsi.base + idx.idx);
280}
281
282static inline u32 dsi_read_reg(const struct dsi_reg idx)
283{
284 return __raw_readl(dsi.base + idx.idx);
285}
286
287
288void dsi_save_context(void)
289{
290}
291
292void dsi_restore_context(void)
293{
294}
295
296void dsi_bus_lock(void)
297{
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200298 down(&dsi.bus_lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200299}
300EXPORT_SYMBOL(dsi_bus_lock);
301
302void dsi_bus_unlock(void)
303{
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200304 up(&dsi.bus_lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200305}
306EXPORT_SYMBOL(dsi_bus_unlock);
307
Tomi Valkeinen4f765022010-01-18 16:27:52 +0200308static bool dsi_bus_is_locked(void)
309{
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200310 return dsi.bus_lock.count == 0;
Tomi Valkeinen4f765022010-01-18 16:27:52 +0200311}
312
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200313static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
314 int value)
315{
316 int t = 100000;
317
318 while (REG_GET(idx, bitnum, bitnum) != value) {
319 if (--t == 0)
320 return !value;
321 }
322
323 return value;
324}
325
326#ifdef DEBUG
327static void dsi_perf_mark_setup(void)
328{
329 dsi.perf_setup_time = ktime_get();
330}
331
332static void dsi_perf_mark_start(void)
333{
334 dsi.perf_start_time = ktime_get();
335}
336
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200337static void dsi_perf_show(const char *name)
338{
339 ktime_t t, setup_time, trans_time;
340 u32 total_bytes;
341 u32 setup_us, trans_us, total_us;
342
343 if (!dsi_perf)
344 return;
345
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200346 t = ktime_get();
347
348 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
349 setup_us = (u32)ktime_to_us(setup_time);
350 if (setup_us == 0)
351 setup_us = 1;
352
353 trans_time = ktime_sub(t, dsi.perf_start_time);
354 trans_us = (u32)ktime_to_us(trans_time);
355 if (trans_us == 0)
356 trans_us = 1;
357
358 total_us = setup_us + trans_us;
359
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200360 total_bytes = dsi.update_region.w *
361 dsi.update_region.h *
362 dsi.update_region.device->ctrl.pixel_size / 8;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200363
Tomi Valkeinen1bbb2752010-01-11 16:41:10 +0200364 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
365 "%u bytes, %u kbytes/sec\n",
366 name,
367 setup_us,
368 trans_us,
369 total_us,
370 1000*1000 / total_us,
371 total_bytes,
372 total_bytes * 1000 / total_us);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200373}
374#else
375#define dsi_perf_mark_setup()
376#define dsi_perf_mark_start()
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200377#define dsi_perf_show(x)
378#endif
379
380static void print_irq_status(u32 status)
381{
382#ifndef VERBOSE_IRQ
383 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
384 return;
385#endif
386 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
387
388#define PIS(x) \
389 if (status & DSI_IRQ_##x) \
390 printk(#x " ");
391#ifdef VERBOSE_IRQ
392 PIS(VC0);
393 PIS(VC1);
394 PIS(VC2);
395 PIS(VC3);
396#endif
397 PIS(WAKEUP);
398 PIS(RESYNC);
399 PIS(PLL_LOCK);
400 PIS(PLL_UNLOCK);
401 PIS(PLL_RECALL);
402 PIS(COMPLEXIO_ERR);
403 PIS(HS_TX_TIMEOUT);
404 PIS(LP_RX_TIMEOUT);
405 PIS(TE_TRIGGER);
406 PIS(ACK_TRIGGER);
407 PIS(SYNC_LOST);
408 PIS(LDO_POWER_GOOD);
409 PIS(TA_TIMEOUT);
410#undef PIS
411
412 printk("\n");
413}
414
415static void print_irq_status_vc(int channel, u32 status)
416{
417#ifndef VERBOSE_IRQ
418 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
419 return;
420#endif
421 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
422
423#define PIS(x) \
424 if (status & DSI_VC_IRQ_##x) \
425 printk(#x " ");
426 PIS(CS);
427 PIS(ECC_CORR);
428#ifdef VERBOSE_IRQ
429 PIS(PACKET_SENT);
430#endif
431 PIS(FIFO_TX_OVF);
432 PIS(FIFO_RX_OVF);
433 PIS(BTA);
434 PIS(ECC_NO_CORR);
435 PIS(FIFO_TX_UDF);
436 PIS(PP_BUSY_CHANGE);
437#undef PIS
438 printk("\n");
439}
440
441static void print_irq_status_cio(u32 status)
442{
443 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
444
445#define PIS(x) \
446 if (status & DSI_CIO_IRQ_##x) \
447 printk(#x " ");
448 PIS(ERRSYNCESC1);
449 PIS(ERRSYNCESC2);
450 PIS(ERRSYNCESC3);
451 PIS(ERRESC1);
452 PIS(ERRESC2);
453 PIS(ERRESC3);
454 PIS(ERRCONTROL1);
455 PIS(ERRCONTROL2);
456 PIS(ERRCONTROL3);
457 PIS(STATEULPS1);
458 PIS(STATEULPS2);
459 PIS(STATEULPS3);
460 PIS(ERRCONTENTIONLP0_1);
461 PIS(ERRCONTENTIONLP1_1);
462 PIS(ERRCONTENTIONLP0_2);
463 PIS(ERRCONTENTIONLP1_2);
464 PIS(ERRCONTENTIONLP0_3);
465 PIS(ERRCONTENTIONLP1_3);
466 PIS(ULPSACTIVENOT_ALL0);
467 PIS(ULPSACTIVENOT_ALL1);
468#undef PIS
469
470 printk("\n");
471}
472
473static int debug_irq;
474
475/* called from dss */
476void dsi_irq_handler(void)
477{
478 u32 irqstatus, vcstatus, ciostatus;
479 int i;
480
481 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
482
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200483#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
484 spin_lock(&dsi.irq_stats_lock);
485 dsi.irq_stats.irq_count++;
486 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
487#endif
488
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200489 if (irqstatus & DSI_IRQ_ERROR_MASK) {
490 DSSERR("DSI error, irqstatus %x\n", irqstatus);
491 print_irq_status(irqstatus);
492 spin_lock(&dsi.errors_lock);
493 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
494 spin_unlock(&dsi.errors_lock);
495 } else if (debug_irq) {
496 print_irq_status(irqstatus);
497 }
498
499#ifdef DSI_CATCH_MISSING_TE
500 if (irqstatus & DSI_IRQ_TE_TRIGGER)
501 del_timer(&dsi.te_timer);
502#endif
503
504 for (i = 0; i < 4; ++i) {
505 if ((irqstatus & (1<<i)) == 0)
506 continue;
507
508 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
509
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200510#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
511 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
512#endif
513
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200514 if (vcstatus & DSI_VC_IRQ_BTA)
515 complete(&dsi.bta_completion);
516
517 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
518 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
519 i, vcstatus);
520 print_irq_status_vc(i, vcstatus);
521 } else if (debug_irq) {
522 print_irq_status_vc(i, vcstatus);
523 }
524
525 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
526 /* flush posted write */
527 dsi_read_reg(DSI_VC_IRQSTATUS(i));
528 }
529
530 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
531 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
532
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200533#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
534 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
535#endif
536
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200537 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
538 /* flush posted write */
539 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
540
541 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
542 print_irq_status_cio(ciostatus);
543 }
544
545 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
546 /* flush posted write */
547 dsi_read_reg(DSI_IRQSTATUS);
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200548
549#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
550 spin_unlock(&dsi.irq_stats_lock);
551#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200552}
553
554
555static void _dsi_initialize_irq(void)
556{
557 u32 l;
558 int i;
559
560 /* disable all interrupts */
561 dsi_write_reg(DSI_IRQENABLE, 0);
562 for (i = 0; i < 4; ++i)
563 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
564 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
565
566 /* clear interrupt status */
567 l = dsi_read_reg(DSI_IRQSTATUS);
568 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
569
570 for (i = 0; i < 4; ++i) {
571 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
572 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
573 }
574
575 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
576 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
577
578 /* enable error irqs */
579 l = DSI_IRQ_ERROR_MASK;
580#ifdef DSI_CATCH_MISSING_TE
581 l |= DSI_IRQ_TE_TRIGGER;
582#endif
583 dsi_write_reg(DSI_IRQENABLE, l);
584
585 l = DSI_VC_IRQ_ERROR_MASK;
586 for (i = 0; i < 4; ++i)
587 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
588
589 /* XXX zonda responds incorrectly, causing control error:
590 Exit from LP-ESC mode to LP11 uses wrong transition states on the
591 data lines LP0 and LN0. */
592 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
593 -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
594}
595
596static u32 dsi_get_errors(void)
597{
598 unsigned long flags;
599 u32 e;
600 spin_lock_irqsave(&dsi.errors_lock, flags);
601 e = dsi.errors;
602 dsi.errors = 0;
603 spin_unlock_irqrestore(&dsi.errors_lock, flags);
604 return e;
605}
606
607static void dsi_vc_enable_bta_irq(int channel)
608{
609 u32 l;
610
611 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
612
613 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
614 l |= DSI_VC_IRQ_BTA;
615 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
616}
617
618static void dsi_vc_disable_bta_irq(int channel)
619{
620 u32 l;
621
622 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
623 l &= ~DSI_VC_IRQ_BTA;
624 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
625}
626
627/* DSI func clock. this could also be DSI2_PLL_FCLK */
628static inline void enable_clocks(bool enable)
629{
630 if (enable)
631 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
632 else
633 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
634}
635
636/* source clock for DSI PLL. this could also be PCLKFREE */
637static inline void dsi_enable_pll_clock(bool enable)
638{
639 if (enable)
640 dss_clk_enable(DSS_CLK_FCK2);
641 else
642 dss_clk_disable(DSS_CLK_FCK2);
643
644 if (enable && dsi.pll_locked) {
645 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
646 DSSERR("cannot lock PLL when enabling clocks\n");
647 }
648}
649
650#ifdef DEBUG
651static void _dsi_print_reset_status(void)
652{
653 u32 l;
654
655 if (!dss_debug)
656 return;
657
658 /* A dummy read using the SCP interface to any DSIPHY register is
659 * required after DSIPHY reset to complete the reset of the DSI complex
660 * I/O. */
661 l = dsi_read_reg(DSI_DSIPHY_CFG5);
662
663 printk(KERN_DEBUG "DSI resets: ");
664
665 l = dsi_read_reg(DSI_PLL_STATUS);
666 printk("PLL (%d) ", FLD_GET(l, 0, 0));
667
668 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
669 printk("CIO (%d) ", FLD_GET(l, 29, 29));
670
671 l = dsi_read_reg(DSI_DSIPHY_CFG5);
672 printk("PHY (%x, %d, %d, %d)\n",
673 FLD_GET(l, 28, 26),
674 FLD_GET(l, 29, 29),
675 FLD_GET(l, 30, 30),
676 FLD_GET(l, 31, 31));
677}
678#else
679#define _dsi_print_reset_status()
680#endif
681
682static inline int dsi_if_enable(bool enable)
683{
684 DSSDBG("dsi_if_enable(%d)\n", enable);
685
686 enable = enable ? 1 : 0;
687 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
688
689 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
690 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
691 return -EIO;
692 }
693
694 return 0;
695}
696
697unsigned long dsi_get_dsi1_pll_rate(void)
698{
699 return dsi.current_cinfo.dsi1_pll_fclk;
700}
701
702static unsigned long dsi_get_dsi2_pll_rate(void)
703{
704 return dsi.current_cinfo.dsi2_pll_fclk;
705}
706
707static unsigned long dsi_get_txbyteclkhs(void)
708{
709 return dsi.current_cinfo.clkin4ddr / 16;
710}
711
712static unsigned long dsi_fclk_rate(void)
713{
714 unsigned long r;
715
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +0200716 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200717 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
718 r = dss_clk_get_rate(DSS_CLK_FCK1);
719 } else {
720 /* DSI FCLK source is DSI2_PLL_FCLK */
721 r = dsi_get_dsi2_pll_rate();
722 }
723
724 return r;
725}
726
727static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
728{
729 unsigned long dsi_fclk;
730 unsigned lp_clk_div;
731 unsigned long lp_clk;
732
733 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
734
735 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
736 return -EINVAL;
737
738 dsi_fclk = dsi_fclk_rate();
739
740 lp_clk = dsi_fclk / 2 / lp_clk_div;
741
742 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
743 dsi.current_cinfo.lp_clk = lp_clk;
744 dsi.current_cinfo.lp_clk_div = lp_clk_div;
745
746 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
747
748 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
749 21, 21); /* LP_RX_SYNCHRO_ENABLE */
750
751 return 0;
752}
753
754
755enum dsi_pll_power_state {
756 DSI_PLL_POWER_OFF = 0x0,
757 DSI_PLL_POWER_ON_HSCLK = 0x1,
758 DSI_PLL_POWER_ON_ALL = 0x2,
759 DSI_PLL_POWER_ON_DIV = 0x3,
760};
761
762static int dsi_pll_power(enum dsi_pll_power_state state)
763{
764 int t = 0;
765
766 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
767
768 /* PLL_PWR_STATUS */
769 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200770 if (++t > 1000) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200771 DSSERR("Failed to set DSI PLL power mode to %d\n",
772 state);
773 return -ENODEV;
774 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200775 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200776 }
777
778 return 0;
779}
780
781/* calculate clock rates using dividers in cinfo */
782static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
783{
784 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
785 return -EINVAL;
786
787 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
788 return -EINVAL;
789
790 if (cinfo->regm3 > REGM3_MAX)
791 return -EINVAL;
792
793 if (cinfo->regm4 > REGM4_MAX)
794 return -EINVAL;
795
796 if (cinfo->use_dss2_fck) {
797 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
798 /* XXX it is unclear if highfreq should be used
799 * with DSS2_FCK source also */
800 cinfo->highfreq = 0;
801 } else {
802 cinfo->clkin = dispc_pclk_rate();
803
804 if (cinfo->clkin < 32000000)
805 cinfo->highfreq = 0;
806 else
807 cinfo->highfreq = 1;
808 }
809
810 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
811
812 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
813 return -EINVAL;
814
815 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
816
817 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
818 return -EINVAL;
819
820 if (cinfo->regm3 > 0)
821 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
822 else
823 cinfo->dsi1_pll_fclk = 0;
824
825 if (cinfo->regm4 > 0)
826 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
827 else
828 cinfo->dsi2_pll_fclk = 0;
829
830 return 0;
831}
832
833int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
834 struct dsi_clock_info *dsi_cinfo,
835 struct dispc_clock_info *dispc_cinfo)
836{
837 struct dsi_clock_info cur, best;
838 struct dispc_clock_info best_dispc;
839 int min_fck_per_pck;
840 int match = 0;
841 unsigned long dss_clk_fck2;
842
843 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
844
845 if (req_pck == dsi.cache_req_pck &&
846 dsi.cache_cinfo.clkin == dss_clk_fck2) {
847 DSSDBG("DSI clock info found from cache\n");
848 *dsi_cinfo = dsi.cache_cinfo;
849 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
850 dispc_cinfo);
851 return 0;
852 }
853
854 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
855
856 if (min_fck_per_pck &&
857 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
858 DSSERR("Requested pixel clock not possible with the current "
859 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
860 "the constraint off.\n");
861 min_fck_per_pck = 0;
862 }
863
864 DSSDBG("dsi_pll_calc\n");
865
866retry:
867 memset(&best, 0, sizeof(best));
868 memset(&best_dispc, 0, sizeof(best_dispc));
869
870 memset(&cur, 0, sizeof(cur));
871 cur.clkin = dss_clk_fck2;
872 cur.use_dss2_fck = 1;
873 cur.highfreq = 0;
874
875 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
876 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
877 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
878 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
879 if (cur.highfreq == 0)
880 cur.fint = cur.clkin / cur.regn;
881 else
882 cur.fint = cur.clkin / (2 * cur.regn);
883
884 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
885 continue;
886
887 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
888 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
889 unsigned long a, b;
890
891 a = 2 * cur.regm * (cur.clkin/1000);
892 b = cur.regn * (cur.highfreq + 1);
893 cur.clkin4ddr = a / b * 1000;
894
895 if (cur.clkin4ddr > 1800 * 1000 * 1000)
896 break;
897
898 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
899 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
900 ++cur.regm3) {
901 struct dispc_clock_info cur_dispc;
902 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
903
904 /* this will narrow down the search a bit,
905 * but still give pixclocks below what was
906 * requested */
907 if (cur.dsi1_pll_fclk < req_pck)
908 break;
909
910 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
911 continue;
912
913 if (min_fck_per_pck &&
914 cur.dsi1_pll_fclk <
915 req_pck * min_fck_per_pck)
916 continue;
917
918 match = 1;
919
920 dispc_find_clk_divs(is_tft, req_pck,
921 cur.dsi1_pll_fclk,
922 &cur_dispc);
923
924 if (abs(cur_dispc.pck - req_pck) <
925 abs(best_dispc.pck - req_pck)) {
926 best = cur;
927 best_dispc = cur_dispc;
928
929 if (cur_dispc.pck == req_pck)
930 goto found;
931 }
932 }
933 }
934 }
935found:
936 if (!match) {
937 if (min_fck_per_pck) {
938 DSSERR("Could not find suitable clock settings.\n"
939 "Turning FCK/PCK constraint off and"
940 "trying again.\n");
941 min_fck_per_pck = 0;
942 goto retry;
943 }
944
945 DSSERR("Could not find suitable clock settings.\n");
946
947 return -EINVAL;
948 }
949
950 /* DSI2_PLL_FCLK (regm4) is not used */
951 best.regm4 = 0;
952 best.dsi2_pll_fclk = 0;
953
954 if (dsi_cinfo)
955 *dsi_cinfo = best;
956 if (dispc_cinfo)
957 *dispc_cinfo = best_dispc;
958
959 dsi.cache_req_pck = req_pck;
960 dsi.cache_clk_freq = 0;
961 dsi.cache_cinfo = best;
962
963 return 0;
964}
965
966int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
967{
968 int r = 0;
969 u32 l;
970 int f;
971
972 DSSDBGF();
973
974 dsi.current_cinfo.fint = cinfo->fint;
975 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
976 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
977 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
978
979 dsi.current_cinfo.regn = cinfo->regn;
980 dsi.current_cinfo.regm = cinfo->regm;
981 dsi.current_cinfo.regm3 = cinfo->regm3;
982 dsi.current_cinfo.regm4 = cinfo->regm4;
983
984 DSSDBG("DSI Fint %ld\n", cinfo->fint);
985
986 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
987 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
988 cinfo->clkin,
989 cinfo->highfreq);
990
991 /* DSIPHY == CLKIN4DDR */
992 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
993 cinfo->regm,
994 cinfo->regn,
995 cinfo->clkin,
996 cinfo->highfreq + 1,
997 cinfo->clkin4ddr);
998
999 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1000 cinfo->clkin4ddr / 1000 / 1000 / 2);
1001
1002 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1003
1004 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1005 cinfo->regm3, cinfo->dsi1_pll_fclk);
1006 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1007 cinfo->regm4, cinfo->dsi2_pll_fclk);
1008
1009 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1010
1011 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1012 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1013 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1014 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1015 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1016 22, 19); /* DSI_CLOCK_DIV */
1017 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1018 26, 23); /* DSIPROTO_CLOCK_DIV */
1019 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1020
1021 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1022 if (cinfo->fint < 1000000)
1023 f = 0x3;
1024 else if (cinfo->fint < 1250000)
1025 f = 0x4;
1026 else if (cinfo->fint < 1500000)
1027 f = 0x5;
1028 else if (cinfo->fint < 1750000)
1029 f = 0x6;
1030 else
1031 f = 0x7;
1032
1033 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1034 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1035 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1036 11, 11); /* DSI_PLL_CLKSEL */
1037 l = FLD_MOD(l, cinfo->highfreq,
1038 12, 12); /* DSI_PLL_HIGHFREQ */
1039 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1040 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1041 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1042 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1043
1044 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1045
1046 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1047 DSSERR("dsi pll go bit not going down.\n");
1048 r = -EIO;
1049 goto err;
1050 }
1051
1052 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1053 DSSERR("cannot lock PLL\n");
1054 r = -EIO;
1055 goto err;
1056 }
1057
1058 dsi.pll_locked = 1;
1059
1060 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1061 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1062 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1063 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1064 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1065 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1066 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1067 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1068 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1069 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1070 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1071 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1072 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1073 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1074 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1075 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1076
1077 DSSDBG("PLL config done\n");
1078err:
1079 return r;
1080}
1081
1082int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1083 bool enable_hsdiv)
1084{
1085 int r = 0;
1086 enum dsi_pll_power_state pwstate;
1087
1088 DSSDBG("PLL init\n");
1089
1090 enable_clocks(1);
1091 dsi_enable_pll_clock(1);
1092
1093 r = regulator_enable(dsi.vdds_dsi_reg);
1094 if (r)
1095 goto err0;
1096
1097 /* XXX PLL does not come out of reset without this... */
1098 dispc_pck_free_enable(1);
1099
1100 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1101 DSSERR("PLL not coming out of reset.\n");
1102 r = -ENODEV;
Ville Syrjälä481dfa02010-04-22 22:50:04 +02001103 dispc_pck_free_enable(0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001104 goto err1;
1105 }
1106
1107 /* XXX ... but if left on, we get problems when planes do not
1108 * fill the whole display. No idea about this */
1109 dispc_pck_free_enable(0);
1110
1111 if (enable_hsclk && enable_hsdiv)
1112 pwstate = DSI_PLL_POWER_ON_ALL;
1113 else if (enable_hsclk)
1114 pwstate = DSI_PLL_POWER_ON_HSCLK;
1115 else if (enable_hsdiv)
1116 pwstate = DSI_PLL_POWER_ON_DIV;
1117 else
1118 pwstate = DSI_PLL_POWER_OFF;
1119
1120 r = dsi_pll_power(pwstate);
1121
1122 if (r)
1123 goto err1;
1124
1125 DSSDBG("PLL init done\n");
1126
1127 return 0;
1128err1:
1129 regulator_disable(dsi.vdds_dsi_reg);
1130err0:
1131 enable_clocks(0);
1132 dsi_enable_pll_clock(0);
1133 return r;
1134}
1135
1136void dsi_pll_uninit(void)
1137{
1138 enable_clocks(0);
1139 dsi_enable_pll_clock(0);
1140
1141 dsi.pll_locked = 0;
1142 dsi_pll_power(DSI_PLL_POWER_OFF);
1143 regulator_disable(dsi.vdds_dsi_reg);
1144 DSSDBG("PLL uninit done\n");
1145}
1146
1147void dsi_dump_clocks(struct seq_file *s)
1148{
1149 int clksel;
1150 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1151
1152 enable_clocks(1);
1153
1154 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1155
1156 seq_printf(s, "- DSI PLL -\n");
1157
1158 seq_printf(s, "dsi pll source = %s\n",
1159 clksel == 0 ?
1160 "dss2_alwon_fclk" : "pclkfree");
1161
1162 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1163
1164 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1165 cinfo->clkin4ddr, cinfo->regm);
1166
1167 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1168 cinfo->dsi1_pll_fclk,
1169 cinfo->regm3,
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +02001170 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1171 "off" : "on");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001172
1173 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1174 cinfo->dsi2_pll_fclk,
1175 cinfo->regm4,
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +02001176 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1177 "off" : "on");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001178
1179 seq_printf(s, "- DSI -\n");
1180
1181 seq_printf(s, "dsi fclk source = %s\n",
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +02001182 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001183 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1184
1185 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1186
1187 seq_printf(s, "DDR_CLK\t\t%lu\n",
1188 cinfo->clkin4ddr / 4);
1189
1190 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1191
1192 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1193
1194 seq_printf(s, "VP_CLK\t\t%lu\n"
1195 "VP_PCLK\t\t%lu\n",
1196 dispc_lclk_rate(),
1197 dispc_pclk_rate());
1198
1199 enable_clocks(0);
1200}
1201
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02001202#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1203void dsi_dump_irqs(struct seq_file *s)
1204{
1205 unsigned long flags;
1206 struct dsi_irq_stats stats;
1207
1208 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1209
1210 stats = dsi.irq_stats;
1211 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1212 dsi.irq_stats.last_reset = jiffies;
1213
1214 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1215
1216 seq_printf(s, "period %u ms\n",
1217 jiffies_to_msecs(jiffies - stats.last_reset));
1218
1219 seq_printf(s, "irqs %d\n", stats.irq_count);
1220#define PIS(x) \
1221 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1222
1223 seq_printf(s, "-- DSI interrupts --\n");
1224 PIS(VC0);
1225 PIS(VC1);
1226 PIS(VC2);
1227 PIS(VC3);
1228 PIS(WAKEUP);
1229 PIS(RESYNC);
1230 PIS(PLL_LOCK);
1231 PIS(PLL_UNLOCK);
1232 PIS(PLL_RECALL);
1233 PIS(COMPLEXIO_ERR);
1234 PIS(HS_TX_TIMEOUT);
1235 PIS(LP_RX_TIMEOUT);
1236 PIS(TE_TRIGGER);
1237 PIS(ACK_TRIGGER);
1238 PIS(SYNC_LOST);
1239 PIS(LDO_POWER_GOOD);
1240 PIS(TA_TIMEOUT);
1241#undef PIS
1242
1243#define PIS(x) \
1244 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1245 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1246 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1247 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1248 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1249
1250 seq_printf(s, "-- VC interrupts --\n");
1251 PIS(CS);
1252 PIS(ECC_CORR);
1253 PIS(PACKET_SENT);
1254 PIS(FIFO_TX_OVF);
1255 PIS(FIFO_RX_OVF);
1256 PIS(BTA);
1257 PIS(ECC_NO_CORR);
1258 PIS(FIFO_TX_UDF);
1259 PIS(PP_BUSY_CHANGE);
1260#undef PIS
1261
1262#define PIS(x) \
1263 seq_printf(s, "%-20s %10d\n", #x, \
1264 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1265
1266 seq_printf(s, "-- CIO interrupts --\n");
1267 PIS(ERRSYNCESC1);
1268 PIS(ERRSYNCESC2);
1269 PIS(ERRSYNCESC3);
1270 PIS(ERRESC1);
1271 PIS(ERRESC2);
1272 PIS(ERRESC3);
1273 PIS(ERRCONTROL1);
1274 PIS(ERRCONTROL2);
1275 PIS(ERRCONTROL3);
1276 PIS(STATEULPS1);
1277 PIS(STATEULPS2);
1278 PIS(STATEULPS3);
1279 PIS(ERRCONTENTIONLP0_1);
1280 PIS(ERRCONTENTIONLP1_1);
1281 PIS(ERRCONTENTIONLP0_2);
1282 PIS(ERRCONTENTIONLP1_2);
1283 PIS(ERRCONTENTIONLP0_3);
1284 PIS(ERRCONTENTIONLP1_3);
1285 PIS(ULPSACTIVENOT_ALL0);
1286 PIS(ULPSACTIVENOT_ALL1);
1287#undef PIS
1288}
1289#endif
1290
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001291void dsi_dump_regs(struct seq_file *s)
1292{
1293#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1294
1295 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1296
1297 DUMPREG(DSI_REVISION);
1298 DUMPREG(DSI_SYSCONFIG);
1299 DUMPREG(DSI_SYSSTATUS);
1300 DUMPREG(DSI_IRQSTATUS);
1301 DUMPREG(DSI_IRQENABLE);
1302 DUMPREG(DSI_CTRL);
1303 DUMPREG(DSI_COMPLEXIO_CFG1);
1304 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1305 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1306 DUMPREG(DSI_CLK_CTRL);
1307 DUMPREG(DSI_TIMING1);
1308 DUMPREG(DSI_TIMING2);
1309 DUMPREG(DSI_VM_TIMING1);
1310 DUMPREG(DSI_VM_TIMING2);
1311 DUMPREG(DSI_VM_TIMING3);
1312 DUMPREG(DSI_CLK_TIMING);
1313 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1314 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1315 DUMPREG(DSI_COMPLEXIO_CFG2);
1316 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1317 DUMPREG(DSI_VM_TIMING4);
1318 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1319 DUMPREG(DSI_VM_TIMING5);
1320 DUMPREG(DSI_VM_TIMING6);
1321 DUMPREG(DSI_VM_TIMING7);
1322 DUMPREG(DSI_STOPCLK_TIMING);
1323
1324 DUMPREG(DSI_VC_CTRL(0));
1325 DUMPREG(DSI_VC_TE(0));
1326 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1327 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1328 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1329 DUMPREG(DSI_VC_IRQSTATUS(0));
1330 DUMPREG(DSI_VC_IRQENABLE(0));
1331
1332 DUMPREG(DSI_VC_CTRL(1));
1333 DUMPREG(DSI_VC_TE(1));
1334 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1335 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1336 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1337 DUMPREG(DSI_VC_IRQSTATUS(1));
1338 DUMPREG(DSI_VC_IRQENABLE(1));
1339
1340 DUMPREG(DSI_VC_CTRL(2));
1341 DUMPREG(DSI_VC_TE(2));
1342 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1343 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1344 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1345 DUMPREG(DSI_VC_IRQSTATUS(2));
1346 DUMPREG(DSI_VC_IRQENABLE(2));
1347
1348 DUMPREG(DSI_VC_CTRL(3));
1349 DUMPREG(DSI_VC_TE(3));
1350 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1351 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1352 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1353 DUMPREG(DSI_VC_IRQSTATUS(3));
1354 DUMPREG(DSI_VC_IRQENABLE(3));
1355
1356 DUMPREG(DSI_DSIPHY_CFG0);
1357 DUMPREG(DSI_DSIPHY_CFG1);
1358 DUMPREG(DSI_DSIPHY_CFG2);
1359 DUMPREG(DSI_DSIPHY_CFG5);
1360
1361 DUMPREG(DSI_PLL_CONTROL);
1362 DUMPREG(DSI_PLL_STATUS);
1363 DUMPREG(DSI_PLL_GO);
1364 DUMPREG(DSI_PLL_CONFIGURATION1);
1365 DUMPREG(DSI_PLL_CONFIGURATION2);
1366
1367 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1368#undef DUMPREG
1369}
1370
1371enum dsi_complexio_power_state {
1372 DSI_COMPLEXIO_POWER_OFF = 0x0,
1373 DSI_COMPLEXIO_POWER_ON = 0x1,
1374 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1375};
1376
1377static int dsi_complexio_power(enum dsi_complexio_power_state state)
1378{
1379 int t = 0;
1380
1381 /* PWR_CMD */
1382 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1383
1384 /* PWR_STATUS */
1385 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001386 if (++t > 1000) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001387 DSSERR("failed to set complexio power state to "
1388 "%d\n", state);
1389 return -ENODEV;
1390 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001391 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001392 }
1393
1394 return 0;
1395}
1396
1397static void dsi_complexio_config(struct omap_dss_device *dssdev)
1398{
1399 u32 r;
1400
1401 int clk_lane = dssdev->phy.dsi.clk_lane;
1402 int data1_lane = dssdev->phy.dsi.data1_lane;
1403 int data2_lane = dssdev->phy.dsi.data2_lane;
1404 int clk_pol = dssdev->phy.dsi.clk_pol;
1405 int data1_pol = dssdev->phy.dsi.data1_pol;
1406 int data2_pol = dssdev->phy.dsi.data2_pol;
1407
1408 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1409 r = FLD_MOD(r, clk_lane, 2, 0);
1410 r = FLD_MOD(r, clk_pol, 3, 3);
1411 r = FLD_MOD(r, data1_lane, 6, 4);
1412 r = FLD_MOD(r, data1_pol, 7, 7);
1413 r = FLD_MOD(r, data2_lane, 10, 8);
1414 r = FLD_MOD(r, data2_pol, 11, 11);
1415 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1416
1417 /* The configuration of the DSI complex I/O (number of data lanes,
1418 position, differential order) should not be changed while
1419 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1420 the hardware to take into account a new configuration of the complex
1421 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1422 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1423 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1424 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1425 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1426 DSI complex I/O configuration is unknown. */
1427
1428 /*
1429 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1430 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1431 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1432 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1433 */
1434}
1435
1436static inline unsigned ns2ddr(unsigned ns)
1437{
1438 /* convert time in ns to ddr ticks, rounding up */
1439 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1440 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1441}
1442
1443static inline unsigned ddr2ns(unsigned ddr)
1444{
1445 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1446 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1447}
1448
1449static void dsi_complexio_timings(void)
1450{
1451 u32 r;
1452 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1453 u32 tlpx_half, tclk_trail, tclk_zero;
1454 u32 tclk_prepare;
1455
1456 /* calculate timings */
1457
1458 /* 1 * DDR_CLK = 2 * UI */
1459
1460 /* min 40ns + 4*UI max 85ns + 6*UI */
1461 ths_prepare = ns2ddr(70) + 2;
1462
1463 /* min 145ns + 10*UI */
1464 ths_prepare_ths_zero = ns2ddr(175) + 2;
1465
1466 /* min max(8*UI, 60ns+4*UI) */
1467 ths_trail = ns2ddr(60) + 5;
1468
1469 /* min 100ns */
1470 ths_exit = ns2ddr(145);
1471
1472 /* tlpx min 50n */
1473 tlpx_half = ns2ddr(25);
1474
1475 /* min 60ns */
1476 tclk_trail = ns2ddr(60) + 2;
1477
1478 /* min 38ns, max 95ns */
1479 tclk_prepare = ns2ddr(65);
1480
1481 /* min tclk-prepare + tclk-zero = 300ns */
1482 tclk_zero = ns2ddr(260);
1483
1484 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1485 ths_prepare, ddr2ns(ths_prepare),
1486 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1487 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1488 ths_trail, ddr2ns(ths_trail),
1489 ths_exit, ddr2ns(ths_exit));
1490
1491 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1492 "tclk_zero %u (%uns)\n",
1493 tlpx_half, ddr2ns(tlpx_half),
1494 tclk_trail, ddr2ns(tclk_trail),
1495 tclk_zero, ddr2ns(tclk_zero));
1496 DSSDBG("tclk_prepare %u (%uns)\n",
1497 tclk_prepare, ddr2ns(tclk_prepare));
1498
1499 /* program timings */
1500
1501 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1502 r = FLD_MOD(r, ths_prepare, 31, 24);
1503 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1504 r = FLD_MOD(r, ths_trail, 15, 8);
1505 r = FLD_MOD(r, ths_exit, 7, 0);
1506 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1507
1508 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1509 r = FLD_MOD(r, tlpx_half, 22, 16);
1510 r = FLD_MOD(r, tclk_trail, 15, 8);
1511 r = FLD_MOD(r, tclk_zero, 7, 0);
1512 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1513
1514 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1515 r = FLD_MOD(r, tclk_prepare, 7, 0);
1516 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1517}
1518
1519
1520static int dsi_complexio_init(struct omap_dss_device *dssdev)
1521{
1522 int r = 0;
1523
1524 DSSDBG("dsi_complexio_init\n");
1525
1526 /* CIO_CLK_ICG, enable L3 clk to CIO */
1527 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1528
1529 /* A dummy read using the SCP interface to any DSIPHY register is
1530 * required after DSIPHY reset to complete the reset of the DSI complex
1531 * I/O. */
1532 dsi_read_reg(DSI_DSIPHY_CFG5);
1533
1534 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1535 DSSERR("ComplexIO PHY not coming out of reset.\n");
1536 r = -ENODEV;
1537 goto err;
1538 }
1539
1540 dsi_complexio_config(dssdev);
1541
1542 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1543
1544 if (r)
1545 goto err;
1546
1547 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1548 DSSERR("ComplexIO not coming out of reset.\n");
1549 r = -ENODEV;
1550 goto err;
1551 }
1552
1553 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1554 DSSERR("ComplexIO LDO power down.\n");
1555 r = -ENODEV;
1556 goto err;
1557 }
1558
1559 dsi_complexio_timings();
1560
1561 /*
1562 The configuration of the DSI complex I/O (number of data lanes,
1563 position, differential order) should not be changed while
1564 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1565 hardware to recognize a new configuration of the complex I/O (done
1566 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1567 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1568 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1569 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1570 bit to 1. If the sequence is not followed, the DSi complex I/O
1571 configuration is undetermined.
1572 */
1573 dsi_if_enable(1);
1574 dsi_if_enable(0);
1575 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1576 dsi_if_enable(1);
1577 dsi_if_enable(0);
1578
1579 DSSDBG("CIO init done\n");
1580err:
1581 return r;
1582}
1583
1584static void dsi_complexio_uninit(void)
1585{
1586 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1587}
1588
1589static int _dsi_wait_reset(void)
1590{
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001591 int t = 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001592
1593 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001594 if (++t > 5) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001595 DSSERR("soft reset failed\n");
1596 return -ENODEV;
1597 }
1598 udelay(1);
1599 }
1600
1601 return 0;
1602}
1603
1604static int _dsi_reset(void)
1605{
1606 /* Soft reset */
1607 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1608 return _dsi_wait_reset();
1609}
1610
1611static void dsi_reset_tx_fifo(int channel)
1612{
1613 u32 mask;
1614 u32 l;
1615
1616 /* set fifosize of the channel to 0, then return the old size */
1617 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1618
1619 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1620 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1621
1622 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1623}
1624
1625static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1626 enum fifo_size size3, enum fifo_size size4)
1627{
1628 u32 r = 0;
1629 int add = 0;
1630 int i;
1631
1632 dsi.vc[0].fifo_size = size1;
1633 dsi.vc[1].fifo_size = size2;
1634 dsi.vc[2].fifo_size = size3;
1635 dsi.vc[3].fifo_size = size4;
1636
1637 for (i = 0; i < 4; i++) {
1638 u8 v;
1639 int size = dsi.vc[i].fifo_size;
1640
1641 if (add + size > 4) {
1642 DSSERR("Illegal FIFO configuration\n");
1643 BUG();
1644 }
1645
1646 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1647 r |= v << (8 * i);
1648 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1649 add += size;
1650 }
1651
1652 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1653}
1654
1655static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1656 enum fifo_size size3, enum fifo_size size4)
1657{
1658 u32 r = 0;
1659 int add = 0;
1660 int i;
1661
1662 dsi.vc[0].fifo_size = size1;
1663 dsi.vc[1].fifo_size = size2;
1664 dsi.vc[2].fifo_size = size3;
1665 dsi.vc[3].fifo_size = size4;
1666
1667 for (i = 0; i < 4; i++) {
1668 u8 v;
1669 int size = dsi.vc[i].fifo_size;
1670
1671 if (add + size > 4) {
1672 DSSERR("Illegal FIFO configuration\n");
1673 BUG();
1674 }
1675
1676 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1677 r |= v << (8 * i);
1678 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1679 add += size;
1680 }
1681
1682 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1683}
1684
1685static int dsi_force_tx_stop_mode_io(void)
1686{
1687 u32 r;
1688
1689 r = dsi_read_reg(DSI_TIMING1);
1690 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1691 dsi_write_reg(DSI_TIMING1, r);
1692
1693 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1694 DSSERR("TX_STOP bit not going down\n");
1695 return -EIO;
1696 }
1697
1698 return 0;
1699}
1700
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001701static int dsi_vc_enable(int channel, bool enable)
1702{
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02001703 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1704 channel, enable);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001705
1706 enable = enable ? 1 : 0;
1707
1708 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1709
1710 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1711 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1712 return -EIO;
1713 }
1714
1715 return 0;
1716}
1717
1718static void dsi_vc_initial_config(int channel)
1719{
1720 u32 r;
1721
1722 DSSDBGF("%d", channel);
1723
1724 r = dsi_read_reg(DSI_VC_CTRL(channel));
1725
1726 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1727 DSSERR("VC(%d) busy when trying to configure it!\n",
1728 channel);
1729
1730 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1731 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1732 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1733 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1734 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1735 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1736 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1737
1738 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1739 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1740
1741 dsi_write_reg(DSI_VC_CTRL(channel), r);
1742
1743 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1744}
1745
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001746static int dsi_vc_config_l4(int channel)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001747{
1748 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001749 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001750
1751 DSSDBGF("%d", channel);
1752
1753 dsi_vc_enable(channel, 0);
1754
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001755 /* VC_BUSY */
1756 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001757 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001758 return -EIO;
1759 }
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001760
1761 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1762
1763 dsi_vc_enable(channel, 1);
1764
1765 dsi.vc[channel].mode = DSI_VC_MODE_L4;
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001766
1767 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001768}
1769
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001770static int dsi_vc_config_vp(int channel)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001771{
1772 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001773 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001774
1775 DSSDBGF("%d", channel);
1776
1777 dsi_vc_enable(channel, 0);
1778
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001779 /* VC_BUSY */
1780 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001781 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001782 return -EIO;
1783 }
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001784
1785 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1786
1787 dsi_vc_enable(channel, 1);
1788
1789 dsi.vc[channel].mode = DSI_VC_MODE_VP;
Tomi Valkeinen9ecd9682010-04-30 11:24:33 +03001790
1791 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001792}
1793
1794
Tomi Valkeinen61140c92010-01-12 16:00:30 +02001795void omapdss_dsi_vc_enable_hs(int channel, bool enable)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001796{
1797 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1798
Tomi Valkeinen61140c92010-01-12 16:00:30 +02001799 WARN_ON(!dsi_bus_is_locked());
1800
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001801 dsi_vc_enable(channel, 0);
1802 dsi_if_enable(0);
1803
1804 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1805
1806 dsi_vc_enable(channel, 1);
1807 dsi_if_enable(1);
1808
1809 dsi_force_tx_stop_mode_io();
1810}
Tomi Valkeinen61140c92010-01-12 16:00:30 +02001811EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001812
1813static void dsi_vc_flush_long_data(int channel)
1814{
1815 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1816 u32 val;
1817 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1818 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1819 (val >> 0) & 0xff,
1820 (val >> 8) & 0xff,
1821 (val >> 16) & 0xff,
1822 (val >> 24) & 0xff);
1823 }
1824}
1825
1826static void dsi_show_rx_ack_with_err(u16 err)
1827{
1828 DSSERR("\tACK with ERROR (%#x):\n", err);
1829 if (err & (1 << 0))
1830 DSSERR("\t\tSoT Error\n");
1831 if (err & (1 << 1))
1832 DSSERR("\t\tSoT Sync Error\n");
1833 if (err & (1 << 2))
1834 DSSERR("\t\tEoT Sync Error\n");
1835 if (err & (1 << 3))
1836 DSSERR("\t\tEscape Mode Entry Command Error\n");
1837 if (err & (1 << 4))
1838 DSSERR("\t\tLP Transmit Sync Error\n");
1839 if (err & (1 << 5))
1840 DSSERR("\t\tHS Receive Timeout Error\n");
1841 if (err & (1 << 6))
1842 DSSERR("\t\tFalse Control Error\n");
1843 if (err & (1 << 7))
1844 DSSERR("\t\t(reserved7)\n");
1845 if (err & (1 << 8))
1846 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1847 if (err & (1 << 9))
1848 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1849 if (err & (1 << 10))
1850 DSSERR("\t\tChecksum Error\n");
1851 if (err & (1 << 11))
1852 DSSERR("\t\tData type not recognized\n");
1853 if (err & (1 << 12))
1854 DSSERR("\t\tInvalid VC ID\n");
1855 if (err & (1 << 13))
1856 DSSERR("\t\tInvalid Transmission Length\n");
1857 if (err & (1 << 14))
1858 DSSERR("\t\t(reserved14)\n");
1859 if (err & (1 << 15))
1860 DSSERR("\t\tDSI Protocol Violation\n");
1861}
1862
1863static u16 dsi_vc_flush_receive_data(int channel)
1864{
1865 /* RX_FIFO_NOT_EMPTY */
1866 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1867 u32 val;
1868 u8 dt;
1869 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
Tomi Valkeinen86a78672010-03-16 16:19:06 +02001870 DSSERR("\trawval %#08x\n", val);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001871 dt = FLD_GET(val, 5, 0);
1872 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1873 u16 err = FLD_GET(val, 23, 8);
1874 dsi_show_rx_ack_with_err(err);
1875 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
Tomi Valkeinen86a78672010-03-16 16:19:06 +02001876 DSSERR("\tDCS short response, 1 byte: %#x\n",
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001877 FLD_GET(val, 23, 8));
1878 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
Tomi Valkeinen86a78672010-03-16 16:19:06 +02001879 DSSERR("\tDCS short response, 2 byte: %#x\n",
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001880 FLD_GET(val, 23, 8));
1881 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
Tomi Valkeinen86a78672010-03-16 16:19:06 +02001882 DSSERR("\tDCS long response, len %d\n",
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001883 FLD_GET(val, 23, 8));
1884 dsi_vc_flush_long_data(channel);
1885 } else {
1886 DSSERR("\tunknown datatype 0x%02x\n", dt);
1887 }
1888 }
1889 return 0;
1890}
1891
1892static int dsi_vc_send_bta(int channel)
1893{
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02001894 if (dsi.debug_write || dsi.debug_read)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001895 DSSDBG("dsi_vc_send_bta %d\n", channel);
1896
Tomi Valkeinen4f765022010-01-18 16:27:52 +02001897 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001898
1899 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1900 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1901 dsi_vc_flush_receive_data(channel);
1902 }
1903
1904 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1905
1906 return 0;
1907}
1908
1909int dsi_vc_send_bta_sync(int channel)
1910{
1911 int r = 0;
1912 u32 err;
1913
1914 INIT_COMPLETION(dsi.bta_completion);
1915
1916 dsi_vc_enable_bta_irq(channel);
1917
1918 r = dsi_vc_send_bta(channel);
1919 if (r)
1920 goto err;
1921
1922 if (wait_for_completion_timeout(&dsi.bta_completion,
1923 msecs_to_jiffies(500)) == 0) {
1924 DSSERR("Failed to receive BTA\n");
1925 r = -EIO;
1926 goto err;
1927 }
1928
1929 err = dsi_get_errors();
1930 if (err) {
1931 DSSERR("Error while sending BTA: %x\n", err);
1932 r = -EIO;
1933 goto err;
1934 }
1935err:
1936 dsi_vc_disable_bta_irq(channel);
1937
1938 return r;
1939}
1940EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1941
1942static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1943 u16 len, u8 ecc)
1944{
1945 u32 val;
1946 u8 data_id;
1947
Tomi Valkeinen4f765022010-01-18 16:27:52 +02001948 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001949
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02001950 data_id = data_type | channel << 6;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001951
1952 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1953 FLD_VAL(ecc, 31, 24);
1954
1955 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1956}
1957
1958static inline void dsi_vc_write_long_payload(int channel,
1959 u8 b1, u8 b2, u8 b3, u8 b4)
1960{
1961 u32 val;
1962
1963 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1964
1965/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1966 b1, b2, b3, b4, val); */
1967
1968 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1969}
1970
1971static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1972 u8 ecc)
1973{
1974 /*u32 val; */
1975 int i;
1976 u8 *p;
1977 int r = 0;
1978 u8 b1, b2, b3, b4;
1979
1980 if (dsi.debug_write)
1981 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1982
1983 /* len + header */
1984 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1985 DSSERR("unable to send long packet: packet too long.\n");
1986 return -EINVAL;
1987 }
1988
1989 dsi_vc_config_l4(channel);
1990
1991 dsi_vc_write_long_header(channel, data_type, len, ecc);
1992
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001993 p = data;
1994 for (i = 0; i < len >> 2; i++) {
1995 if (dsi.debug_write)
1996 DSSDBG("\tsending full packet %d\n", i);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001997
1998 b1 = *p++;
1999 b2 = *p++;
2000 b3 = *p++;
2001 b4 = *p++;
2002
2003 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2004 }
2005
2006 i = len % 4;
2007 if (i) {
2008 b1 = 0; b2 = 0; b3 = 0;
2009
2010 if (dsi.debug_write)
2011 DSSDBG("\tsending remainder bytes %d\n", i);
2012
2013 switch (i) {
2014 case 3:
2015 b1 = *p++;
2016 b2 = *p++;
2017 b3 = *p++;
2018 break;
2019 case 2:
2020 b1 = *p++;
2021 b2 = *p++;
2022 break;
2023 case 1:
2024 b1 = *p++;
2025 break;
2026 }
2027
2028 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2029 }
2030
2031 return r;
2032}
2033
2034static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2035{
2036 u32 r;
2037 u8 data_id;
2038
Tomi Valkeinen4f765022010-01-18 16:27:52 +02002039 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002040
2041 if (dsi.debug_write)
2042 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2043 channel,
2044 data_type, data & 0xff, (data >> 8) & 0xff);
2045
2046 dsi_vc_config_l4(channel);
2047
2048 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2049 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2050 return -EINVAL;
2051 }
2052
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002053 data_id = data_type | channel << 6;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002054
2055 r = (data_id << 0) | (data << 8) | (ecc << 24);
2056
2057 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2058
2059 return 0;
2060}
2061
2062int dsi_vc_send_null(int channel)
2063{
2064 u8 nullpkg[] = {0, 0, 0, 0};
Tomi Valkeinen397bb3c2009-12-03 13:37:31 +02002065 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002066}
2067EXPORT_SYMBOL(dsi_vc_send_null);
2068
2069int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2070{
2071 int r;
2072
2073 BUG_ON(len == 0);
2074
2075 if (len == 1) {
2076 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2077 data[0], 0);
2078 } else if (len == 2) {
2079 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2080 data[0] | (data[1] << 8), 0);
2081 } else {
2082 /* 0x39 = DCS Long Write */
2083 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2084 data, len, 0);
2085 }
2086
2087 return r;
2088}
2089EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2090
2091int dsi_vc_dcs_write(int channel, u8 *data, int len)
2092{
2093 int r;
2094
2095 r = dsi_vc_dcs_write_nosync(channel, data, len);
2096 if (r)
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002097 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002098
2099 r = dsi_vc_send_bta_sync(channel);
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002100 if (r)
2101 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002102
Tomi Valkeinenb63ac1e2010-04-09 13:20:57 +03002103 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2104 DSSERR("rx fifo not empty after write, dumping data:\n");
2105 dsi_vc_flush_receive_data(channel);
2106 r = -EIO;
2107 goto err;
2108 }
2109
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002110 return 0;
2111err:
2112 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2113 channel, data[0], len);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002114 return r;
2115}
2116EXPORT_SYMBOL(dsi_vc_dcs_write);
2117
Tomi Valkeinen828c48f2009-12-16 14:53:15 +02002118int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2119{
2120 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2121}
2122EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2123
2124int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2125{
2126 u8 buf[2];
2127 buf[0] = dcs_cmd;
2128 buf[1] = param;
2129 return dsi_vc_dcs_write(channel, buf, 2);
2130}
2131EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2132
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002133int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2134{
2135 u32 val;
2136 u8 dt;
2137 int r;
2138
2139 if (dsi.debug_read)
Tomi Valkeinenff90a342009-12-03 13:38:04 +02002140 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002141
2142 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2143 if (r)
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002144 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002145
2146 r = dsi_vc_send_bta_sync(channel);
2147 if (r)
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002148 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002149
2150 /* RX_FIFO_NOT_EMPTY */
2151 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2152 DSSERR("RX fifo empty when trying to read.\n");
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002153 r = -EIO;
2154 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002155 }
2156
2157 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2158 if (dsi.debug_read)
2159 DSSDBG("\theader: %08x\n", val);
2160 dt = FLD_GET(val, 5, 0);
2161 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2162 u16 err = FLD_GET(val, 23, 8);
2163 dsi_show_rx_ack_with_err(err);
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002164 r = -EIO;
2165 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002166
2167 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2168 u8 data = FLD_GET(val, 15, 8);
2169 if (dsi.debug_read)
2170 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2171
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002172 if (buflen < 1) {
2173 r = -EIO;
2174 goto err;
2175 }
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002176
2177 buf[0] = data;
2178
2179 return 1;
2180 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2181 u16 data = FLD_GET(val, 23, 8);
2182 if (dsi.debug_read)
2183 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2184
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002185 if (buflen < 2) {
2186 r = -EIO;
2187 goto err;
2188 }
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002189
2190 buf[0] = data & 0xff;
2191 buf[1] = (data >> 8) & 0xff;
2192
2193 return 2;
2194 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2195 int w;
2196 int len = FLD_GET(val, 23, 8);
2197 if (dsi.debug_read)
2198 DSSDBG("\tDCS long response, len %d\n", len);
2199
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002200 if (len > buflen) {
2201 r = -EIO;
2202 goto err;
2203 }
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002204
2205 /* two byte checksum ends the packet, not included in len */
2206 for (w = 0; w < len + 2;) {
2207 int b;
2208 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2209 if (dsi.debug_read)
2210 DSSDBG("\t\t%02x %02x %02x %02x\n",
2211 (val >> 0) & 0xff,
2212 (val >> 8) & 0xff,
2213 (val >> 16) & 0xff,
2214 (val >> 24) & 0xff);
2215
2216 for (b = 0; b < 4; ++b) {
2217 if (w < len)
2218 buf[w] = (val >> (b * 8)) & 0xff;
2219 /* we discard the 2 byte checksum */
2220 ++w;
2221 }
2222 }
2223
2224 return len;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002225 } else {
2226 DSSERR("\tunknown datatype 0x%02x\n", dt);
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002227 r = -EIO;
2228 goto err;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002229 }
Tomi Valkeinen5d68e032010-02-26 11:32:56 +02002230
2231 BUG();
2232err:
2233 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2234 channel, dcs_cmd);
2235 return r;
2236
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002237}
2238EXPORT_SYMBOL(dsi_vc_dcs_read);
2239
Tomi Valkeinen828c48f2009-12-16 14:53:15 +02002240int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2241{
2242 int r;
2243
2244 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2245
2246 if (r < 0)
2247 return r;
2248
2249 if (r != 1)
2250 return -EIO;
2251
2252 return 0;
2253}
2254EXPORT_SYMBOL(dsi_vc_dcs_read_1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002255
Tomi Valkeinen0c244f72010-06-09 15:19:29 +03002256int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
Tomi Valkeinen53055aa2010-02-25 11:38:13 +02002257{
Tomi Valkeinen0c244f72010-06-09 15:19:29 +03002258 u8 buf[2];
Tomi Valkeinen53055aa2010-02-25 11:38:13 +02002259 int r;
2260
Tomi Valkeinen0c244f72010-06-09 15:19:29 +03002261 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
Tomi Valkeinen53055aa2010-02-25 11:38:13 +02002262
2263 if (r < 0)
2264 return r;
2265
2266 if (r != 2)
2267 return -EIO;
2268
Tomi Valkeinen0c244f72010-06-09 15:19:29 +03002269 *data1 = buf[0];
2270 *data2 = buf[1];
2271
Tomi Valkeinen53055aa2010-02-25 11:38:13 +02002272 return 0;
2273}
2274EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2275
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002276int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2277{
2278 int r;
2279 r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2280 len, 0);
2281
2282 if (r)
2283 return r;
2284
2285 r = dsi_vc_send_bta_sync(channel);
2286
2287 return r;
2288}
2289EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2290
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002291static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002292{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002293 unsigned long fck;
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002294 unsigned long total_ticks;
2295 u32 r;
2296
2297 BUG_ON(ticks > 0x1fff);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002298
2299 /* ticks in DSI_FCK */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002300 fck = dsi_fclk_rate();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002301
2302 r = dsi_read_reg(DSI_TIMING2);
2303 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002304 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2305 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002306 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2307 dsi_write_reg(DSI_TIMING2, r);
2308
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002309 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2310
2311 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2312 total_ticks,
2313 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2314 (total_ticks * 1000) / (fck / 1000 / 1000));
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002315}
2316
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002317static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002318{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002319 unsigned long fck;
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002320 unsigned long total_ticks;
2321 u32 r;
2322
2323 BUG_ON(ticks > 0x1fff);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002324
2325 /* ticks in DSI_FCK */
2326 fck = dsi_fclk_rate();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002327
2328 r = dsi_read_reg(DSI_TIMING1);
2329 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002330 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2331 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002332 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2333 dsi_write_reg(DSI_TIMING1, r);
2334
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002335 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2336
2337 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2338 total_ticks,
2339 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2340 (total_ticks * 1000) / (fck / 1000 / 1000));
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002341}
2342
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002343static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002344{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002345 unsigned long fck;
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002346 unsigned long total_ticks;
2347 u32 r;
2348
2349 BUG_ON(ticks > 0x1fff);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002350
2351 /* ticks in DSI_FCK */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002352 fck = dsi_fclk_rate();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002353
2354 r = dsi_read_reg(DSI_TIMING1);
2355 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002356 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2357 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002358 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2359 dsi_write_reg(DSI_TIMING1, r);
2360
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002361 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2362
2363 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2364 total_ticks,
2365 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2366 (total_ticks * 1000) / (fck / 1000 / 1000));
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002367}
2368
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002369static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002370{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002371 unsigned long fck;
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002372 unsigned long total_ticks;
2373 u32 r;
2374
2375 BUG_ON(ticks > 0x1fff);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002376
2377 /* ticks in TxByteClkHS */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002378 fck = dsi_get_txbyteclkhs();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002379
2380 r = dsi_read_reg(DSI_TIMING2);
2381 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002382 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2383 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002384 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2385 dsi_write_reg(DSI_TIMING2, r);
2386
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002387 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2388
2389 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2390 total_ticks,
2391 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2392 (total_ticks * 1000) / (fck / 1000 / 1000));
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002393}
2394static int dsi_proto_config(struct omap_dss_device *dssdev)
2395{
2396 u32 r;
2397 int buswidth = 0;
2398
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002399 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2400 DSI_FIFO_SIZE_32,
2401 DSI_FIFO_SIZE_32,
2402 DSI_FIFO_SIZE_32);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002403
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002404 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2405 DSI_FIFO_SIZE_32,
2406 DSI_FIFO_SIZE_32,
2407 DSI_FIFO_SIZE_32);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002408
2409 /* XXX what values for the timeouts? */
Tomi Valkeinen4ffa3572010-04-12 10:40:12 +03002410 dsi_set_stop_state_counter(0x1000, false, false);
2411 dsi_set_ta_timeout(0x1fff, true, true);
2412 dsi_set_lp_rx_timeout(0x1fff, true, true);
2413 dsi_set_hs_tx_timeout(0x1fff, true, true);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002414
2415 switch (dssdev->ctrl.pixel_size) {
2416 case 16:
2417 buswidth = 0;
2418 break;
2419 case 18:
2420 buswidth = 1;
2421 break;
2422 case 24:
2423 buswidth = 2;
2424 break;
2425 default:
2426 BUG();
2427 }
2428
2429 r = dsi_read_reg(DSI_CTRL);
2430 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2431 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2432 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2433 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2434 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2435 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2436 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2437 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2438 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2439 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2440 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2441
2442 dsi_write_reg(DSI_CTRL, r);
2443
2444 dsi_vc_initial_config(0);
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002445 dsi_vc_initial_config(1);
2446 dsi_vc_initial_config(2);
2447 dsi_vc_initial_config(3);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002448
2449 return 0;
2450}
2451
2452static void dsi_proto_timings(struct omap_dss_device *dssdev)
2453{
2454 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2455 unsigned tclk_pre, tclk_post;
2456 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2457 unsigned ths_trail, ths_exit;
2458 unsigned ddr_clk_pre, ddr_clk_post;
2459 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2460 unsigned ths_eot;
2461 u32 r;
2462
2463 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2464 ths_prepare = FLD_GET(r, 31, 24);
2465 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2466 ths_zero = ths_prepare_ths_zero - ths_prepare;
2467 ths_trail = FLD_GET(r, 15, 8);
2468 ths_exit = FLD_GET(r, 7, 0);
2469
2470 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2471 tlpx = FLD_GET(r, 22, 16) * 2;
2472 tclk_trail = FLD_GET(r, 15, 8);
2473 tclk_zero = FLD_GET(r, 7, 0);
2474
2475 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2476 tclk_prepare = FLD_GET(r, 7, 0);
2477
2478 /* min 8*UI */
2479 tclk_pre = 20;
2480 /* min 60ns + 52*UI */
2481 tclk_post = ns2ddr(60) + 26;
2482
2483 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2484 if (dssdev->phy.dsi.data1_lane != 0 &&
2485 dssdev->phy.dsi.data2_lane != 0)
2486 ths_eot = 2;
2487 else
2488 ths_eot = 4;
2489
2490 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2491 4);
2492 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2493
2494 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2495 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2496
2497 r = dsi_read_reg(DSI_CLK_TIMING);
2498 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2499 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2500 dsi_write_reg(DSI_CLK_TIMING, r);
2501
2502 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2503 ddr_clk_pre,
2504 ddr_clk_post);
2505
2506 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2507 DIV_ROUND_UP(ths_prepare, 4) +
2508 DIV_ROUND_UP(ths_zero + 3, 4);
2509
2510 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2511
2512 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2513 FLD_VAL(exit_hs_mode_lat, 15, 0);
2514 dsi_write_reg(DSI_VM_TIMING7, r);
2515
2516 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2517 enter_hs_mode_lat, exit_hs_mode_lat);
2518}
2519
2520
2521#define DSI_DECL_VARS \
2522 int __dsi_cb = 0; u32 __dsi_cv = 0;
2523
2524#define DSI_FLUSH(ch) \
2525 if (__dsi_cb > 0) { \
2526 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2527 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2528 __dsi_cb = __dsi_cv = 0; \
2529 }
2530
2531#define DSI_PUSH(ch, data) \
2532 do { \
2533 __dsi_cv |= (data) << (__dsi_cb * 8); \
2534 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2535 if (++__dsi_cb > 3) \
2536 DSI_FLUSH(ch); \
2537 } while (0)
2538
2539static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2540 int x, int y, int w, int h)
2541{
2542 /* Note: supports only 24bit colors in 32bit container */
2543 int first = 1;
2544 int fifo_stalls = 0;
2545 int max_dsi_packet_size;
2546 int max_data_per_packet;
2547 int max_pixels_per_packet;
2548 int pixels_left;
2549 int bytespp = dssdev->ctrl.pixel_size / 8;
2550 int scr_width;
2551 u32 __iomem *data;
2552 int start_offset;
2553 int horiz_inc;
2554 int current_x;
2555 struct omap_overlay *ovl;
2556
2557 debug_irq = 0;
2558
2559 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2560 x, y, w, h);
2561
2562 ovl = dssdev->manager->overlays[0];
2563
2564 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2565 return -EINVAL;
2566
2567 if (dssdev->ctrl.pixel_size != 24)
2568 return -EINVAL;
2569
2570 scr_width = ovl->info.screen_width;
2571 data = ovl->info.vaddr;
2572
2573 start_offset = scr_width * y + x;
2574 horiz_inc = scr_width - w;
2575 current_x = x;
2576
2577 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2578 * in fifo */
2579
2580 /* When using CPU, max long packet size is TX buffer size */
2581 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2582
2583 /* we seem to get better perf if we divide the tx fifo to half,
2584 and while the other half is being sent, we fill the other half
2585 max_dsi_packet_size /= 2; */
2586
2587 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2588
2589 max_pixels_per_packet = max_data_per_packet / bytespp;
2590
2591 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2592
2593 pixels_left = w * h;
2594
2595 DSSDBG("total pixels %d\n", pixels_left);
2596
2597 data += start_offset;
2598
2599 while (pixels_left > 0) {
2600 /* 0x2c = write_memory_start */
2601 /* 0x3c = write_memory_continue */
2602 u8 dcs_cmd = first ? 0x2c : 0x3c;
2603 int pixels;
2604 DSI_DECL_VARS;
2605 first = 0;
2606
2607#if 1
2608 /* using fifo not empty */
2609 /* TX_FIFO_NOT_EMPTY */
2610 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002611 fifo_stalls++;
2612 if (fifo_stalls > 0xfffff) {
2613 DSSERR("fifo stalls overflow, pixels left %d\n",
2614 pixels_left);
2615 dsi_if_enable(0);
2616 return -EIO;
2617 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02002618 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002619 }
2620#elif 1
2621 /* using fifo emptiness */
2622 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2623 max_dsi_packet_size) {
2624 fifo_stalls++;
2625 if (fifo_stalls > 0xfffff) {
2626 DSSERR("fifo stalls overflow, pixels left %d\n",
2627 pixels_left);
2628 dsi_if_enable(0);
2629 return -EIO;
2630 }
2631 }
2632#else
2633 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2634 fifo_stalls++;
2635 if (fifo_stalls > 0xfffff) {
2636 DSSERR("fifo stalls overflow, pixels left %d\n",
2637 pixels_left);
2638 dsi_if_enable(0);
2639 return -EIO;
2640 }
2641 }
2642#endif
2643 pixels = min(max_pixels_per_packet, pixels_left);
2644
2645 pixels_left -= pixels;
2646
2647 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2648 1 + pixels * bytespp, 0);
2649
2650 DSI_PUSH(0, dcs_cmd);
2651
2652 while (pixels-- > 0) {
2653 u32 pix = __raw_readl(data++);
2654
2655 DSI_PUSH(0, (pix >> 16) & 0xff);
2656 DSI_PUSH(0, (pix >> 8) & 0xff);
2657 DSI_PUSH(0, (pix >> 0) & 0xff);
2658
2659 current_x++;
2660 if (current_x == x+w) {
2661 current_x = x;
2662 data += horiz_inc;
2663 }
2664 }
2665
2666 DSI_FLUSH(0);
2667 }
2668
2669 return 0;
2670}
2671
2672static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2673 u16 x, u16 y, u16 w, u16 h)
2674{
2675 unsigned bytespp;
2676 unsigned bytespl;
2677 unsigned bytespf;
2678 unsigned total_len;
2679 unsigned packet_payload;
2680 unsigned packet_len;
2681 u32 l;
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03002682 int r;
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002683 const unsigned channel = dsi.update_channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002684 /* line buffer is 1024 x 24bits */
2685 /* XXX: for some reason using full buffer size causes considerable TX
2686 * slowdown with update sizes that fill the whole buffer */
2687 const unsigned line_buf_size = 1023 * 3;
2688
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02002689 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2690 x, y, w, h);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002691
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002692 dsi_vc_config_vp(channel);
2693
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002694 bytespp = dssdev->ctrl.pixel_size / 8;
2695 bytespl = w * bytespp;
2696 bytespf = bytespl * h;
2697
2698 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2699 * number of lines in a packet. See errata about VP_CLK_RATIO */
2700
2701 if (bytespf < line_buf_size)
2702 packet_payload = bytespf;
2703 else
2704 packet_payload = (line_buf_size) / bytespl * bytespl;
2705
2706 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2707 total_len = (bytespf / packet_payload) * packet_len;
2708
2709 if (bytespf % packet_payload)
2710 total_len += (bytespf % packet_payload) + 1;
2711
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002712 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2713 dsi_write_reg(DSI_VC_TE(channel), l);
2714
2715 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2716
Tomi Valkeinen942a91a2010-02-10 17:27:39 +02002717 if (dsi.te_enabled)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002718 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2719 else
2720 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2721 dsi_write_reg(DSI_VC_TE(channel), l);
2722
2723 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2724 * because DSS interrupts are not capable of waking up the CPU and the
2725 * framedone interrupt could be delayed for quite a long time. I think
2726 * the same goes for any DSS interrupts, but for some reason I have not
2727 * seen the problem anywhere else than here.
2728 */
2729 dispc_disable_sidle();
2730
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002731 dsi_perf_mark_start();
2732
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03002733 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002734 msecs_to_jiffies(250));
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03002735 BUG_ON(r == 0);
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002736
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002737 dss_start_update(dssdev);
2738
Tomi Valkeinen942a91a2010-02-10 17:27:39 +02002739 if (dsi.te_enabled) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002740 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2741 * for TE is longer than the timer allows */
2742 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2743
2744 dsi_vc_send_bta(channel);
2745
2746#ifdef DSI_CATCH_MISSING_TE
2747 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2748#endif
2749 }
2750}
2751
2752#ifdef DSI_CATCH_MISSING_TE
2753static void dsi_te_timeout(unsigned long arg)
2754{
2755 DSSERR("TE not received for 250ms!\n");
2756}
2757#endif
2758
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002759static void dsi_framedone_timeout_work_callback(struct work_struct *work)
2760{
2761 int r;
2762 const int channel = dsi.update_channel;
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002763
2764 DSSERR("Framedone not received for 250ms!\n");
2765
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03002766 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
2767 * 250ms which would conflict with this timeout work. What should be
2768 * done is first cancel the transfer on the HW, and then cancel the
2769 * possibly scheduled framedone work */
2770
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002771 /* SIDLEMODE back to smart-idle */
2772 dispc_enable_sidle();
2773
Tomi Valkeinen942a91a2010-02-10 17:27:39 +02002774 if (dsi.te_enabled) {
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002775 /* enable LP_RX_TO again after the TE */
2776 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2777 }
2778
2779 /* Send BTA after the frame. We need this for the TE to work, as TE
2780 * trigger is only sent for BTAs without preceding packet. Thus we need
2781 * to BTA after the pixel packets so that next BTA will cause TE
2782 * trigger.
2783 *
2784 * This is not needed when TE is not in use, but we do it anyway to
2785 * make sure that the transfer has been completed. It would be more
2786 * optimal, but more complex, to wait only just before starting next
2787 * transfer. */
2788 r = dsi_vc_send_bta_sync(channel);
2789 if (r)
2790 DSSERR("BTA after framedone failed\n");
2791
2792 /* RX_FIFO_NOT_EMPTY */
2793 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2794 DSSERR("Received error during frame transfer:\n");
2795 dsi_vc_flush_receive_data(channel);
2796 }
2797
2798 dsi.framedone_callback(-ETIMEDOUT, dsi.framedone_data);
2799}
2800
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002801static void dsi_framedone_irq_callback(void *data, u32 mask)
2802{
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03002803 int r;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002804 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2805 * turns itself off. However, DSI still has the pixels in its buffers,
2806 * and is sending the data.
2807 */
2808
2809 /* SIDLEMODE back to smart-idle */
2810 dispc_enable_sidle();
2811
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03002812 r = queue_work(dsi.workqueue, &dsi.framedone_work);
2813 BUG_ON(r == 0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002814}
2815
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002816static void dsi_handle_framedone(void)
2817{
2818 int r;
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002819 const int channel = dsi.update_channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002820
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02002821 DSSDBG("FRAMEDONE\n");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002822
Tomi Valkeinen942a91a2010-02-10 17:27:39 +02002823 if (dsi.te_enabled) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002824 /* enable LP_RX_TO again after the TE */
2825 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2826 }
2827
2828 /* Send BTA after the frame. We need this for the TE to work, as TE
2829 * trigger is only sent for BTAs without preceding packet. Thus we need
2830 * to BTA after the pixel packets so that next BTA will cause TE
2831 * trigger.
2832 *
2833 * This is not needed when TE is not in use, but we do it anyway to
2834 * make sure that the transfer has been completed. It would be more
2835 * optimal, but more complex, to wait only just before starting next
2836 * transfer. */
2837 r = dsi_vc_send_bta_sync(channel);
2838 if (r)
2839 DSSERR("BTA after framedone failed\n");
2840
2841 /* RX_FIFO_NOT_EMPTY */
2842 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2843 DSSERR("Received error during frame transfer:\n");
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002844 dsi_vc_flush_receive_data(channel);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002845 }
2846
2847#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2848 dispc_fake_vsync_irq();
2849#endif
2850}
2851
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002852static void dsi_framedone_work_callback(struct work_struct *work)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002853{
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002854 DSSDBGF();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002855
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002856 cancel_delayed_work_sync(&dsi.framedone_timeout_work);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002857
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002858 dsi_handle_framedone();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002859
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002860 dsi_perf_show("DISPC");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002861
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002862 dsi.framedone_callback(0, dsi.framedone_data);
2863}
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002864
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002865int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
2866 u16 *x, u16 *y, u16 *w, u16 *h)
2867{
2868 u16 dw, dh;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002869
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002870 dssdev->driver->get_resolution(dssdev, &dw, &dh);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002871
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002872 if (*x > dw || *y > dh)
2873 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002874
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002875 if (*x + *w > dw)
2876 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002877
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002878 if (*y + *h > dh)
2879 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002880
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002881 if (*w == 1)
2882 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002883
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002884 if (*w == 0 || *h == 0)
2885 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002886
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002887 dsi_perf_mark_setup();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002888
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002889 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2890 dss_setup_partial_planes(dssdev, x, y, w, h);
2891 dispc_set_lcd_size(*w, *h);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002892 }
2893
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002894 return 0;
2895}
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002896EXPORT_SYMBOL(omap_dsi_prepare_update);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002897
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002898int omap_dsi_update(struct omap_dss_device *dssdev,
2899 int channel,
2900 u16 x, u16 y, u16 w, u16 h,
2901 void (*callback)(int, void *), void *data)
2902{
2903 dsi.update_channel = channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002904
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002905 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2906 dsi.framedone_callback = callback;
2907 dsi.framedone_data = data;
2908
2909 dsi.update_region.x = x;
2910 dsi.update_region.y = y;
2911 dsi.update_region.w = w;
2912 dsi.update_region.h = h;
2913 dsi.update_region.device = dssdev;
2914
2915 dsi_update_screen_dispc(dssdev, x, y, w, h);
2916 } else {
2917 dsi_update_screen_l4(dssdev, x, y, w, h);
2918 dsi_perf_show("L4");
2919 callback(0, data);
2920 }
2921
2922 return 0;
2923}
2924EXPORT_SYMBOL(omap_dsi_update);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002925
2926/* Display funcs */
2927
2928static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2929{
2930 int r;
2931
2932 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2933 DISPC_IRQ_FRAMEDONE);
2934 if (r) {
2935 DSSERR("can't get FRAMEDONE irq\n");
2936 return r;
2937 }
2938
2939 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
2940
2941 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
2942 dispc_enable_fifohandcheck(1);
2943
2944 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
2945
2946 {
2947 struct omap_video_timings timings = {
2948 .hsw = 1,
2949 .hfp = 1,
2950 .hbp = 1,
2951 .vsw = 1,
2952 .vfp = 0,
2953 .vbp = 0,
2954 };
2955
2956 dispc_set_lcd_timings(&timings);
2957 }
2958
2959 return 0;
2960}
2961
2962static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
2963{
2964 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
2965 DISPC_IRQ_FRAMEDONE);
2966}
2967
2968static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2969{
2970 struct dsi_clock_info cinfo;
2971 int r;
2972
2973 /* we always use DSS2_FCK as input clock */
2974 cinfo.use_dss2_fck = true;
2975 cinfo.regn = dssdev->phy.dsi.div.regn;
2976 cinfo.regm = dssdev->phy.dsi.div.regm;
2977 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2978 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
2979 r = dsi_calc_clock_rates(&cinfo);
Ville Syrjäläebf0a3f2010-04-22 22:50:05 +02002980 if (r) {
2981 DSSERR("Failed to calc dsi clocks\n");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002982 return r;
Ville Syrjäläebf0a3f2010-04-22 22:50:05 +02002983 }
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002984
2985 r = dsi_pll_set_clock_div(&cinfo);
2986 if (r) {
2987 DSSERR("Failed to set dsi clocks\n");
2988 return r;
2989 }
2990
2991 return 0;
2992}
2993
2994static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
2995{
2996 struct dispc_clock_info dispc_cinfo;
2997 int r;
2998 unsigned long long fck;
2999
3000 fck = dsi_get_dsi1_pll_rate();
3001
3002 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3003 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3004
3005 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3006 if (r) {
3007 DSSERR("Failed to calc dispc clocks\n");
3008 return r;
3009 }
3010
3011 r = dispc_set_clock_div(&dispc_cinfo);
3012 if (r) {
3013 DSSERR("Failed to set dispc clocks\n");
3014 return r;
3015 }
3016
3017 return 0;
3018}
3019
3020static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3021{
3022 int r;
3023
3024 _dsi_print_reset_status();
3025
3026 r = dsi_pll_init(dssdev, true, true);
3027 if (r)
3028 goto err0;
3029
3030 r = dsi_configure_dsi_clocks(dssdev);
3031 if (r)
3032 goto err1;
3033
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003034 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3035 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003036
3037 DSSDBG("PLL OK\n");
3038
3039 r = dsi_configure_dispc_clocks(dssdev);
3040 if (r)
3041 goto err2;
3042
3043 r = dsi_complexio_init(dssdev);
3044 if (r)
3045 goto err2;
3046
3047 _dsi_print_reset_status();
3048
3049 dsi_proto_timings(dssdev);
3050 dsi_set_lp_clk_divisor(dssdev);
3051
3052 if (1)
3053 _dsi_print_reset_status();
3054
3055 r = dsi_proto_config(dssdev);
3056 if (r)
3057 goto err3;
3058
3059 /* enable interface */
3060 dsi_vc_enable(0, 1);
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02003061 dsi_vc_enable(1, 1);
3062 dsi_vc_enable(2, 1);
3063 dsi_vc_enable(3, 1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003064 dsi_if_enable(1);
3065 dsi_force_tx_stop_mode_io();
3066
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003067 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003068err3:
3069 dsi_complexio_uninit();
3070err2:
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003071 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3072 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003073err1:
3074 dsi_pll_uninit();
3075err0:
3076 return r;
3077}
3078
3079static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3080{
Ville Syrjäläd7370102010-04-22 22:50:09 +02003081 /* disable interface */
3082 dsi_if_enable(0);
3083 dsi_vc_enable(0, 0);
3084 dsi_vc_enable(1, 0);
3085 dsi_vc_enable(2, 0);
3086 dsi_vc_enable(3, 0);
3087
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003088 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3089 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003090 dsi_complexio_uninit();
3091 dsi_pll_uninit();
3092}
3093
3094static int dsi_core_init(void)
3095{
3096 /* Autoidle */
3097 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3098
3099 /* ENWAKEUP */
3100 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3101
3102 /* SIDLEMODE smart-idle */
3103 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3104
3105 _dsi_initialize_irq();
3106
3107 return 0;
3108}
3109
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003110int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003111{
3112 int r = 0;
3113
3114 DSSDBG("dsi_display_enable\n");
3115
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003116 WARN_ON(!dsi_bus_is_locked());
3117
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003118 mutex_lock(&dsi.lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003119
3120 r = omap_dss_start_device(dssdev);
3121 if (r) {
3122 DSSERR("failed to start device\n");
3123 goto err0;
3124 }
3125
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003126 enable_clocks(1);
3127 dsi_enable_pll_clock(1);
3128
3129 r = _dsi_reset();
3130 if (r)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003131 goto err1;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003132
3133 dsi_core_init();
3134
3135 r = dsi_display_init_dispc(dssdev);
3136 if (r)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003137 goto err1;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003138
3139 r = dsi_display_init_dsi(dssdev);
3140 if (r)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003141 goto err2;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003142
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003143 mutex_unlock(&dsi.lock);
3144
3145 return 0;
3146
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003147err2:
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003148 dsi_display_uninit_dispc(dssdev);
3149err1:
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003150 enable_clocks(0);
3151 dsi_enable_pll_clock(0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003152 omap_dss_stop_device(dssdev);
3153err0:
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003154 mutex_unlock(&dsi.lock);
3155 DSSDBG("dsi_display_enable FAILED\n");
3156 return r;
3157}
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003158EXPORT_SYMBOL(omapdss_dsi_display_enable);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003159
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003160void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003161{
3162 DSSDBG("dsi_display_disable\n");
3163
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003164 WARN_ON(!dsi_bus_is_locked());
3165
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003166 mutex_lock(&dsi.lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003167
3168 dsi_display_uninit_dispc(dssdev);
3169
3170 dsi_display_uninit_dsi(dssdev);
3171
3172 enable_clocks(0);
3173 dsi_enable_pll_clock(0);
3174
3175 omap_dss_stop_device(dssdev);
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003176
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003177 mutex_unlock(&dsi.lock);
3178}
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003179EXPORT_SYMBOL(omapdss_dsi_display_disable);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003180
Tomi Valkeinen225b6502010-01-11 15:11:01 +02003181int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003182{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003183 dsi.te_enabled = enable;
Tomi Valkeinen225b6502010-01-11 15:11:01 +02003184 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003185}
Tomi Valkeinen225b6502010-01-11 15:11:01 +02003186EXPORT_SYMBOL(omapdss_dsi_enable_te);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003187
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003188void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3189 u32 fifo_size, enum omap_burst_size *burst_size,
3190 u32 *fifo_low, u32 *fifo_high)
3191{
3192 unsigned burst_size_bytes;
3193
3194 *burst_size = OMAP_DSS_BURST_16x32;
3195 burst_size_bytes = 16 * 32 / 8;
3196
3197 *fifo_high = fifo_size - burst_size_bytes;
3198 *fifo_low = fifo_size - burst_size_bytes * 8;
3199}
3200
3201int dsi_init_display(struct omap_dss_device *dssdev)
3202{
3203 DSSDBG("DSI init\n");
3204
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003205 /* XXX these should be figured out dynamically */
3206 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3207 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3208
3209 dsi.vc[0].dssdev = dssdev;
3210 dsi.vc[1].dssdev = dssdev;
3211
3212 return 0;
3213}
3214
Tomi Valkeinene406f902010-06-09 15:28:12 +03003215void dsi_wait_dsi1_pll_active(void)
3216{
3217 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3218 DSSERR("DSI1 PLL clock not active\n");
3219}
3220
3221void dsi_wait_dsi2_pll_active(void)
3222{
3223 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3224 DSSERR("DSI2 PLL clock not active\n");
3225}
3226
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003227int dsi_init(struct platform_device *pdev)
3228{
3229 u32 rev;
3230 int r;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003231
3232 spin_lock_init(&dsi.errors_lock);
3233 dsi.errors = 0;
3234
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02003235#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3236 spin_lock_init(&dsi.irq_stats_lock);
3237 dsi.irq_stats.last_reset = jiffies;
3238#endif
3239
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003240 init_completion(&dsi.bta_completion);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003241
3242 mutex_init(&dsi.lock);
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +02003243 sema_init(&dsi.bus_lock, 1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003244
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03003245 dsi.workqueue = create_singlethread_workqueue("dsi");
3246 if (dsi.workqueue == NULL)
3247 return -ENOMEM;
3248
Tomi Valkeinen18946f62010-01-12 14:16:41 +02003249 INIT_WORK(&dsi.framedone_work, dsi_framedone_work_callback);
3250 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3251 dsi_framedone_timeout_work_callback);
3252
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003253#ifdef DSI_CATCH_MISSING_TE
3254 init_timer(&dsi.te_timer);
3255 dsi.te_timer.function = dsi_te_timeout;
3256 dsi.te_timer.data = 0;
3257#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003258 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3259 if (!dsi.base) {
3260 DSSERR("can't ioremap DSI\n");
3261 r = -ENOMEM;
3262 goto err1;
3263 }
3264
Tomi Valkeinen8a2cfea2010-02-04 17:03:41 +02003265 dsi.vdds_dsi_reg = dss_get_vdds_dsi();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003266 if (IS_ERR(dsi.vdds_dsi_reg)) {
3267 iounmap(dsi.base);
3268 DSSERR("can't get VDDS_DSI regulator\n");
3269 r = PTR_ERR(dsi.vdds_dsi_reg);
3270 goto err2;
3271 }
3272
3273 enable_clocks(1);
3274
3275 rev = dsi_read_reg(DSI_REVISION);
3276 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3277 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3278
3279 enable_clocks(0);
3280
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003281 return 0;
3282err2:
3283 iounmap(dsi.base);
3284err1:
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03003285 destroy_workqueue(dsi.workqueue);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003286 return r;
3287}
3288
3289void dsi_exit(void)
3290{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003291 iounmap(dsi.base);
3292
Tomi Valkeinen0f16aa02010-04-12 09:57:19 +03003293 destroy_workqueue(dsi.workqueue);
3294
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003295 DSSDBG("omap_dsi_exit\n");
3296}
3297