blob: e0ac549dccb54c43261d71df59da196144502d67 [file] [log] [blame]
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -07001/*
Tomoya MORINAGAf4574be2011-10-28 09:23:33 +09002 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -07003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040017#include <linux/module.h>
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070018#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/gpio.h>
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +090021#include <linux/interrupt.h>
22#include <linux/irq.h>
Linus Walleij349b6c52014-05-27 15:15:21 +020023#include <linux/slab.h>
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +090024
25#define PCH_EDGE_FALLING 0
26#define PCH_EDGE_RISING BIT(0)
27#define PCH_LEVEL_L BIT(1)
28#define PCH_LEVEL_H (BIT(0) | BIT(1))
29#define PCH_EDGE_BOTH BIT(2)
30#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define PCH_IRQ_BASE 24
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070033
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070034struct pch_regs {
35 u32 ien;
36 u32 istatus;
37 u32 idisp;
38 u32 iclr;
39 u32 imask;
40 u32 imaskclr;
41 u32 po;
42 u32 pi;
43 u32 pm;
44 u32 im0;
45 u32 im1;
Tomoya MORINAGAe98bed72011-07-21 09:19:58 +090046 u32 reserved[3];
47 u32 gpio_use_sel;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070048 u32 reset;
49};
50
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +090051enum pch_type_t {
52 INTEL_EG20T_PCH,
Tomoya MORINAGAf4574be2011-10-28 09:23:33 +090053 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
54 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +090055};
56
57/* Specifies number of GPIO PINS */
58static int gpio_pins[] = {
59 [INTEL_EG20T_PCH] = 12,
60 [OKISEMI_ML7223m_IOH] = 8,
61 [OKISEMI_ML7223n_IOH] = 8,
62};
63
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070064/**
65 * struct pch_gpio_reg_data - The register store data.
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +090066 * @ien_reg: To store contents of IEN register.
67 * @imask_reg: To store contents of IMASK register.
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070068 * @po_reg: To store contents of PO register.
69 * @pm_reg: To store contents of PM register.
Tomoya MORINAGAe98bed72011-07-21 09:19:58 +090070 * @im0_reg: To store contents of IM0 register.
71 * @im1_reg: To store contents of IM1 register.
72 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
73 * (Only ML7223 Bus-n)
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070074 */
75struct pch_gpio_reg_data {
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +090076 u32 ien_reg;
77 u32 imask_reg;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070078 u32 po_reg;
79 u32 pm_reg;
Tomoya MORINAGAe98bed72011-07-21 09:19:58 +090080 u32 im0_reg;
81 u32 im1_reg;
82 u32 gpio_use_sel_reg;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070083};
84
85/**
86 * struct pch_gpio - GPIO private data structure.
87 * @base: PCI base address of Memory mapped I/O register.
88 * @reg: Memory mapped PCH GPIO register list.
89 * @dev: Pointer to device structure.
90 * @gpio: Data for GPIO infrastructure.
91 * @pch_gpio_reg: Memory mapped Register data is saved here
92 * when suspend.
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +090093 * @lock: Used for register access protection
94 * @irq_base: Save base of IRQ number for interrupt
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +090095 * @ioh: IOH ID
Axel Lin7cb65802012-07-29 10:55:54 +080096 * @spinlock: Used for register access protection
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -070097 */
98struct pch_gpio {
99 void __iomem *base;
100 struct pch_regs __iomem *reg;
101 struct device *dev;
102 struct gpio_chip gpio;
103 struct pch_gpio_reg_data pch_gpio_reg;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900104 int irq_base;
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +0900105 enum pch_type_t ioh;
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900106 spinlock_t spinlock;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700107};
108
109static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
110{
111 u32 reg_val;
112 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
Axel Lin7cb65802012-07-29 10:55:54 +0800113 unsigned long flags;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700114
Axel Lin7cb65802012-07-29 10:55:54 +0800115 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700116 reg_val = ioread32(&chip->reg->po);
117 if (val)
118 reg_val |= (1 << nr);
119 else
120 reg_val &= ~(1 << nr);
121
122 iowrite32(reg_val, &chip->reg->po);
Axel Lin7cb65802012-07-29 10:55:54 +0800123 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700124}
125
126static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
127{
128 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
129
130 return ioread32(&chip->reg->pi) & (1 << nr);
131}
132
133static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
134 int val)
135{
136 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
137 u32 pm;
138 u32 reg_val;
Axel Lin7cb65802012-07-29 10:55:54 +0800139 unsigned long flags;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700140
Axel Lin7cb65802012-07-29 10:55:54 +0800141 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700142
143 reg_val = ioread32(&chip->reg->po);
144 if (val)
145 reg_val |= (1 << nr);
146 else
147 reg_val &= ~(1 << nr);
Peter Tyser88aab932011-03-25 10:04:00 -0500148 iowrite32(reg_val, &chip->reg->po);
Daniel Krueger2ddf6cd2014-03-25 10:32:47 +0100149
150 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
151 pm |= (1 << nr);
152 iowrite32(pm, &chip->reg->pm);
153
Axel Lin7cb65802012-07-29 10:55:54 +0800154 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700155
156 return 0;
157}
158
159static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
160{
161 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
162 u32 pm;
Axel Lin7cb65802012-07-29 10:55:54 +0800163 unsigned long flags;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700164
Axel Lin7cb65802012-07-29 10:55:54 +0800165 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +0900166 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700167 pm &= ~(1 << nr);
168 iowrite32(pm, &chip->reg->pm);
Axel Lin7cb65802012-07-29 10:55:54 +0800169 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700170
171 return 0;
172}
173
174/*
175 * Save register configuration and disable interrupts.
176 */
177static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
178{
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900179 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
180 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700181 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
182 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
Tomoya MORINAGAe98bed72011-07-21 09:19:58 +0900183 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
184 if (chip->ioh == INTEL_EG20T_PCH)
185 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
186 if (chip->ioh == OKISEMI_ML7223n_IOH)
187 chip->pch_gpio_reg.gpio_use_sel_reg =\
188 ioread32(&chip->reg->gpio_use_sel);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700189}
190
191/*
192 * This function restores the register configuration of the GPIO device.
193 */
194static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
195{
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900196 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
197 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700198 /* to store contents of PO register */
199 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
200 /* to store contents of PM register */
201 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
Tomoya MORINAGAe98bed72011-07-21 09:19:58 +0900202 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
203 if (chip->ioh == INTEL_EG20T_PCH)
204 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
205 if (chip->ioh == OKISEMI_ML7223n_IOH)
206 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
207 &chip->reg->gpio_use_sel);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700208}
209
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900210static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
211{
212 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
213 return chip->irq_base + offset;
214}
215
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700216static void pch_gpio_setup(struct pch_gpio *chip)
217{
218 struct gpio_chip *gpio = &chip->gpio;
219
220 gpio->label = dev_name(chip->dev);
Alexander Stein5c868fc2012-11-02 16:02:25 +0100221 gpio->dev = chip->dev;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700222 gpio->owner = THIS_MODULE;
223 gpio->direction_input = pch_gpio_direction_input;
224 gpio->get = pch_gpio_get;
225 gpio->direction_output = pch_gpio_direction_output;
226 gpio->set = pch_gpio_set;
227 gpio->dbg_show = NULL;
228 gpio->base = -1;
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +0900229 gpio->ngpio = gpio_pins[chip->ioh];
Linus Walleij9fb1f392013-12-04 14:42:46 +0100230 gpio->can_sleep = false;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900231 gpio->to_irq = pch_gpio_to_irq;
232}
233
234static int pch_irq_type(struct irq_data *d, unsigned int type)
235{
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900236 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
237 struct pch_gpio *chip = gc->private;
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200238 u32 im, im_pos, val;
239 u32 __iomem *im_reg;
240 unsigned long flags;
241 int ch, irq = d->irq;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900242
243 ch = irq - chip->irq_base;
244 if (irq <= chip->irq_base + 7) {
245 im_reg = &chip->reg->im0;
246 im_pos = ch;
247 } else {
248 im_reg = &chip->reg->im1;
249 im_pos = ch - 8;
250 }
251 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
252 __func__, irq, type, ch, im_pos);
253
254 spin_lock_irqsave(&chip->spinlock, flags);
255
256 switch (type) {
257 case IRQ_TYPE_EDGE_RISING:
258 val = PCH_EDGE_RISING;
259 break;
260 case IRQ_TYPE_EDGE_FALLING:
261 val = PCH_EDGE_FALLING;
262 break;
263 case IRQ_TYPE_EDGE_BOTH:
264 val = PCH_EDGE_BOTH;
265 break;
266 case IRQ_TYPE_LEVEL_HIGH:
267 val = PCH_LEVEL_H;
268 break;
269 case IRQ_TYPE_LEVEL_LOW:
270 val = PCH_LEVEL_L;
271 break;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900272 default:
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200273 goto unlock;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900274 }
275
276 /* Set interrupt mode */
277 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
278 iowrite32(im | (val << (im_pos * 4)), im_reg);
279
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200280 /* And the handler */
281 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
282 __irq_set_handler_locked(d->irq, handle_level_irq);
283 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
284 __irq_set_handler_locked(d->irq, handle_edge_irq);
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900285
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200286unlock:
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900287 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900288 return 0;
289}
290
291static void pch_irq_unmask(struct irq_data *d)
292{
293 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
294 struct pch_gpio *chip = gc->private;
295
296 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
297}
298
299static void pch_irq_mask(struct irq_data *d)
300{
301 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
302 struct pch_gpio *chip = gc->private;
303
304 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
305}
306
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200307static void pch_irq_ack(struct irq_data *d)
308{
309 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
310 struct pch_gpio *chip = gc->private;
311
312 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
313}
314
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900315static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
316{
317 struct pch_gpio *chip = dev_id;
318 u32 reg_val = ioread32(&chip->reg->istatus);
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200319 int i, ret = IRQ_NONE;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900320
321 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
322 if (reg_val & BIT(i)) {
323 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
324 __func__, i, irq, reg_val);
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900325 generic_handle_irq(chip->irq_base + i);
326 ret = IRQ_HANDLED;
327 }
328 }
329 return ret;
330}
331
Bill Pemberton38363092012-11-19 13:22:34 -0500332static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900333 unsigned int irq_start, unsigned int num)
334{
335 struct irq_chip_generic *gc;
336 struct irq_chip_type *ct;
337
338 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
339 handle_simple_irq);
340 gc->private = chip;
341 ct = gc->chip_types;
342
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200343 ct->chip.irq_ack = pch_irq_ack;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900344 ct->chip.irq_mask = pch_irq_mask;
345 ct->chip.irq_unmask = pch_irq_unmask;
346 ct->chip.irq_set_type = pch_irq_type;
347
348 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
349 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700350}
351
Bill Pemberton38363092012-11-19 13:22:34 -0500352static int pch_gpio_probe(struct pci_dev *pdev,
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700353 const struct pci_device_id *id)
354{
355 s32 ret;
356 struct pch_gpio *chip;
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900357 int irq_base;
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200358 u32 msk;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700359
360 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
361 if (chip == NULL)
362 return -ENOMEM;
363
364 chip->dev = &pdev->dev;
365 ret = pci_enable_device(pdev);
366 if (ret) {
367 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
368 goto err_pci_enable;
369 }
370
371 ret = pci_request_regions(pdev, KBUILD_MODNAME);
372 if (ret) {
373 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
374 goto err_request_regions;
375 }
376
377 chip->base = pci_iomap(pdev, 1, 0);
Márton Némethc4addcb2012-01-15 11:32:30 +0100378 if (!chip->base) {
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700379 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
380 ret = -ENOMEM;
381 goto err_iomap;
382 }
383
Tomoya MORINAGAd4260e62011-07-21 09:19:57 +0900384 if (pdev->device == 0x8803)
385 chip->ioh = INTEL_EG20T_PCH;
386 else if (pdev->device == 0x8014)
387 chip->ioh = OKISEMI_ML7223m_IOH;
388 else if (pdev->device == 0x8043)
389 chip->ioh = OKISEMI_ML7223n_IOH;
390
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700391 chip->reg = chip->base;
392 pci_set_drvdata(pdev, chip);
Axel Lind1663702012-02-01 10:51:53 +0800393 spin_lock_init(&chip->spinlock);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700394 pch_gpio_setup(chip);
395 ret = gpiochip_add(&chip->gpio);
396 if (ret) {
397 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
398 goto err_gpiochip_add;
399 }
400
Tomoya MORINAGA2824bc9c2011-10-19 10:37:39 +0900401 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900402 if (irq_base < 0) {
403 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
404 chip->irq_base = -1;
405 goto end;
406 }
407 chip->irq_base = irq_base;
408
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200409 /* Mask all interrupts, but enable them */
410 msk = (1 << gpio_pins[chip->ioh]) - 1;
411 iowrite32(msk, &chip->reg->imask);
412 iowrite32(msk, &chip->reg->ien);
413
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900414 ret = request_irq(pdev->irq, pch_gpio_handler,
Thomas Gleixnerdf9541a2012-04-28 10:13:45 +0200415 IRQF_SHARED, KBUILD_MODNAME, chip);
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900416 if (ret != 0) {
417 dev_err(&pdev->dev,
418 "%s request_irq failed\n", __func__);
419 goto err_request_irq;
420 }
421
422 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
423
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900424end:
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700425 return 0;
426
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900427err_request_irq:
428 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200429 gpiochip_remove(&chip->gpio);
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900430
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700431err_gpiochip_add:
432 pci_iounmap(pdev, chip->base);
433
434err_iomap:
435 pci_release_regions(pdev);
436
437err_request_regions:
438 pci_disable_device(pdev);
439
440err_pci_enable:
441 kfree(chip);
442 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
443 return ret;
444}
445
Bill Pemberton206210c2012-11-19 13:25:50 -0500446static void pch_gpio_remove(struct pci_dev *pdev)
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700447{
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700448 struct pch_gpio *chip = pci_get_drvdata(pdev);
449
Tomoya MORINAGA38eb18a2011-07-21 09:19:59 +0900450 if (chip->irq_base != -1) {
451 free_irq(pdev->irq, chip);
452
453 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
454 }
455
abdoulaye berthe9f5132a2014-07-12 22:30:12 +0200456 gpiochip_remove(&chip->gpio);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700457 pci_iounmap(pdev, chip->base);
458 pci_release_regions(pdev);
459 pci_disable_device(pdev);
460 kfree(chip);
461}
462
463#ifdef CONFIG_PM
464static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
465{
466 s32 ret;
467 struct pch_gpio *chip = pci_get_drvdata(pdev);
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900468 unsigned long flags;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700469
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900470 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700471 pch_gpio_save_reg_conf(chip);
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900472 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700473
474 ret = pci_save_state(pdev);
475 if (ret) {
476 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
477 return ret;
478 }
479 pci_disable_device(pdev);
480 pci_set_power_state(pdev, PCI_D0);
481 ret = pci_enable_wake(pdev, PCI_D0, 1);
482 if (ret)
483 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
484
485 return 0;
486}
487
488static int pch_gpio_resume(struct pci_dev *pdev)
489{
490 s32 ret;
491 struct pch_gpio *chip = pci_get_drvdata(pdev);
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900492 unsigned long flags;
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700493
494 ret = pci_enable_wake(pdev, PCI_D0, 0);
495
496 pci_set_power_state(pdev, PCI_D0);
497 ret = pci_enable_device(pdev);
498 if (ret) {
499 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
500 return ret;
501 }
502 pci_restore_state(pdev);
503
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900504 spin_lock_irqsave(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700505 iowrite32(0x01, &chip->reg->reset);
506 iowrite32(0x00, &chip->reg->reset);
507 pch_gpio_restore_reg_conf(chip);
Tomoya MORINAGAd568a682011-07-21 09:19:55 +0900508 spin_unlock_irqrestore(&chip->spinlock, flags);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700509
510 return 0;
511}
512#else
513#define pch_gpio_suspend NULL
514#define pch_gpio_resume NULL
515#endif
516
Tomoya MORINAGAbc786cc2011-05-09 19:58:49 +0900517#define PCI_VENDOR_ID_ROHM 0x10DB
Jingoo Han14f4a882013-12-03 08:08:45 +0900518static const struct pci_device_id pch_gpio_pcidev_id[] = {
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700519 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
Tomoya MORINAGAbc786cc2011-05-09 19:58:49 +0900520 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
Tomoya MORINAGAc3520a12011-07-21 09:19:56 +0900521 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
Tomoya MORINAGA868fea02011-10-28 09:23:32 +0900522 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700523 { 0, }
524};
Axel Lin19234cd2011-03-11 14:58:30 -0800525MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700526
527static struct pci_driver pch_gpio_driver = {
528 .name = "pch_gpio",
529 .id_table = pch_gpio_pcidev_id,
530 .probe = pch_gpio_probe,
Bill Pemberton8283c4f2012-11-19 13:20:08 -0500531 .remove = pch_gpio_remove,
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700532 .suspend = pch_gpio_suspend,
533 .resume = pch_gpio_resume
534};
535
Axel Lin93baa652012-04-06 20:13:30 +0800536module_pci_driver(pch_gpio_driver);
Tomoya MORINAGA04c17aa82010-10-27 15:33:21 -0700537
538MODULE_DESCRIPTION("PCH GPIO PCI Driver");
539MODULE_LICENSE("GPL");