Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Chip-specific setup code for the AT91SAM9G45 family |
| 3 | * |
| 4 | * Copyright (C) 2009 Atmel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
Jon Medhurst | f407c2e | 2011-08-04 16:04:24 +0100 | [diff] [blame] | 14 | #include <linux/dma-mapping.h> |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 15 | |
| 16 | #include <asm/irq.h> |
| 17 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame^] | 19 | #include <asm/system_misc.h> |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 20 | #include <mach/at91sam9g45.h> |
| 21 | #include <mach/at91_pmc.h> |
Nicolas Ferre | 5f9f0a4 | 2010-06-11 12:53:14 +0100 | [diff] [blame] | 22 | #include <mach/cpu.h> |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 23 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 24 | #include "soc.h" |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 25 | #include "generic.h" |
| 26 | #include "clock.h" |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 27 | #include "sam9_smc.h" |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 28 | |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 29 | /* -------------------------------------------------------------------- |
| 30 | * Clocks |
| 31 | * -------------------------------------------------------------------- */ |
| 32 | |
| 33 | /* |
| 34 | * The peripheral clocks. |
| 35 | */ |
| 36 | static struct clk pioA_clk = { |
| 37 | .name = "pioA_clk", |
| 38 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOA, |
| 39 | .type = CLK_TYPE_PERIPHERAL, |
| 40 | }; |
| 41 | static struct clk pioB_clk = { |
| 42 | .name = "pioB_clk", |
| 43 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOB, |
| 44 | .type = CLK_TYPE_PERIPHERAL, |
| 45 | }; |
| 46 | static struct clk pioC_clk = { |
| 47 | .name = "pioC_clk", |
| 48 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOC, |
| 49 | .type = CLK_TYPE_PERIPHERAL, |
| 50 | }; |
| 51 | static struct clk pioDE_clk = { |
| 52 | .name = "pioDE_clk", |
| 53 | .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, |
| 54 | .type = CLK_TYPE_PERIPHERAL, |
| 55 | }; |
Peter Korsgaard | 237a62a | 2011-10-06 17:41:33 +0200 | [diff] [blame] | 56 | static struct clk trng_clk = { |
| 57 | .name = "trng_clk", |
| 58 | .pmc_mask = 1 << AT91SAM9G45_ID_TRNG, |
| 59 | .type = CLK_TYPE_PERIPHERAL, |
| 60 | }; |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 61 | static struct clk usart0_clk = { |
| 62 | .name = "usart0_clk", |
| 63 | .pmc_mask = 1 << AT91SAM9G45_ID_US0, |
| 64 | .type = CLK_TYPE_PERIPHERAL, |
| 65 | }; |
| 66 | static struct clk usart1_clk = { |
| 67 | .name = "usart1_clk", |
| 68 | .pmc_mask = 1 << AT91SAM9G45_ID_US1, |
| 69 | .type = CLK_TYPE_PERIPHERAL, |
| 70 | }; |
| 71 | static struct clk usart2_clk = { |
| 72 | .name = "usart2_clk", |
| 73 | .pmc_mask = 1 << AT91SAM9G45_ID_US2, |
| 74 | .type = CLK_TYPE_PERIPHERAL, |
| 75 | }; |
| 76 | static struct clk usart3_clk = { |
| 77 | .name = "usart3_clk", |
| 78 | .pmc_mask = 1 << AT91SAM9G45_ID_US3, |
| 79 | .type = CLK_TYPE_PERIPHERAL, |
| 80 | }; |
| 81 | static struct clk mmc0_clk = { |
| 82 | .name = "mci0_clk", |
| 83 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI0, |
| 84 | .type = CLK_TYPE_PERIPHERAL, |
| 85 | }; |
| 86 | static struct clk twi0_clk = { |
| 87 | .name = "twi0_clk", |
| 88 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI0, |
| 89 | .type = CLK_TYPE_PERIPHERAL, |
| 90 | }; |
| 91 | static struct clk twi1_clk = { |
| 92 | .name = "twi1_clk", |
| 93 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI1, |
| 94 | .type = CLK_TYPE_PERIPHERAL, |
| 95 | }; |
| 96 | static struct clk spi0_clk = { |
| 97 | .name = "spi0_clk", |
| 98 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI0, |
| 99 | .type = CLK_TYPE_PERIPHERAL, |
| 100 | }; |
| 101 | static struct clk spi1_clk = { |
| 102 | .name = "spi1_clk", |
| 103 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI1, |
| 104 | .type = CLK_TYPE_PERIPHERAL, |
| 105 | }; |
| 106 | static struct clk ssc0_clk = { |
| 107 | .name = "ssc0_clk", |
| 108 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC0, |
| 109 | .type = CLK_TYPE_PERIPHERAL, |
| 110 | }; |
| 111 | static struct clk ssc1_clk = { |
| 112 | .name = "ssc1_clk", |
| 113 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC1, |
| 114 | .type = CLK_TYPE_PERIPHERAL, |
| 115 | }; |
Fabian Godehardt | ab64511 | 2010-09-03 13:31:33 +0100 | [diff] [blame] | 116 | static struct clk tcb0_clk = { |
| 117 | .name = "tcb0_clk", |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 118 | .pmc_mask = 1 << AT91SAM9G45_ID_TCB, |
| 119 | .type = CLK_TYPE_PERIPHERAL, |
| 120 | }; |
| 121 | static struct clk pwm_clk = { |
| 122 | .name = "pwm_clk", |
| 123 | .pmc_mask = 1 << AT91SAM9G45_ID_PWMC, |
| 124 | .type = CLK_TYPE_PERIPHERAL, |
| 125 | }; |
| 126 | static struct clk tsc_clk = { |
| 127 | .name = "tsc_clk", |
| 128 | .pmc_mask = 1 << AT91SAM9G45_ID_TSC, |
| 129 | .type = CLK_TYPE_PERIPHERAL, |
| 130 | }; |
| 131 | static struct clk dma_clk = { |
| 132 | .name = "dma_clk", |
| 133 | .pmc_mask = 1 << AT91SAM9G45_ID_DMA, |
| 134 | .type = CLK_TYPE_PERIPHERAL, |
| 135 | }; |
| 136 | static struct clk uhphs_clk = { |
| 137 | .name = "uhphs_clk", |
| 138 | .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS, |
| 139 | .type = CLK_TYPE_PERIPHERAL, |
| 140 | }; |
| 141 | static struct clk lcdc_clk = { |
| 142 | .name = "lcdc_clk", |
| 143 | .pmc_mask = 1 << AT91SAM9G45_ID_LCDC, |
| 144 | .type = CLK_TYPE_PERIPHERAL, |
| 145 | }; |
| 146 | static struct clk ac97_clk = { |
| 147 | .name = "ac97_clk", |
| 148 | .pmc_mask = 1 << AT91SAM9G45_ID_AC97C, |
| 149 | .type = CLK_TYPE_PERIPHERAL, |
| 150 | }; |
| 151 | static struct clk macb_clk = { |
Jamie Iles | 865d605 | 2011-08-09 16:51:11 +0200 | [diff] [blame] | 152 | .name = "pclk", |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 153 | .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, |
| 154 | .type = CLK_TYPE_PERIPHERAL, |
| 155 | }; |
| 156 | static struct clk isi_clk = { |
| 157 | .name = "isi_clk", |
| 158 | .pmc_mask = 1 << AT91SAM9G45_ID_ISI, |
| 159 | .type = CLK_TYPE_PERIPHERAL, |
| 160 | }; |
| 161 | static struct clk udphs_clk = { |
| 162 | .name = "udphs_clk", |
| 163 | .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS, |
| 164 | .type = CLK_TYPE_PERIPHERAL, |
| 165 | }; |
| 166 | static struct clk mmc1_clk = { |
| 167 | .name = "mci1_clk", |
| 168 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI1, |
| 169 | .type = CLK_TYPE_PERIPHERAL, |
| 170 | }; |
| 171 | |
Nicolas Ferre | 5f9f0a4 | 2010-06-11 12:53:14 +0100 | [diff] [blame] | 172 | /* Video decoder clock - Only for sam9m10/sam9m11 */ |
| 173 | static struct clk vdec_clk = { |
| 174 | .name = "vdec_clk", |
| 175 | .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, |
| 176 | .type = CLK_TYPE_PERIPHERAL, |
| 177 | }; |
| 178 | |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 179 | static struct clk *periph_clocks[] __initdata = { |
| 180 | &pioA_clk, |
| 181 | &pioB_clk, |
| 182 | &pioC_clk, |
| 183 | &pioDE_clk, |
Peter Korsgaard | 237a62a | 2011-10-06 17:41:33 +0200 | [diff] [blame] | 184 | &trng_clk, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 185 | &usart0_clk, |
| 186 | &usart1_clk, |
| 187 | &usart2_clk, |
| 188 | &usart3_clk, |
| 189 | &mmc0_clk, |
| 190 | &twi0_clk, |
| 191 | &twi1_clk, |
| 192 | &spi0_clk, |
| 193 | &spi1_clk, |
| 194 | &ssc0_clk, |
| 195 | &ssc1_clk, |
Fabian Godehardt | ab64511 | 2010-09-03 13:31:33 +0100 | [diff] [blame] | 196 | &tcb0_clk, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 197 | &pwm_clk, |
| 198 | &tsc_clk, |
| 199 | &dma_clk, |
| 200 | &uhphs_clk, |
| 201 | &lcdc_clk, |
| 202 | &ac97_clk, |
| 203 | &macb_clk, |
| 204 | &isi_clk, |
| 205 | &udphs_clk, |
| 206 | &mmc1_clk, |
| 207 | // irq0 |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 208 | }; |
| 209 | |
| 210 | static struct clk_lookup periph_clocks_lookups[] = { |
Jamie Iles | 865d605 | 2011-08-09 16:51:11 +0200 | [diff] [blame] | 211 | /* One additional fake clock for macb_hclk */ |
| 212 | CLKDEV_CON_ID("hclk", &macb_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 213 | /* One additional fake clock for ohci */ |
| 214 | CLKDEV_CON_ID("ohci_clk", &uhphs_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 9d87159 | 2011-06-21 14:24:33 +0800 | [diff] [blame] | 215 | CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), |
| 216 | CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), |
| 217 | CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), |
| 218 | CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), |
| 219 | CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 220 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
| 221 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), |
| 222 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), |
| 223 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), |
| 224 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 225 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
Peter Korsgaard | 237a62a | 2011-10-06 17:41:33 +0200 | [diff] [blame] | 226 | CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 227 | /* more usart lookup table for DT entries */ |
| 228 | CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), |
| 229 | CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk), |
| 230 | CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk), |
| 231 | CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk), |
| 232 | CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 0af4316 | 2011-08-30 03:29:28 +0200 | [diff] [blame] | 233 | /* fake hclk clock */ |
| 234 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 619d4a4 | 2011-11-13 13:00:58 +0800 | [diff] [blame] | 235 | CLKDEV_CON_ID("pioA", &pioA_clk), |
| 236 | CLKDEV_CON_ID("pioB", &pioB_clk), |
| 237 | CLKDEV_CON_ID("pioC", &pioC_clk), |
| 238 | CLKDEV_CON_ID("pioD", &pioDE_clk), |
| 239 | CLKDEV_CON_ID("pioE", &pioDE_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 240 | }; |
| 241 | |
| 242 | static struct clk_lookup usart_clocks_lookups[] = { |
| 243 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 244 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 245 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 246 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 247 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | /* |
| 251 | * The two programmable clocks. |
| 252 | * You must configure pin multiplexing to bring these signals out. |
| 253 | */ |
| 254 | static struct clk pck0 = { |
| 255 | .name = "pck0", |
| 256 | .pmc_mask = AT91_PMC_PCK0, |
| 257 | .type = CLK_TYPE_PROGRAMMABLE, |
| 258 | .id = 0, |
| 259 | }; |
| 260 | static struct clk pck1 = { |
| 261 | .name = "pck1", |
| 262 | .pmc_mask = AT91_PMC_PCK1, |
| 263 | .type = CLK_TYPE_PROGRAMMABLE, |
| 264 | .id = 1, |
| 265 | }; |
| 266 | |
| 267 | static void __init at91sam9g45_register_clocks(void) |
| 268 | { |
| 269 | int i; |
| 270 | |
| 271 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 272 | clk_register(periph_clocks[i]); |
| 273 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 274 | clkdev_add_table(periph_clocks_lookups, |
| 275 | ARRAY_SIZE(periph_clocks_lookups)); |
| 276 | clkdev_add_table(usart_clocks_lookups, |
| 277 | ARRAY_SIZE(usart_clocks_lookups)); |
| 278 | |
Nicolas Ferre | 5f9f0a4 | 2010-06-11 12:53:14 +0100 | [diff] [blame] | 279 | if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) |
| 280 | clk_register(&vdec_clk); |
| 281 | |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 282 | clk_register(&pck0); |
| 283 | clk_register(&pck1); |
| 284 | } |
| 285 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 286 | static struct clk_lookup console_clock_lookup; |
| 287 | |
| 288 | void __init at91sam9g45_set_console_clock(int id) |
| 289 | { |
| 290 | if (id >= ARRAY_SIZE(usart_clocks_lookups)) |
| 291 | return; |
| 292 | |
| 293 | console_clock_lookup.con_id = "usart"; |
| 294 | console_clock_lookup.clk = usart_clocks_lookups[id].clk; |
| 295 | clkdev_add(&console_clock_lookup); |
| 296 | } |
| 297 | |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 298 | /* -------------------------------------------------------------------- |
| 299 | * GPIO |
| 300 | * -------------------------------------------------------------------- */ |
| 301 | |
Jean-Christophe PLAGNIOL-VILLARD | 1a2d915 | 2011-10-17 14:28:38 +0800 | [diff] [blame] | 302 | static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = { |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 303 | { |
| 304 | .id = AT91SAM9G45_ID_PIOA, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 305 | .regbase = AT91SAM9G45_BASE_PIOA, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 306 | }, { |
| 307 | .id = AT91SAM9G45_ID_PIOB, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 308 | .regbase = AT91SAM9G45_BASE_PIOB, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 309 | }, { |
| 310 | .id = AT91SAM9G45_ID_PIOC, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 311 | .regbase = AT91SAM9G45_BASE_PIOC, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 312 | }, { |
| 313 | .id = AT91SAM9G45_ID_PIODE, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 314 | .regbase = AT91SAM9G45_BASE_PIOD, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 315 | }, { |
| 316 | .id = AT91SAM9G45_ID_PIODE, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 317 | .regbase = AT91SAM9G45_BASE_PIOE, |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 318 | } |
| 319 | }; |
| 320 | |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 321 | /* -------------------------------------------------------------------- |
| 322 | * AT91SAM9G45 processor initialization |
| 323 | * -------------------------------------------------------------------- */ |
| 324 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 325 | static void __init at91sam9g45_map_io(void) |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 326 | { |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 327 | at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); |
Jon Medhurst | f407c2e | 2011-08-04 16:04:24 +0100 | [diff] [blame] | 328 | init_consistent_dma_size(SZ_4M); |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 329 | } |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 330 | |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 331 | static void __init at91sam9g45_ioremap_registers(void) |
| 332 | { |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 333 | at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); |
Jean-Christophe PLAGNIOL-VILLARD | e9f68b5 | 2011-11-18 01:25:52 +0800 | [diff] [blame] | 334 | at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 335 | at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 336 | at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 337 | } |
| 338 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 339 | static void __init at91sam9g45_initialize(void) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 340 | { |
Russell King | 1b2073e | 2011-11-03 09:53:29 +0000 | [diff] [blame] | 341 | arm_pm_restart = at91sam9g45_restart; |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 342 | at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); |
| 343 | |
Nicolas Ferre | 789b23b | 2009-06-26 15:36:58 +0100 | [diff] [blame] | 344 | /* Register GPIO subsystem */ |
| 345 | at91_gpio_init(at91sam9g45_gpio, 5); |
| 346 | } |
| 347 | |
| 348 | /* -------------------------------------------------------------------- |
| 349 | * Interrupt initialization |
| 350 | * -------------------------------------------------------------------- */ |
| 351 | |
| 352 | /* |
| 353 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 354 | */ |
| 355 | static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 356 | 7, /* Advanced Interrupt Controller (FIQ) */ |
| 357 | 7, /* System Peripherals */ |
| 358 | 1, /* Parallel IO Controller A */ |
| 359 | 1, /* Parallel IO Controller B */ |
| 360 | 1, /* Parallel IO Controller C */ |
| 361 | 1, /* Parallel IO Controller D and E */ |
| 362 | 0, |
| 363 | 5, /* USART 0 */ |
| 364 | 5, /* USART 1 */ |
| 365 | 5, /* USART 2 */ |
| 366 | 5, /* USART 3 */ |
| 367 | 0, /* Multimedia Card Interface 0 */ |
| 368 | 6, /* Two-Wire Interface 0 */ |
| 369 | 6, /* Two-Wire Interface 1 */ |
| 370 | 5, /* Serial Peripheral Interface 0 */ |
| 371 | 5, /* Serial Peripheral Interface 1 */ |
| 372 | 4, /* Serial Synchronous Controller 0 */ |
| 373 | 4, /* Serial Synchronous Controller 1 */ |
| 374 | 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ |
| 375 | 0, /* Pulse Width Modulation Controller */ |
| 376 | 0, /* Touch Screen Controller */ |
| 377 | 0, /* DMA Controller */ |
| 378 | 2, /* USB Host High Speed port */ |
| 379 | 3, /* LDC Controller */ |
| 380 | 5, /* AC97 Controller */ |
| 381 | 3, /* Ethernet */ |
| 382 | 0, /* Image Sensor Interface */ |
| 383 | 2, /* USB Device High speed port */ |
| 384 | 0, |
| 385 | 0, /* Multimedia Card Interface 1 */ |
| 386 | 0, |
| 387 | 0, /* Advanced Interrupt Controller (IRQ0) */ |
| 388 | }; |
| 389 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 390 | struct at91_init_soc __initdata at91sam9g45_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 391 | .map_io = at91sam9g45_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 392 | .default_irq_priority = at91sam9g45_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 393 | .ioremap_registers = at91sam9g45_ioremap_registers, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 394 | .register_clocks = at91sam9g45_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 395 | .init = at91sam9g45_initialize, |
| 396 | }; |