Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/plat-iop/pci.c |
| 3 | * |
| 4 | * PCI support for the Intel IOP32X and IOP33X processors |
| 5 | * |
| 6 | * Author: Rory Bolt <rorybolt@pacbell.net> |
| 7 | * Copyright (C) 2002 Rory Bolt |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/mm.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/ioport.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 20 | #include <linux/io.h> |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 21 | #include <asm/irq.h> |
Alexey Dobriyan | e8edc6e | 2007-05-21 01:22:52 +0400 | [diff] [blame] | 22 | #include <asm/signal.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | #include <mach/hardware.h> |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 24 | #include <asm/mach/pci.h> |
| 25 | #include <asm/hardware/iop3xx.h> |
| 26 | |
| 27 | // #define DEBUG |
| 28 | |
| 29 | #ifdef DEBUG |
| 30 | #define DBG(x...) printk(x) |
| 31 | #else |
| 32 | #define DBG(x...) do { } while (0) |
| 33 | #endif |
| 34 | |
| 35 | /* |
| 36 | * This routine builds either a type0 or type1 configuration command. If the |
| 37 | * bus is on the 803xx then a type0 made, else a type1 is created. |
| 38 | */ |
| 39 | static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) |
| 40 | { |
| 41 | struct pci_sys_data *sys = bus->sysdata; |
| 42 | u32 addr; |
| 43 | |
| 44 | if (sys->busnr == bus->number) |
| 45 | addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); |
| 46 | else |
| 47 | addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; |
| 48 | |
| 49 | addr |= PCI_FUNC(devfn) << 8 | (where & ~3); |
| 50 | |
| 51 | return addr; |
| 52 | } |
| 53 | |
| 54 | /* |
| 55 | * This routine checks the status of the last configuration cycle. If an error |
| 56 | * was detected it returns a 1, else it returns a 0. The errors being checked |
| 57 | * are parity, master abort, target abort (master and target). These types of |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 58 | * errors occur during a config cycle where there is no device, like during |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 59 | * the discovery stage. |
| 60 | */ |
| 61 | static int iop3xx_pci_status(void) |
| 62 | { |
| 63 | unsigned int status; |
| 64 | int ret = 0; |
| 65 | |
| 66 | /* |
| 67 | * Check the status registers. |
| 68 | */ |
| 69 | status = *IOP3XX_ATUSR; |
| 70 | if (status & 0xf900) { |
| 71 | DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); |
| 72 | *IOP3XX_ATUSR = status & 0xf900; |
| 73 | ret = 1; |
| 74 | } |
| 75 | |
| 76 | status = *IOP3XX_ATUISR; |
| 77 | if (status & 0x679f) { |
| 78 | DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); |
| 79 | *IOP3XX_ATUISR = status & 0x679f; |
| 80 | ret = 1; |
| 81 | } |
| 82 | |
| 83 | return ret; |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * Simply write the address register and read the configuration |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 88 | * data. Note that the 4 nops ensure that we are able to handle |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 89 | * a delayed abort (in theory.) |
| 90 | */ |
Dan Williams | d73d801 | 2007-05-15 01:03:36 +0100 | [diff] [blame] | 91 | static u32 iop3xx_read(unsigned long addr) |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 92 | { |
| 93 | u32 val; |
| 94 | |
| 95 | __asm__ __volatile__( |
| 96 | "str %1, [%2]\n\t" |
| 97 | "ldr %0, [%3]\n\t" |
| 98 | "nop\n\t" |
| 99 | "nop\n\t" |
| 100 | "nop\n\t" |
| 101 | "nop\n\t" |
| 102 | : "=r" (val) |
| 103 | : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); |
| 104 | |
| 105 | return val; |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | * The read routines must check the error status of the last configuration |
| 110 | * cycle. If there was an error, the routine returns all hex f's. |
| 111 | */ |
| 112 | static int |
| 113 | iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 114 | int size, u32 *value) |
| 115 | { |
| 116 | unsigned long addr = iop3xx_cfg_address(bus, devfn, where); |
| 117 | u32 val = iop3xx_read(addr) >> ((where & 3) * 8); |
| 118 | |
| 119 | if (iop3xx_pci_status()) |
| 120 | val = 0xffffffff; |
| 121 | |
| 122 | *value = val; |
| 123 | |
| 124 | return PCIBIOS_SUCCESSFUL; |
| 125 | } |
| 126 | |
| 127 | static int |
| 128 | iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 129 | int size, u32 value) |
| 130 | { |
| 131 | unsigned long addr = iop3xx_cfg_address(bus, devfn, where); |
| 132 | u32 val; |
| 133 | |
| 134 | if (size != 4) { |
| 135 | val = iop3xx_read(addr); |
| 136 | if (iop3xx_pci_status()) |
| 137 | return PCIBIOS_SUCCESSFUL; |
| 138 | |
| 139 | where = (where & 3) * 8; |
| 140 | |
| 141 | if (size == 1) |
| 142 | val &= ~(0xff << where); |
| 143 | else |
| 144 | val &= ~(0xffff << where); |
| 145 | |
| 146 | *IOP3XX_OCCDR = val | value << where; |
| 147 | } else { |
| 148 | asm volatile( |
| 149 | "str %1, [%2]\n\t" |
| 150 | "str %0, [%3]\n\t" |
| 151 | "nop\n\t" |
| 152 | "nop\n\t" |
| 153 | "nop\n\t" |
| 154 | "nop\n\t" |
| 155 | : |
| 156 | : "r" (value), "r" (addr), |
| 157 | "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); |
| 158 | } |
| 159 | |
| 160 | return PCIBIOS_SUCCESSFUL; |
| 161 | } |
| 162 | |
| 163 | static struct pci_ops iop3xx_ops = { |
| 164 | .read = iop3xx_read_config, |
| 165 | .write = iop3xx_write_config, |
| 166 | }; |
| 167 | |
| 168 | /* |
| 169 | * When a PCI device does not exist during config cycles, the 80200 gets a |
| 170 | * bus error instead of returning 0xffffffff. This handler simply returns. |
| 171 | */ |
| 172 | static int |
| 173 | iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) |
| 174 | { |
| 175 | DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", |
| 176 | addr, fsr, regs->ARM_pc, regs->ARM_lr); |
| 177 | |
| 178 | /* |
| 179 | * If it was an imprecise abort, then we need to correct the |
| 180 | * return address to be _after_ the instruction. |
| 181 | */ |
| 182 | if (fsr & (1 << 10)) |
| 183 | regs->ARM_pc += 4; |
| 184 | |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) |
| 189 | { |
| 190 | struct resource *res; |
| 191 | |
| 192 | if (nr != 0) |
| 193 | return 0; |
| 194 | |
| 195 | res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); |
| 196 | if (!res) |
| 197 | panic("PCI: unable to alloc resources"); |
| 198 | |
Dan Williams | 6df2670 | 2007-02-13 17:11:04 +0100 | [diff] [blame] | 199 | res[0].start = IOP3XX_PCI_LOWER_IO_PA; |
| 200 | res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 201 | res[0].name = "IOP3XX PCI I/O Space"; |
| 202 | res[0].flags = IORESOURCE_IO; |
| 203 | request_resource(&ioport_resource, &res[0]); |
| 204 | |
| 205 | res[1].start = IOP3XX_PCI_LOWER_MEM_PA; |
| 206 | res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; |
| 207 | res[1].name = "IOP3XX PCI Memory Space"; |
| 208 | res[1].flags = IORESOURCE_MEM; |
| 209 | request_resource(&iomem_resource, &res[1]); |
| 210 | |
Russell King | 27eedbf | 2008-03-26 18:44:58 -0700 | [diff] [blame] | 211 | /* |
| 212 | * Use whatever translation is already setup. |
| 213 | */ |
| 214 | sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; |
| 215 | sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 216 | |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 217 | pci_add_resource(&sys->resources, &res[0]); |
| 218 | pci_add_resource(&sys->resources, &res[1]); |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 219 | |
| 220 | return 1; |
| 221 | } |
| 222 | |
| 223 | struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) |
| 224 | { |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 225 | return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys, |
| 226 | &sys->resources); |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 227 | } |
| 228 | |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 229 | void __init iop3xx_atu_setup(void) |
| 230 | { |
| 231 | /* BAR 0 ( Disabled ) */ |
| 232 | *IOP3XX_IAUBAR0 = 0x0; |
| 233 | *IOP3XX_IABAR0 = 0x0; |
| 234 | *IOP3XX_IATVR0 = 0x0; |
| 235 | *IOP3XX_IALR0 = 0x0; |
| 236 | |
| 237 | /* BAR 1 ( Disabled ) */ |
| 238 | *IOP3XX_IAUBAR1 = 0x0; |
| 239 | *IOP3XX_IABAR1 = 0x0; |
| 240 | *IOP3XX_IALR1 = 0x0; |
| 241 | |
| 242 | /* BAR 2 (1:1 mapping with Physical RAM) */ |
| 243 | /* Set limit and enable */ |
| 244 | *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1; |
| 245 | *IOP3XX_IAUBAR2 = 0x0; |
| 246 | |
| 247 | /* Align the inbound bar with the base of memory */ |
| 248 | *IOP3XX_IABAR2 = PHYS_OFFSET | |
| 249 | PCI_BASE_ADDRESS_MEM_TYPE_64 | |
| 250 | PCI_BASE_ADDRESS_MEM_PREFETCH; |
| 251 | |
| 252 | *IOP3XX_IATVR2 = PHYS_OFFSET; |
| 253 | |
| 254 | /* Outbound window 0 */ |
Russell King | 97c4604 | 2008-03-26 18:46:42 -0700 | [diff] [blame] | 255 | *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 256 | *IOP3XX_OUMWTVR0 = 0; |
| 257 | |
| 258 | /* Outbound window 1 */ |
Aaro Koskinen | 5b9eda3 | 2009-07-31 12:16:21 +0300 | [diff] [blame] | 259 | *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + |
| 260 | IOP3XX_PCI_MEM_WINDOW_SIZE / 2; |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 261 | *IOP3XX_OUMWTVR1 = 0; |
| 262 | |
| 263 | /* BAR 3 ( Disabled ) */ |
| 264 | *IOP3XX_IAUBAR3 = 0x0; |
| 265 | *IOP3XX_IABAR3 = 0x0; |
| 266 | *IOP3XX_IATVR3 = 0x0; |
| 267 | *IOP3XX_IALR3 = 0x0; |
| 268 | |
| 269 | /* Setup the I/O Bar |
| 270 | */ |
Russell King | 97c4604 | 2008-03-26 18:46:42 -0700 | [diff] [blame] | 271 | *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 272 | |
| 273 | /* Enable inbound and outbound cycles |
| 274 | */ |
| 275 | *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
| 276 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; |
| 277 | *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN; |
| 278 | } |
| 279 | |
| 280 | void __init iop3xx_atu_disable(void) |
| 281 | { |
| 282 | *IOP3XX_ATUCMD = 0; |
| 283 | *IOP3XX_ATUCR = 0; |
| 284 | |
| 285 | /* wait for cycles to quiesce */ |
| 286 | while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY | |
| 287 | IOP3XX_PCSR_IN_Q_BUSY)) |
| 288 | cpu_relax(); |
| 289 | |
| 290 | /* BAR 0 ( Disabled ) */ |
| 291 | *IOP3XX_IAUBAR0 = 0x0; |
| 292 | *IOP3XX_IABAR0 = 0x0; |
| 293 | *IOP3XX_IATVR0 = 0x0; |
| 294 | *IOP3XX_IALR0 = 0x0; |
| 295 | |
| 296 | /* BAR 1 ( Disabled ) */ |
| 297 | *IOP3XX_IAUBAR1 = 0x0; |
| 298 | *IOP3XX_IABAR1 = 0x0; |
| 299 | *IOP3XX_IALR1 = 0x0; |
| 300 | |
| 301 | /* BAR 2 ( Disabled ) */ |
| 302 | *IOP3XX_IAUBAR2 = 0x0; |
| 303 | *IOP3XX_IABAR2 = 0x0; |
| 304 | *IOP3XX_IATVR2 = 0x0; |
| 305 | *IOP3XX_IALR2 = 0x0; |
| 306 | |
| 307 | /* BAR 3 ( Disabled ) */ |
| 308 | *IOP3XX_IAUBAR3 = 0x0; |
| 309 | *IOP3XX_IABAR3 = 0x0; |
| 310 | *IOP3XX_IATVR3 = 0x0; |
| 311 | *IOP3XX_IALR3 = 0x0; |
| 312 | |
| 313 | /* Clear the outbound windows */ |
| 314 | *IOP3XX_OIOWTVR = 0; |
| 315 | |
| 316 | /* Outbound window 0 */ |
| 317 | *IOP3XX_OMWTVR0 = 0; |
| 318 | *IOP3XX_OUMWTVR0 = 0; |
| 319 | |
| 320 | /* Outbound window 1 */ |
| 321 | *IOP3XX_OMWTVR1 = 0; |
| 322 | *IOP3XX_OUMWTVR1 = 0; |
| 323 | } |
| 324 | |
| 325 | /* Flag to determine whether the ATU is initialized and the PCI bus scanned */ |
| 326 | int init_atu; |
| 327 | |
Dan Williams | c34002c | 2008-03-26 19:12:38 -0700 | [diff] [blame] | 328 | int iop3xx_get_init_atu(void) { |
| 329 | /* check if default has been overridden */ |
| 330 | if (init_atu != IOP3XX_INIT_ATU_DEFAULT) |
| 331 | return init_atu; |
| 332 | else |
| 333 | return IOP3XX_INIT_ATU_DISABLE; |
| 334 | } |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 335 | |
Dan Williams | c34002c | 2008-03-26 19:12:38 -0700 | [diff] [blame] | 336 | static void __init iop3xx_atu_debug(void) |
| 337 | { |
Russell King | c3a1c9c | 2008-03-26 18:42:10 -0700 | [diff] [blame] | 338 | DBG("PCI: Intel IOP3xx PCI init.\n"); |
| 339 | DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", |
| 340 | *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); |
| 341 | DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", |
| 342 | *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); |
| 343 | DBG("PCI: Outbound IO window: PCI 0x%08x\n", |
| 344 | *IOP3XX_OIOWTVR); |
| 345 | |
| 346 | DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", |
| 347 | *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); |
| 348 | DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", |
| 349 | *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); |
| 350 | DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", |
| 351 | *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); |
| 352 | DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", |
| 353 | *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); |
| 354 | |
| 355 | DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", |
| 356 | 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); |
| 357 | |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 358 | DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 359 | DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 360 | |
Kirill A. Shutemov | 6338a6a | 2010-07-22 13:18:19 +0100 | [diff] [blame] | 361 | hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort"); |
Lennert Buytenhek | 0cb015f | 2006-09-18 23:16:23 +0100 | [diff] [blame] | 362 | } |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 363 | |
Dan Williams | c34002c | 2008-03-26 19:12:38 -0700 | [diff] [blame] | 364 | /* for platforms that might be host-bus-adapters */ |
| 365 | void __init iop3xx_pci_preinit_cond(void) |
| 366 | { |
| 367 | if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { |
| 368 | iop3xx_atu_disable(); |
| 369 | iop3xx_atu_setup(); |
| 370 | iop3xx_atu_debug(); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | void __init iop3xx_pci_preinit(void) |
| 375 | { |
Rob Herring | c9d95fb | 2011-06-28 21:16:13 -0500 | [diff] [blame] | 376 | pcibios_min_io = 0; |
| 377 | pcibios_min_mem = 0; |
| 378 | |
Dan Williams | c34002c | 2008-03-26 19:12:38 -0700 | [diff] [blame] | 379 | iop3xx_atu_disable(); |
| 380 | iop3xx_atu_setup(); |
| 381 | iop3xx_atu_debug(); |
| 382 | } |
| 383 | |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 384 | /* allow init_atu to be user overridden */ |
| 385 | static int __init iop3xx_init_atu_setup(char *str) |
| 386 | { |
| 387 | init_atu = IOP3XX_INIT_ATU_DEFAULT; |
| 388 | if (str) { |
| 389 | while (*str != '\0') { |
| 390 | switch (*str) { |
| 391 | case 'y': |
| 392 | case 'Y': |
| 393 | init_atu = IOP3XX_INIT_ATU_ENABLE; |
| 394 | break; |
| 395 | case 'n': |
| 396 | case 'N': |
| 397 | init_atu = IOP3XX_INIT_ATU_DISABLE; |
| 398 | break; |
| 399 | case ',': |
| 400 | case '=': |
| 401 | break; |
| 402 | default: |
| 403 | printk(KERN_DEBUG "\"%s\" malformed at " |
| 404 | "character: \'%c\'", |
Harvey Harrison | 8e86f42 | 2008-03-04 15:08:02 -0800 | [diff] [blame] | 405 | __func__, |
Dan Williams | e90ddd8 | 2007-05-02 17:59:44 +0100 | [diff] [blame] | 406 | *str); |
| 407 | *(str + 1) = '\0'; |
| 408 | } |
| 409 | str++; |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | return 1; |
| 414 | } |
| 415 | |
| 416 | __setup("iop3xx_init_atu", iop3xx_init_atu_setup); |
| 417 | |