blob: 38990a77d7b780081167fa14ded35745025553c1 [file] [log] [blame]
Takashi Iwai14752412015-04-14 12:15:47 +02001/*
2 * HD-audio stream operations
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/export.h>
Takashi Iwai5f26fac2015-04-16 11:31:12 +02008#include <linux/clocksource.h>
Takashi Iwai14752412015-04-14 12:15:47 +02009#include <sound/core.h>
10#include <sound/pcm.h>
11#include <sound/hdaudio.h>
12#include <sound/hda_register.h>
Libin Yang598dfb52015-05-12 09:43:20 +080013#include "trace.h"
Takashi Iwai14752412015-04-14 12:15:47 +020014
15/**
16 * snd_hdac_stream_init - initialize each stream (aka device)
17 * @bus: HD-audio core bus
18 * @azx_dev: HD-audio core stream object to initialize
19 * @idx: stream index number
20 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
21 * @tag: the tag id to assign
22 *
23 * Assign the starting bdl address to each stream (device) and initialize.
24 */
25void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
26 int idx, int direction, int tag)
27{
28 azx_dev->bus = bus;
Takashi Iwai14752412015-04-14 12:15:47 +020029 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
30 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
31 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
32 azx_dev->sd_int_sta_mask = 1 << idx;
33 azx_dev->index = idx;
34 azx_dev->direction = direction;
35 azx_dev->stream_tag = tag;
Takashi Iwai8f3f6002015-04-14 12:53:28 +020036 snd_hdac_dsp_lock_init(azx_dev);
Takashi Iwai14752412015-04-14 12:15:47 +020037 list_add_tail(&azx_dev->list, &bus->stream_list);
38}
39EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
40
41/**
42 * snd_hdac_stream_start - start a stream
43 * @azx_dev: HD-audio core stream to start
44 * @fresh_start: false = wallclock timestamp relative to period wallclock
45 *
46 * Start a stream, set start_wallclk and set the running flag.
47 */
48void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
49{
50 struct hdac_bus *bus = azx_dev->bus;
51
Libin Yang598dfb52015-05-12 09:43:20 +080052 trace_snd_hdac_stream_start(bus, azx_dev);
53
Takashi Iwai14752412015-04-14 12:15:47 +020054 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
55 if (!fresh_start)
56 azx_dev->start_wallclk -= azx_dev->period_wallclk;
57
58 /* enable SIE */
59 snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
60 /* set DMA start and interrupt mask */
61 snd_hdac_stream_updateb(azx_dev, SD_CTL,
62 0, SD_CTL_DMA_START | SD_INT_MASK);
63 azx_dev->running = true;
64}
65EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
66
67/**
68 * snd_hdac_stream_clear - stop a stream DMA
69 * @azx_dev: HD-audio core stream to stop
70 */
71void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
72{
73 snd_hdac_stream_updateb(azx_dev, SD_CTL,
74 SD_CTL_DMA_START | SD_INT_MASK, 0);
75 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
76 azx_dev->running = false;
77}
78EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
79
80/**
81 * snd_hdac_stream_stop - stop a stream
82 * @azx_dev: HD-audio core stream to stop
83 *
84 * Stop a stream DMA and disable stream interrupt
85 */
86void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
87{
Libin Yang598dfb52015-05-12 09:43:20 +080088 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
89
Takashi Iwai14752412015-04-14 12:15:47 +020090 snd_hdac_stream_clear(azx_dev);
91 /* disable SIE */
92 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
93}
94EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
95
96/**
97 * snd_hdac_stream_reset - reset a stream
98 * @azx_dev: HD-audio core stream to reset
99 */
100void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
101{
102 unsigned char val;
103 int timeout;
104
105 snd_hdac_stream_clear(azx_dev);
106
107 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
108 udelay(3);
109 timeout = 300;
110 do {
111 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
112 SD_CTL_STREAM_RESET;
113 if (val)
114 break;
115 } while (--timeout);
116 val &= ~SD_CTL_STREAM_RESET;
117 snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
118 udelay(3);
119
120 timeout = 300;
121 /* waiting for hardware to report that the stream is out of reset */
122 do {
123 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
124 SD_CTL_STREAM_RESET;
125 if (!val)
126 break;
127 } while (--timeout);
128
129 /* reset first position - may not be synced with hw at this time */
130 if (azx_dev->posbuf)
131 *azx_dev->posbuf = 0;
132}
133EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
134
135/**
136 * snd_hdac_stream_setup - set up the SD for streaming
137 * @azx_dev: HD-audio core stream to set up
138 */
139int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
140{
141 struct hdac_bus *bus = azx_dev->bus;
Takashi Iwai4214c532015-05-19 11:35:13 +0200142 struct snd_pcm_runtime *runtime;
Takashi Iwai14752412015-04-14 12:15:47 +0200143 unsigned int val;
144
Takashi Iwai4214c532015-05-19 11:35:13 +0200145 if (azx_dev->substream)
146 runtime = azx_dev->substream->runtime;
147 else
148 runtime = NULL;
Takashi Iwai14752412015-04-14 12:15:47 +0200149 /* make sure the run bit is zero for SD */
150 snd_hdac_stream_clear(azx_dev);
151 /* program the stream_tag */
152 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
153 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
154 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
155 if (!bus->snoop)
156 val |= SD_CTL_TRAFFIC_PRIO;
157 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
158
159 /* program the length of samples in cyclic buffer */
160 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
161
162 /* program the stream format */
163 /* this value needs to be the same as the one programmed */
164 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
165
166 /* program the stream LVI (last valid index) of the BDL */
167 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
168
169 /* program the BDL address */
170 /* lower BDL address */
171 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
172 /* upper BDL address */
173 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
174 upper_32_bits(azx_dev->bdl.addr));
175
176 /* enable the position buffer */
177 if (bus->use_posbuf && bus->posbuf.addr) {
178 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
179 snd_hdac_chip_writel(bus, DPLBASE,
180 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
181 }
182
183 /* set the interrupt enable bits in the descriptor control register */
184 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
185
186 if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
187 azx_dev->fifo_size =
188 snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
189 else
190 azx_dev->fifo_size = 0;
191
192 /* when LPIB delay correction gives a small negative value,
193 * we ignore it; currently set the threshold statically to
194 * 64 frames
195 */
Takashi Iwai4214c532015-05-19 11:35:13 +0200196 if (runtime && runtime->period_size > 64)
Takashi Iwai14752412015-04-14 12:15:47 +0200197 azx_dev->delay_negative_threshold =
198 -frames_to_bytes(runtime, 64);
199 else
200 azx_dev->delay_negative_threshold = 0;
201
202 /* wallclk has 24Mhz clock source */
Takashi Iwai4214c532015-05-19 11:35:13 +0200203 if (runtime)
204 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
Takashi Iwai14752412015-04-14 12:15:47 +0200205 runtime->rate) * 1000);
206
207 return 0;
208}
209EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
210
211/**
212 * snd_hdac_stream_cleanup - cleanup a stream
213 * @azx_dev: HD-audio core stream to clean up
214 */
215void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
216{
217 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
218 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
219 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
220 azx_dev->bufsize = 0;
221 azx_dev->period_bytes = 0;
222 azx_dev->format_val = 0;
223}
224EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
225
226/**
227 * snd_hdac_stream_assign - assign a stream for the PCM
228 * @bus: HD-audio core bus
229 * @substream: PCM substream to assign
230 *
231 * Look for an unused stream for the given PCM substream, assign it
232 * and return the stream object. If no stream is free, returns NULL.
233 * The function tries to keep using the same stream object when it's used
234 * beforehand. Also, when bus->reverse_assign flag is set, the last free
235 * or matching entry is returned. This is needed for some strange codecs.
236 */
237struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
238 struct snd_pcm_substream *substream)
239{
240 struct hdac_stream *azx_dev;
241 struct hdac_stream *res = NULL;
242
243 /* make a non-zero unique key for the substream */
244 int key = (substream->pcm->device << 16) | (substream->number << 2) |
245 (substream->stream + 1);
246
247 list_for_each_entry(azx_dev, &bus->stream_list, list) {
248 if (azx_dev->direction != substream->stream)
249 continue;
250 if (azx_dev->opened)
251 continue;
252 if (azx_dev->assigned_key == key) {
253 res = azx_dev;
254 break;
255 }
256 if (!res || bus->reverse_assign)
257 res = azx_dev;
258 }
259 if (res) {
260 spin_lock_irq(&bus->reg_lock);
261 res->opened = 1;
262 res->running = 0;
263 res->assigned_key = key;
264 res->substream = substream;
265 spin_unlock_irq(&bus->reg_lock);
266 }
267 return res;
268}
269EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
270
271/**
272 * snd_hdac_stream_release - release the assigned stream
273 * @azx_dev: HD-audio core stream to release
274 *
275 * Release the stream that has been assigned by snd_hdac_stream_assign().
276 */
277void snd_hdac_stream_release(struct hdac_stream *azx_dev)
278{
279 struct hdac_bus *bus = azx_dev->bus;
280
281 spin_lock_irq(&bus->reg_lock);
282 azx_dev->opened = 0;
283 azx_dev->running = 0;
284 azx_dev->substream = NULL;
285 spin_unlock_irq(&bus->reg_lock);
286}
287EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
288
Jeeja KP4308c9b2015-08-23 11:52:51 +0530289/**
290 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
291 * direction
292 *
293 * @bus: HD-audio core bus
294 * @dir: direction for the stream to be found
295 * @stream_tag: stream tag for stream to be found
296 */
297struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
298 int dir, int stream_tag)
299{
300 struct hdac_stream *s;
301
302 list_for_each_entry(s, &bus->stream_list, list) {
303 if (s->direction == dir && s->stream_tag == stream_tag)
304 return s;
305 }
306
307 return NULL;
308}
309EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
310
Takashi Iwai14752412015-04-14 12:15:47 +0200311/*
312 * set up a BDL entry
313 */
314static int setup_bdle(struct hdac_bus *bus,
315 struct snd_dma_buffer *dmab,
316 struct hdac_stream *azx_dev, __le32 **bdlp,
317 int ofs, int size, int with_ioc)
318{
319 __le32 *bdl = *bdlp;
320
321 while (size > 0) {
322 dma_addr_t addr;
323 int chunk;
324
325 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
326 return -EINVAL;
327
328 addr = snd_sgbuf_get_addr(dmab, ofs);
329 /* program the address field of the BDL entry */
330 bdl[0] = cpu_to_le32((u32)addr);
331 bdl[1] = cpu_to_le32(upper_32_bits(addr));
332 /* program the size field of the BDL entry */
333 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
334 /* one BDLE cannot cross 4K boundary on CTHDA chips */
335 if (bus->align_bdle_4k) {
336 u32 remain = 0x1000 - (ofs & 0xfff);
337
338 if (chunk > remain)
339 chunk = remain;
340 }
341 bdl[2] = cpu_to_le32(chunk);
342 /* program the IOC to enable interrupt
343 * only when the whole fragment is processed
344 */
345 size -= chunk;
346 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
347 bdl += 4;
348 azx_dev->frags++;
349 ofs += chunk;
350 }
351 *bdlp = bdl;
352 return ofs;
353}
354
355/**
356 * snd_hdac_stream_setup_periods - set up BDL entries
357 * @azx_dev: HD-audio core stream to set up
358 *
359 * Set up the buffer descriptor table of the given stream based on the
360 * period and buffer sizes of the assigned PCM substream.
361 */
362int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
363{
364 struct hdac_bus *bus = azx_dev->bus;
365 struct snd_pcm_substream *substream = azx_dev->substream;
366 struct snd_pcm_runtime *runtime = substream->runtime;
367 __le32 *bdl;
368 int i, ofs, periods, period_bytes;
369 int pos_adj, pos_align;
370
371 /* reset BDL address */
372 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
373 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
374
375 period_bytes = azx_dev->period_bytes;
376 periods = azx_dev->bufsize / period_bytes;
377
378 /* program the initial BDL entries */
379 bdl = (__le32 *)azx_dev->bdl.area;
380 ofs = 0;
381 azx_dev->frags = 0;
382
383 pos_adj = bus->bdl_pos_adj;
384 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
385 pos_align = pos_adj;
386 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
387 if (!pos_adj)
388 pos_adj = pos_align;
389 else
390 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
391 pos_align;
392 pos_adj = frames_to_bytes(runtime, pos_adj);
393 if (pos_adj >= period_bytes) {
394 dev_warn(bus->dev, "Too big adjustment %d\n",
395 pos_adj);
396 pos_adj = 0;
397 } else {
398 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
399 azx_dev,
400 &bdl, ofs, pos_adj, true);
401 if (ofs < 0)
402 goto error;
403 }
404 } else
405 pos_adj = 0;
406
407 for (i = 0; i < periods; i++) {
408 if (i == periods - 1 && pos_adj)
409 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
410 azx_dev, &bdl, ofs,
411 period_bytes - pos_adj, 0);
412 else
413 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
414 azx_dev, &bdl, ofs,
415 period_bytes,
416 !azx_dev->no_period_wakeup);
417 if (ofs < 0)
418 goto error;
419 }
420 return 0;
421
422 error:
423 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
424 azx_dev->bufsize, period_bytes);
425 return -EINVAL;
426}
427EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
428
Takashi Iwai78dd5e22015-10-28 12:26:48 +0100429/**
430 * snd_hdac_stream_set_params - set stream parameters
Jeeja KP86f65012015-04-17 17:58:58 +0530431 * @azx_dev: HD-audio core stream for which parameters are to be set
432 * @format_val: format value parameter
433 *
434 * Setup the HD-audio core stream parameters from substream of the stream
435 * and passed format value
436 */
437int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
438 unsigned int format_val)
439{
440
441 unsigned int bufsize, period_bytes;
442 struct snd_pcm_substream *substream = azx_dev->substream;
443 struct snd_pcm_runtime *runtime;
444 int err;
445
446 if (!substream)
447 return -EINVAL;
448 runtime = substream->runtime;
449 bufsize = snd_pcm_lib_buffer_bytes(substream);
450 period_bytes = snd_pcm_lib_period_bytes(substream);
451
452 if (bufsize != azx_dev->bufsize ||
453 period_bytes != azx_dev->period_bytes ||
454 format_val != azx_dev->format_val ||
455 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
456 azx_dev->bufsize = bufsize;
457 azx_dev->period_bytes = period_bytes;
458 azx_dev->format_val = format_val;
459 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
460 err = snd_hdac_stream_setup_periods(azx_dev);
461 if (err < 0)
462 return err;
463 }
464 return 0;
465}
466EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
467
Takashi Iwai14752412015-04-14 12:15:47 +0200468static cycle_t azx_cc_read(const struct cyclecounter *cc)
469{
470 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
471
472 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
473}
474
475static void azx_timecounter_init(struct hdac_stream *azx_dev,
476 bool force, cycle_t last)
477{
478 struct timecounter *tc = &azx_dev->tc;
479 struct cyclecounter *cc = &azx_dev->cc;
480 u64 nsec;
481
482 cc->read = azx_cc_read;
483 cc->mask = CLOCKSOURCE_MASK(32);
484
485 /*
486 * Converting from 24 MHz to ns means applying a 125/3 factor.
487 * To avoid any saturation issues in intermediate operations,
488 * the 125 factor is applied first. The division is applied
489 * last after reading the timecounter value.
490 * Applying the 1/3 factor as part of the multiplication
491 * requires at least 20 bits for a decent precision, however
492 * overflows occur after about 4 hours or less, not a option.
493 */
494
495 cc->mult = 125; /* saturation after 195 years */
496 cc->shift = 0;
497
498 nsec = 0; /* audio time is elapsed time since trigger */
499 timecounter_init(tc, cc, nsec);
500 if (force) {
501 /*
502 * force timecounter to use predefined value,
503 * used for synchronized starts
504 */
505 tc->cycle_last = last;
506 }
507}
508
509/**
510 * snd_hdac_stream_timecounter_init - initialize time counter
511 * @azx_dev: HD-audio core stream (master stream)
512 * @streams: bit flags of streams to set up
513 *
514 * Initializes the time counter of streams marked by the bit flags (each
515 * bit corresponds to the stream index).
516 * The trigger timestamp of PCM substream assigned to the given stream is
517 * updated accordingly, too.
518 */
519void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
520 unsigned int streams)
521{
522 struct hdac_bus *bus = azx_dev->bus;
523 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
524 struct hdac_stream *s;
525 bool inited = false;
526 cycle_t cycle_last = 0;
527 int i = 0;
528
529 list_for_each_entry(s, &bus->stream_list, list) {
530 if (streams & (1 << i)) {
531 azx_timecounter_init(s, inited, cycle_last);
532 if (!inited) {
533 inited = true;
534 cycle_last = s->tc.cycle_last;
535 }
536 }
537 i++;
538 }
539
540 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
541 runtime->trigger_tstamp_latched = true;
542}
543EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
544
545/**
546 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
547 * @azx_dev: HD-audio core stream (master stream)
548 * @streams: bit flags of streams to sync
549 */
550void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
551 unsigned int streams, unsigned int reg)
552{
553 struct hdac_bus *bus = azx_dev->bus;
554 unsigned int val;
555
556 if (!reg)
557 reg = AZX_REG_SSYNC;
558 val = _snd_hdac_chip_read(l, bus, reg);
559 if (set)
560 val |= streams;
561 else
562 val &= ~streams;
563 _snd_hdac_chip_write(l, bus, reg, val);
564}
565EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
566
567/**
568 * snd_hdac_stream_sync - sync with start/strop trigger operation
569 * @azx_dev: HD-audio core stream (master stream)
570 * @start: true = start, false = stop
571 * @streams: bit flags of streams to sync
572 *
573 * For @start = true, wait until all FIFOs get ready.
574 * For @start = false, wait until all RUN bits are cleared.
575 */
576void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
577 unsigned int streams)
578{
579 struct hdac_bus *bus = azx_dev->bus;
580 int i, nwait, timeout;
581 struct hdac_stream *s;
582
583 for (timeout = 5000; timeout; timeout--) {
584 nwait = 0;
585 i = 0;
586 list_for_each_entry(s, &bus->stream_list, list) {
587 if (streams & (1 << i)) {
588 if (start) {
589 /* check FIFO gets ready */
590 if (!(snd_hdac_stream_readb(s, SD_STS) &
591 SD_STS_FIFO_READY))
592 nwait++;
593 } else {
594 /* check RUN bit is cleared */
595 if (snd_hdac_stream_readb(s, SD_CTL) &
596 SD_CTL_DMA_START)
597 nwait++;
598 }
599 }
600 i++;
601 }
602 if (!nwait)
603 break;
604 cpu_relax();
605 }
606}
607EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
Takashi Iwai8f3f6002015-04-14 12:53:28 +0200608
609#ifdef CONFIG_SND_HDA_DSP_LOADER
610/**
611 * snd_hdac_dsp_prepare - prepare for DSP loading
612 * @azx_dev: HD-audio core stream used for DSP loading
613 * @format: HD-audio stream format
614 * @byte_size: data chunk byte size
615 * @bufp: allocated buffer
616 *
617 * Allocate the buffer for the given size and set up the given stream for
618 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
619 */
620int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
621 unsigned int byte_size, struct snd_dma_buffer *bufp)
622{
623 struct hdac_bus *bus = azx_dev->bus;
624 u32 *bdl;
625 int err;
626
627 snd_hdac_dsp_lock(azx_dev);
628 spin_lock_irq(&bus->reg_lock);
629 if (azx_dev->running || azx_dev->locked) {
630 spin_unlock_irq(&bus->reg_lock);
631 err = -EBUSY;
632 goto unlock;
633 }
634 azx_dev->locked = true;
635 spin_unlock_irq(&bus->reg_lock);
636
637 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
638 byte_size, bufp);
639 if (err < 0)
640 goto err_alloc;
641
Takashi Iwai4214c532015-05-19 11:35:13 +0200642 azx_dev->substream = NULL;
Takashi Iwai8f3f6002015-04-14 12:53:28 +0200643 azx_dev->bufsize = byte_size;
644 azx_dev->period_bytes = byte_size;
645 azx_dev->format_val = format;
646
647 snd_hdac_stream_reset(azx_dev);
648
649 /* reset BDL address */
650 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
651 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
652
653 azx_dev->frags = 0;
654 bdl = (u32 *)azx_dev->bdl.area;
655 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
656 if (err < 0)
657 goto error;
658
659 snd_hdac_stream_setup(azx_dev);
660 snd_hdac_dsp_unlock(azx_dev);
661 return azx_dev->stream_tag;
662
663 error:
664 bus->io_ops->dma_free_pages(bus, bufp);
665 err_alloc:
666 spin_lock_irq(&bus->reg_lock);
667 azx_dev->locked = false;
668 spin_unlock_irq(&bus->reg_lock);
669 unlock:
670 snd_hdac_dsp_unlock(azx_dev);
671 return err;
672}
673EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
674
675/**
676 * snd_hdac_dsp_trigger - start / stop DSP loading
677 * @azx_dev: HD-audio core stream used for DSP loading
678 * @start: trigger start or stop
679 */
680void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
681{
682 if (start)
683 snd_hdac_stream_start(azx_dev, true);
684 else
685 snd_hdac_stream_stop(azx_dev);
686}
687EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
688
689/**
690 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
691 * @azx_dev: HD-audio core stream used for DSP loading
692 * @dmab: buffer used by DSP loading
693 */
694void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
695 struct snd_dma_buffer *dmab)
696{
697 struct hdac_bus *bus = azx_dev->bus;
698
699 if (!dmab->area || !azx_dev->locked)
700 return;
701
702 snd_hdac_dsp_lock(azx_dev);
703 /* reset BDL address */
704 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
705 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
706 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
707 azx_dev->bufsize = 0;
708 azx_dev->period_bytes = 0;
709 azx_dev->format_val = 0;
710
711 bus->io_ops->dma_free_pages(bus, dmab);
712 dmab->area = NULL;
713
714 spin_lock_irq(&bus->reg_lock);
715 azx_dev->locked = false;
716 spin_unlock_irq(&bus->reg_lock);
717 snd_hdac_dsp_unlock(azx_dev);
718}
719EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
720#endif /* CONFIG_SND_HDA_DSP_LOADER */