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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050040#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050042#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include "sata_promise.h"
45
46#define DRV_NAME "sata_sx4"
Jeff Garzik8bc3fc42007-05-21 20:26:38 -040047#define DRV_VERSION "0.11"
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49
50enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090051 PDC_MMIO_BAR = 3,
52 PDC_DIMM_BAR = 4,
53
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
55
56 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
57 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
58 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
59 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
60
61 PDC_20621_SEQCTL = 0x400,
62 PDC_20621_SEQMASK = 0x480,
63 PDC_20621_GENERAL_CTL = 0x484,
64 PDC_20621_PAGE_SIZE = (32 * 1024),
65
66 /* chosen, not constant, values; we design our own DIMM mem map */
67 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
68 PDC_20621_DIMM_BASE = 0x00200000,
69 PDC_20621_DIMM_DATA = (64 * 1024),
70 PDC_DIMM_DATA_STEP = (256 * 1024),
71 PDC_DIMM_WINDOW_STEP = (8 * 1024),
72 PDC_DIMM_HOST_PRD = (6 * 1024),
73 PDC_DIMM_HOST_PKT = (128 * 0),
74 PDC_DIMM_HPKT_PRD = (128 * 1),
75 PDC_DIMM_ATA_PKT = (128 * 2),
76 PDC_DIMM_APKT_PRD = (128 * 3),
77 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
78 PDC_PAGE_WINDOW = 0x40,
79 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
80 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
81 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
82
83 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
84
85 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
86 (1<<23),
87
88 board_20621 = 0, /* FastTrak S150 SX4 */
89
Jeff Garzikb2d46b62007-05-27 22:58:54 -040090 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
91 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
Linus Torvalds1da177e2005-04-16 15:20:36 -070092
93 PDC_MAX_HDMA = 32,
94 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
95
Jeff Garzikb2d46b62007-05-27 22:58:54 -040096 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
97 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
98 PDC_I2C_CONTROL = 0x48,
99 PDC_I2C_ADDR_DATA = 0x4C,
100 PDC_DIMM0_CONTROL = 0x80,
101 PDC_DIMM1_CONTROL = 0x84,
102 PDC_SDRAM_CONTROL = 0x88,
103 PDC_I2C_WRITE = 0, /* master -> slave */
104 PDC_I2C_READ = (1 << 6), /* master <- slave */
105 PDC_I2C_START = (1 << 7), /* start I2C proto */
106 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
107 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
108 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
109 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
110 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
111 PDC_DIMM_SPD_ROW_NUM = 3,
112 PDC_DIMM_SPD_COLUMN_NUM = 4,
113 PDC_DIMM_SPD_MODULE_ROW = 5,
114 PDC_DIMM_SPD_TYPE = 11,
115 PDC_DIMM_SPD_FRESH_RATE = 12,
116 PDC_DIMM_SPD_BANK_NUM = 17,
117 PDC_DIMM_SPD_CAS_LATENCY = 18,
118 PDC_DIMM_SPD_ATTRIBUTE = 21,
119 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
120 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
121 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
122 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
123 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
124 PDC_CTL_STATUS = 0x08,
125 PDC_DIMM_WINDOW_CTLR = 0x0C,
126 PDC_TIME_CONTROL = 0x3C,
127 PDC_TIME_PERIOD = 0x40,
128 PDC_TIME_COUNTER = 0x44,
129 PDC_GENERAL_CTLR = 0x484,
130 PCI_PLL_INIT = 0x8A531824,
131 PCI_X_TCOUNT = 0xEE1E5CFF,
132
133 /* PDC_TIME_CONTROL bits */
134 PDC_TIMER_BUZZER = (1 << 10),
135 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
136 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
137 PDC_TIMER_ENABLE = (1 << 7),
138 PDC_TIMER_MASK_INT = (1 << 5),
139 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
140 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
141 PDC_TIMER_ENABLE |
142 PDC_TIMER_MASK_INT,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143};
144
145
146struct pdc_port_priv {
147 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
148 u8 *pkt;
149 dma_addr_t pkt_dma;
150};
151
152struct pdc_host_priv {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 unsigned int doing_hdma;
154 unsigned int hdma_prod;
155 unsigned int hdma_cons;
156 struct {
157 struct ata_queued_cmd *qc;
158 unsigned int seq;
159 unsigned long pkt_ofs;
160 } hdma[32];
161};
162
163
164static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165static void pdc_eng_timeout(struct ata_port *ap);
166static void pdc_20621_phy_reset (struct ata_port *ap);
167static int pdc_port_start(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
Jeff Garzik057ace52005-10-22 14:27:05 -0400169static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
170static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
Tejun Heo4447d352007-04-17 23:44:08 +0900171static unsigned int pdc20621_dimm_init(struct ata_host *host);
172static int pdc20621_detect_dimm(struct ata_host *host);
173static unsigned int pdc20621_i2c_read(struct ata_host *host,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 u32 device, u32 subaddr, u32 *pdata);
Tejun Heo4447d352007-04-17 23:44:08 +0900175static int pdc20621_prog_dimm0(struct ata_host *host);
176static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177#ifdef ATA_VERBOSE_DEBUG
Tejun Heo4447d352007-04-17 23:44:08 +0900178static void pdc20621_get_from_dimm(struct ata_host *host,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 void *psource, u32 offset, u32 size);
180#endif
Tejun Heo4447d352007-04-17 23:44:08 +0900181static void pdc20621_put_to_dimm(struct ata_host *host,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182 void *psource, u32 offset, u32 size);
183static void pdc20621_irq_clear(struct ata_port *ap);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900184static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185
186
Jeff Garzik193515d2005-11-07 00:59:37 -0500187static struct scsi_host_template pdc_sata_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 .module = THIS_MODULE,
189 .name = DRV_NAME,
190 .ioctl = ata_scsi_ioctl,
191 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 .can_queue = ATA_DEF_QUEUE,
193 .this_id = ATA_SHT_THIS_ID,
194 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
196 .emulated = ATA_SHT_EMULATED,
197 .use_clustering = ATA_SHT_USE_CLUSTERING,
198 .proc_name = DRV_NAME,
199 .dma_boundary = ATA_DMA_BOUNDARY,
200 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900201 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203};
204
Jeff Garzik057ace52005-10-22 14:27:05 -0400205static const struct ata_port_operations pdc_20621_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 .port_disable = ata_port_disable,
207 .tf_load = pdc_tf_load_mmio,
208 .tf_read = ata_tf_read,
209 .check_status = ata_check_status,
210 .exec_command = pdc_exec_command_mmio,
211 .dev_select = ata_std_dev_select,
212 .phy_reset = pdc_20621_phy_reset,
213 .qc_prep = pdc20621_qc_prep,
214 .qc_issue = pdc20621_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900215 .data_xfer = ata_data_xfer,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 .eng_timeout = pdc_eng_timeout,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 .irq_clear = pdc20621_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900218 .irq_on = ata_irq_on,
219 .irq_ack = ata_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 .port_start = pdc_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221};
222
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100223static const struct ata_port_info pdc_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 /* board_20621 */
225 {
Jeff Garzikcca39742006-08-24 03:19:22 -0400226 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Jeff Garzik50630192005-12-13 02:29:45 -0500227 ATA_FLAG_SRST | ATA_FLAG_MMIO |
Albert Lee1f3461a2006-05-23 18:12:30 +0800228 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 .pio_mask = 0x1f, /* pio0-4 */
230 .mwdma_mask = 0x07, /* mwdma0-2 */
231 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
232 .port_ops = &pdc_20621_ops,
233 },
234
235};
236
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500237static const struct pci_device_id pdc_sata_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400238 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
239
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 { } /* terminate list */
241};
242
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243static struct pci_driver pdc_sata_pci_driver = {
244 .name = DRV_NAME,
245 .id_table = pdc_sata_pci_tbl,
246 .probe = pdc_sata_init_one,
247 .remove = ata_pci_remove_one,
248};
249
250
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251static int pdc_port_start(struct ata_port *ap)
252{
Jeff Garzikcca39742006-08-24 03:19:22 -0400253 struct device *dev = ap->host->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 struct pdc_port_priv *pp;
255 int rc;
256
257 rc = ata_port_start(ap);
258 if (rc)
259 return rc;
260
Tejun Heo24dc5f32007-01-20 16:00:28 +0900261 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
262 if (!pp)
263 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
Tejun Heo24dc5f32007-01-20 16:00:28 +0900265 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
266 if (!pp->pkt)
267 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268
269 ap->private_data = pp;
270
271 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272}
273
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274static void pdc_20621_phy_reset (struct ata_port *ap)
275{
276 VPRINTK("ENTER\n");
277 ap->cbl = ATA_CBL_SATA;
278 ata_port_probe(ap);
279 ata_bus_reset(ap);
280}
281
282static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
283 unsigned int portno,
284 unsigned int total_len)
285{
286 u32 addr;
287 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
288 u32 *buf32 = (u32 *) buf;
289
290 /* output ATA packet S/G table */
291 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
292 (PDC_DIMM_DATA_STEP * portno);
293 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
294 buf32[dw] = cpu_to_le32(addr);
295 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
296
297 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
298 PDC_20621_DIMM_BASE +
299 (PDC_DIMM_WINDOW_STEP * portno) +
300 PDC_DIMM_APKT_PRD,
301 buf32[dw], buf32[dw + 1]);
302}
303
304static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
305 unsigned int portno,
306 unsigned int total_len)
307{
308 u32 addr;
309 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
310 u32 *buf32 = (u32 *) buf;
311
312 /* output Host DMA packet S/G table */
313 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
314 (PDC_DIMM_DATA_STEP * portno);
315
316 buf32[dw] = cpu_to_le32(addr);
317 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
318
319 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
320 PDC_20621_DIMM_BASE +
321 (PDC_DIMM_WINDOW_STEP * portno) +
322 PDC_DIMM_HPKT_PRD,
323 buf32[dw], buf32[dw + 1]);
324}
325
326static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
327 unsigned int devno, u8 *buf,
328 unsigned int portno)
329{
330 unsigned int i, dw;
331 u32 *buf32 = (u32 *) buf;
332 u8 dev_reg;
333
334 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
335 (PDC_DIMM_WINDOW_STEP * portno) +
336 PDC_DIMM_APKT_PRD;
337 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
338
339 i = PDC_DIMM_ATA_PKT;
340
341 /*
342 * Set up ATA packet
343 */
344 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
345 buf[i++] = PDC_PKT_READ;
346 else if (tf->protocol == ATA_PROT_NODATA)
347 buf[i++] = PDC_PKT_NODATA;
348 else
349 buf[i++] = 0;
350 buf[i++] = 0; /* reserved */
351 buf[i++] = portno + 1; /* seq. id */
352 buf[i++] = 0xff; /* delay seq. id */
353
354 /* dimm dma S/G, and next-pkt */
355 dw = i >> 2;
356 if (tf->protocol == ATA_PROT_NODATA)
357 buf32[dw] = 0;
358 else
359 buf32[dw] = cpu_to_le32(dimm_sg);
360 buf32[dw + 1] = 0;
361 i += 8;
362
363 if (devno == 0)
364 dev_reg = ATA_DEVICE_OBS;
365 else
366 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
367
368 /* select device */
369 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
370 buf[i++] = dev_reg;
371
372 /* device control register */
373 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
374 buf[i++] = tf->ctl;
375
376 return i;
377}
378
379static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
380 unsigned int portno)
381{
382 unsigned int dw;
383 u32 tmp, *buf32 = (u32 *) buf;
384
385 unsigned int host_sg = PDC_20621_DIMM_BASE +
386 (PDC_DIMM_WINDOW_STEP * portno) +
387 PDC_DIMM_HOST_PRD;
388 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
389 (PDC_DIMM_WINDOW_STEP * portno) +
390 PDC_DIMM_HPKT_PRD;
391 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
392 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
393
394 dw = PDC_DIMM_HOST_PKT >> 2;
395
396 /*
397 * Set up Host DMA packet
398 */
399 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
400 tmp = PDC_PKT_READ;
401 else
402 tmp = 0;
403 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
404 tmp |= (0xff << 24); /* delay seq. id */
405 buf32[dw + 0] = cpu_to_le32(tmp);
406 buf32[dw + 1] = cpu_to_le32(host_sg);
407 buf32[dw + 2] = cpu_to_le32(dimm_sg);
408 buf32[dw + 3] = 0;
409
410 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
411 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
412 PDC_DIMM_HOST_PKT,
413 buf32[dw + 0],
414 buf32[dw + 1],
415 buf32[dw + 2],
416 buf32[dw + 3]);
417}
418
419static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
420{
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400421 struct scatterlist *sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 struct ata_port *ap = qc->ap;
423 struct pdc_port_priv *pp = ap->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900424 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
425 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 unsigned int portno = ap->port_no;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400427 unsigned int i, idx, total_len = 0, sgt_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
429
Tejun Heobeec7db2006-02-11 19:11:13 +0900430 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431
Tejun Heo44877b42007-02-21 01:06:51 +0900432 VPRINTK("ata%u: ENTER\n", ap->print_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433
434 /* hard-code chip #0 */
435 mmio += PDC_CHIP0_OFS;
436
437 /*
438 * Build S/G table
439 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 idx = 0;
Jeff Garzikcedc9a42005-10-05 07:13:30 -0400441 ata_for_each_sg(sg, qc) {
442 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
443 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
444 total_len += sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 }
446 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
447 sgt_len = idx * 4;
448
449 /*
450 * Build ATA, host DMA packets
451 */
452 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
453 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
454
455 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
456 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
457
458 if (qc->tf.flags & ATA_TFLAG_LBA48)
459 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
460 else
461 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
462
463 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
464
465 /* copy three S/G tables and two packets to DIMM MMIO window */
466 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
467 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
468 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
469 PDC_DIMM_HOST_PRD,
470 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
471
472 /* force host FIFO dump */
473 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
474
475 readl(dimm_mmio); /* MMIO PCI posting flush */
476
477 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
478}
479
480static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
481{
482 struct ata_port *ap = qc->ap;
483 struct pdc_port_priv *pp = ap->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900484 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
485 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486 unsigned int portno = ap->port_no;
487 unsigned int i;
488
Tejun Heo44877b42007-02-21 01:06:51 +0900489 VPRINTK("ata%u: ENTER\n", ap->print_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490
491 /* hard-code chip #0 */
492 mmio += PDC_CHIP0_OFS;
493
494 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
495
496 if (qc->tf.flags & ATA_TFLAG_LBA48)
497 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
498 else
499 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
500
501 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
502
503 /* copy three S/G tables and two packets to DIMM MMIO window */
504 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
505 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
506
507 /* force host FIFO dump */
508 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
509
510 readl(dimm_mmio); /* MMIO PCI posting flush */
511
512 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
513}
514
515static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
516{
517 switch (qc->tf.protocol) {
518 case ATA_PROT_DMA:
519 pdc20621_dma_prep(qc);
520 break;
521 case ATA_PROT_NODATA:
522 pdc20621_nodata_prep(qc);
523 break;
524 default:
525 break;
526 }
527}
528
529static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
530 unsigned int seq,
531 u32 pkt_ofs)
532{
533 struct ata_port *ap = qc->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400534 struct ata_host *host = ap->host;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900535 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536
537 /* hard-code chip #0 */
538 mmio += PDC_CHIP0_OFS;
539
540 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
541 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
542
543 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
544 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
545}
546
547static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
548 unsigned int seq,
549 u32 pkt_ofs)
550{
551 struct ata_port *ap = qc->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400552 struct pdc_host_priv *pp = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
554
555 if (!pp->doing_hdma) {
556 __pdc20621_push_hdma(qc, seq, pkt_ofs);
557 pp->doing_hdma = 1;
558 return;
559 }
560
561 pp->hdma[idx].qc = qc;
562 pp->hdma[idx].seq = seq;
563 pp->hdma[idx].pkt_ofs = pkt_ofs;
564 pp->hdma_prod++;
565}
566
567static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
568{
569 struct ata_port *ap = qc->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400570 struct pdc_host_priv *pp = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
572
573 /* if nothing on queue, we're done */
574 if (pp->hdma_prod == pp->hdma_cons) {
575 pp->doing_hdma = 0;
576 return;
577 }
578
579 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
580 pp->hdma[idx].pkt_ofs);
581 pp->hdma_cons++;
582}
583
584#ifdef ATA_VERBOSE_DEBUG
585static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
586{
587 struct ata_port *ap = qc->ap;
588 unsigned int port_no = ap->port_no;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900589 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590
591 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
592 dimm_mmio += PDC_DIMM_HOST_PKT;
593
594 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
595 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
596 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
597 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
598}
599#else
600static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
601#endif /* ATA_VERBOSE_DEBUG */
602
603static void pdc20621_packet_start(struct ata_queued_cmd *qc)
604{
605 struct ata_port *ap = qc->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400606 struct ata_host *host = ap->host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607 unsigned int port_no = ap->port_no;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900608 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
610 u8 seq = (u8) (port_no + 1);
611 unsigned int port_ofs;
612
613 /* hard-code chip #0 */
614 mmio += PDC_CHIP0_OFS;
615
Tejun Heo44877b42007-02-21 01:06:51 +0900616 VPRINTK("ata%u: ENTER\n", ap->print_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617
618 wmb(); /* flush PRD, pkt writes */
619
620 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
621
622 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
623 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
624 seq += 4;
625
626 pdc20621_dump_hdma(qc);
627 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
628 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
629 port_ofs + PDC_DIMM_HOST_PKT,
630 port_ofs + PDC_DIMM_HOST_PKT,
631 seq);
632 } else {
633 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
634 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
635
636 writel(port_ofs + PDC_DIMM_ATA_PKT,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900637 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
638 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
640 port_ofs + PDC_DIMM_ATA_PKT,
641 port_ofs + PDC_DIMM_ATA_PKT,
642 seq);
643 }
644}
645
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900646static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647{
648 switch (qc->tf.protocol) {
649 case ATA_PROT_DMA:
650 case ATA_PROT_NODATA:
651 pdc20621_packet_start(qc);
652 return 0;
653
654 case ATA_PROT_ATAPI_DMA:
655 BUG();
656 break;
657
658 default:
659 break;
660 }
661
662 return ata_qc_issue_prot(qc);
663}
664
665static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
666 struct ata_queued_cmd *qc,
667 unsigned int doing_hdma,
Jeff Garzikea6ba102005-08-30 05:18:18 -0400668 void __iomem *mmio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669{
670 unsigned int port_no = ap->port_no;
671 unsigned int port_ofs =
672 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
673 u8 status;
674 unsigned int handled = 0;
675
676 VPRINTK("ENTER\n");
677
678 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
679 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
680
681 /* step two - DMA from DIMM to host */
682 if (doing_hdma) {
Tejun Heo44877b42007-02-21 01:06:51 +0900683 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
685 /* get drive status; clear intr; complete txn */
Albert Leea22e2eb2005-12-05 15:38:02 +0800686 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
687 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 pdc20621_pop_hdma(qc);
689 }
690
691 /* step one - exec ATA command */
692 else {
693 u8 seq = (u8) (port_no + 1 + 4);
Tejun Heo44877b42007-02-21 01:06:51 +0900694 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
696
697 /* submit hdma pkt */
698 pdc20621_dump_hdma(qc);
699 pdc20621_push_hdma(qc, seq,
700 port_ofs + PDC_DIMM_HOST_PKT);
701 }
702 handled = 1;
703
704 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
705
706 /* step one - DMA from host to DIMM */
707 if (doing_hdma) {
708 u8 seq = (u8) (port_no + 1);
Tejun Heo44877b42007-02-21 01:06:51 +0900709 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
711
712 /* submit ata pkt */
713 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
714 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
715 writel(port_ofs + PDC_DIMM_ATA_PKT,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900716 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
717 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 }
719
720 /* step two - execute ATA command */
721 else {
Tejun Heo44877b42007-02-21 01:06:51 +0900722 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
724 /* get drive status; clear intr; complete txn */
Albert Leea22e2eb2005-12-05 15:38:02 +0800725 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
726 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 pdc20621_pop_hdma(qc);
728 }
729 handled = 1;
730
731 /* command completion, but no data xfer */
732 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
733
734 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
735 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
Albert Leea22e2eb2005-12-05 15:38:02 +0800736 qc->err_mask |= ac_err_mask(status);
737 ata_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738 handled = 1;
739
740 } else {
741 ap->stats.idle_irq++;
742 }
743
744 return handled;
745}
746
747static void pdc20621_irq_clear(struct ata_port *ap)
748{
Jeff Garzikcca39742006-08-24 03:19:22 -0400749 struct ata_host *host = ap->host;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900750 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
752 mmio += PDC_CHIP0_OFS;
753
754 readl(mmio + PDC_20621_SEQMASK);
755}
756
David Howells7d12e782006-10-05 14:55:46 +0100757static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758{
Jeff Garzikcca39742006-08-24 03:19:22 -0400759 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 struct ata_port *ap;
761 u32 mask = 0;
762 unsigned int i, tmp, port_no;
763 unsigned int handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400764 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765
766 VPRINTK("ENTER\n");
767
Tejun Heo0d5ff562007-02-01 15:06:36 +0900768 if (!host || !host->iomap[PDC_MMIO_BAR]) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 VPRINTK("QUICK EXIT\n");
770 return IRQ_NONE;
771 }
772
Tejun Heo0d5ff562007-02-01 15:06:36 +0900773 mmio_base = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
775 /* reading should also clear interrupts */
776 mmio_base += PDC_CHIP0_OFS;
777 mask = readl(mmio_base + PDC_20621_SEQMASK);
778 VPRINTK("mask == 0x%x\n", mask);
779
780 if (mask == 0xffffffff) {
781 VPRINTK("QUICK EXIT 2\n");
782 return IRQ_NONE;
783 }
784 mask &= 0xffff; /* only 16 tags possible */
785 if (!mask) {
786 VPRINTK("QUICK EXIT 3\n");
787 return IRQ_NONE;
788 }
789
Jeff Garzikcca39742006-08-24 03:19:22 -0400790 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791
792 for (i = 1; i < 9; i++) {
793 port_no = i - 1;
794 if (port_no > 3)
795 port_no -= 4;
Jeff Garzikcca39742006-08-24 03:19:22 -0400796 if (port_no >= host->n_ports)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 ap = NULL;
798 else
Jeff Garzikcca39742006-08-24 03:19:22 -0400799 ap = host->ports[port_no];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 tmp = mask & (1 << i);
801 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
Tejun Heoc1389502005-08-22 14:59:24 +0900802 if (tmp && ap &&
Jeff Garzik029f5462006-04-02 10:30:40 -0400803 !(ap->flags & ATA_FLAG_DISABLED)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 struct ata_queued_cmd *qc;
805
806 qc = ata_qc_from_tag(ap, ap->active_tag);
Albert Leee50362e2005-09-27 17:39:50 +0800807 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 handled += pdc20621_host_intr(ap, qc, (i > 4),
809 mmio_base);
810 }
811 }
812
Jeff Garzikcca39742006-08-24 03:19:22 -0400813 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
815 VPRINTK("mask == 0x%x\n", mask);
816
817 VPRINTK("EXIT\n");
818
819 return IRQ_RETVAL(handled);
820}
821
822static void pdc_eng_timeout(struct ata_port *ap)
823{
824 u8 drv_stat;
Jeff Garzikcca39742006-08-24 03:19:22 -0400825 struct ata_host *host = ap->host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826 struct ata_queued_cmd *qc;
Jeff Garzikb8f61532005-08-25 22:01:20 -0400827 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828
829 DPRINTK("ENTER\n");
830
Jeff Garzikcca39742006-08-24 03:19:22 -0400831 spin_lock_irqsave(&host->lock, flags);
Jeff Garzikb8f61532005-08-25 22:01:20 -0400832
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 qc = ata_qc_from_tag(ap, ap->active_tag);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 switch (qc->tf.protocol) {
836 case ATA_PROT_DMA:
837 case ATA_PROT_NODATA:
Tejun Heof15a1da2006-05-15 20:57:56 +0900838 ata_port_printk(ap, KERN_ERR, "command timeout\n");
Albert Leea22e2eb2005-12-05 15:38:02 +0800839 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 break;
841
842 default:
843 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
844
Tejun Heof15a1da2006-05-15 20:57:56 +0900845 ata_port_printk(ap, KERN_ERR,
846 "unknown timeout, cmd 0x%x stat 0x%x\n",
847 qc->tf.command, drv_stat);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848
Albert Leea22e2eb2005-12-05 15:38:02 +0800849 qc->err_mask |= ac_err_mask(drv_stat);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 break;
851 }
852
Jeff Garzikcca39742006-08-24 03:19:22 -0400853 spin_unlock_irqrestore(&host->lock, flags);
Tejun Heof6379022006-02-10 15:10:48 +0900854 ata_eh_qc_complete(qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855 DPRINTK("EXIT\n");
856}
857
Jeff Garzik057ace52005-10-22 14:27:05 -0400858static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859{
860 WARN_ON (tf->protocol == ATA_PROT_DMA ||
861 tf->protocol == ATA_PROT_NODATA);
862 ata_tf_load(ap, tf);
863}
864
865
Jeff Garzik057ace52005-10-22 14:27:05 -0400866static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867{
868 WARN_ON (tf->protocol == ATA_PROT_DMA ||
869 tf->protocol == ATA_PROT_NODATA);
870 ata_exec_command(ap, tf);
871}
872
873
Tejun Heo0d5ff562007-02-01 15:06:36 +0900874static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875{
876 port->cmd_addr = base;
877 port->data_addr = base;
878 port->feature_addr =
879 port->error_addr = base + 0x4;
880 port->nsect_addr = base + 0x8;
881 port->lbal_addr = base + 0xc;
882 port->lbam_addr = base + 0x10;
883 port->lbah_addr = base + 0x14;
884 port->device_addr = base + 0x18;
885 port->command_addr =
886 port->status_addr = base + 0x1c;
887 port->altstatus_addr =
888 port->ctl_addr = base + 0x38;
889}
890
891
892#ifdef ATA_VERBOSE_DEBUG
Tejun Heo4447d352007-04-17 23:44:08 +0900893static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 u32 offset, u32 size)
895{
896 u32 window_size;
897 u16 idx;
898 u8 page_mask;
899 long dist;
Tejun Heo4447d352007-04-17 23:44:08 +0900900 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
901 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902
903 /* hard-code chip #0 */
904 mmio += PDC_CHIP0_OFS;
905
Jeff Garzik8a60a072005-07-31 13:13:24 -0400906 page_mask = 0x00;
907 window_size = 0x2000 * 4; /* 32K byte uchar size */
908 idx = (u16) (offset / window_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909
910 writel(0x01, mmio + PDC_GENERAL_CTLR);
911 readl(mmio + PDC_GENERAL_CTLR);
912 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
913 readl(mmio + PDC_DIMM_WINDOW_CTLR);
914
915 offset -= (idx * window_size);
916 idx++;
Jeff Garzik8a60a072005-07-31 13:13:24 -0400917 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 (long) (window_size - offset);
Jeff Garzik8a60a072005-07-31 13:13:24 -0400919 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 dist);
921
Jeff Garzik8a60a072005-07-31 13:13:24 -0400922 psource += dist;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700923 size -= dist;
924 for (; (long) size >= (long) window_size ;) {
925 writel(0x01, mmio + PDC_GENERAL_CTLR);
926 readl(mmio + PDC_GENERAL_CTLR);
927 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
928 readl(mmio + PDC_DIMM_WINDOW_CTLR);
Jeff Garzik8a60a072005-07-31 13:13:24 -0400929 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 window_size / 4);
931 psource += window_size;
932 size -= window_size;
933 idx ++;
934 }
935
936 if (size) {
937 writel(0x01, mmio + PDC_GENERAL_CTLR);
938 readl(mmio + PDC_GENERAL_CTLR);
939 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
940 readl(mmio + PDC_DIMM_WINDOW_CTLR);
Jeff Garzik8a60a072005-07-31 13:13:24 -0400941 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942 size / 4);
943 }
944}
945#endif
946
947
Tejun Heo4447d352007-04-17 23:44:08 +0900948static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949 u32 offset, u32 size)
950{
951 u32 window_size;
952 u16 idx;
953 u8 page_mask;
954 long dist;
Tejun Heo4447d352007-04-17 23:44:08 +0900955 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
956 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957
Jeff Garzik8a60a072005-07-31 13:13:24 -0400958 /* hard-code chip #0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959 mmio += PDC_CHIP0_OFS;
960
Jeff Garzik8a60a072005-07-31 13:13:24 -0400961 page_mask = 0x00;
962 window_size = 0x2000 * 4; /* 32K byte uchar size */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700963 idx = (u16) (offset / window_size);
964
965 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
966 readl(mmio + PDC_DIMM_WINDOW_CTLR);
Jeff Garzik8a60a072005-07-31 13:13:24 -0400967 offset -= (idx * window_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968 idx++;
969 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
970 (long) (window_size - offset);
Al Viroa9afd7c2005-10-21 06:46:02 +0100971 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972 writel(0x01, mmio + PDC_GENERAL_CTLR);
973 readl(mmio + PDC_GENERAL_CTLR);
974
Jeff Garzik8a60a072005-07-31 13:13:24 -0400975 psource += dist;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700976 size -= dist;
977 for (; (long) size >= (long) window_size ;) {
978 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
979 readl(mmio + PDC_DIMM_WINDOW_CTLR);
Al Viroa9afd7c2005-10-21 06:46:02 +0100980 memcpy_toio(dimm_mmio, psource, window_size / 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981 writel(0x01, mmio + PDC_GENERAL_CTLR);
982 readl(mmio + PDC_GENERAL_CTLR);
983 psource += window_size;
984 size -= window_size;
985 idx ++;
986 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400987
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 if (size) {
989 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
990 readl(mmio + PDC_DIMM_WINDOW_CTLR);
Al Viroa9afd7c2005-10-21 06:46:02 +0100991 memcpy_toio(dimm_mmio, psource, size / 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 writel(0x01, mmio + PDC_GENERAL_CTLR);
993 readl(mmio + PDC_GENERAL_CTLR);
994 }
995}
996
997
Tejun Heo4447d352007-04-17 23:44:08 +0900998static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 u32 subaddr, u32 *pdata)
1000{
Tejun Heo4447d352007-04-17 23:44:08 +09001001 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002 u32 i2creg = 0;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001003 u32 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 u32 count =0;
1005
1006 /* hard-code chip #0 */
1007 mmio += PDC_CHIP0_OFS;
1008
1009 i2creg |= device << 24;
1010 i2creg |= subaddr << 16;
1011
1012 /* Set the device and subaddress */
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001013 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1014 readl(mmio + PDC_I2C_ADDR_DATA);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015
1016 /* Write Control to perform read operation, mask int */
Jeff Garzik8a60a072005-07-31 13:13:24 -04001017 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001018 mmio + PDC_I2C_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019
1020 for (count = 0; count <= 1000; count ++) {
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001021 status = readl(mmio + PDC_I2C_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022 if (status & PDC_I2C_COMPLETE) {
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001023 status = readl(mmio + PDC_I2C_ADDR_DATA);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 break;
1025 } else if (count == 1000)
1026 return 0;
1027 }
1028
1029 *pdata = (status >> 8) & 0x000000ff;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001030 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031}
1032
1033
Tejun Heo4447d352007-04-17 23:44:08 +09001034static int pdc20621_detect_dimm(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035{
1036 u32 data=0 ;
Tejun Heo4447d352007-04-17 23:44:08 +09001037 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1039 if (data == 100)
1040 return 100;
1041 } else
1042 return 0;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001043
Tejun Heo4447d352007-04-17 23:44:08 +09001044 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
Jeff Garzik8a60a072005-07-31 13:13:24 -04001045 if(data <= 0x75)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 return 133;
1047 } else
1048 return 0;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001049
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 return 0;
1051}
1052
1053
Tejun Heo4447d352007-04-17 23:44:08 +09001054static int pdc20621_prog_dimm0(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055{
1056 u32 spd0[50];
1057 u32 data = 0;
1058 int size, i;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001059 u8 bdimmsize;
Tejun Heo4447d352007-04-17 23:44:08 +09001060 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061 static const struct {
1062 unsigned int reg;
1063 unsigned int ofs;
1064 } pdc_i2c_read_data [] = {
Jeff Garzik8a60a072005-07-31 13:13:24 -04001065 { PDC_DIMM_SPD_TYPE, 11 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 { PDC_DIMM_SPD_FRESH_RATE, 12 },
Jeff Garzik8a60a072005-07-31 13:13:24 -04001067 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1069 { PDC_DIMM_SPD_ROW_NUM, 3 },
1070 { PDC_DIMM_SPD_BANK_NUM, 17 },
1071 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1072 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1073 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1074 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1075 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
Jeff Garzik8a60a072005-07-31 13:13:24 -04001076 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 };
1078
1079 /* hard-code chip #0 */
1080 mmio += PDC_CHIP0_OFS;
1081
1082 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
Tejun Heo4447d352007-04-17 23:44:08 +09001083 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
Jeff Garzik8a60a072005-07-31 13:13:24 -04001084 pdc_i2c_read_data[i].reg,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085 &spd0[pdc_i2c_read_data[i].ofs]);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001086
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001088 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 ((((spd0[27] + 9) / 10) - 1) << 8) ;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001090 data |= (((((spd0[29] > spd0[28])
1091 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001093
1094 if (spd0[18] & 0x08)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 data |= ((0x03) << 14);
1096 else if (spd0[18] & 0x04)
1097 data |= ((0x02) << 14);
1098 else if (spd0[18] & 0x01)
1099 data |= ((0x01) << 14);
1100 else
1101 data |= (0 << 14);
1102
Jeff Garzik8a60a072005-07-31 13:13:24 -04001103 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001104 Calculate the size of bDIMMSize (power of 2) and
1105 merge the DIMM size by program start/end address.
1106 */
1107
1108 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1109 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1110 data |= (((size / 16) - 1) << 16);
1111 data |= (0 << 23);
1112 data |= 8;
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001113 writel(data, mmio + PDC_DIMM0_CONTROL);
1114 readl(mmio + PDC_DIMM0_CONTROL);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001115 return size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116}
1117
1118
Tejun Heo4447d352007-04-17 23:44:08 +09001119static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120{
1121 u32 data, spd0;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001122 int error, i;
Tejun Heo4447d352007-04-17 23:44:08 +09001123 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124
1125 /* hard-code chip #0 */
1126 mmio += PDC_CHIP0_OFS;
1127
1128 /*
1129 Set To Default : DIMM Module Global Control Register (0x022259F1)
1130 DIMM Arbitration Disable (bit 20)
1131 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1132 Refresh Enable (bit 17)
1133 */
1134
Jeff Garzik8a60a072005-07-31 13:13:24 -04001135 data = 0x022259F1;
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001136 writel(data, mmio + PDC_SDRAM_CONTROL);
1137 readl(mmio + PDC_SDRAM_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001138
1139 /* Turn on for ECC */
Tejun Heo4447d352007-04-17 23:44:08 +09001140 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 PDC_DIMM_SPD_TYPE, &spd0);
1142 if (spd0 == 0x02) {
1143 data |= (0x01 << 16);
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001144 writel(data, mmio + PDC_SDRAM_CONTROL);
1145 readl(mmio + PDC_SDRAM_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1147 }
1148
1149 /* DIMM Initialization Select/Enable (bit 18/19) */
1150 data &= (~(1<<18));
1151 data |= (1<<19);
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001152 writel(data, mmio + PDC_SDRAM_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153
Jeff Garzik8a60a072005-07-31 13:13:24 -04001154 error = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001156 data = readl(mmio + PDC_SDRAM_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 if (!(data & (1<<19))) {
1158 error = 0;
Jeff Garzik8a60a072005-07-31 13:13:24 -04001159 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160 }
1161 msleep(i*100);
1162 }
1163 return error;
1164}
Jeff Garzik8a60a072005-07-31 13:13:24 -04001165
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166
Tejun Heo4447d352007-04-17 23:44:08 +09001167static unsigned int pdc20621_dimm_init(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168{
Jeff Garzik8a60a072005-07-31 13:13:24 -04001169 int speed, size, length;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170 u32 addr,spd0,pci_status;
1171 u32 tmp=0;
1172 u32 time_period=0;
1173 u32 tcount=0;
1174 u32 ticks=0;
1175 u32 clock=0;
1176 u32 fparam=0;
Tejun Heo4447d352007-04-17 23:44:08 +09001177 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178
1179 /* hard-code chip #0 */
1180 mmio += PDC_CHIP0_OFS;
1181
1182 /* Initialize PLL based upon PCI Bus Frequency */
1183
1184 /* Initialize Time Period Register */
1185 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1186 time_period = readl(mmio + PDC_TIME_PERIOD);
1187 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1188
1189 /* Enable timer */
Jeff Garzikb2d46b62007-05-27 22:58:54 -04001190 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191 readl(mmio + PDC_TIME_CONTROL);
1192
1193 /* Wait 3 seconds */
1194 msleep(3000);
1195
Jeff Garzik8a60a072005-07-31 13:13:24 -04001196 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 When timer is enabled, counter is decreased every internal
1198 clock cycle.
1199 */
1200
1201 tcount = readl(mmio + PDC_TIME_COUNTER);
1202 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1203
Jeff Garzik8a60a072005-07-31 13:13:24 -04001204 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1206 register should be >= (0xffffffff - 3x10^8).
1207 */
1208 if(tcount >= PCI_X_TCOUNT) {
1209 ticks = (time_period - tcount);
1210 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001211
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212 clock = (ticks / 300000);
1213 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001214
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215 clock = (clock * 33);
1216 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1217
1218 /* PLL F Param (bit 22:16) */
1219 fparam = (1400000 / clock) - 2;
1220 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001221
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1223 pci_status = (0x8a001824 | (fparam << 16));
1224 } else
1225 pci_status = PCI_PLL_INIT;
1226
1227 /* Initialize PLL. */
1228 VPRINTK("pci_status: 0x%x\n", pci_status);
1229 writel(pci_status, mmio + PDC_CTL_STATUS);
1230 readl(mmio + PDC_CTL_STATUS);
1231
Jeff Garzik8a60a072005-07-31 13:13:24 -04001232 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 Read SPD of DIMM by I2C interface,
1234 and program the DIMM Module Controller.
1235 */
Tejun Heo4447d352007-04-17 23:44:08 +09001236 if (!(speed = pdc20621_detect_dimm(host))) {
Jeff Garzik8a60a072005-07-31 13:13:24 -04001237 printk(KERN_ERR "Detect Local DIMM Fail\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 return 1; /* DIMM error */
1239 }
1240 VPRINTK("Local DIMM Speed = %d\n", speed);
1241
Jeff Garzik8a60a072005-07-31 13:13:24 -04001242 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
Tejun Heo4447d352007-04-17 23:44:08 +09001243 size = pdc20621_prog_dimm0(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244 VPRINTK("Local DIMM Size = %dMB\n",size);
1245
Jeff Garzik8a60a072005-07-31 13:13:24 -04001246 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
Tejun Heo4447d352007-04-17 23:44:08 +09001247 if (pdc20621_prog_dimm_global(host)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1249 return 1;
1250 }
1251
1252#ifdef ATA_VERBOSE_DEBUG
1253 {
1254 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1255 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1256 '1','.','1','0',
1257 '9','8','0','3','1','6','1','2',0,0};
1258 u8 test_parttern2[40] = {0};
1259
Tejun Heo4447d352007-04-17 23:44:08 +09001260 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
1261 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262
Tejun Heo4447d352007-04-17 23:44:08 +09001263 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
1264 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001265 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266 test_parttern2[1], &(test_parttern2[2]));
Tejun Heo4447d352007-04-17 23:44:08 +09001267 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 40);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001269 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 test_parttern2[1], &(test_parttern2[2]));
1271
Tejun Heo4447d352007-04-17 23:44:08 +09001272 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
1273 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
Jeff Garzik8a60a072005-07-31 13:13:24 -04001274 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275 test_parttern2[1], &(test_parttern2[2]));
1276 }
1277#endif
1278
1279 /* ECC initiliazation. */
1280
Tejun Heo4447d352007-04-17 23:44:08 +09001281 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001282 PDC_DIMM_SPD_TYPE, &spd0);
1283 if (spd0 == 0x02) {
1284 VPRINTK("Start ECC initialization\n");
1285 addr = 0;
1286 length = size * 1024 * 1024;
1287 while (addr < length) {
Tejun Heo4447d352007-04-17 23:44:08 +09001288 pdc20621_put_to_dimm(host, (void *) &tmp, addr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289 sizeof(u32));
1290 addr += sizeof(u32);
1291 }
1292 VPRINTK("Finish ECC initialization\n");
1293 }
1294 return 0;
1295}
1296
1297
Tejun Heo4447d352007-04-17 23:44:08 +09001298static void pdc_20621_init(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299{
1300 u32 tmp;
Tejun Heo4447d352007-04-17 23:44:08 +09001301 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302
1303 /* hard-code chip #0 */
1304 mmio += PDC_CHIP0_OFS;
1305
1306 /*
1307 * Select page 0x40 for our 32k DIMM window
1308 */
1309 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1310 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1311 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1312
1313 /*
1314 * Reset Host DMA
1315 */
1316 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1317 tmp |= PDC_RESET;
1318 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1319 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1320
1321 udelay(10);
1322
1323 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1324 tmp &= ~PDC_RESET;
1325 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1326 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1327}
1328
1329static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1330{
1331 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09001332 const struct ata_port_info *ppi[] =
1333 { &pdc_port_info[ent->driver_data], NULL };
1334 struct ata_host *host;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001335 void __iomem *base;
Tejun Heo24dc5f32007-01-20 16:00:28 +09001336 struct pdc_host_priv *hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 int rc;
1338
1339 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001340 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341
Tejun Heo4447d352007-04-17 23:44:08 +09001342 /* allocate host */
1343 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1344 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1345 if (!host || !hpriv)
1346 return -ENOMEM;
1347
1348 host->private_data = hpriv;
1349
1350 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001351 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 if (rc)
1353 return rc;
1354
Tejun Heo0d5ff562007-02-01 15:06:36 +09001355 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1356 DRV_NAME);
1357 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001358 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001359 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001360 return rc;
Tejun Heo4447d352007-04-17 23:44:08 +09001361 host->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362
Tejun Heo4447d352007-04-17 23:44:08 +09001363 base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1364 pdc_sata_setup_port(&host->ports[0]->ioaddr, base + 0x200);
1365 pdc_sata_setup_port(&host->ports[1]->ioaddr, base + 0x280);
1366 pdc_sata_setup_port(&host->ports[2]->ioaddr, base + 0x300);
1367 pdc_sata_setup_port(&host->ports[3]->ioaddr, base + 0x380);
1368
1369 /* configure and activate */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1371 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001372 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1374 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001375 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376
Tejun Heo4447d352007-04-17 23:44:08 +09001377 if (pdc20621_dimm_init(host))
Tejun Heo24dc5f32007-01-20 16:00:28 +09001378 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001379 pdc_20621_init(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380
1381 pci_set_master(pdev);
Tejun Heo4447d352007-04-17 23:44:08 +09001382 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1383 IRQF_SHARED, &pdc_sata_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384}
1385
1386
1387static int __init pdc_sata_init(void)
1388{
Pavel Roskinb7887192006-08-10 18:13:18 +09001389 return pci_register_driver(&pdc_sata_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390}
1391
1392
1393static void __exit pdc_sata_exit(void)
1394{
1395 pci_unregister_driver(&pdc_sata_pci_driver);
1396}
1397
1398
1399MODULE_AUTHOR("Jeff Garzik");
1400MODULE_DESCRIPTION("Promise SATA low-level driver");
1401MODULE_LICENSE("GPL");
1402MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1403MODULE_VERSION(DRV_VERSION);
1404
1405module_init(pdc_sata_init);
1406module_exit(pdc_sata_exit);