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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * $Id: cpu-sa1110.c,v 1.9 2002/07/06 16:53:18 rmk Exp $
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Note: there are two erratas that apply to the SA1110 here:
13 * 7 - SDRAM auto-power-up failure (rev A0)
14 * 13 - Corruption of internal register reads/writes following
15 * SDRAM reads (rev A0, B0, B1)
16 *
17 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
Russell Kingba532012006-06-29 20:56:47 +010018 *
19 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 */
Russell Kingba532012006-06-29 20:56:47 +010021#include <linux/moduleparam.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/cpufreq.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28
Russell Kingbe509722008-08-04 10:41:28 +010029#include <asm/arch/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <asm/mach-types.h>
31#include <asm/io.h>
32#include <asm/system.h>
33
34#include "generic.h"
35
36#undef DEBUG
37
38static struct cpufreq_driver sa1110_driver;
39
40struct sdram_params {
Russell Kingba532012006-06-29 20:56:47 +010041 const char name[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 u_char rows; /* bits */
43 u_char cas_latency; /* cycles */
44 u_char tck; /* clock cycle time (ns) */
45 u_char trcd; /* activate to r/w (ns) */
46 u_char trp; /* precharge to activate (ns) */
47 u_char twr; /* write recovery time (ns) */
48 u_short refresh; /* refresh time for array (us) */
49};
50
51struct sdram_info {
52 u_int mdcnfg;
53 u_int mdrefr;
54 u_int mdcas[3];
55};
56
Russell Kingba532012006-06-29 20:56:47 +010057static struct sdram_params sdram_tbl[] __initdata = {
58 { /* Toshiba TC59SM716 CL2 */
59 .name = "TC59SM716-CL2",
60 .rows = 12,
61 .tck = 10,
62 .trcd = 20,
63 .trp = 20,
64 .twr = 10,
65 .refresh = 64000,
66 .cas_latency = 2,
67 }, { /* Toshiba TC59SM716 CL3 */
68 .name = "TC59SM716-CL3",
69 .rows = 12,
70 .tck = 8,
71 .trcd = 20,
72 .trp = 20,
73 .twr = 8,
74 .refresh = 64000,
75 .cas_latency = 3,
76 }, { /* Samsung K4S641632D TC75 */
77 .name = "K4S641632D",
78 .rows = 14,
79 .tck = 9,
80 .trcd = 27,
81 .trp = 20,
82 .twr = 9,
83 .refresh = 64000,
84 .cas_latency = 3,
Kristoffer Ericson48e3bec2006-10-08 19:52:30 +010085 }, { /* Samsung K4S281632B-1H */
Kristoffer Ericson9f0f9312006-10-29 22:38:08 +010086 .name = "K4S281632B-1H",
Kristoffer Ericson48e3bec2006-10-08 19:52:30 +010087 .rows = 12,
88 .tck = 10,
89 .trp = 20,
90 .twr = 10,
91 .refresh = 64000,
92 .cas_latency = 3,
Russell Kingba532012006-06-29 20:56:47 +010093 }, { /* Samsung KM416S4030CT */
94 .name = "KM416S4030CT",
95 .rows = 13,
96 .tck = 8,
97 .trcd = 24, /* 3 CLKs */
98 .trp = 24, /* 3 CLKs */
99 .twr = 16, /* Trdl: 2 CLKs */
100 .refresh = 64000,
101 .cas_latency = 3,
102 }, { /* Winbond W982516AH75L CL3 */
103 .name = "W982516AH75L",
104 .rows = 16,
105 .tck = 8,
106 .trcd = 20,
107 .trp = 20,
108 .twr = 8,
109 .refresh = 64000,
110 .cas_latency = 3,
111 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112};
113
114static struct sdram_params sdram_params;
115
116/*
117 * Given a period in ns and frequency in khz, calculate the number of
118 * cycles of frequency in period. Note that we round up to the next
119 * cycle, even if we are only slightly over.
120 */
121static inline u_int ns_to_cycles(u_int ns, u_int khz)
122{
123 return (ns * khz + 999999) / 1000000;
124}
125
126/*
127 * Create the MDCAS register bit pattern.
128 */
129static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
130{
131 u_int shift;
132
133 rcd = 2 * rcd - 1;
134 shift = delayed + 1 + rcd;
135
136 mdcas[0] = (1 << rcd) - 1;
137 mdcas[0] |= 0x55555555 << shift;
138 mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
139}
140
141static void
142sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
143 struct sdram_params *sdram)
144{
145 u_int mem_khz, sd_khz, trp, twr;
146
147 mem_khz = cpu_khz / 2;
148 sd_khz = mem_khz;
149
150 /*
151 * If SDCLK would invalidate the SDRAM timings,
152 * run SDCLK at half speed.
153 *
154 * CPU steppings prior to B2 must either run the memory at
155 * half speed or use delayed read latching (errata 13).
156 */
157 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
158 (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
159 sd_khz /= 2;
160
161 sd->mdcnfg = MDCNFG & 0x007f007f;
162
163 twr = ns_to_cycles(sdram->twr, mem_khz);
164
165 /* trp should always be >1 */
166 trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
167 if (trp < 1)
168 trp = 1;
169
170 sd->mdcnfg |= trp << 8;
171 sd->mdcnfg |= trp << 24;
172 sd->mdcnfg |= sdram->cas_latency << 12;
173 sd->mdcnfg |= sdram->cas_latency << 28;
174 sd->mdcnfg |= twr << 14;
175 sd->mdcnfg |= twr << 30;
176
177 sd->mdrefr = MDREFR & 0xffbffff0;
178 sd->mdrefr |= 7;
179
180 if (sd_khz != mem_khz)
181 sd->mdrefr |= MDREFR_K1DB2;
182
183 /* initial number of '1's in MDCAS + 1 */
184 set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
185
186#ifdef DEBUG
187 printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
188 sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
189#endif
190}
191
192/*
193 * Set the SDRAM refresh rate.
194 */
195static inline void sdram_set_refresh(u_int dri)
196{
197 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
198 (void) MDREFR;
199}
200
201/*
202 * Update the refresh period. We do this such that we always refresh
203 * the SDRAMs within their permissible period. The refresh period is
204 * always a multiple of the memory clock (fixed at cpu_clock / 2).
205 *
206 * FIXME: we don't currently take account of burst accesses here,
207 * but neither do Intels DM nor Angel.
208 */
209static void
210sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
211{
212 u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
213 u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
214
215#ifdef DEBUG
216 mdelay(250);
217 printk("new dri value = %d\n", dri);
218#endif
219
220 sdram_set_refresh(dri);
221}
222
223/*
224 * Ok, set the CPU frequency.
225 */
226static int sa1110_target(struct cpufreq_policy *policy,
227 unsigned int target_freq,
228 unsigned int relation)
229{
230 struct sdram_params *sdram = &sdram_params;
231 struct cpufreq_freqs freqs;
232 struct sdram_info sd;
233 unsigned long flags;
234 unsigned int ppcr, unused;
235
236 switch(relation){
237 case CPUFREQ_RELATION_L:
238 ppcr = sa11x0_freq_to_ppcr(target_freq);
239 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
240 ppcr--;
241 break;
242 case CPUFREQ_RELATION_H:
243 ppcr = sa11x0_freq_to_ppcr(target_freq);
244 if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
245 (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
246 ppcr--;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 freqs.old = sa11x0_getspeed(0);
253 freqs.new = sa11x0_ppcr_to_freq(ppcr);
254 freqs.cpu = 0;
255
256 sdram_calculate_timing(&sd, freqs.new, sdram);
257
258#if 0
259 /*
260 * These values are wrong according to the SA1110 documentation
261 * and errata, but they seem to work. Need to get a storage
262 * scope on to the SDRAM signals to work out why.
263 */
264 if (policy->max < 147500) {
265 sd.mdrefr |= MDREFR_K1DB2;
266 sd.mdcas[0] = 0xaaaaaa7f;
267 } else {
268 sd.mdrefr &= ~MDREFR_K1DB2;
269 sd.mdcas[0] = 0xaaaaaa9f;
270 }
271 sd.mdcas[1] = 0xaaaaaaaa;
272 sd.mdcas[2] = 0xaaaaaaaa;
273#endif
274
275 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
276
277 /*
278 * The clock could be going away for some time. Set the SDRAMs
279 * to refresh rapidly (every 64 memory clock cycles). To get
280 * through the whole array, we need to wait 262144 mclk cycles.
281 * We wait 20ms to be safe.
282 */
283 sdram_set_refresh(2);
284 if (!irqs_disabled()) {
Nishanth Aravamudandb579552005-07-01 12:11:51 +0100285 msleep(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 } else {
287 mdelay(20);
288 }
289
290 /*
291 * Reprogram the DRAM timings with interrupts disabled, and
292 * ensure that we are doing this within a complete cache line.
293 * This means that we won't access SDRAM for the duration of
294 * the programming.
295 */
296 local_irq_save(flags);
297 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
298 udelay(10);
299 __asm__ __volatile__(" \n\
300 b 2f \n\
301 .align 5 \n\
3021: str %3, [%1, #0] @ MDCNFG \n\
303 str %4, [%1, #28] @ MDREFR \n\
304 str %5, [%1, #4] @ MDCAS0 \n\
305 str %6, [%1, #8] @ MDCAS1 \n\
306 str %7, [%1, #12] @ MDCAS2 \n\
307 str %8, [%2, #0] @ PPCR \n\
308 ldr %0, [%1, #0] \n\
309 b 3f \n\
3102: b 1b \n\
3113: nop \n\
312 nop"
313 : "=&r" (unused)
314 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
315 "r" (sd.mdrefr), "r" (sd.mdcas[0]),
316 "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
317 local_irq_restore(flags);
318
319 /*
320 * Now, return the SDRAM refresh back to normal.
321 */
322 sdram_update_refresh(freqs.new, sdram);
323
324 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
325
326 return 0;
327}
328
329static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
330{
331 if (policy->cpu != 0)
332 return -EINVAL;
333 policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 policy->cpuinfo.min_freq = 59000;
335 policy->cpuinfo.max_freq = 287000;
336 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
337 return 0;
338}
339
340static struct cpufreq_driver sa1110_driver = {
341 .flags = CPUFREQ_STICKY,
342 .verify = sa11x0_verify_speed,
343 .target = sa1110_target,
344 .get = sa11x0_getspeed,
345 .init = sa1110_cpu_init,
346 .name = "sa1110",
347};
348
Russell Kingba532012006-06-29 20:56:47 +0100349static struct sdram_params *sa1110_find_sdram(const char *name)
350{
351 struct sdram_params *sdram;
352
353 for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
354 if (strcmp(name, sdram->name) == 0)
355 return sdram;
356
357 return NULL;
358}
359
360static char sdram_name[16];
361
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362static int __init sa1110_clk_init(void)
363{
Russell Kingba532012006-06-29 20:56:47 +0100364 struct sdram_params *sdram;
365 const char *name = sdram_name;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366
Russell Kingba532012006-06-29 20:56:47 +0100367 if (!name[0]) {
368 if (machine_is_assabet())
369 name = "TC59SM716-CL3";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370
Russell Kingba532012006-06-29 20:56:47 +0100371 if (machine_is_pt_system3())
372 name = "K4S641632D";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
Russell Kingba532012006-06-29 20:56:47 +0100374 if (machine_is_h3100())
375 name = "KM416S4030CT";
Kristoffer Ericson48e3bec2006-10-08 19:52:30 +0100376 if (machine_is_jornada720())
377 name = "K4S281632B-1H";
Russell Kingba532012006-06-29 20:56:47 +0100378 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379
Russell Kingba532012006-06-29 20:56:47 +0100380 sdram = sa1110_find_sdram(name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 if (sdram) {
382 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
383 " twr: %d refresh: %d cas_latency: %d\n",
384 sdram->tck, sdram->trcd, sdram->trp,
385 sdram->twr, sdram->refresh, sdram->cas_latency);
386
387 memcpy(&sdram_params, sdram, sizeof(sdram_params));
388
389 return cpufreq_register_driver(&sa1110_driver);
390 }
391
392 return 0;
393}
394
Russell Kingba532012006-06-29 20:56:47 +0100395module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396arch_initcall(sa1110_clk_init);