| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame^] | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h |
| 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * S3C2410 GPIO register definitions |
| 11 | */ |
| 12 | |
| 13 | |
| 14 | #ifndef __ASM_ARCH_REGS_GPIO_H |
| 15 | #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $" |
| 16 | |
| 17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) |
| 18 | |
| 19 | #define S3C2410_GPIO_BANKA (32*0) |
| 20 | #define S3C2410_GPIO_BANKB (32*1) |
| 21 | #define S3C2410_GPIO_BANKC (32*2) |
| 22 | #define S3C2410_GPIO_BANKD (32*3) |
| 23 | #define S3C2410_GPIO_BANKE (32*4) |
| 24 | #define S3C2410_GPIO_BANKF (32*5) |
| 25 | #define S3C2410_GPIO_BANKG (32*6) |
| 26 | #define S3C2410_GPIO_BANKH (32*7) |
| 27 | |
| 28 | #ifdef CONFIG_CPU_S3C2400 |
| 29 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) |
| 30 | #define S3C24XX_MISCCR S3C2400_MISCCR |
| 31 | #else |
| 32 | #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) |
| 33 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) |
| 34 | #endif /* CONFIG_CPU_S3C2400 */ |
| 35 | |
| 36 | |
| 37 | /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ |
| 38 | |
| 39 | #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) |
| 40 | #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) |
| 41 | #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ |
| 42 | (2 * (S3C2400_BANKNUM(pin)-2))) |
| 43 | |
| 44 | #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ |
| 45 | S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ |
| 46 | S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) |
| 47 | |
| 48 | |
| 49 | #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) |
| 50 | #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) |
| 51 | |
| 52 | /* general configuration options */ |
| 53 | |
| 54 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) |
| 55 | #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ |
| 56 | #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) |
| 57 | #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ |
| 58 | #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ |
| 59 | #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ |
| 60 | |
| 61 | /* register address for the GPIO registers. |
| 62 | * S3C24XX_GPIOREG2 is for the second set of registers in the |
| 63 | * GPIO which move between s3c2410 and s3c2412 type systems */ |
| 64 | |
| 65 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) |
| 66 | #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) |
| 67 | |
| 68 | |
| 69 | /* configure GPIO ports A..G */ |
| 70 | |
| 71 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output |
| 72 | * S3C2400: 18bits, zero in bit X makes pin X output |
| 73 | * 1 makes port special function, this is default |
| 74 | */ |
| 75 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) |
| 76 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) |
| 77 | |
| 78 | #define S3C2400_GPACON S3C2410_GPIOREG(0x00) |
| 79 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) |
| 80 | |
| 81 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) |
| 82 | #define S3C2410_GPA0_OUT (0<<0) |
| 83 | #define S3C2410_GPA0_ADDR0 (1<<0) |
| 84 | |
| 85 | #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) |
| 86 | #define S3C2410_GPA1_OUT (0<<1) |
| 87 | #define S3C2410_GPA1_ADDR16 (1<<1) |
| 88 | |
| 89 | #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) |
| 90 | #define S3C2410_GPA2_OUT (0<<2) |
| 91 | #define S3C2410_GPA2_ADDR17 (1<<2) |
| 92 | |
| 93 | #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) |
| 94 | #define S3C2410_GPA3_OUT (0<<3) |
| 95 | #define S3C2410_GPA3_ADDR18 (1<<3) |
| 96 | |
| 97 | #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) |
| 98 | #define S3C2410_GPA4_OUT (0<<4) |
| 99 | #define S3C2410_GPA4_ADDR19 (1<<4) |
| 100 | |
| 101 | #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) |
| 102 | #define S3C2410_GPA5_OUT (0<<5) |
| 103 | #define S3C2410_GPA5_ADDR20 (1<<5) |
| 104 | |
| 105 | #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) |
| 106 | #define S3C2410_GPA6_OUT (0<<6) |
| 107 | #define S3C2410_GPA6_ADDR21 (1<<6) |
| 108 | |
| 109 | #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) |
| 110 | #define S3C2410_GPA7_OUT (0<<7) |
| 111 | #define S3C2410_GPA7_ADDR22 (1<<7) |
| 112 | |
| 113 | #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) |
| 114 | #define S3C2410_GPA8_OUT (0<<8) |
| 115 | #define S3C2410_GPA8_ADDR23 (1<<8) |
| 116 | |
| 117 | #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) |
| 118 | #define S3C2410_GPA9_OUT (0<<9) |
| 119 | #define S3C2410_GPA9_ADDR24 (1<<9) |
| 120 | |
| 121 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) |
| 122 | #define S3C2410_GPA10_OUT (0<<10) |
| 123 | #define S3C2410_GPA10_ADDR25 (1<<10) |
| 124 | #define S3C2400_GPA10_SCKE (1<<10) |
| 125 | |
| 126 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) |
| 127 | #define S3C2410_GPA11_OUT (0<<11) |
| 128 | #define S3C2410_GPA11_ADDR26 (1<<11) |
| 129 | #define S3C2400_GPA11_nCAS0 (1<<11) |
| 130 | |
| 131 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) |
| 132 | #define S3C2410_GPA12_OUT (0<<12) |
| 133 | #define S3C2410_GPA12_nGCS1 (1<<12) |
| 134 | #define S3C2400_GPA12_nCAS1 (1<<12) |
| 135 | |
| 136 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) |
| 137 | #define S3C2410_GPA13_OUT (0<<13) |
| 138 | #define S3C2410_GPA13_nGCS2 (1<<13) |
| 139 | #define S3C2400_GPA13_nGCS1 (1<<13) |
| 140 | |
| 141 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) |
| 142 | #define S3C2410_GPA14_OUT (0<<14) |
| 143 | #define S3C2410_GPA14_nGCS3 (1<<14) |
| 144 | #define S3C2400_GPA14_nGCS2 (1<<14) |
| 145 | |
| 146 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) |
| 147 | #define S3C2410_GPA15_OUT (0<<15) |
| 148 | #define S3C2410_GPA15_nGCS4 (1<<15) |
| 149 | #define S3C2400_GPA15_nGCS3 (1<<15) |
| 150 | |
| 151 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) |
| 152 | #define S3C2410_GPA16_OUT (0<<16) |
| 153 | #define S3C2410_GPA16_nGCS5 (1<<16) |
| 154 | #define S3C2400_GPA16_nGCS4 (1<<16) |
| 155 | |
| 156 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) |
| 157 | #define S3C2410_GPA17_OUT (0<<17) |
| 158 | #define S3C2410_GPA17_CLE (1<<17) |
| 159 | #define S3C2400_GPA17_nGCS5 (1<<17) |
| 160 | |
| 161 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) |
| 162 | #define S3C2410_GPA18_OUT (0<<18) |
| 163 | #define S3C2410_GPA18_ALE (1<<18) |
| 164 | |
| 165 | #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) |
| 166 | #define S3C2410_GPA19_OUT (0<<19) |
| 167 | #define S3C2410_GPA19_nFWE (1<<19) |
| 168 | |
| 169 | #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) |
| 170 | #define S3C2410_GPA20_OUT (0<<20) |
| 171 | #define S3C2410_GPA20_nFRE (1<<20) |
| 172 | |
| 173 | #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) |
| 174 | #define S3C2410_GPA21_OUT (0<<21) |
| 175 | #define S3C2410_GPA21_nRSTOUT (1<<21) |
| 176 | |
| 177 | #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) |
| 178 | #define S3C2410_GPA22_OUT (0<<22) |
| 179 | #define S3C2410_GPA22_nFCE (1<<22) |
| 180 | |
| 181 | /* 0x08 and 0x0c are reserved on S3C2410 */ |
| 182 | |
| 183 | /* S3C2410: |
| 184 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. |
| 185 | * 00 = input, 01 = output, 10=special function, 11=reserved |
| 186 | |
| 187 | * S3C2400: |
| 188 | * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. |
| 189 | * 00 = input, 01 = output, 10=data, 11=special function |
| 190 | |
| 191 | * bit 0,1 = pin 0, 2,3= pin 1... |
| 192 | * |
| 193 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled |
| 194 | */ |
| 195 | |
| 196 | #define S3C2410_GPBCON S3C2410_GPIOREG(0x10) |
| 197 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) |
| 198 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) |
| 199 | |
| 200 | #define S3C2400_GPBCON S3C2410_GPIOREG(0x08) |
| 201 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) |
| 202 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) |
| 203 | |
| 204 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ |
| 205 | |
| 206 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) |
| 207 | #define S3C2410_GPB0_INP (0x00 << 0) |
| 208 | #define S3C2410_GPB0_OUTP (0x01 << 0) |
| 209 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) |
| 210 | #define S3C2400_GPB0_DATA16 (0x02 << 0) |
| 211 | |
| 212 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) |
| 213 | #define S3C2410_GPB1_INP (0x00 << 2) |
| 214 | #define S3C2410_GPB1_OUTP (0x01 << 2) |
| 215 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) |
| 216 | #define S3C2400_GPB1_DATA17 (0x02 << 2) |
| 217 | |
| 218 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) |
| 219 | #define S3C2410_GPB2_INP (0x00 << 4) |
| 220 | #define S3C2410_GPB2_OUTP (0x01 << 4) |
| 221 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) |
| 222 | #define S3C2400_GPB2_DATA18 (0x02 << 4) |
| 223 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) |
| 224 | |
| 225 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) |
| 226 | #define S3C2410_GPB3_INP (0x00 << 6) |
| 227 | #define S3C2410_GPB3_OUTP (0x01 << 6) |
| 228 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) |
| 229 | #define S3C2400_GPB3_DATA19 (0x02 << 6) |
| 230 | #define S3C2400_GPB3_TXD1 (0x03 << 6) |
| 231 | |
| 232 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) |
| 233 | #define S3C2410_GPB4_INP (0x00 << 8) |
| 234 | #define S3C2410_GPB4_OUTP (0x01 << 8) |
| 235 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) |
| 236 | #define S3C2400_GPB4_DATA20 (0x02 << 8) |
| 237 | #define S3C2410_GPB4_MASK (0x03 << 8) |
| 238 | #define S3C2400_GPB4_RXD1 (0x03 << 8) |
| 239 | #define S3C2400_GPB4_MASK (0x03 << 8) |
| 240 | |
| 241 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) |
| 242 | #define S3C2410_GPB5_INP (0x00 << 10) |
| 243 | #define S3C2410_GPB5_OUTP (0x01 << 10) |
| 244 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
| 245 | #define S3C2443_GPB5_XBACK (0x03 << 10) |
| 246 | #define S3C2400_GPB5_DATA21 (0x02 << 10) |
| 247 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) |
| 248 | |
| 249 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) |
| 250 | #define S3C2410_GPB6_INP (0x00 << 12) |
| 251 | #define S3C2410_GPB6_OUTP (0x01 << 12) |
| 252 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
| 253 | #define S3C2443_GPB6_XBREQ (0x03 << 12) |
| 254 | #define S3C2400_GPB6_DATA22 (0x02 << 12) |
| 255 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) |
| 256 | |
| 257 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) |
| 258 | #define S3C2410_GPB7_INP (0x00 << 14) |
| 259 | #define S3C2410_GPB7_OUTP (0x01 << 14) |
| 260 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
| 261 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) |
| 262 | #define S3C2400_GPB7_DATA23 (0x02 << 14) |
| 263 | |
| 264 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) |
| 265 | #define S3C2410_GPB8_INP (0x00 << 16) |
| 266 | #define S3C2410_GPB8_OUTP (0x01 << 16) |
| 267 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) |
| 268 | #define S3C2400_GPB8_DATA24 (0x02 << 16) |
| 269 | |
| 270 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) |
| 271 | #define S3C2410_GPB9_INP (0x00 << 18) |
| 272 | #define S3C2410_GPB9_OUTP (0x01 << 18) |
| 273 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
| 274 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) |
| 275 | #define S3C2400_GPB9_DATA25 (0x02 << 18) |
| 276 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) |
| 277 | |
| 278 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) |
| 279 | #define S3C2410_GPB10_INP (0x00 << 20) |
| 280 | #define S3C2410_GPB10_OUTP (0x01 << 20) |
| 281 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
| 282 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) |
| 283 | #define S3C2400_GPB10_DATA26 (0x02 << 20) |
| 284 | #define S3C2400_GPB10_nSS (0x03 << 20) |
| 285 | |
| 286 | #define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) |
| 287 | #define S3C2400_GPB11_INP (0x00 << 22) |
| 288 | #define S3C2400_GPB11_OUTP (0x01 << 22) |
| 289 | #define S3C2400_GPB11_DATA27 (0x02 << 22) |
| 290 | |
| 291 | #define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) |
| 292 | #define S3C2400_GPB12_INP (0x00 << 24) |
| 293 | #define S3C2400_GPB12_OUTP (0x01 << 24) |
| 294 | #define S3C2400_GPB12_DATA28 (0x02 << 24) |
| 295 | |
| 296 | #define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) |
| 297 | #define S3C2400_GPB13_INP (0x00 << 26) |
| 298 | #define S3C2400_GPB13_OUTP (0x01 << 26) |
| 299 | #define S3C2400_GPB13_DATA29 (0x02 << 26) |
| 300 | |
| 301 | #define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) |
| 302 | #define S3C2400_GPB14_INP (0x00 << 28) |
| 303 | #define S3C2400_GPB14_OUTP (0x01 << 28) |
| 304 | #define S3C2400_GPB14_DATA30 (0x02 << 28) |
| 305 | |
| 306 | #define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) |
| 307 | #define S3C2400_GPB15_INP (0x00 << 30) |
| 308 | #define S3C2400_GPB15_OUTP (0x01 << 30) |
| 309 | #define S3C2400_GPB15_DATA31 (0x02 << 30) |
| 310 | |
| 311 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) |
| 312 | |
| 313 | /* Port C consits of 16 GPIO/Special function |
| 314 | * |
| 315 | * almost identical setup to port b, but the special functions are mostly |
| 316 | * to do with the video system's sync/etc. |
| 317 | */ |
| 318 | |
| 319 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) |
| 320 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) |
| 321 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) |
| 322 | |
| 323 | #define S3C2400_GPCCON S3C2410_GPIOREG(0x14) |
| 324 | #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) |
| 325 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) |
| 326 | |
| 327 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) |
| 328 | #define S3C2410_GPC0_INP (0x00 << 0) |
| 329 | #define S3C2410_GPC0_OUTP (0x01 << 0) |
| 330 | #define S3C2410_GPC0_LEND (0x02 << 0) |
| 331 | #define S3C2400_GPC0_VD0 (0x02 << 0) |
| 332 | |
| 333 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) |
| 334 | #define S3C2410_GPC1_INP (0x00 << 2) |
| 335 | #define S3C2410_GPC1_OUTP (0x01 << 2) |
| 336 | #define S3C2410_GPC1_VCLK (0x02 << 2) |
| 337 | #define S3C2400_GPC1_VD1 (0x02 << 2) |
| 338 | |
| 339 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) |
| 340 | #define S3C2410_GPC2_INP (0x00 << 4) |
| 341 | #define S3C2410_GPC2_OUTP (0x01 << 4) |
| 342 | #define S3C2410_GPC2_VLINE (0x02 << 4) |
| 343 | #define S3C2400_GPC2_VD2 (0x02 << 4) |
| 344 | |
| 345 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) |
| 346 | #define S3C2410_GPC3_INP (0x00 << 6) |
| 347 | #define S3C2410_GPC3_OUTP (0x01 << 6) |
| 348 | #define S3C2410_GPC3_VFRAME (0x02 << 6) |
| 349 | #define S3C2400_GPC3_VD3 (0x02 << 6) |
| 350 | |
| 351 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) |
| 352 | #define S3C2410_GPC4_INP (0x00 << 8) |
| 353 | #define S3C2410_GPC4_OUTP (0x01 << 8) |
| 354 | #define S3C2410_GPC4_VM (0x02 << 8) |
| 355 | #define S3C2400_GPC4_VD4 (0x02 << 8) |
| 356 | |
| 357 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) |
| 358 | #define S3C2410_GPC5_INP (0x00 << 10) |
| 359 | #define S3C2410_GPC5_OUTP (0x01 << 10) |
| 360 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) |
| 361 | #define S3C2400_GPC5_VD5 (0x02 << 10) |
| 362 | |
| 363 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) |
| 364 | #define S3C2410_GPC6_INP (0x00 << 12) |
| 365 | #define S3C2410_GPC6_OUTP (0x01 << 12) |
| 366 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) |
| 367 | #define S3C2400_GPC6_VD6 (0x02 << 12) |
| 368 | |
| 369 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) |
| 370 | #define S3C2410_GPC7_INP (0x00 << 14) |
| 371 | #define S3C2410_GPC7_OUTP (0x01 << 14) |
| 372 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) |
| 373 | #define S3C2400_GPC7_VD7 (0x02 << 14) |
| 374 | |
| 375 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) |
| 376 | #define S3C2410_GPC8_INP (0x00 << 16) |
| 377 | #define S3C2410_GPC8_OUTP (0x01 << 16) |
| 378 | #define S3C2410_GPC8_VD0 (0x02 << 16) |
| 379 | #define S3C2400_GPC8_VD8 (0x02 << 16) |
| 380 | |
| 381 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) |
| 382 | #define S3C2410_GPC9_INP (0x00 << 18) |
| 383 | #define S3C2410_GPC9_OUTP (0x01 << 18) |
| 384 | #define S3C2410_GPC9_VD1 (0x02 << 18) |
| 385 | #define S3C2400_GPC9_VD9 (0x02 << 18) |
| 386 | |
| 387 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) |
| 388 | #define S3C2410_GPC10_INP (0x00 << 20) |
| 389 | #define S3C2410_GPC10_OUTP (0x01 << 20) |
| 390 | #define S3C2410_GPC10_VD2 (0x02 << 20) |
| 391 | #define S3C2400_GPC10_VD10 (0x02 << 20) |
| 392 | |
| 393 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) |
| 394 | #define S3C2410_GPC11_INP (0x00 << 22) |
| 395 | #define S3C2410_GPC11_OUTP (0x01 << 22) |
| 396 | #define S3C2410_GPC11_VD3 (0x02 << 22) |
| 397 | #define S3C2400_GPC11_VD11 (0x02 << 22) |
| 398 | |
| 399 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) |
| 400 | #define S3C2410_GPC12_INP (0x00 << 24) |
| 401 | #define S3C2410_GPC12_OUTP (0x01 << 24) |
| 402 | #define S3C2410_GPC12_VD4 (0x02 << 24) |
| 403 | #define S3C2400_GPC12_VD12 (0x02 << 24) |
| 404 | |
| 405 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) |
| 406 | #define S3C2410_GPC13_INP (0x00 << 26) |
| 407 | #define S3C2410_GPC13_OUTP (0x01 << 26) |
| 408 | #define S3C2410_GPC13_VD5 (0x02 << 26) |
| 409 | #define S3C2400_GPC13_VD13 (0x02 << 26) |
| 410 | |
| 411 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) |
| 412 | #define S3C2410_GPC14_INP (0x00 << 28) |
| 413 | #define S3C2410_GPC14_OUTP (0x01 << 28) |
| 414 | #define S3C2410_GPC14_VD6 (0x02 << 28) |
| 415 | #define S3C2400_GPC14_VD14 (0x02 << 28) |
| 416 | |
| 417 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) |
| 418 | #define S3C2410_GPC15_INP (0x00 << 30) |
| 419 | #define S3C2410_GPC15_OUTP (0x01 << 30) |
| 420 | #define S3C2410_GPC15_VD7 (0x02 << 30) |
| 421 | #define S3C2400_GPC15_VD15 (0x02 << 30) |
| 422 | |
| 423 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) |
| 424 | |
| 425 | /* |
| 426 | * S3C2410: Port D consists of 16 GPIO/Special function |
| 427 | * |
| 428 | * almost identical setup to port b, but the special functions are mostly |
| 429 | * to do with the video system's data. |
| 430 | * |
| 431 | * S3C2400: Port D consists of 11 GPIO/Special function |
| 432 | * |
| 433 | * almost identical setup to port c |
| 434 | */ |
| 435 | |
| 436 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) |
| 437 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) |
| 438 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) |
| 439 | |
| 440 | #define S3C2400_GPDCON S3C2410_GPIOREG(0x20) |
| 441 | #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) |
| 442 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) |
| 443 | |
| 444 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) |
| 445 | #define S3C2410_GPD0_INP (0x00 << 0) |
| 446 | #define S3C2410_GPD0_OUTP (0x01 << 0) |
| 447 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
| 448 | #define S3C2400_GPD0_VFRAME (0x02 << 0) |
| 449 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) |
| 450 | |
| 451 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) |
| 452 | #define S3C2410_GPD1_INP (0x00 << 2) |
| 453 | #define S3C2410_GPD1_OUTP (0x01 << 2) |
| 454 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
| 455 | #define S3C2400_GPD1_VM (0x02 << 2) |
| 456 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) |
| 457 | |
| 458 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) |
| 459 | #define S3C2410_GPD2_INP (0x00 << 4) |
| 460 | #define S3C2410_GPD2_OUTP (0x01 << 4) |
| 461 | #define S3C2410_GPD2_VD10 (0x02 << 4) |
| 462 | #define S3C2400_GPD2_VLINE (0x02 << 4) |
| 463 | |
| 464 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) |
| 465 | #define S3C2410_GPD3_INP (0x00 << 6) |
| 466 | #define S3C2410_GPD3_OUTP (0x01 << 6) |
| 467 | #define S3C2410_GPD3_VD11 (0x02 << 6) |
| 468 | #define S3C2400_GPD3_VCLK (0x02 << 6) |
| 469 | |
| 470 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) |
| 471 | #define S3C2410_GPD4_INP (0x00 << 8) |
| 472 | #define S3C2410_GPD4_OUTP (0x01 << 8) |
| 473 | #define S3C2410_GPD4_VD12 (0x02 << 8) |
| 474 | #define S3C2400_GPD4_LEND (0x02 << 8) |
| 475 | |
| 476 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) |
| 477 | #define S3C2410_GPD5_INP (0x00 << 10) |
| 478 | #define S3C2410_GPD5_OUTP (0x01 << 10) |
| 479 | #define S3C2410_GPD5_VD13 (0x02 << 10) |
| 480 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) |
| 481 | |
| 482 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) |
| 483 | #define S3C2410_GPD6_INP (0x00 << 12) |
| 484 | #define S3C2410_GPD6_OUTP (0x01 << 12) |
| 485 | #define S3C2410_GPD6_VD14 (0x02 << 12) |
| 486 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) |
| 487 | |
| 488 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) |
| 489 | #define S3C2410_GPD7_INP (0x00 << 14) |
| 490 | #define S3C2410_GPD7_OUTP (0x01 << 14) |
| 491 | #define S3C2410_GPD7_VD15 (0x02 << 14) |
| 492 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) |
| 493 | |
| 494 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) |
| 495 | #define S3C2410_GPD8_INP (0x00 << 16) |
| 496 | #define S3C2410_GPD8_OUTP (0x01 << 16) |
| 497 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
| 498 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) |
| 499 | |
| 500 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) |
| 501 | #define S3C2410_GPD9_INP (0x00 << 18) |
| 502 | #define S3C2410_GPD9_OUTP (0x01 << 18) |
| 503 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
| 504 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) |
| 505 | #define S3C2410_GPD9_MASK (0x03 << 18) |
| 506 | |
| 507 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) |
| 508 | #define S3C2410_GPD10_INP (0x00 << 20) |
| 509 | #define S3C2410_GPD10_OUTP (0x01 << 20) |
| 510 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
| 511 | #define S3C2400_GPD10_nWAIT (0x02 << 20) |
| 512 | |
| 513 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) |
| 514 | #define S3C2410_GPD11_INP (0x00 << 22) |
| 515 | #define S3C2410_GPD11_OUTP (0x01 << 22) |
| 516 | #define S3C2410_GPD11_VD19 (0x02 << 22) |
| 517 | |
| 518 | #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) |
| 519 | #define S3C2410_GPD12_INP (0x00 << 24) |
| 520 | #define S3C2410_GPD12_OUTP (0x01 << 24) |
| 521 | #define S3C2410_GPD12_VD20 (0x02 << 24) |
| 522 | |
| 523 | #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) |
| 524 | #define S3C2410_GPD13_INP (0x00 << 26) |
| 525 | #define S3C2410_GPD13_OUTP (0x01 << 26) |
| 526 | #define S3C2410_GPD13_VD21 (0x02 << 26) |
| 527 | |
| 528 | #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) |
| 529 | #define S3C2410_GPD14_INP (0x00 << 28) |
| 530 | #define S3C2410_GPD14_OUTP (0x01 << 28) |
| 531 | #define S3C2410_GPD14_VD22 (0x02 << 28) |
| 532 | #define S3C2410_GPD14_nSS1 (0x03 << 28) |
| 533 | |
| 534 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) |
| 535 | #define S3C2410_GPD15_INP (0x00 << 30) |
| 536 | #define S3C2410_GPD15_OUTP (0x01 << 30) |
| 537 | #define S3C2410_GPD15_VD23 (0x02 << 30) |
| 538 | #define S3C2410_GPD15_nSS0 (0x03 << 30) |
| 539 | |
| 540 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) |
| 541 | |
| 542 | /* S3C2410: |
| 543 | * Port E consists of 16 GPIO/Special function |
| 544 | * |
| 545 | * again, the same as port B, but dealing with I2S, SDI, and |
| 546 | * more miscellaneous functions |
| 547 | * |
| 548 | * S3C2400: |
| 549 | * Port E consists of 12 GPIO/Special function |
| 550 | * |
| 551 | * GPIO / interrupt inputs |
| 552 | */ |
| 553 | |
| 554 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) |
| 555 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) |
| 556 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) |
| 557 | |
| 558 | #define S3C2400_GPECON S3C2410_GPIOREG(0x2C) |
| 559 | #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) |
| 560 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) |
| 561 | |
| 562 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) |
| 563 | #define S3C2410_GPE0_INP (0x00 << 0) |
| 564 | #define S3C2410_GPE0_OUTP (0x01 << 0) |
| 565 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
| 566 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) |
| 567 | #define S3C2400_GPE0_EINT0 (0x02 << 0) |
| 568 | #define S3C2410_GPE0_MASK (0x03 << 0) |
| 569 | |
| 570 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) |
| 571 | #define S3C2410_GPE1_INP (0x00 << 2) |
| 572 | #define S3C2410_GPE1_OUTP (0x01 << 2) |
| 573 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
| 574 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) |
| 575 | #define S3C2400_GPE1_EINT1 (0x02 << 2) |
| 576 | #define S3C2400_GPE1_nSS (0x03 << 2) |
| 577 | #define S3C2410_GPE1_MASK (0x03 << 2) |
| 578 | |
| 579 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) |
| 580 | #define S3C2410_GPE2_INP (0x00 << 4) |
| 581 | #define S3C2410_GPE2_OUTP (0x01 << 4) |
| 582 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
| 583 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) |
| 584 | #define S3C2400_GPE2_EINT2 (0x02 << 4) |
| 585 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) |
| 586 | |
| 587 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) |
| 588 | #define S3C2410_GPE3_INP (0x00 << 6) |
| 589 | #define S3C2410_GPE3_OUTP (0x01 << 6) |
| 590 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
| 591 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) |
| 592 | #define S3C2400_GPE3_EINT3 (0x02 << 6) |
| 593 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) |
| 594 | #define S3C2410_GPE3_nSS0 (0x03 << 6) |
| 595 | #define S3C2410_GPE3_MASK (0x03 << 6) |
| 596 | |
| 597 | #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) |
| 598 | #define S3C2410_GPE4_INP (0x00 << 8) |
| 599 | #define S3C2410_GPE4_OUTP (0x01 << 8) |
| 600 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
| 601 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) |
| 602 | #define S3C2400_GPE4_EINT4 (0x02 << 8) |
| 603 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) |
| 604 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) |
| 605 | #define S3C2410_GPE4_MASK (0x03 << 8) |
| 606 | |
| 607 | #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) |
| 608 | #define S3C2410_GPE5_INP (0x00 << 10) |
| 609 | #define S3C2410_GPE5_OUTP (0x01 << 10) |
| 610 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
| 611 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) |
| 612 | #define S3C2400_GPE5_EINT5 (0x02 << 10) |
| 613 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) |
| 614 | |
| 615 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) |
| 616 | #define S3C2410_GPE6_INP (0x00 << 12) |
| 617 | #define S3C2410_GPE6_OUTP (0x01 << 12) |
| 618 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
| 619 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) |
| 620 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) |
| 621 | #define S3C2400_GPE6_EINT6 (0x02 << 12) |
| 622 | |
| 623 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) |
| 624 | #define S3C2410_GPE7_INP (0x00 << 14) |
| 625 | #define S3C2410_GPE7_OUTP (0x01 << 14) |
| 626 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
| 627 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) |
| 628 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) |
| 629 | #define S3C2400_GPE7_EINT7 (0x02 << 14) |
| 630 | |
| 631 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) |
| 632 | #define S3C2410_GPE8_INP (0x00 << 16) |
| 633 | #define S3C2410_GPE8_OUTP (0x01 << 16) |
| 634 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
| 635 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) |
| 636 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) |
| 637 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) |
| 638 | |
| 639 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) |
| 640 | #define S3C2410_GPE9_INP (0x00 << 18) |
| 641 | #define S3C2410_GPE9_OUTP (0x01 << 18) |
| 642 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
| 643 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) |
| 644 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) |
| 645 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) |
| 646 | #define S3C2400_GPE9_nXBACK (0x03 << 18) |
| 647 | |
| 648 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) |
| 649 | #define S3C2410_GPE10_INP (0x00 << 20) |
| 650 | #define S3C2410_GPE10_OUTP (0x01 << 20) |
| 651 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
| 652 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) |
| 653 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) |
| 654 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) |
| 655 | |
| 656 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) |
| 657 | #define S3C2410_GPE11_INP (0x00 << 22) |
| 658 | #define S3C2410_GPE11_OUTP (0x01 << 22) |
| 659 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |
| 660 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) |
| 661 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) |
| 662 | |
| 663 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) |
| 664 | #define S3C2410_GPE12_INP (0x00 << 24) |
| 665 | #define S3C2410_GPE12_OUTP (0x01 << 24) |
| 666 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) |
| 667 | |
| 668 | #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) |
| 669 | #define S3C2410_GPE13_INP (0x00 << 26) |
| 670 | #define S3C2410_GPE13_OUTP (0x01 << 26) |
| 671 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) |
| 672 | |
| 673 | #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) |
| 674 | #define S3C2410_GPE14_INP (0x00 << 28) |
| 675 | #define S3C2410_GPE14_OUTP (0x01 << 28) |
| 676 | #define S3C2410_GPE14_IICSCL (0x02 << 28) |
| 677 | #define S3C2410_GPE14_MASK (0x03 << 28) |
| 678 | |
| 679 | #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) |
| 680 | #define S3C2410_GPE15_INP (0x00 << 30) |
| 681 | #define S3C2410_GPE15_OUTP (0x01 << 30) |
| 682 | #define S3C2410_GPE15_IICSDA (0x02 << 30) |
| 683 | #define S3C2410_GPE15_MASK (0x03 << 30) |
| 684 | |
| 685 | #define S3C2440_GPE0_ACSYNC (0x03 << 0) |
| 686 | #define S3C2440_GPE1_ACBITCLK (0x03 << 2) |
| 687 | #define S3C2440_GPE2_ACRESET (0x03 << 4) |
| 688 | #define S3C2440_GPE3_ACIN (0x03 << 6) |
| 689 | #define S3C2440_GPE4_ACOUT (0x03 << 8) |
| 690 | |
| 691 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) |
| 692 | |
| 693 | /* S3C2410: |
| 694 | * Port F consists of 8 GPIO/Special function |
| 695 | * |
| 696 | * GPIO / interrupt inputs |
| 697 | * |
| 698 | * GPFCON has 2 bits for each of the input pins on port F |
| 699 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined |
| 700 | * |
| 701 | * pull up works like all other ports. |
| 702 | * |
| 703 | * S3C2400: |
| 704 | * Port F consists of 7 GPIO/Special function |
| 705 | * |
| 706 | * GPIO/serial/misc pins |
| 707 | */ |
| 708 | |
| 709 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) |
| 710 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) |
| 711 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) |
| 712 | |
| 713 | #define S3C2400_GPFCON S3C2410_GPIOREG(0x38) |
| 714 | #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) |
| 715 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) |
| 716 | |
| 717 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) |
| 718 | #define S3C2410_GPF0_INP (0x00 << 0) |
| 719 | #define S3C2410_GPF0_OUTP (0x01 << 0) |
| 720 | #define S3C2410_GPF0_EINT0 (0x02 << 0) |
| 721 | #define S3C2400_GPF0_RXD0 (0x02 << 0) |
| 722 | |
| 723 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) |
| 724 | #define S3C2410_GPF1_INP (0x00 << 2) |
| 725 | #define S3C2410_GPF1_OUTP (0x01 << 2) |
| 726 | #define S3C2410_GPF1_EINT1 (0x02 << 2) |
| 727 | #define S3C2400_GPF1_RXD1 (0x02 << 2) |
| 728 | #define S3C2400_GPF1_IICSDA (0x03 << 2) |
| 729 | |
| 730 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) |
| 731 | #define S3C2410_GPF2_INP (0x00 << 4) |
| 732 | #define S3C2410_GPF2_OUTP (0x01 << 4) |
| 733 | #define S3C2410_GPF2_EINT2 (0x02 << 4) |
| 734 | #define S3C2400_GPF2_TXD0 (0x02 << 4) |
| 735 | |
| 736 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) |
| 737 | #define S3C2410_GPF3_INP (0x00 << 6) |
| 738 | #define S3C2410_GPF3_OUTP (0x01 << 6) |
| 739 | #define S3C2410_GPF3_EINT3 (0x02 << 6) |
| 740 | #define S3C2400_GPF3_TXD1 (0x02 << 6) |
| 741 | #define S3C2400_GPF3_IICSCL (0x03 << 6) |
| 742 | |
| 743 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) |
| 744 | #define S3C2410_GPF4_INP (0x00 << 8) |
| 745 | #define S3C2410_GPF4_OUTP (0x01 << 8) |
| 746 | #define S3C2410_GPF4_EINT4 (0x02 << 8) |
| 747 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) |
| 748 | #define S3C2400_GPF4_nXBACK (0x03 << 8) |
| 749 | |
| 750 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) |
| 751 | #define S3C2410_GPF5_INP (0x00 << 10) |
| 752 | #define S3C2410_GPF5_OUTP (0x01 << 10) |
| 753 | #define S3C2410_GPF5_EINT5 (0x02 << 10) |
| 754 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) |
| 755 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) |
| 756 | |
| 757 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) |
| 758 | #define S3C2410_GPF6_INP (0x00 << 12) |
| 759 | #define S3C2410_GPF6_OUTP (0x01 << 12) |
| 760 | #define S3C2410_GPF6_EINT6 (0x02 << 12) |
| 761 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) |
| 762 | |
| 763 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) |
| 764 | #define S3C2410_GPF7_INP (0x00 << 14) |
| 765 | #define S3C2410_GPF7_OUTP (0x01 << 14) |
| 766 | #define S3C2410_GPF7_EINT7 (0x02 << 14) |
| 767 | |
| 768 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) |
| 769 | |
| 770 | /* S3C2410: |
| 771 | * Port G consists of 8 GPIO/IRQ/Special function |
| 772 | * |
| 773 | * GPGCON has 2 bits for each of the input pins on port F |
| 774 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
| 775 | * |
| 776 | * pull up works like all other ports. |
| 777 | * |
| 778 | * S3C2400: |
| 779 | * Port G consists of 10 GPIO/Special function |
| 780 | */ |
| 781 | |
| 782 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) |
| 783 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) |
| 784 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) |
| 785 | |
| 786 | #define S3C2400_GPGCON S3C2410_GPIOREG(0x44) |
| 787 | #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) |
| 788 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) |
| 789 | |
| 790 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) |
| 791 | #define S3C2410_GPG0_INP (0x00 << 0) |
| 792 | #define S3C2410_GPG0_OUTP (0x01 << 0) |
| 793 | #define S3C2410_GPG0_EINT8 (0x02 << 0) |
| 794 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) |
| 795 | |
| 796 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) |
| 797 | #define S3C2410_GPG1_INP (0x00 << 2) |
| 798 | #define S3C2410_GPG1_OUTP (0x01 << 2) |
| 799 | #define S3C2410_GPG1_EINT9 (0x02 << 2) |
| 800 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) |
| 801 | |
| 802 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) |
| 803 | #define S3C2410_GPG2_INP (0x00 << 4) |
| 804 | #define S3C2410_GPG2_OUTP (0x01 << 4) |
| 805 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
| 806 | #define S3C2410_GPG2_nSS0 (0x03 << 4) |
| 807 | #define S3C2400_GPG2_CDCLK (0x02 << 4) |
| 808 | |
| 809 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) |
| 810 | #define S3C2410_GPG3_INP (0x00 << 6) |
| 811 | #define S3C2410_GPG3_OUTP (0x01 << 6) |
| 812 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
| 813 | #define S3C2410_GPG3_nSS1 (0x03 << 6) |
| 814 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) |
| 815 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) |
| 816 | |
| 817 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) |
| 818 | #define S3C2410_GPG4_INP (0x00 << 8) |
| 819 | #define S3C2410_GPG4_OUTP (0x01 << 8) |
| 820 | #define S3C2410_GPG4_EINT12 (0x02 << 8) |
| 821 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) |
| 822 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) |
| 823 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) |
| 824 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) |
| 825 | |
| 826 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) |
| 827 | #define S3C2410_GPG5_INP (0x00 << 10) |
| 828 | #define S3C2410_GPG5_OUTP (0x01 << 10) |
| 829 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
| 830 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) |
| 831 | #define S3C2400_GPG5_IICSDA (0x03 << 10) |
| 832 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ |
| 833 | |
| 834 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) |
| 835 | #define S3C2410_GPG6_INP (0x00 << 12) |
| 836 | #define S3C2410_GPG6_OUTP (0x01 << 12) |
| 837 | #define S3C2410_GPG6_EINT14 (0x02 << 12) |
| 838 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) |
| 839 | #define S3C2400_GPG6_IICSCL (0x03 << 12) |
| 840 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) |
| 841 | |
| 842 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) |
| 843 | #define S3C2410_GPG7_INP (0x00 << 14) |
| 844 | #define S3C2410_GPG7_OUTP (0x01 << 14) |
| 845 | #define S3C2410_GPG7_EINT15 (0x02 << 14) |
| 846 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) |
| 847 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) |
| 848 | #define S3C2400_GPG7_IICSDA (0x03 << 14) |
| 849 | |
| 850 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) |
| 851 | #define S3C2410_GPG8_INP (0x00 << 16) |
| 852 | #define S3C2410_GPG8_OUTP (0x01 << 16) |
| 853 | #define S3C2410_GPG8_EINT16 (0x02 << 16) |
| 854 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) |
| 855 | #define S3C2400_GPG8_IICSCL (0x03 << 16) |
| 856 | |
| 857 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) |
| 858 | #define S3C2410_GPG9_INP (0x00 << 18) |
| 859 | #define S3C2410_GPG9_OUTP (0x01 << 18) |
| 860 | #define S3C2410_GPG9_EINT17 (0x02 << 18) |
| 861 | #define S3C2400_GPG9_SPICLK (0x02 << 18) |
| 862 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) |
| 863 | |
| 864 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) |
| 865 | #define S3C2410_GPG10_INP (0x00 << 20) |
| 866 | #define S3C2410_GPG10_OUTP (0x01 << 20) |
| 867 | #define S3C2410_GPG10_EINT18 (0x02 << 20) |
| 868 | |
| 869 | #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) |
| 870 | #define S3C2410_GPG11_INP (0x00 << 22) |
| 871 | #define S3C2410_GPG11_OUTP (0x01 << 22) |
| 872 | #define S3C2410_GPG11_EINT19 (0x02 << 22) |
| 873 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) |
| 874 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) |
| 875 | |
| 876 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) |
| 877 | #define S3C2410_GPG12_INP (0x00 << 24) |
| 878 | #define S3C2410_GPG12_OUTP (0x01 << 24) |
| 879 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
| 880 | #define S3C2410_GPG12_XMON (0x03 << 24) |
| 881 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) |
| 882 | #define S3C2443_GPG12_nINPACK (0x03 << 24) |
| 883 | |
| 884 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) |
| 885 | #define S3C2410_GPG13_INP (0x00 << 26) |
| 886 | #define S3C2410_GPG13_OUTP (0x01 << 26) |
| 887 | #define S3C2410_GPG13_EINT21 (0x02 << 26) |
| 888 | #define S3C2410_GPG13_nXPON (0x03 << 26) |
| 889 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) |
| 890 | |
| 891 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) |
| 892 | #define S3C2410_GPG14_INP (0x00 << 28) |
| 893 | #define S3C2410_GPG14_OUTP (0x01 << 28) |
| 894 | #define S3C2410_GPG14_EINT22 (0x02 << 28) |
| 895 | #define S3C2410_GPG14_YMON (0x03 << 28) |
| 896 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) |
| 897 | |
| 898 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) |
| 899 | #define S3C2410_GPG15_INP (0x00 << 30) |
| 900 | #define S3C2410_GPG15_OUTP (0x01 << 30) |
| 901 | #define S3C2410_GPG15_EINT23 (0x02 << 30) |
| 902 | #define S3C2410_GPG15_nYPON (0x03 << 30) |
| 903 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) |
| 904 | |
| 905 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) |
| 906 | |
| 907 | /* Port H consists of11 GPIO/serial/Misc pins |
| 908 | * |
| 909 | * GPGCON has 2 bits for each of the input pins on port F |
| 910 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
| 911 | * |
| 912 | * pull up works like all other ports. |
| 913 | */ |
| 914 | |
| 915 | #define S3C2410_GPHCON S3C2410_GPIOREG(0x70) |
| 916 | #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) |
| 917 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) |
| 918 | |
| 919 | #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) |
| 920 | #define S3C2410_GPH0_INP (0x00 << 0) |
| 921 | #define S3C2410_GPH0_OUTP (0x01 << 0) |
| 922 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) |
| 923 | |
| 924 | #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) |
| 925 | #define S3C2410_GPH1_INP (0x00 << 2) |
| 926 | #define S3C2410_GPH1_OUTP (0x01 << 2) |
| 927 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) |
| 928 | |
| 929 | #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) |
| 930 | #define S3C2410_GPH2_INP (0x00 << 4) |
| 931 | #define S3C2410_GPH2_OUTP (0x01 << 4) |
| 932 | #define S3C2410_GPH2_TXD0 (0x02 << 4) |
| 933 | |
| 934 | #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) |
| 935 | #define S3C2410_GPH3_INP (0x00 << 6) |
| 936 | #define S3C2410_GPH3_OUTP (0x01 << 6) |
| 937 | #define S3C2410_GPH3_RXD0 (0x02 << 6) |
| 938 | |
| 939 | #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) |
| 940 | #define S3C2410_GPH4_INP (0x00 << 8) |
| 941 | #define S3C2410_GPH4_OUTP (0x01 << 8) |
| 942 | #define S3C2410_GPH4_TXD1 (0x02 << 8) |
| 943 | |
| 944 | #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) |
| 945 | #define S3C2410_GPH5_INP (0x00 << 10) |
| 946 | #define S3C2410_GPH5_OUTP (0x01 << 10) |
| 947 | #define S3C2410_GPH5_RXD1 (0x02 << 10) |
| 948 | |
| 949 | #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) |
| 950 | #define S3C2410_GPH6_INP (0x00 << 12) |
| 951 | #define S3C2410_GPH6_OUTP (0x01 << 12) |
| 952 | #define S3C2410_GPH6_TXD2 (0x02 << 12) |
| 953 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) |
| 954 | |
| 955 | #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) |
| 956 | #define S3C2410_GPH7_INP (0x00 << 14) |
| 957 | #define S3C2410_GPH7_OUTP (0x01 << 14) |
| 958 | #define S3C2410_GPH7_RXD2 (0x02 << 14) |
| 959 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) |
| 960 | |
| 961 | #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) |
| 962 | #define S3C2410_GPH8_INP (0x00 << 16) |
| 963 | #define S3C2410_GPH8_OUTP (0x01 << 16) |
| 964 | #define S3C2410_GPH8_UCLK (0x02 << 16) |
| 965 | |
| 966 | #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) |
| 967 | #define S3C2410_GPH9_INP (0x00 << 18) |
| 968 | #define S3C2410_GPH9_OUTP (0x01 << 18) |
| 969 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) |
| 970 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) |
| 971 | |
| 972 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) |
| 973 | #define S3C2410_GPH10_INP (0x00 << 20) |
| 974 | #define S3C2410_GPH10_OUTP (0x01 << 20) |
| 975 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) |
| 976 | |
| 977 | /* The S3C2412 and S3C2413 move the GPJ register set to after |
| 978 | * GPH, which means all registers after 0x80 are now offset by 0x10 |
| 979 | * for the 2412/2413 from the 2410/2440/2442 |
| 980 | */ |
| 981 | |
| 982 | /* miscellaneous control */ |
| 983 | #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) |
| 984 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) |
| 985 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) |
| 986 | |
| 987 | #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) |
| 988 | |
| 989 | /* see clock.h for dclk definitions */ |
| 990 | |
| 991 | /* pullup control on databus */ |
| 992 | #define S3C2410_MISCCR_SPUCR_HEN (0<<0) |
| 993 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) |
| 994 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) |
| 995 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) |
| 996 | |
| 997 | #define S3C2400_MISCCR_SPUCR_LEN (0<<0) |
| 998 | #define S3C2400_MISCCR_SPUCR_LDIS (1<<0) |
| 999 | #define S3C2400_MISCCR_SPUCR_HEN (0<<1) |
| 1000 | #define S3C2400_MISCCR_SPUCR_HDIS (1<<1) |
| 1001 | |
| 1002 | #define S3C2400_MISCCR_HZ_STOPEN (0<<2) |
| 1003 | #define S3C2400_MISCCR_HZ_STOPPREV (1<<2) |
| 1004 | |
| 1005 | #define S3C2410_MISCCR_USBDEV (0<<3) |
| 1006 | #define S3C2410_MISCCR_USBHOST (1<<3) |
| 1007 | |
| 1008 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) |
| 1009 | #define S3C2410_MISCCR_CLK0_UPLL (1<<4) |
| 1010 | #define S3C2410_MISCCR_CLK0_FCLK (2<<4) |
| 1011 | #define S3C2410_MISCCR_CLK0_HCLK (3<<4) |
| 1012 | #define S3C2410_MISCCR_CLK0_PCLK (4<<4) |
| 1013 | #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) |
| 1014 | #define S3C2410_MISCCR_CLK0_MASK (7<<4) |
| 1015 | |
| 1016 | #define S3C2412_MISCCR_CLK0_RTC (2<<4) |
| 1017 | |
| 1018 | #define S3C2410_MISCCR_CLK1_MPLL (0<<8) |
| 1019 | #define S3C2410_MISCCR_CLK1_UPLL (1<<8) |
| 1020 | #define S3C2410_MISCCR_CLK1_FCLK (2<<8) |
| 1021 | #define S3C2410_MISCCR_CLK1_HCLK (3<<8) |
| 1022 | #define S3C2410_MISCCR_CLK1_PCLK (4<<8) |
| 1023 | #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) |
| 1024 | #define S3C2410_MISCCR_CLK1_MASK (7<<8) |
| 1025 | |
| 1026 | #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) |
| 1027 | |
| 1028 | #define S3C2410_MISCCR_USBSUSPND0 (1<<12) |
| 1029 | #define S3C2410_MISCCR_USBSUSPND1 (1<<13) |
| 1030 | |
| 1031 | #define S3C2410_MISCCR_nRSTCON (1<<16) |
| 1032 | |
| 1033 | #define S3C2410_MISCCR_nEN_SCLK0 (1<<17) |
| 1034 | #define S3C2410_MISCCR_nEN_SCLK1 (1<<18) |
| 1035 | #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ |
| 1036 | #define S3C2410_MISCCR_SDSLEEP (7<<17) |
| 1037 | |
| 1038 | /* external interrupt control... */ |
| 1039 | /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 |
| 1040 | * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 |
| 1041 | * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 |
| 1042 | * |
| 1043 | * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 |
| 1044 | * |
| 1045 | * Samsung datasheet p9-25 |
| 1046 | */ |
| 1047 | #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) |
| 1048 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) |
| 1049 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) |
| 1050 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) |
| 1051 | |
| 1052 | #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) |
| 1053 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) |
| 1054 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) |
| 1055 | |
| 1056 | /* values for S3C2410_EXTINT0/1/2 */ |
| 1057 | #define S3C2410_EXTINT_LOWLEV (0x00) |
| 1058 | #define S3C2410_EXTINT_HILEV (0x01) |
| 1059 | #define S3C2410_EXTINT_FALLEDGE (0x02) |
| 1060 | #define S3C2410_EXTINT_RISEEDGE (0x04) |
| 1061 | #define S3C2410_EXTINT_BOTHEDGE (0x06) |
| 1062 | |
| 1063 | /* interrupt filtering conrrol for EINT16..EINT23 */ |
| 1064 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) |
| 1065 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) |
| 1066 | #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) |
| 1067 | #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) |
| 1068 | |
| 1069 | #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) |
| 1070 | #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) |
| 1071 | #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) |
| 1072 | #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) |
| 1073 | |
| 1074 | /* values for interrupt filtering */ |
| 1075 | #define S3C2410_EINTFLT_PCLK (0x00) |
| 1076 | #define S3C2410_EINTFLT_EXTCLK (1<<7) |
| 1077 | #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) |
| 1078 | |
| 1079 | /* removed EINTxxxx defs from here, not meant for this */ |
| 1080 | |
| 1081 | /* GSTATUS have miscellaneous information in them |
| 1082 | * |
| 1083 | * These move between s3c2410 and s3c2412 style systems. |
| 1084 | */ |
| 1085 | |
| 1086 | #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) |
| 1087 | #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) |
| 1088 | #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) |
| 1089 | #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) |
| 1090 | #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) |
| 1091 | |
| 1092 | #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) |
| 1093 | #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) |
| 1094 | #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) |
| 1095 | #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) |
| 1096 | #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) |
| 1097 | |
| 1098 | #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) |
| 1099 | #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) |
| 1100 | #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) |
| 1101 | #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) |
| 1102 | #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) |
| 1103 | |
| 1104 | #define S3C2410_GSTATUS0_nWAIT (1<<3) |
| 1105 | #define S3C2410_GSTATUS0_NCON (1<<2) |
| 1106 | #define S3C2410_GSTATUS0_RnB (1<<1) |
| 1107 | #define S3C2410_GSTATUS0_nBATTFLT (1<<0) |
| 1108 | |
| 1109 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) |
| 1110 | #define S3C2410_GSTATUS1_2410 (0x32410000) |
| 1111 | #define S3C2410_GSTATUS1_2412 (0x32412001) |
| 1112 | #define S3C2410_GSTATUS1_2440 (0x32440000) |
| 1113 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) |
| 1114 | |
| 1115 | #define S3C2410_GSTATUS2_WTRESET (1<<2) |
| 1116 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) |
| 1117 | #define S3C2410_GSTATUS2_PONRESET (1<<0) |
| 1118 | |
| 1119 | /* open drain control register */ |
| 1120 | #define S3C2400_OPENCR S3C2410_GPIOREG(0x50) |
| 1121 | |
| 1122 | #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) |
| 1123 | #define S3C2400_OPENCR_OPC_RXD1EN (1<<0) |
| 1124 | #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) |
| 1125 | #define S3C2400_OPENCR_OPC_TXD1EN (1<<1) |
| 1126 | #define S3C2400_OPENCR_OPC_CMDDIS (0<<2) |
| 1127 | #define S3C2400_OPENCR_OPC_CMDEN (1<<2) |
| 1128 | #define S3C2400_OPENCR_OPC_DATDIS (0<<3) |
| 1129 | #define S3C2400_OPENCR_OPC_DATEN (1<<3) |
| 1130 | #define S3C2400_OPENCR_OPC_MISODIS (0<<4) |
| 1131 | #define S3C2400_OPENCR_OPC_MISOEN (1<<4) |
| 1132 | #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) |
| 1133 | #define S3C2400_OPENCR_OPC_MOSIEN (1<<5) |
| 1134 | |
| 1135 | /* 2412/2413 sleep configuration registers */ |
| 1136 | |
| 1137 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) |
| 1138 | #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) |
| 1139 | #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) |
| 1140 | #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) |
| 1141 | #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) |
| 1142 | #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) |
| 1143 | |
| 1144 | /* definitions for each pin bit */ |
| 1145 | #define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) |
| 1146 | #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) |
| 1147 | #define S3C2412_GPIO_SLPCON_IN ( 0x02 ) |
| 1148 | #define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) |
| 1149 | |
| 1150 | #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) |
| 1151 | #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) |
| 1152 | #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) |
| 1153 | #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) |
| 1154 | #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ |
| 1155 | #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) |
| 1156 | |
| 1157 | #define S3C2412_SLPCON_ALL_LOW (0x0) |
| 1158 | #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) |
| 1159 | #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) |
| 1160 | #define S3C2412_SLPCON_ALL_PULL (0x33333333) |
| 1161 | |
| 1162 | #endif /* __ASM_ARCH_REGS_GPIO_H */ |
| 1163 | |