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Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -07001/*
2 * pci_regs.h
3 *
4 * PCI standard defines
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
Eric W. Biedermane78d0162006-10-04 02:16:54 -070015 *
16 * For hypertransport information, please consult the following manuals
17 * from http://www.hypertransport.org
18 *
19 * The Hypertransport I/O Link Specification
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -070020 */
21
22#ifndef LINUX_PCI_REGS_H
23#define LINUX_PCI_REGS_H
24
25/*
26 * Under PCI, each device has 256 bytes of configuration address space,
27 * of which the first 64 bytes are standardized as follows:
28 */
Alex Williamsona0dee2e2012-06-11 05:27:45 +000029#define PCI_STD_HEADER_SIZEOF 64
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -070030#define PCI_VENDOR_ID 0x00 /* 16 bits */
31#define PCI_DEVICE_ID 0x02 /* 16 bits */
32#define PCI_COMMAND 0x04 /* 16 bits */
33#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
34#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
35#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
36#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
37#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
38#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
39#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
40#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
41#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
42#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
43#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
44
45#define PCI_STATUS 0x06 /* 16 bits */
Michael S. Tsirkinccb86a62009-07-20 10:29:34 +030046#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -070047#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
48#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
49#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
50#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
51#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
52#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
53#define PCI_STATUS_DEVSEL_FAST 0x000
54#define PCI_STATUS_DEVSEL_MEDIUM 0x200
55#define PCI_STATUS_DEVSEL_SLOW 0x400
56#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
57#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
58#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
59#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
60#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
61
62#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
63#define PCI_REVISION_ID 0x08 /* Revision ID */
64#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
65#define PCI_CLASS_DEVICE 0x0a /* Device class */
66
67#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
68#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
69#define PCI_HEADER_TYPE 0x0e /* 8 bits */
70#define PCI_HEADER_TYPE_NORMAL 0
71#define PCI_HEADER_TYPE_BRIDGE 1
72#define PCI_HEADER_TYPE_CARDBUS 2
73
74#define PCI_BIST 0x0f /* 8 bits */
75#define PCI_BIST_CODE_MASK 0x0f /* Return result */
76#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
77#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
78
79/*
80 * Base addresses specify locations in memory or I/O space.
81 * Decoded size can be determined by writing a value of
82 * 0xffffffff to the register, and reading it back. Only
83 * 1 bits are decoded.
84 */
85#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
86#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
87#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
88#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
89#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
90#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
91#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
92#define PCI_BASE_ADDRESS_SPACE_IO 0x01
93#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
94#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
95#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
96#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
97#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
98#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
99#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
100#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
101/* bit 1 is reserved if address_space = 1 */
102
103/* Header type 0 (normal devices) */
104#define PCI_CARDBUS_CIS 0x28
105#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
106#define PCI_SUBSYSTEM_ID 0x2e
107#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
108#define PCI_ROM_ADDRESS_ENABLE 0x01
109#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
110
111#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
112
113/* 0x35-0x3b are reserved */
114#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
115#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
116#define PCI_MIN_GNT 0x3e /* 8 bits */
117#define PCI_MAX_LAT 0x3f /* 8 bits */
118
119/* Header type 1 (PCI-to-PCI bridges) */
120#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
121#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
122#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
123#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
124#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
125#define PCI_IO_LIMIT 0x1d
126#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
127#define PCI_IO_RANGE_TYPE_16 0x00
128#define PCI_IO_RANGE_TYPE_32 0x01
129#define PCI_IO_RANGE_MASK (~0x0fUL)
130#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
131#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
132#define PCI_MEMORY_LIMIT 0x22
133#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
134#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
135#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
136#define PCI_PREF_MEMORY_LIMIT 0x26
137#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
138#define PCI_PREF_RANGE_TYPE_32 0x00
139#define PCI_PREF_RANGE_TYPE_64 0x01
140#define PCI_PREF_RANGE_MASK (~0x0fUL)
141#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
142#define PCI_PREF_LIMIT_UPPER32 0x2c
143#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
144#define PCI_IO_LIMIT_UPPER16 0x32
145/* 0x34 same as for htype 0 */
146/* 0x35-0x3b is reserved */
147#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
148/* 0x3c-0x3d are same as for htype 0 */
149#define PCI_BRIDGE_CONTROL 0x3e
150#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
151#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
Gary Hade11949252007-10-08 16:24:16 -0700152#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700153#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
154#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
155#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
156#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
157
158/* Header type 2 (CardBus bridges) */
159#define PCI_CB_CAPABILITY_LIST 0x14
160/* 0x15 reserved */
161#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
162#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
163#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
164#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
165#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
166#define PCI_CB_MEMORY_BASE_0 0x1c
167#define PCI_CB_MEMORY_LIMIT_0 0x20
168#define PCI_CB_MEMORY_BASE_1 0x24
169#define PCI_CB_MEMORY_LIMIT_1 0x28
170#define PCI_CB_IO_BASE_0 0x2c
171#define PCI_CB_IO_BASE_0_HI 0x2e
172#define PCI_CB_IO_LIMIT_0 0x30
173#define PCI_CB_IO_LIMIT_0_HI 0x32
174#define PCI_CB_IO_BASE_1 0x34
175#define PCI_CB_IO_BASE_1_HI 0x36
176#define PCI_CB_IO_LIMIT_1 0x38
177#define PCI_CB_IO_LIMIT_1_HI 0x3a
178#define PCI_CB_IO_RANGE_MASK (~0x03UL)
179/* 0x3c-0x3d are same as for htype 0 */
180#define PCI_CB_BRIDGE_CONTROL 0x3e
181#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
182#define PCI_CB_BRIDGE_CTL_SERR 0x02
183#define PCI_CB_BRIDGE_CTL_ISA 0x04
184#define PCI_CB_BRIDGE_CTL_VGA 0x08
185#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
186#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
187#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
188#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
189#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
190#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
191#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
192#define PCI_CB_SUBSYSTEM_ID 0x42
193#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
194/* 0x48-0x7f reserved */
195
196/* Capability lists */
197
198#define PCI_CAP_LIST_ID 0 /* Capability ID */
199#define PCI_CAP_ID_PM 0x01 /* Power Management */
200#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
201#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
202#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
203#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
204#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
205#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
Brice Goglin46ff3462006-08-31 01:55:24 -0400206#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
Alex Chiang9f672152007-08-21 17:49:07 -0600207#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
208#define PCI_CAP_ID_DBG 0x0A /* Debug port */
209#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700210#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
Alex Chiang9f672152007-08-21 17:49:07 -0600211#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
212#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000213#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700214#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
215#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000216#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
Sheng Yangf7b7baa2008-11-11 17:17:46 +0800217#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000218#define PCI_CAP_ID_MAX PCI_CAP_ID_AF
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700219#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
220#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
221#define PCI_CAP_SIZEOF 4
222
223/* Power Management Registers */
224
225#define PCI_PM_PMC 2 /* PM Capabilities Register */
226#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
227#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
228#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
229#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300230#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700231#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
232#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
233#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
234#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
235#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
236#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
237#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
238#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
239#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200240#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700241#define PCI_PM_CTRL 4 /* PM control and status register */
242#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
Yu Zhao998dd7c2009-02-25 13:15:52 +0800243#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700244#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
245#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
246#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
247#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
248#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
249#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
250#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
251#define PCI_PM_DATA_REGISTER 7 /* (??) */
252#define PCI_PM_SIZEOF 8
253
254/* AGP registers */
255
256#define PCI_AGP_VERSION 2 /* BCD version number */
257#define PCI_AGP_RFU 3 /* Rest of capability flags */
258#define PCI_AGP_STATUS 4 /* Status register */
259#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
260#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
261#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
262#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
263#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
264#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
265#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
266#define PCI_AGP_COMMAND 8 /* Control register */
267#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
268#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
269#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
270#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
271#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
272#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
273#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
274#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
275#define PCI_AGP_SIZEOF 12
276
277/* Vital Product Data */
278
279#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
280#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
281#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
282#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000283#define PCI_CAP_VPD_SIZEOF 8
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700284
285/* Slot Identification */
286
287#define PCI_SID_ESR 2 /* Expansion Slot Register */
288#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
289#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
290#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
291
292/* Message Signalled Interrupts registers */
293
294#define PCI_MSI_FLAGS 2 /* Various flags */
295#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
296#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
297#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
298#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
299#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
300#define PCI_MSI_RFU 3 /* Rest of capability flags */
301#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
302#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
303#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
Hidetoshi Seto67b5db62009-04-20 10:54:59 +0900304#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000305#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700306#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
Hidetoshi Seto67b5db62009-04-20 10:54:59 +0900307#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000308#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700309
Hidetoshi Setodb500412010-10-13 15:00:23 +0900310/* MSI-X registers */
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -0800311#define PCI_MSIX_FLAGS 2
312#define PCI_MSIX_FLAGS_QSIZE 0x7FF
313#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
Eric W. Biederman392ee1e2007-03-08 13:04:57 -0700314#define PCI_MSIX_FLAGS_MASKALL (1 << 14)
Hidetoshi Setodb500412010-10-13 15:00:23 +0900315#define PCI_MSIX_TABLE 4
316#define PCI_MSIX_PBA 8
317#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000318#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
Michael Ellermane65e5fb2006-11-07 18:21:21 +1100319
Sheng Yang00aaaef2010-11-11 15:46:54 +0800320/* MSI-X entry's format */
321#define PCI_MSIX_ENTRY_SIZE 16
322#define PCI_MSIX_ENTRY_LOWER_ADDR 0
323#define PCI_MSIX_ENTRY_UPPER_ADDR 4
324#define PCI_MSIX_ENTRY_DATA 8
325#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
Sheng Yang8d805282010-11-11 15:46:55 +0800326#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
Sheng Yang00aaaef2010-11-11 15:46:54 +0800327
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700328/* CompactPCI Hotswap Register */
329
330#define PCI_CHSWP_CSR 2 /* Control and Status Register */
331#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
332#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
333#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
334#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
335#define PCI_CHSWP_PI 0x30 /* Programming Interface */
336#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
337#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
338
Sheng Yangf7b7baa2008-11-11 17:17:46 +0800339/* PCI Advanced Feature registers */
340
341#define PCI_AF_LENGTH 2
342#define PCI_AF_CAP 3
343#define PCI_AF_CAP_TP 0x01
344#define PCI_AF_CAP_FLR 0x02
345#define PCI_AF_CTRL 4
346#define PCI_AF_CTRL_FLR 0x01
347#define PCI_AF_STATUS 5
348#define PCI_AF_STATUS_TP 0x01
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000349#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */
Sheng Yangf7b7baa2008-11-11 17:17:46 +0800350
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700351/* PCI-X registers */
352
353#define PCI_X_CMD 2 /* Modes & Features */
354#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
355#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
Matt Carlson9974a352007-10-07 23:27:28 -0700356#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
357#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
358#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
359#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700360#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
Matt Carlson9974a352007-10-07 23:27:28 -0700361 /* Max # of outstanding split transactions */
362#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */
363#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */
364#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */
365#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */
366#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */
367#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */
368#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */
369#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700370#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
371#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
372#define PCI_X_STATUS 4 /* PCI-X capabilities */
373#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
374#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
375#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
376#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
377#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
378#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
379#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
380#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
381#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
382#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
383#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
384#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
385#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000386#define PCI_X_ECC_CSR 8 /* ECC control and status */
387#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */
388#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */
389#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700390
Gabe Blackbc577d22009-10-06 10:45:19 -0500391/* PCI Bridge Subsystem ID registers */
392
393#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
394#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */
395
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700396/* PCI Express capability registers */
397
398#define PCI_EXP_FLAGS 2 /* Capabilities register */
399#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
400#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
401#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
402#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
403#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
404#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
405#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
406#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
Anthony PERARD9ad52e62012-02-21 16:22:10 +0000407#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
Yu Zhaod1b054d2009-03-20 11:25:11 +0800408#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
Alex Williamson1830ea912011-11-16 09:24:16 -0700409#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700410#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
411#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
412#define PCI_EXP_DEVCAP 4 /* Device capabilities */
413#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
414#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
415#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
416#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
417#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
418#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
419#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
420#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
Shaohua Li149e1632008-07-23 10:32:31 +0800421#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700422#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
423#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
Sheng Yang8dd7f802008-10-21 17:38:25 +0800424#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700425#define PCI_EXP_DEVCTL 8 /* Device Control */
426#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
427#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
428#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
429#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
430#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
431#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
432#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
433#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
434#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
435#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
436#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
Sheng Yang8dd7f802008-10-21 17:38:25 +0800437#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700438#define PCI_EXP_DEVSTA 10 /* Device Status */
439#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
440#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
441#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
442#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
443#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
444#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
445#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900446#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
447#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
448#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
449#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
450#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
451#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300452#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900453#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
454#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
455#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700456#define PCI_EXP_LNKCTL 16 /* Link Control */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900457#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
458#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
459#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
460#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
461#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */
462#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */
Michael Chanc7835a72006-11-15 21:14:42 -0800463#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900464#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
465#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
466#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700467#define PCI_EXP_LNKSTA 18 /* Link Status */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900468#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
Alexander Duyckff846f52010-04-27 01:02:40 +0000469#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
470#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900471#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
Alexander Duyckff846f52010-04-27 01:02:40 +0000472#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900473#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
Shaohua Li7d715a62008-02-25 09:46:41 +0800474#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900475#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
476#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
477#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000478#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700479#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900480#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
481#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
482#define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */
483#define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */
484#define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */
485#define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
486#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
487#define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */
488#define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */
489#define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */
490#define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */
491#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700492#define PCI_EXP_SLTCTL 24 /* Slot Control */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900493#define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */
494#define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
495#define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */
496#define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */
497#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
498#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
499#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
500#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
501#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
502#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
503#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700504#define PCI_EXP_SLTSTA 26 /* Slot Status */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900505#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
506#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */
507#define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */
508#define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */
509#define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */
510#define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */
511#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */
512#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */
513#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700514#define PCI_EXP_RTCTL 28 /* Root Control */
515#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
516#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
517#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
518#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
519#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
520#define PCI_EXP_RTCAP 30 /* Root Capabilities */
521#define PCI_EXP_RTSTA 32 /* Root Status */
Rafael J. Wysockife31e692010-12-19 15:57:16 +0100522#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
523#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
Yu Zhao58c3a722008-10-14 14:02:53 +0800524#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
525#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
Jesse Barnes51c2e0a2011-01-14 08:53:04 -0800526#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
Jesse Barnes48a92a82011-01-10 12:46:36 -0800527#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
528#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
529#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
Yu Zhao58c3a722008-10-14 14:02:53 +0800530#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
531#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
Jesse Barnesb48d4422010-10-19 13:07:57 -0700532#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
533#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
Jesse Barnes51c2e0a2011-01-14 08:53:04 -0800534#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
Jesse Barnes48a92a82011-01-10 12:46:36 -0800535#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
536#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
537#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000538#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
Yu Zhao89858512009-02-16 02:55:47 +0800539#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
540#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700541
542/* Extended Capabilities (PCI-X 2.0 and Express) */
543#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
544#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
545#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
546
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000547#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
548#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
549#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
550#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
551#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
552#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
553#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
554#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
555#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
556#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
557#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */
558#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
559#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
560#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
561#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
562#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
563#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
564#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
565#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
566#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */
567#define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */
568#define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */
569#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */
570#define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */
571#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */
572#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
573#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
574#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
575
576#define PCI_EXT_CAP_DSN_SIZEOF 12
577#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700578
579/* Advanced Error Reporting */
580#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
581#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
582#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000583#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700584#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
585#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
586#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
587#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
588#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
589#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
590#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
591#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
592#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000593#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
594#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */
595#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */
596#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */
597#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700598#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
599 /* Same bits as above */
600#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
601 /* Same bits as above */
602#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
603#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
604#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
605#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
606#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
607#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000608#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
609#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */
610#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700611#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
612 /* Same bits as above */
613#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
614#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
615#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
616#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
617#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
618#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
619#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
620#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
Zhang, Yanmin6f0312f2006-07-12 09:41:47 +0800621/* Correctable Err Reporting Enable */
622#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
623/* Non-fatal Err Reporting Enable */
624#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
625/* Fatal Err Reporting Enable */
626#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700627#define PCI_ERR_ROOT_STATUS 48
Zhang, Yanmin6f0312f2006-07-12 09:41:47 +0800628#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
629/* Multi ERR_COR Received */
630#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
631/* ERR_FATAL/NONFATAL Recevied */
632#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
633/* Multi ERR_FATAL/NONFATAL Recevied */
634#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
635#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
636#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
637#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
Hidetoshi Setof647a442010-04-15 13:17:33 +0900638#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700639
640/* Virtual Channel */
641#define PCI_VC_PORT_REG1 4
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000642#define PCI_VC_REG1_EVCC 0x7 /* extended vc count */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700643#define PCI_VC_PORT_REG2 8
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000644#define PCI_VC_REG2_32_PHASE 0x2
645#define PCI_VC_REG2_64_PHASE 0x4
646#define PCI_VC_REG2_128_PHASE 0x8
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700647#define PCI_VC_PORT_CTRL 12
648#define PCI_VC_PORT_STATUS 14
649#define PCI_VC_RES_CAP 16
650#define PCI_VC_RES_CTRL 20
651#define PCI_VC_RES_STATUS 26
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000652#define PCI_CAP_VC_BASE_SIZEOF 0x10
653#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700654
655/* Power Budgeting */
656#define PCI_PWR_DSR 4 /* Data Select Register */
657#define PCI_PWR_DATA 8 /* Data Register */
658#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
659#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
660#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
661#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
662#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
663#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
664#define PCI_PWR_CAP 12 /* Capability */
665#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000666#define PCI_EXT_CAP_PWR_SIZEOF 16
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700667
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100668/*
669 * Hypertransport sub capability types
670 *
671 * Unfortunately there are both 3 bit and 5 bit capability types defined
672 * in the HT spec, catering for that is a little messy. You probably don't
673 * want to use these directly, just use pci_find_ht_capability() and it
674 * will do the right thing for you.
675 */
676#define HT_3BIT_CAP_MASK 0xE0
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700677#define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */
678#define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100679
680#define HT_5BIT_CAP_MASK 0xF8
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700681#define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */
682#define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */
683#define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */
684#define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */
685#define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */
686#define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */
Michael Ellermand010b512006-11-22 18:26:20 +1100687#define HT_MSI_FLAGS 0x02 /* Offset to flags */
688#define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */
689#define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */
690#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */
691#define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */
692#define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */
693#define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700694#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
695#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */
696#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
697#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
698#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000699#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */
700#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700701
Yu Zhao58c3a722008-10-14 14:02:53 +0800702/* Alternative Routing-ID Interpretation */
703#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
704#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
705#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
706#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
707#define PCI_ARI_CTRL 0x06 /* ARI Control Register */
708#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
709#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
710#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000711#define PCI_EXT_CAP_ARI_SIZEOF 8
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700712
Yu Zhao302b4212009-05-18 13:51:32 +0800713/* Address Translation Service */
714#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
715#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */
716#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */
717#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
718#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
719#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
720#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000721#define PCI_EXT_CAP_ATS_SIZEOF 8
Yu Zhao302b4212009-05-18 13:51:32 +0800722
Joerg Roedelc320b972011-09-27 15:57:15 +0200723/* Page Request Interface */
Alex Williamson91f57d52011-11-11 10:07:36 -0700724#define PCI_PRI_CTRL 0x04 /* PRI control register */
725#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
726#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
727#define PCI_PRI_STATUS 0x06 /* PRI status register */
728#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
729#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
730#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
731#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
732#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000733#define PCI_EXT_CAP_PRI_SIZEOF 16
Joerg Roedelc320b972011-09-27 15:57:15 +0200734
Joerg Roedel086ac112011-09-27 15:57:16 +0200735/* PASID capability */
Alex Williamson91f57d52011-11-11 10:07:36 -0700736#define PCI_PASID_CAP 0x04 /* PASID feature register */
737#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */
738#define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */
739#define PCI_PASID_CTRL 0x06 /* PASID control register */
740#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
741#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
742#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000743#define PCI_EXT_CAP_PASID_SIZEOF 8
Joerg Roedel086ac112011-09-27 15:57:16 +0200744
Yu Zhaod1b054d2009-03-20 11:25:11 +0800745/* Single Root I/O Virtualization */
746#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
747#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
748#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
749#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
750#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
751#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
752#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
753#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
754#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
755#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
756#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
757#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
758#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
759#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
760#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
761#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
762#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
763#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
764#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
765#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */
766#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */
767#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */
768#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/
769#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */
770#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */
771#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */
772#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
773#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
774#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000775#define PCI_EXT_CAP_SRIOV_SIZEOF 64
Yu Zhaod1b054d2009-03-20 11:25:11 +0800776
Jesse Barnes51c2e0a2011-01-14 08:53:04 -0800777#define PCI_LTR_MAX_SNOOP_LAT 0x4
778#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
779#define PCI_LTR_VALUE_MASK 0x000003ff
780#define PCI_LTR_SCALE_MASK 0x00001c00
781#define PCI_LTR_SCALE_SHIFT 10
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000782#define PCI_EXT_CAP_LTR_SIZEOF 8
Jesse Barnes51c2e0a2011-01-14 08:53:04 -0800783
Allen Kayae21ee62009-10-07 10:27:17 -0700784/* Access Control Service */
785#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
786#define PCI_ACS_SV 0x01 /* Source Validation */
787#define PCI_ACS_TB 0x02 /* Translation Blocking */
788#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
789#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
790#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
791#define PCI_ACS_EC 0x20 /* P2P Egress Control */
792#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000793#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
Allen Kayae21ee62009-10-07 10:27:17 -0700794#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
795#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
796
Alex Williamsona0dee2e2012-06-11 05:27:45 +0000797#define PCI_VSEC_HDR 4 /* extended cap - vendor specific */
798#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */
799
800/* sata capability */
801#define PCI_SATA_REGS 4 /* SATA REGs specifier */
802#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
803#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */
804#define PCI_SATA_SIZEOF_SHORT 8
805#define PCI_SATA_SIZEOF_LONG 16
806
807/* resizable BARs */
808#define PCI_REBAR_CTRL 8 /* control register */
809#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
810#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
811
812/* dynamic power allocation */
813#define PCI_DPA_CAP 4 /* capability register */
814#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
815#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */
816
817/* TPH Requester */
818#define PCI_TPH_CAP 4 /* capability register */
819#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
820#define PCI_TPH_LOC_NONE 0x000 /* no location */
821#define PCI_TPH_LOC_CAP 0x200 /* in capability */
822#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
823#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */
824#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */
825#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */
826
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700827#endif /* LINUX_PCI_REGS_H */