Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 2 | * All Rights Reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the |
| 6 | * "Software"), to deal in the Software without restriction, including |
| 7 | * without limitation the rights to use, copy, modify, merge, publish, |
| 8 | * distribute, sub license, and/or sell copies of the Software, and to |
| 9 | * permit persons to whom the Software is furnished to do so, subject to |
| 10 | * the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the |
| 13 | * next paragraph) shall be included in all copies or substantial portions |
| 14 | * of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #ifndef _I915_REG_H_ |
| 26 | #define _I915_REG_H_ |
| 27 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 28 | /* |
| 29 | * The Bridge device's PCI config space has information about the |
| 30 | * fb aperture size and the amount of pre-reserved memory. |
| 31 | */ |
| 32 | #define INTEL_GMCH_CTRL 0x52 |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 33 | #define INTEL_GMCH_VGA_DISABLE (1 << 1) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 34 | #define INTEL_GMCH_ENABLED 0x4 |
| 35 | #define INTEL_GMCH_MEM_MASK 0x1 |
| 36 | #define INTEL_GMCH_MEM_64M 0x1 |
| 37 | #define INTEL_GMCH_MEM_128M 0 |
| 38 | |
Eric Anholt | 241fa85 | 2009-01-02 18:05:51 -0800 | [diff] [blame] | 39 | #define INTEL_GMCH_GMS_MASK (0xf << 4) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 40 | #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) |
| 41 | #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) |
| 42 | #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) |
| 43 | #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) |
| 44 | #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) |
| 45 | #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) |
| 46 | |
| 47 | #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) |
| 48 | #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) |
Eric Anholt | 241fa85 | 2009-01-02 18:05:51 -0800 | [diff] [blame] | 49 | #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) |
| 50 | #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) |
| 51 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) |
| 52 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) |
| 53 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) |
| 54 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 55 | |
Zhenyu Wang | 14bc490 | 2009-11-11 01:25:25 +0800 | [diff] [blame] | 56 | #define SNB_GMCH_CTRL 0x50 |
| 57 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 |
| 58 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) |
| 59 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) |
| 60 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) |
| 61 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) |
| 62 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) |
| 63 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) |
| 64 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) |
| 65 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) |
| 66 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) |
| 67 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) |
| 68 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) |
| 69 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) |
| 70 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) |
| 71 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) |
| 72 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) |
| 73 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) |
| 74 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 75 | /* PCI config space */ |
| 76 | |
| 77 | #define HPLLCC 0xc0 /* 855 only */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 78 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 79 | #define GC_CLOCK_133_200 (0 << 0) |
| 80 | #define GC_CLOCK_100_200 (1 << 0) |
| 81 | #define GC_CLOCK_100_133 (2 << 0) |
| 82 | #define GC_CLOCK_166_250 (3 << 0) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 83 | #define GCFGC2 0xda |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 84 | #define GCFGC 0xf0 /* 915+ only */ |
| 85 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
| 86 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
| 87 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) |
| 88 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 89 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
| 90 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
| 91 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) |
| 92 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) |
| 93 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) |
| 94 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) |
| 95 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) |
| 96 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) |
| 97 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) |
| 98 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) |
| 99 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) |
| 100 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
| 101 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
| 102 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) |
| 103 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) |
| 104 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) |
| 105 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) |
| 106 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) |
| 107 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 108 | #define LBB 0xf4 |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 109 | #define GDRST 0xc0 |
| 110 | #define GDRST_FULL (0<<2) |
| 111 | #define GDRST_RENDER (1<<2) |
| 112 | #define GDRST_MEDIA (3<<2) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 113 | |
| 114 | /* VGA stuff */ |
| 115 | |
| 116 | #define VGA_ST01_MDA 0x3ba |
| 117 | #define VGA_ST01_CGA 0x3da |
| 118 | |
| 119 | #define VGA_MSR_WRITE 0x3c2 |
| 120 | #define VGA_MSR_READ 0x3cc |
| 121 | #define VGA_MSR_MEM_EN (1<<1) |
| 122 | #define VGA_MSR_CGA_MODE (1<<0) |
| 123 | |
| 124 | #define VGA_SR_INDEX 0x3c4 |
| 125 | #define VGA_SR_DATA 0x3c5 |
| 126 | |
| 127 | #define VGA_AR_INDEX 0x3c0 |
| 128 | #define VGA_AR_VID_EN (1<<5) |
| 129 | #define VGA_AR_DATA_WRITE 0x3c0 |
| 130 | #define VGA_AR_DATA_READ 0x3c1 |
| 131 | |
| 132 | #define VGA_GR_INDEX 0x3ce |
| 133 | #define VGA_GR_DATA 0x3cf |
| 134 | /* GR05 */ |
| 135 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 |
| 136 | #define VGA_GR_MEM_READ_MODE_PLANE 1 |
| 137 | /* GR06 */ |
| 138 | #define VGA_GR_MEM_MODE_MASK 0xc |
| 139 | #define VGA_GR_MEM_MODE_SHIFT 2 |
| 140 | #define VGA_GR_MEM_A0000_AFFFF 0 |
| 141 | #define VGA_GR_MEM_A0000_BFFFF 1 |
| 142 | #define VGA_GR_MEM_B0000_B7FFF 2 |
| 143 | #define VGA_GR_MEM_B0000_BFFFF 3 |
| 144 | |
| 145 | #define VGA_DACMASK 0x3c6 |
| 146 | #define VGA_DACRX 0x3c7 |
| 147 | #define VGA_DACWX 0x3c8 |
| 148 | #define VGA_DACDATA 0x3c9 |
| 149 | |
| 150 | #define VGA_CR_INDEX_MDA 0x3b4 |
| 151 | #define VGA_CR_DATA_MDA 0x3b5 |
| 152 | #define VGA_CR_INDEX_CGA 0x3d4 |
| 153 | #define VGA_CR_DATA_CGA 0x3d5 |
| 154 | |
| 155 | /* |
| 156 | * Memory interface instructions used by the kernel |
| 157 | */ |
| 158 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) |
| 159 | |
| 160 | #define MI_NOOP MI_INSTR(0, 0) |
| 161 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) |
| 162 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 163 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 164 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
| 165 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
| 166 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
| 167 | #define MI_FLUSH MI_INSTR(0x04, 0) |
| 168 | #define MI_READ_FLUSH (1 << 0) |
| 169 | #define MI_EXE_FLUSH (1 << 1) |
| 170 | #define MI_NO_WRITE_FLUSH (1 << 2) |
| 171 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
| 172 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
| 173 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
| 174 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 175 | #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) |
| 176 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
| 177 | #define MI_OVERLAY_ON (0x1<<21) |
| 178 | #define MI_OVERLAY_OFF (0x2<<21) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 179 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 180 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
| 181 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 182 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
| 183 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
| 184 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
| 185 | #define MI_STORE_DWORD_INDEX_SHIFT 2 |
| 186 | #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) |
| 187 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
| 188 | #define MI_BATCH_NON_SECURE (1) |
| 189 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
| 190 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
| 191 | |
| 192 | /* |
| 193 | * 3D instructions used by the kernel |
| 194 | */ |
| 195 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) |
| 196 | |
| 197 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) |
| 198 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
| 199 | #define SC_UPDATE_SCISSOR (0x1<<1) |
| 200 | #define SC_ENABLE_MASK (0x1<<0) |
| 201 | #define SC_ENABLE (0x1<<0) |
| 202 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
| 203 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
| 204 | #define SCI_YMIN_MASK (0xffff<<16) |
| 205 | #define SCI_XMIN_MASK (0xffff<<0) |
| 206 | #define SCI_YMAX_MASK (0xffff<<16) |
| 207 | #define SCI_XMAX_MASK (0xffff<<0) |
| 208 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
| 209 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) |
| 210 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) |
| 211 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
| 212 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) |
| 213 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) |
| 214 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) |
| 215 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) |
| 216 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
| 217 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
| 218 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
| 219 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) |
| 220 | #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) |
| 221 | #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) |
| 222 | #define BLT_DEPTH_8 (0<<24) |
| 223 | #define BLT_DEPTH_16_565 (1<<24) |
| 224 | #define BLT_DEPTH_16_1555 (2<<24) |
| 225 | #define BLT_DEPTH_32 (3<<24) |
| 226 | #define BLT_ROP_GXCOPY (0xcc<<16) |
| 227 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
| 228 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ |
| 229 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) |
| 230 | #define ASYNC_FLIP (1<<22) |
| 231 | #define DISPLAY_PLANE_A (0<<20) |
| 232 | #define DISPLAY_PLANE_B (1<<20) |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 233 | #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) |
| 234 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
| 235 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
| 236 | #define PIPE_CONTROL_WC_FLUSH (1<<12) |
| 237 | #define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ |
| 238 | #define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ |
| 239 | #define PIPE_CONTROL_ISP_DIS (1<<9) |
| 240 | #define PIPE_CONTROL_NOTIFY (1<<8) |
| 241 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
| 242 | #define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 243 | |
| 244 | /* |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 245 | * Fence registers |
| 246 | */ |
| 247 | #define FENCE_REG_830_0 0x2000 |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 248 | #define FENCE_REG_945_8 0x3000 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 249 | #define I830_FENCE_START_MASK 0x07f80000 |
| 250 | #define I830_FENCE_TILING_Y_SHIFT 12 |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 251 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 252 | #define I830_FENCE_PITCH_SHIFT 4 |
| 253 | #define I830_FENCE_REG_VALID (1<<0) |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 254 | #define I915_FENCE_MAX_PITCH_VAL 4 |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 255 | #define I830_FENCE_MAX_PITCH_VAL 6 |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 256 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 257 | |
| 258 | #define I915_FENCE_START_MASK 0x0ff00000 |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 259 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 260 | |
| 261 | #define FENCE_REG_965_0 0x03000 |
| 262 | #define I965_FENCE_PITCH_SHIFT 2 |
| 263 | #define I965_FENCE_TILING_Y_SHIFT 1 |
| 264 | #define I965_FENCE_REG_VALID (1<<0) |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 265 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 266 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 267 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
| 268 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 |
| 269 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 270 | /* |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 271 | * Instruction and interrupt control regs |
| 272 | */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 273 | #define PGTBL_ER 0x02024 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 274 | #define PRB0_TAIL 0x02030 |
| 275 | #define PRB0_HEAD 0x02034 |
| 276 | #define PRB0_START 0x02038 |
| 277 | #define PRB0_CTL 0x0203c |
| 278 | #define TAIL_ADDR 0x001FFFF8 |
| 279 | #define HEAD_WRAP_COUNT 0xFFE00000 |
| 280 | #define HEAD_WRAP_ONE 0x00200000 |
| 281 | #define HEAD_ADDR 0x001FFFFC |
| 282 | #define RING_NR_PAGES 0x001FF000 |
| 283 | #define RING_REPORT_MASK 0x00000006 |
| 284 | #define RING_REPORT_64K 0x00000002 |
| 285 | #define RING_REPORT_128K 0x00000004 |
| 286 | #define RING_NO_REPORT 0x00000000 |
| 287 | #define RING_VALID_MASK 0x00000001 |
| 288 | #define RING_VALID 0x00000001 |
| 289 | #define RING_INVALID 0x00000000 |
| 290 | #define PRB1_TAIL 0x02040 /* 915+ only */ |
| 291 | #define PRB1_HEAD 0x02044 /* 915+ only */ |
| 292 | #define PRB1_START 0x02048 /* 915+ only */ |
| 293 | #define PRB1_CTL 0x0204c /* 915+ only */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 294 | #define IPEIR_I965 0x02064 |
| 295 | #define IPEHR_I965 0x02068 |
| 296 | #define INSTDONE_I965 0x0206c |
| 297 | #define INSTPS 0x02070 /* 965+ only */ |
| 298 | #define INSTDONE1 0x0207c /* 965+ only */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 299 | #define ACTHD_I965 0x02074 |
| 300 | #define HWS_PGA 0x02080 |
Eric Anholt | f6e450a | 2009-11-02 12:08:22 -0800 | [diff] [blame] | 301 | #define HWS_PGA_GEN6 0x04080 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 302 | #define HWS_ADDRESS_MASK 0xfffff000 |
| 303 | #define HWS_START_ADDRESS_SHIFT 4 |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 304 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
| 305 | #define PWRCTX_EN (1<<0) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 306 | #define IPEIR 0x02088 |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 307 | #define IPEHR 0x0208c |
| 308 | #define INSTDONE 0x02090 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 309 | #define NOPID 0x02094 |
| 310 | #define HWSTAM 0x02098 |
Eric Anholt | 71cf39b | 2010-03-08 23:41:55 -0800 | [diff] [blame] | 311 | |
| 312 | #define MI_MODE 0x0209c |
| 313 | # define VS_TIMER_DISPATCH (1 << 6) |
| 314 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 315 | #define SCPD0 0x0209c /* 915+ only */ |
| 316 | #define IER 0x020a0 |
| 317 | #define IIR 0x020a4 |
| 318 | #define IMR 0x020a8 |
| 319 | #define ISR 0x020ac |
| 320 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
| 321 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) |
| 322 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 323 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 324 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
| 325 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) |
| 326 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
| 327 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
| 328 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
| 329 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
| 330 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) |
| 331 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) |
| 332 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) |
| 333 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) |
| 334 | #define I915_DEBUG_INTERRUPT (1<<2) |
| 335 | #define I915_USER_INTERRUPT (1<<1) |
| 336 | #define I915_ASLE_INTERRUPT (1<<0) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 337 | #define I915_BSD_USER_INTERRUPT (1<<25) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 338 | #define EIR 0x020b0 |
| 339 | #define EMR 0x020b4 |
| 340 | #define ESR 0x020b8 |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 341 | #define GM45_ERROR_PAGE_TABLE (1<<5) |
| 342 | #define GM45_ERROR_MEM_PRIV (1<<4) |
| 343 | #define I915_ERROR_PAGE_TABLE (1<<4) |
| 344 | #define GM45_ERROR_CP_PRIV (1<<3) |
| 345 | #define I915_ERROR_MEMORY_REFRESH (1<<1) |
| 346 | #define I915_ERROR_INSTRUCTION (1<<0) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 347 | #define INSTPM 0x020c0 |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 348 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 349 | #define ACTHD 0x020c8 |
| 350 | #define FW_BLC 0x020d8 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 351 | #define FW_BLC2 0x020dc |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 352 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
Li Peng | ee980b8 | 2010-01-27 19:01:11 +0800 | [diff] [blame] | 353 | #define FW_BLC_SELF_EN_MASK (1<<31) |
| 354 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ |
| 355 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 356 | #define MM_BURST_LENGTH 0x00700000 |
| 357 | #define MM_FIFO_WATERMARK 0x0001F000 |
| 358 | #define LM_BURST_LENGTH 0x00000700 |
| 359 | #define LM_FIFO_WATERMARK 0x0000001F |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 360 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
| 361 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
| 362 | #define CM0_MASK_SHIFT 16 |
| 363 | #define CM0_IZ_OPT_DISABLE (1<<6) |
| 364 | #define CM0_ZR_OPT_DISABLE (1<<5) |
| 365 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
| 366 | #define CM0_COLOR_EVICT_DISABLE (1<<3) |
| 367 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) |
| 368 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 369 | #define BB_ADDR 0x02140 /* 8 bytes */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 370 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ |
| 371 | |
Zhenyu Wang | a1786bd | 2010-05-27 10:26:43 +0800 | [diff] [blame^] | 372 | /* GEN6 interrupt control */ |
| 373 | #define GEN6_RENDER_HWSTAM 0x2098 |
| 374 | #define GEN6_RENDER_IMR 0x20a8 |
| 375 | #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
| 376 | #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) |
| 377 | #define GEN6_RENDER TIMEOUT_COUNTER_EXPIRED (1 << 6) |
| 378 | #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) |
| 379 | #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) |
| 380 | #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) |
| 381 | #define GEN6_RENDER_SYNC_STATUS (1 << 2) |
| 382 | #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) |
| 383 | #define GEN6_RENDER_USER_INTERRUPT (1 << 0) |
| 384 | |
| 385 | #define GEN6_BLITTER_HWSTAM 0x22098 |
| 386 | #define GEN6_BLITTER_IMR 0x220a8 |
| 387 | #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) |
| 388 | #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) |
| 389 | #define GEN6_BLITTER_SYNC_STATUS (1 << 24) |
| 390 | #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 391 | /* |
| 392 | * BSD (bit stream decoder instruction and interrupt control register defines |
| 393 | * (G4X and Ironlake only) |
| 394 | */ |
| 395 | |
| 396 | #define BSD_RING_TAIL 0x04030 |
| 397 | #define BSD_RING_HEAD 0x04034 |
| 398 | #define BSD_RING_START 0x04038 |
| 399 | #define BSD_RING_CTL 0x0403c |
| 400 | #define BSD_RING_ACTHD 0x04074 |
| 401 | #define BSD_HWS_PGA 0x04080 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 402 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 403 | /* |
| 404 | * Framebuffer compression (915+ only) |
| 405 | */ |
| 406 | |
| 407 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ |
| 408 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ |
| 409 | #define FBC_CONTROL 0x03208 |
| 410 | #define FBC_CTL_EN (1<<31) |
| 411 | #define FBC_CTL_PERIODIC (1<<30) |
| 412 | #define FBC_CTL_INTERVAL_SHIFT (16) |
| 413 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) |
Priit Laes | 4967790 | 2010-03-02 11:37:00 +0200 | [diff] [blame] | 414 | #define FBC_CTL_C3_IDLE (1<<13) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 415 | #define FBC_CTL_STRIDE_SHIFT (5) |
| 416 | #define FBC_CTL_FENCENO (1<<0) |
| 417 | #define FBC_COMMAND 0x0320c |
| 418 | #define FBC_CMD_COMPRESS (1<<0) |
| 419 | #define FBC_STATUS 0x03210 |
| 420 | #define FBC_STAT_COMPRESSING (1<<31) |
| 421 | #define FBC_STAT_COMPRESSED (1<<30) |
| 422 | #define FBC_STAT_MODIFIED (1<<29) |
| 423 | #define FBC_STAT_CURRENT_LINE (1<<0) |
| 424 | #define FBC_CONTROL2 0x03214 |
| 425 | #define FBC_CTL_FENCE_DBL (0<<4) |
| 426 | #define FBC_CTL_IDLE_IMM (0<<2) |
| 427 | #define FBC_CTL_IDLE_FULL (1<<2) |
| 428 | #define FBC_CTL_IDLE_LINE (2<<2) |
| 429 | #define FBC_CTL_IDLE_DEBUG (3<<2) |
| 430 | #define FBC_CTL_CPU_FENCE (1<<1) |
| 431 | #define FBC_CTL_PLANEA (0<<0) |
| 432 | #define FBC_CTL_PLANEB (1<<0) |
| 433 | #define FBC_FENCE_OFF 0x0321b |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 434 | #define FBC_TAG 0x03300 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 435 | |
| 436 | #define FBC_LL_SIZE (1536) |
| 437 | |
Jesse Barnes | 74dff28 | 2009-09-14 15:39:40 -0700 | [diff] [blame] | 438 | /* Framebuffer compression for GM45+ */ |
| 439 | #define DPFC_CB_BASE 0x3200 |
| 440 | #define DPFC_CONTROL 0x3208 |
| 441 | #define DPFC_CTL_EN (1<<31) |
| 442 | #define DPFC_CTL_PLANEA (0<<30) |
| 443 | #define DPFC_CTL_PLANEB (1<<30) |
| 444 | #define DPFC_CTL_FENCE_EN (1<<29) |
| 445 | #define DPFC_SR_EN (1<<10) |
| 446 | #define DPFC_CTL_LIMIT_1X (0<<6) |
| 447 | #define DPFC_CTL_LIMIT_2X (1<<6) |
| 448 | #define DPFC_CTL_LIMIT_4X (2<<6) |
| 449 | #define DPFC_RECOMP_CTL 0x320c |
| 450 | #define DPFC_RECOMP_STALL_EN (1<<27) |
| 451 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) |
| 452 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) |
| 453 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) |
| 454 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) |
| 455 | #define DPFC_STATUS 0x3210 |
| 456 | #define DPFC_INVAL_SEG_SHIFT (16) |
| 457 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) |
| 458 | #define DPFC_COMP_SEG_SHIFT (0) |
| 459 | #define DPFC_COMP_SEG_MASK (0x000003ff) |
| 460 | #define DPFC_STATUS2 0x3214 |
| 461 | #define DPFC_FENCE_YOFF 0x3218 |
| 462 | #define DPFC_CHICKEN 0x3224 |
| 463 | #define DPFC_HT_MODIFY (1<<31) |
| 464 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 465 | /* |
| 466 | * GPIO regs |
| 467 | */ |
| 468 | #define GPIOA 0x5010 |
| 469 | #define GPIOB 0x5014 |
| 470 | #define GPIOC 0x5018 |
| 471 | #define GPIOD 0x501c |
| 472 | #define GPIOE 0x5020 |
| 473 | #define GPIOF 0x5024 |
| 474 | #define GPIOG 0x5028 |
| 475 | #define GPIOH 0x502c |
| 476 | # define GPIO_CLOCK_DIR_MASK (1 << 0) |
| 477 | # define GPIO_CLOCK_DIR_IN (0 << 1) |
| 478 | # define GPIO_CLOCK_DIR_OUT (1 << 1) |
| 479 | # define GPIO_CLOCK_VAL_MASK (1 << 2) |
| 480 | # define GPIO_CLOCK_VAL_OUT (1 << 3) |
| 481 | # define GPIO_CLOCK_VAL_IN (1 << 4) |
| 482 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) |
| 483 | # define GPIO_DATA_DIR_MASK (1 << 8) |
| 484 | # define GPIO_DATA_DIR_IN (0 << 9) |
| 485 | # define GPIO_DATA_DIR_OUT (1 << 9) |
| 486 | # define GPIO_DATA_VAL_MASK (1 << 10) |
| 487 | # define GPIO_DATA_VAL_OUT (1 << 11) |
| 488 | # define GPIO_DATA_VAL_IN (1 << 12) |
| 489 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) |
| 490 | |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 491 | #define GMBUS0 0x5100 |
| 492 | #define GMBUS1 0x5104 |
| 493 | #define GMBUS2 0x5108 |
| 494 | #define GMBUS3 0x510c |
| 495 | #define GMBUS4 0x5110 |
| 496 | #define GMBUS5 0x5120 |
| 497 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 498 | /* |
| 499 | * Clock control & power management |
| 500 | */ |
| 501 | |
| 502 | #define VGA0 0x6000 |
| 503 | #define VGA1 0x6004 |
| 504 | #define VGA_PD 0x6010 |
| 505 | #define VGA0_PD_P2_DIV_4 (1 << 7) |
| 506 | #define VGA0_PD_P1_DIV_2 (1 << 5) |
| 507 | #define VGA0_PD_P1_SHIFT 0 |
| 508 | #define VGA0_PD_P1_MASK (0x1f << 0) |
| 509 | #define VGA1_PD_P2_DIV_4 (1 << 15) |
| 510 | #define VGA1_PD_P1_DIV_2 (1 << 13) |
| 511 | #define VGA1_PD_P1_SHIFT 8 |
| 512 | #define VGA1_PD_P1_MASK (0x1f << 8) |
| 513 | #define DPLL_A 0x06014 |
| 514 | #define DPLL_B 0x06018 |
| 515 | #define DPLL_VCO_ENABLE (1 << 31) |
| 516 | #define DPLL_DVO_HIGH_SPEED (1 << 30) |
| 517 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
| 518 | #define DPLL_VGA_MODE_DIS (1 << 28) |
| 519 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ |
| 520 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ |
| 521 | #define DPLL_MODE_MASK (3 << 26) |
| 522 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ |
| 523 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ |
| 524 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ |
| 525 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 526 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ |
| 527 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 528 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 529 | |
| 530 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) |
| 531 | #define I915_CRC_ERROR_ENABLE (1UL<<29) |
| 532 | #define I915_CRC_DONE_ENABLE (1UL<<28) |
| 533 | #define I915_GMBUS_EVENT_ENABLE (1UL<<27) |
| 534 | #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
| 535 | #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
| 536 | #define I915_DPST_EVENT_ENABLE (1UL<<23) |
| 537 | #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
| 538 | #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
| 539 | #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
| 540 | #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
| 541 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
| 542 | #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) |
| 543 | #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
| 544 | #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
| 545 | #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) |
| 546 | #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) |
| 547 | #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
| 548 | #define I915_DPST_EVENT_STATUS (1UL<<7) |
| 549 | #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
| 550 | #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
| 551 | #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
| 552 | #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
| 553 | #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) |
| 554 | #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) |
| 555 | |
| 556 | #define SRX_INDEX 0x3c4 |
| 557 | #define SRX_DATA 0x3c5 |
| 558 | #define SR01 1 |
| 559 | #define SR01_SCREEN_OFF (1<<5) |
| 560 | |
| 561 | #define PPCR 0x61204 |
| 562 | #define PPCR_ON (1<<0) |
| 563 | |
| 564 | #define DVOB 0x61140 |
| 565 | #define DVOB_ON (1<<31) |
| 566 | #define DVOC 0x61160 |
| 567 | #define DVOC_ON (1<<31) |
| 568 | #define LVDS 0x61180 |
| 569 | #define LVDS_ON (1<<31) |
| 570 | |
| 571 | #define ADPA 0x61100 |
| 572 | #define ADPA_DPMS_MASK (~(3<<10)) |
| 573 | #define ADPA_DPMS_ON (0<<10) |
| 574 | #define ADPA_DPMS_SUSPEND (1<<10) |
| 575 | #define ADPA_DPMS_STANDBY (2<<10) |
| 576 | #define ADPA_DPMS_OFF (3<<10) |
| 577 | |
| 578 | #define RING_TAIL 0x00 |
| 579 | #define TAIL_ADDR 0x001FFFF8 |
| 580 | #define RING_HEAD 0x04 |
| 581 | #define HEAD_WRAP_COUNT 0xFFE00000 |
| 582 | #define HEAD_WRAP_ONE 0x00200000 |
| 583 | #define HEAD_ADDR 0x001FFFFC |
| 584 | #define RING_START 0x08 |
| 585 | #define START_ADDR 0xFFFFF000 |
| 586 | #define RING_LEN 0x0C |
| 587 | #define RING_NR_PAGES 0x001FF000 |
| 588 | #define RING_REPORT_MASK 0x00000006 |
| 589 | #define RING_REPORT_64K 0x00000002 |
| 590 | #define RING_REPORT_128K 0x00000004 |
| 591 | #define RING_NO_REPORT 0x00000000 |
| 592 | #define RING_VALID_MASK 0x00000001 |
| 593 | #define RING_VALID 0x00000001 |
| 594 | #define RING_INVALID 0x00000000 |
| 595 | |
| 596 | /* Scratch pad debug 0 reg: |
| 597 | */ |
| 598 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
| 599 | /* |
| 600 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within |
| 601 | * this field (only one bit may be set). |
| 602 | */ |
| 603 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 |
| 604 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 605 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 606 | /* i830, required in DVO non-gang */ |
| 607 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) |
| 608 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ |
| 609 | #define PLL_REF_INPUT_DREFCLK (0 << 13) |
| 610 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ |
| 611 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ |
| 612 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) |
| 613 | #define PLL_REF_INPUT_MASK (3 << 13) |
| 614 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 615 | /* Ironlake */ |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 616 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
| 617 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) |
| 618 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) |
| 619 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 |
| 620 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff |
| 621 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 622 | /* |
| 623 | * Parallel to Serial Load Pulse phase selection. |
| 624 | * Selects the phase for the 10X DPLL clock for the PCIe |
| 625 | * digital display port. The range is 4 to 13; 10 or more |
| 626 | * is just a flip delay. The default is 6 |
| 627 | */ |
| 628 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) |
| 629 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) |
| 630 | /* |
| 631 | * SDVO multiplier for 945G/GM. Not used on 965. |
| 632 | */ |
| 633 | #define SDVO_MULTIPLIER_MASK 0x000000ff |
| 634 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 |
| 635 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 |
| 636 | #define DPLL_A_MD 0x0601c /* 965+ only */ |
| 637 | /* |
| 638 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. |
| 639 | * |
| 640 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. |
| 641 | */ |
| 642 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 |
| 643 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 |
| 644 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ |
| 645 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 |
| 646 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 |
| 647 | /* |
| 648 | * SDVO/UDI pixel multiplier. |
| 649 | * |
| 650 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus |
| 651 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate |
| 652 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing |
| 653 | * dummy bytes in the datastream at an increased clock rate, with both sides of |
| 654 | * the link knowing how many bytes are fill. |
| 655 | * |
| 656 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock |
| 657 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be |
| 658 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and |
| 659 | * through an SDVO command. |
| 660 | * |
| 661 | * This register field has values of multiplication factor minus 1, with |
| 662 | * a maximum multiplier of 5 for SDVO. |
| 663 | */ |
| 664 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 |
| 665 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 |
| 666 | /* |
| 667 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. |
| 668 | * This best be set to the default value (3) or the CRT won't work. No, |
| 669 | * I don't entirely understand what this does... |
| 670 | */ |
| 671 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f |
| 672 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 |
| 673 | #define DPLL_B_MD 0x06020 /* 965+ only */ |
| 674 | #define FPA0 0x06040 |
| 675 | #define FPA1 0x06044 |
| 676 | #define FPB0 0x06048 |
| 677 | #define FPB1 0x0604c |
| 678 | #define FP_N_DIV_MASK 0x003f0000 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 679 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 680 | #define FP_N_DIV_SHIFT 16 |
| 681 | #define FP_M1_DIV_MASK 0x00003f00 |
| 682 | #define FP_M1_DIV_SHIFT 8 |
| 683 | #define FP_M2_DIV_MASK 0x0000003f |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 684 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 685 | #define FP_M2_DIV_SHIFT 0 |
| 686 | #define DPLL_TEST 0x606c |
| 687 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) |
| 688 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) |
| 689 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) |
| 690 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) |
| 691 | #define DPLLB_TEST_N_BYPASS (1 << 19) |
| 692 | #define DPLLB_TEST_M_BYPASS (1 << 18) |
| 693 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) |
| 694 | #define DPLLA_TEST_N_BYPASS (1 << 3) |
| 695 | #define DPLLA_TEST_M_BYPASS (1 << 2) |
| 696 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) |
| 697 | #define D_STATE 0x6104 |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 698 | #define DSTATE_PLL_D3_OFF (1<<3) |
| 699 | #define DSTATE_GFX_CLOCK_GATING (1<<1) |
| 700 | #define DSTATE_DOT_CLOCK_GATING (1<<0) |
| 701 | #define DSPCLK_GATE_D 0x6200 |
| 702 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
| 703 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ |
| 704 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ |
| 705 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ |
| 706 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ |
| 707 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ |
| 708 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ |
| 709 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ |
| 710 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ |
| 711 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ |
| 712 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ |
| 713 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ |
| 714 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ |
| 715 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ |
| 716 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ |
| 717 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ |
| 718 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ |
| 719 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ |
| 720 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ |
| 721 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
| 722 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) |
| 723 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
| 724 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) |
| 725 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ |
| 726 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ |
| 727 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ |
| 728 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) |
| 729 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) |
| 730 | /** |
| 731 | * This bit must be set on the 830 to prevent hangs when turning off the |
| 732 | * overlay scaler. |
| 733 | */ |
| 734 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) |
| 735 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) |
| 736 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) |
| 737 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ |
| 738 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ |
| 739 | |
| 740 | #define RENCLK_GATE_D1 0x6204 |
| 741 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ |
| 742 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ |
| 743 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) |
| 744 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) |
| 745 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) |
| 746 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) |
| 747 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) |
| 748 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) |
| 749 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) |
| 750 | /** This bit must be unset on 855,865 */ |
| 751 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
| 752 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) |
| 753 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) |
| 754 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) |
| 755 | /** This bit must be set on 855,865. */ |
| 756 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
| 757 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) |
| 758 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) |
| 759 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) |
| 760 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) |
| 761 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) |
| 762 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) |
| 763 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) |
| 764 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) |
| 765 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) |
| 766 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) |
| 767 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) |
| 768 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) |
| 769 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) |
| 770 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) |
| 771 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) |
| 772 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) |
| 773 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) |
| 774 | |
| 775 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) |
| 776 | /** This bit must always be set on 965G/965GM */ |
| 777 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
| 778 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) |
| 779 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) |
| 780 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) |
| 781 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) |
| 782 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) |
| 783 | /** This bit must always be set on 965G */ |
| 784 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
| 785 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) |
| 786 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) |
| 787 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) |
| 788 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) |
| 789 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) |
| 790 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) |
| 791 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) |
| 792 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) |
| 793 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) |
| 794 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) |
| 795 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) |
| 796 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) |
| 797 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) |
| 798 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) |
| 799 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) |
| 800 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) |
| 801 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) |
| 802 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) |
| 803 | |
| 804 | #define RENCLK_GATE_D2 0x6208 |
| 805 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) |
| 806 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) |
| 807 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) |
| 808 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
| 809 | #define DEUC 0x6214 /* CRL only */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 810 | |
| 811 | /* |
| 812 | * Palette regs |
| 813 | */ |
| 814 | |
| 815 | #define PALETTE_A 0x0a000 |
| 816 | #define PALETTE_B 0x0a800 |
| 817 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 818 | /* MCH MMIO space */ |
| 819 | |
| 820 | /* |
| 821 | * MCHBAR mirror. |
| 822 | * |
| 823 | * This mirrors the MCHBAR MMIO space whose location is determined by |
| 824 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in |
| 825 | * every way. It is not accessible from the CP register read instructions. |
| 826 | * |
| 827 | */ |
| 828 | #define MCHBAR_MIRROR_BASE 0x10000 |
| 829 | |
| 830 | /** 915-945 and GM965 MCH register controlling DRAM channel access */ |
| 831 | #define DCC 0x10200 |
| 832 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) |
| 833 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) |
| 834 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) |
| 835 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) |
| 836 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) |
Eric Anholt | a7f014f | 2008-11-25 14:02:05 -0800 | [diff] [blame] | 837 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 838 | |
Li Peng | 9553426 | 2010-05-18 18:58:44 +0800 | [diff] [blame] | 839 | /** Pineview MCH register contains DDR3 setting */ |
| 840 | #define CSHRDDR3CTL 0x101a8 |
| 841 | #define CSHRDDR3CTL_DDR3 (1 << 2) |
| 842 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 843 | /** 965 MCH register controlling DRAM channel configuration */ |
| 844 | #define C0DRB3 0x10206 |
| 845 | #define C1DRB3 0x10606 |
| 846 | |
Keith Packard | b11248d | 2009-06-11 22:28:56 -0700 | [diff] [blame] | 847 | /* Clocking configuration register */ |
| 848 | #define CLKCFG 0x10c00 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 849 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
Keith Packard | b11248d | 2009-06-11 22:28:56 -0700 | [diff] [blame] | 850 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
| 851 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ |
| 852 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ |
| 853 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ |
| 854 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 855 | /* Note, below two are guess */ |
Keith Packard | b11248d | 2009-06-11 22:28:56 -0700 | [diff] [blame] | 856 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 857 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ |
Keith Packard | b11248d | 2009-06-11 22:28:56 -0700 | [diff] [blame] | 858 | #define CLKCFG_FSB_MASK (7 << 0) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 859 | #define CLKCFG_MEM_533 (1 << 4) |
| 860 | #define CLKCFG_MEM_667 (2 << 4) |
| 861 | #define CLKCFG_MEM_800 (3 << 4) |
| 862 | #define CLKCFG_MEM_MASK (7 << 4) |
| 863 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 864 | #define TR1 0x11006 |
| 865 | #define TSFS 0x11020 |
| 866 | #define TSFS_SLOPE_MASK 0x0000ff00 |
| 867 | #define TSFS_SLOPE_SHIFT 8 |
| 868 | #define TSFS_INTR_MASK 0x000000ff |
| 869 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 870 | #define CRSTANDVID 0x11100 |
| 871 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ |
| 872 | #define PXVFREQ_PX_MASK 0x7f000000 |
| 873 | #define PXVFREQ_PX_SHIFT 24 |
| 874 | #define VIDFREQ_BASE 0x11110 |
| 875 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ |
| 876 | #define VIDFREQ2 0x11114 |
| 877 | #define VIDFREQ3 0x11118 |
| 878 | #define VIDFREQ4 0x1111c |
| 879 | #define VIDFREQ_P0_MASK 0x1f000000 |
| 880 | #define VIDFREQ_P0_SHIFT 24 |
| 881 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 |
| 882 | #define VIDFREQ_P0_CSCLK_SHIFT 20 |
| 883 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 |
| 884 | #define VIDFREQ_P0_CRCLK_SHIFT 16 |
| 885 | #define VIDFREQ_P1_MASK 0x00001f00 |
| 886 | #define VIDFREQ_P1_SHIFT 8 |
| 887 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 |
| 888 | #define VIDFREQ_P1_CSCLK_SHIFT 4 |
| 889 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f |
| 890 | #define INTTOEXT_BASE_ILK 0x11300 |
| 891 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ |
| 892 | #define INTTOEXT_MAP3_SHIFT 24 |
| 893 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) |
| 894 | #define INTTOEXT_MAP2_SHIFT 16 |
| 895 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) |
| 896 | #define INTTOEXT_MAP1_SHIFT 8 |
| 897 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) |
| 898 | #define INTTOEXT_MAP0_SHIFT 0 |
| 899 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) |
| 900 | #define MEMSWCTL 0x11170 /* Ironlake only */ |
| 901 | #define MEMCTL_CMD_MASK 0xe000 |
| 902 | #define MEMCTL_CMD_SHIFT 13 |
| 903 | #define MEMCTL_CMD_RCLK_OFF 0 |
| 904 | #define MEMCTL_CMD_RCLK_ON 1 |
| 905 | #define MEMCTL_CMD_CHFREQ 2 |
| 906 | #define MEMCTL_CMD_CHVID 3 |
| 907 | #define MEMCTL_CMD_VMMOFF 4 |
| 908 | #define MEMCTL_CMD_VMMON 5 |
| 909 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears |
| 910 | when command complete */ |
| 911 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ |
| 912 | #define MEMCTL_FREQ_SHIFT 8 |
| 913 | #define MEMCTL_SFCAVM (1<<7) |
| 914 | #define MEMCTL_TGT_VID_MASK 0x007f |
| 915 | #define MEMIHYST 0x1117c |
| 916 | #define MEMINTREN 0x11180 /* 16 bits */ |
| 917 | #define MEMINT_RSEXIT_EN (1<<8) |
| 918 | #define MEMINT_CX_SUPR_EN (1<<7) |
| 919 | #define MEMINT_CONT_BUSY_EN (1<<6) |
| 920 | #define MEMINT_AVG_BUSY_EN (1<<5) |
| 921 | #define MEMINT_EVAL_CHG_EN (1<<4) |
| 922 | #define MEMINT_MON_IDLE_EN (1<<3) |
| 923 | #define MEMINT_UP_EVAL_EN (1<<2) |
| 924 | #define MEMINT_DOWN_EVAL_EN (1<<1) |
| 925 | #define MEMINT_SW_CMD_EN (1<<0) |
| 926 | #define MEMINTRSTR 0x11182 /* 16 bits */ |
| 927 | #define MEM_RSEXIT_MASK 0xc000 |
| 928 | #define MEM_RSEXIT_SHIFT 14 |
| 929 | #define MEM_CONT_BUSY_MASK 0x3000 |
| 930 | #define MEM_CONT_BUSY_SHIFT 12 |
| 931 | #define MEM_AVG_BUSY_MASK 0x0c00 |
| 932 | #define MEM_AVG_BUSY_SHIFT 10 |
| 933 | #define MEM_EVAL_CHG_MASK 0x0300 |
| 934 | #define MEM_EVAL_BUSY_SHIFT 8 |
| 935 | #define MEM_MON_IDLE_MASK 0x00c0 |
| 936 | #define MEM_MON_IDLE_SHIFT 6 |
| 937 | #define MEM_UP_EVAL_MASK 0x0030 |
| 938 | #define MEM_UP_EVAL_SHIFT 4 |
| 939 | #define MEM_DOWN_EVAL_MASK 0x000c |
| 940 | #define MEM_DOWN_EVAL_SHIFT 2 |
| 941 | #define MEM_SW_CMD_MASK 0x0003 |
| 942 | #define MEM_INT_STEER_GFX 0 |
| 943 | #define MEM_INT_STEER_CMR 1 |
| 944 | #define MEM_INT_STEER_SMI 2 |
| 945 | #define MEM_INT_STEER_SCI 3 |
| 946 | #define MEMINTRSTS 0x11184 |
| 947 | #define MEMINT_RSEXIT (1<<7) |
| 948 | #define MEMINT_CONT_BUSY (1<<6) |
| 949 | #define MEMINT_AVG_BUSY (1<<5) |
| 950 | #define MEMINT_EVAL_CHG (1<<4) |
| 951 | #define MEMINT_MON_IDLE (1<<3) |
| 952 | #define MEMINT_UP_EVAL (1<<2) |
| 953 | #define MEMINT_DOWN_EVAL (1<<1) |
| 954 | #define MEMINT_SW_CMD (1<<0) |
| 955 | #define MEMMODECTL 0x11190 |
| 956 | #define MEMMODE_BOOST_EN (1<<31) |
| 957 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ |
| 958 | #define MEMMODE_BOOST_FREQ_SHIFT 24 |
| 959 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 |
| 960 | #define MEMMODE_IDLE_MODE_SHIFT 16 |
| 961 | #define MEMMODE_IDLE_MODE_EVAL 0 |
| 962 | #define MEMMODE_IDLE_MODE_CONT 1 |
| 963 | #define MEMMODE_HWIDLE_EN (1<<15) |
| 964 | #define MEMMODE_SWMODE_EN (1<<14) |
| 965 | #define MEMMODE_RCLK_GATE (1<<13) |
| 966 | #define MEMMODE_HW_UPDATE (1<<12) |
| 967 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ |
| 968 | #define MEMMODE_FSTART_SHIFT 8 |
| 969 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ |
| 970 | #define MEMMODE_FMAX_SHIFT 4 |
| 971 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ |
| 972 | #define RCBMAXAVG 0x1119c |
| 973 | #define MEMSWCTL2 0x1119e /* Cantiga only */ |
| 974 | #define SWMEMCMD_RENDER_OFF (0 << 13) |
| 975 | #define SWMEMCMD_RENDER_ON (1 << 13) |
| 976 | #define SWMEMCMD_SWFREQ (2 << 13) |
| 977 | #define SWMEMCMD_TARVID (3 << 13) |
| 978 | #define SWMEMCMD_VRM_OFF (4 << 13) |
| 979 | #define SWMEMCMD_VRM_ON (5 << 13) |
| 980 | #define CMDSTS (1<<12) |
| 981 | #define SFCAVM (1<<11) |
| 982 | #define SWFREQ_MASK 0x0380 /* P0-7 */ |
| 983 | #define SWFREQ_SHIFT 7 |
| 984 | #define TARVID_MASK 0x001f |
| 985 | #define MEMSTAT_CTG 0x111a0 |
| 986 | #define RCBMINAVG 0x111a0 |
| 987 | #define RCUPEI 0x111b0 |
| 988 | #define RCDNEI 0x111b4 |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 989 | #define MCHBAR_RENDER_STANDBY 0x111b8 |
Jesse Barnes | 97f5ab6 | 2009-10-08 10:16:48 -0700 | [diff] [blame] | 990 | #define RCX_SW_EXIT (1<<23) |
| 991 | #define RSX_STATUS_MASK 0x00700000 |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 992 | #define VIDCTL 0x111c0 |
| 993 | #define VIDSTS 0x111c8 |
| 994 | #define VIDSTART 0x111cc /* 8 bits */ |
| 995 | #define MEMSTAT_ILK 0x111f8 |
| 996 | #define MEMSTAT_VID_MASK 0x7f00 |
| 997 | #define MEMSTAT_VID_SHIFT 8 |
| 998 | #define MEMSTAT_PSTATE_MASK 0x00f8 |
| 999 | #define MEMSTAT_PSTATE_SHIFT 3 |
| 1000 | #define MEMSTAT_MON_ACTV (1<<2) |
| 1001 | #define MEMSTAT_SRC_CTL_MASK 0x0003 |
| 1002 | #define MEMSTAT_SRC_CTL_CORE 0 |
| 1003 | #define MEMSTAT_SRC_CTL_TRB 1 |
| 1004 | #define MEMSTAT_SRC_CTL_THM 2 |
| 1005 | #define MEMSTAT_SRC_CTL_STDBY 3 |
| 1006 | #define RCPREVBSYTUPAVG 0x113b8 |
| 1007 | #define RCPREVBSYTDNAVG 0x113bc |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1008 | #define SDEW 0x1124c |
| 1009 | #define CSIEW0 0x11250 |
| 1010 | #define CSIEW1 0x11254 |
| 1011 | #define CSIEW2 0x11258 |
| 1012 | #define PEW 0x1125c |
| 1013 | #define DEW 0x11270 |
| 1014 | #define MCHAFE 0x112c0 |
| 1015 | #define CSIEC 0x112e0 |
| 1016 | #define DMIEC 0x112e4 |
| 1017 | #define DDREC 0x112e8 |
| 1018 | #define PEG0EC 0x112ec |
| 1019 | #define PEG1EC 0x112f0 |
| 1020 | #define GFXEC 0x112f4 |
| 1021 | #define RPPREVBSYTUPAVG 0x113b8 |
| 1022 | #define RPPREVBSYTDNAVG 0x113bc |
| 1023 | #define ECR 0x11600 |
| 1024 | #define ECR_GPFE (1<<31) |
| 1025 | #define ECR_IMONE (1<<30) |
| 1026 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ |
| 1027 | #define OGW0 0x11608 |
| 1028 | #define OGW1 0x1160c |
| 1029 | #define EG0 0x11610 |
| 1030 | #define EG1 0x11614 |
| 1031 | #define EG2 0x11618 |
| 1032 | #define EG3 0x1161c |
| 1033 | #define EG4 0x11620 |
| 1034 | #define EG5 0x11624 |
| 1035 | #define EG6 0x11628 |
| 1036 | #define EG7 0x1162c |
| 1037 | #define PXW 0x11664 |
| 1038 | #define PXWL 0x11680 |
| 1039 | #define LCFUSE02 0x116c0 |
| 1040 | #define LCFUSE_HIV_MASK 0x000000ff |
| 1041 | #define CSIPLL0 0x12c10 |
| 1042 | #define DDRMPLL1 0X12c20 |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1043 | #define PEG_BAND_GAP_DATA 0x14d68 |
| 1044 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1045 | /* |
| 1046 | * Overlay regs |
| 1047 | */ |
| 1048 | |
| 1049 | #define OVADD 0x30000 |
| 1050 | #define DOVSTA 0x30008 |
| 1051 | #define OC_BUF (0x3<<20) |
| 1052 | #define OGAMC5 0x30010 |
| 1053 | #define OGAMC4 0x30014 |
| 1054 | #define OGAMC3 0x30018 |
| 1055 | #define OGAMC2 0x3001c |
| 1056 | #define OGAMC1 0x30020 |
| 1057 | #define OGAMC0 0x30024 |
| 1058 | |
| 1059 | /* |
| 1060 | * Display engine regs |
| 1061 | */ |
| 1062 | |
| 1063 | /* Pipe A timing regs */ |
| 1064 | #define HTOTAL_A 0x60000 |
| 1065 | #define HBLANK_A 0x60004 |
| 1066 | #define HSYNC_A 0x60008 |
| 1067 | #define VTOTAL_A 0x6000c |
| 1068 | #define VBLANK_A 0x60010 |
| 1069 | #define VSYNC_A 0x60014 |
| 1070 | #define PIPEASRC 0x6001c |
| 1071 | #define BCLRPAT_A 0x60020 |
| 1072 | |
| 1073 | /* Pipe B timing regs */ |
| 1074 | #define HTOTAL_B 0x61000 |
| 1075 | #define HBLANK_B 0x61004 |
| 1076 | #define HSYNC_B 0x61008 |
| 1077 | #define VTOTAL_B 0x6100c |
| 1078 | #define VBLANK_B 0x61010 |
| 1079 | #define VSYNC_B 0x61014 |
| 1080 | #define PIPEBSRC 0x6101c |
| 1081 | #define BCLRPAT_B 0x61020 |
| 1082 | |
| 1083 | /* VGA port control */ |
| 1084 | #define ADPA 0x61100 |
| 1085 | #define ADPA_DAC_ENABLE (1<<31) |
| 1086 | #define ADPA_DAC_DISABLE 0 |
| 1087 | #define ADPA_PIPE_SELECT_MASK (1<<30) |
| 1088 | #define ADPA_PIPE_A_SELECT 0 |
| 1089 | #define ADPA_PIPE_B_SELECT (1<<30) |
| 1090 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
| 1091 | #define ADPA_SETS_HVPOLARITY 0 |
| 1092 | #define ADPA_VSYNC_CNTL_DISABLE (1<<11) |
| 1093 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
| 1094 | #define ADPA_HSYNC_CNTL_DISABLE (1<<10) |
| 1095 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
| 1096 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) |
| 1097 | #define ADPA_VSYNC_ACTIVE_LOW 0 |
| 1098 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) |
| 1099 | #define ADPA_HSYNC_ACTIVE_LOW 0 |
| 1100 | #define ADPA_DPMS_MASK (~(3<<10)) |
| 1101 | #define ADPA_DPMS_ON (0<<10) |
| 1102 | #define ADPA_DPMS_SUSPEND (1<<10) |
| 1103 | #define ADPA_DPMS_STANDBY (2<<10) |
| 1104 | #define ADPA_DPMS_OFF (3<<10) |
| 1105 | |
| 1106 | /* Hotplug control (945+ only) */ |
| 1107 | #define PORT_HOTPLUG_EN 0x61110 |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1108 | #define HDMIB_HOTPLUG_INT_EN (1 << 29) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1109 | #define DPB_HOTPLUG_INT_EN (1 << 29) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1110 | #define HDMIC_HOTPLUG_INT_EN (1 << 28) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1111 | #define DPC_HOTPLUG_INT_EN (1 << 28) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1112 | #define HDMID_HOTPLUG_INT_EN (1 << 27) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1113 | #define DPD_HOTPLUG_INT_EN (1 << 27) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1114 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
| 1115 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) |
| 1116 | #define TV_HOTPLUG_INT_EN (1 << 18) |
| 1117 | #define CRT_HOTPLUG_INT_EN (1 << 9) |
| 1118 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 1119 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
| 1120 | /* must use period 64 on GM45 according to docs */ |
| 1121 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) |
| 1122 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) |
| 1123 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) |
| 1124 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) |
| 1125 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) |
| 1126 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) |
| 1127 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) |
| 1128 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) |
| 1129 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) |
| 1130 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) |
| 1131 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) |
| 1132 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) |
| 1133 | #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1134 | |
| 1135 | #define PORT_HOTPLUG_STAT 0x61114 |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1136 | #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1137 | #define DPB_HOTPLUG_INT_STATUS (1 << 29) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1138 | #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1139 | #define DPC_HOTPLUG_INT_STATUS (1 << 28) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1140 | #define HDMID_HOTPLUG_INT_STATUS (1 << 27) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1141 | #define DPD_HOTPLUG_INT_STATUS (1 << 27) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1142 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
| 1143 | #define TV_HOTPLUG_INT_STATUS (1 << 10) |
| 1144 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) |
| 1145 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) |
| 1146 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) |
| 1147 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) |
| 1148 | #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) |
| 1149 | #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) |
| 1150 | |
| 1151 | /* SDVO port control */ |
| 1152 | #define SDVOB 0x61140 |
| 1153 | #define SDVOC 0x61160 |
| 1154 | #define SDVO_ENABLE (1 << 31) |
| 1155 | #define SDVO_PIPE_B_SELECT (1 << 30) |
| 1156 | #define SDVO_STALL_SELECT (1 << 29) |
| 1157 | #define SDVO_INTERRUPT_ENABLE (1 << 26) |
| 1158 | /** |
| 1159 | * 915G/GM SDVO pixel multiplier. |
| 1160 | * |
| 1161 | * Programmed value is multiplier - 1, up to 5x. |
| 1162 | * |
| 1163 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
| 1164 | */ |
| 1165 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
| 1166 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
| 1167 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
| 1168 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) |
| 1169 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) |
| 1170 | #define SDVOC_GANG_MODE (1 << 16) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1171 | #define SDVO_ENCODING_SDVO (0x0 << 10) |
| 1172 | #define SDVO_ENCODING_HDMI (0x2 << 10) |
| 1173 | /** Requird for HDMI operation */ |
| 1174 | #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1175 | #define SDVO_BORDER_ENABLE (1 << 7) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1176 | #define SDVO_AUDIO_ENABLE (1 << 6) |
| 1177 | /** New with 965, default is to be set */ |
| 1178 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) |
| 1179 | /** New with 965, default is to be set */ |
| 1180 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1181 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) |
| 1182 | #define SDVO_DETECTED (1 << 2) |
| 1183 | /* Bits to be preserved when writing */ |
| 1184 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) |
| 1185 | #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) |
| 1186 | |
| 1187 | /* DVO port control */ |
| 1188 | #define DVOA 0x61120 |
| 1189 | #define DVOB 0x61140 |
| 1190 | #define DVOC 0x61160 |
| 1191 | #define DVO_ENABLE (1 << 31) |
| 1192 | #define DVO_PIPE_B_SELECT (1 << 30) |
| 1193 | #define DVO_PIPE_STALL_UNUSED (0 << 28) |
| 1194 | #define DVO_PIPE_STALL (1 << 28) |
| 1195 | #define DVO_PIPE_STALL_TV (2 << 28) |
| 1196 | #define DVO_PIPE_STALL_MASK (3 << 28) |
| 1197 | #define DVO_USE_VGA_SYNC (1 << 15) |
| 1198 | #define DVO_DATA_ORDER_I740 (0 << 14) |
| 1199 | #define DVO_DATA_ORDER_FP (1 << 14) |
| 1200 | #define DVO_VSYNC_DISABLE (1 << 11) |
| 1201 | #define DVO_HSYNC_DISABLE (1 << 10) |
| 1202 | #define DVO_VSYNC_TRISTATE (1 << 9) |
| 1203 | #define DVO_HSYNC_TRISTATE (1 << 8) |
| 1204 | #define DVO_BORDER_ENABLE (1 << 7) |
| 1205 | #define DVO_DATA_ORDER_GBRG (1 << 6) |
| 1206 | #define DVO_DATA_ORDER_RGGB (0 << 6) |
| 1207 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) |
| 1208 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) |
| 1209 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) |
| 1210 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) |
| 1211 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) |
| 1212 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ |
| 1213 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ |
| 1214 | #define DVO_PRESERVE_MASK (0x7<<24) |
| 1215 | #define DVOA_SRCDIM 0x61124 |
| 1216 | #define DVOB_SRCDIM 0x61144 |
| 1217 | #define DVOC_SRCDIM 0x61164 |
| 1218 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 |
| 1219 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 |
| 1220 | |
| 1221 | /* LVDS port control */ |
| 1222 | #define LVDS 0x61180 |
| 1223 | /* |
| 1224 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as |
| 1225 | * the DPLL semantics change when the LVDS is assigned to that pipe. |
| 1226 | */ |
| 1227 | #define LVDS_PORT_EN (1 << 31) |
| 1228 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ |
| 1229 | #define LVDS_PIPEB_SELECT (1 << 30) |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 1230 | /* LVDS dithering flag on 965/g4x platform */ |
| 1231 | #define LVDS_ENABLE_DITHER (1 << 25) |
Zhao Yakui | a3e17eb | 2009-10-10 10:42:37 +0800 | [diff] [blame] | 1232 | /* Enable border for unscaled (or aspect-scaled) display */ |
| 1233 | #define LVDS_BORDER_ENABLE (1 << 15) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1234 | /* |
| 1235 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per |
| 1236 | * pixel. |
| 1237 | */ |
| 1238 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) |
| 1239 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) |
| 1240 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) |
| 1241 | /* |
| 1242 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit |
| 1243 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be |
| 1244 | * on. |
| 1245 | */ |
| 1246 | #define LVDS_A3_POWER_MASK (3 << 6) |
| 1247 | #define LVDS_A3_POWER_DOWN (0 << 6) |
| 1248 | #define LVDS_A3_POWER_UP (3 << 6) |
| 1249 | /* |
| 1250 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP |
| 1251 | * is set. |
| 1252 | */ |
| 1253 | #define LVDS_CLKB_POWER_MASK (3 << 4) |
| 1254 | #define LVDS_CLKB_POWER_DOWN (0 << 4) |
| 1255 | #define LVDS_CLKB_POWER_UP (3 << 4) |
| 1256 | /* |
| 1257 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 |
| 1258 | * setting for whether we are in dual-channel mode. The B3 pair will |
| 1259 | * additionally only be powered up when LVDS_A3_POWER_UP is set. |
| 1260 | */ |
| 1261 | #define LVDS_B0B3_POWER_MASK (3 << 2) |
| 1262 | #define LVDS_B0B3_POWER_DOWN (0 << 2) |
| 1263 | #define LVDS_B0B3_POWER_UP (3 << 2) |
| 1264 | |
| 1265 | /* Panel power sequencing */ |
| 1266 | #define PP_STATUS 0x61200 |
| 1267 | #define PP_ON (1 << 31) |
| 1268 | /* |
| 1269 | * Indicates that all dependencies of the panel are on: |
| 1270 | * |
| 1271 | * - PLL enabled |
| 1272 | * - pipe enabled |
| 1273 | * - LVDS/DVOB/DVOC on |
| 1274 | */ |
| 1275 | #define PP_READY (1 << 30) |
| 1276 | #define PP_SEQUENCE_NONE (0 << 28) |
| 1277 | #define PP_SEQUENCE_ON (1 << 28) |
| 1278 | #define PP_SEQUENCE_OFF (2 << 28) |
| 1279 | #define PP_SEQUENCE_MASK 0x30000000 |
| 1280 | #define PP_CONTROL 0x61204 |
| 1281 | #define POWER_TARGET_ON (1 << 0) |
| 1282 | #define PP_ON_DELAYS 0x61208 |
| 1283 | #define PP_OFF_DELAYS 0x6120c |
| 1284 | #define PP_DIVISOR 0x61210 |
| 1285 | |
| 1286 | /* Panel fitting */ |
| 1287 | #define PFIT_CONTROL 0x61230 |
| 1288 | #define PFIT_ENABLE (1 << 31) |
| 1289 | #define PFIT_PIPE_MASK (3 << 29) |
| 1290 | #define PFIT_PIPE_SHIFT 29 |
| 1291 | #define VERT_INTERP_DISABLE (0 << 10) |
| 1292 | #define VERT_INTERP_BILINEAR (1 << 10) |
| 1293 | #define VERT_INTERP_MASK (3 << 10) |
| 1294 | #define VERT_AUTO_SCALE (1 << 9) |
| 1295 | #define HORIZ_INTERP_DISABLE (0 << 6) |
| 1296 | #define HORIZ_INTERP_BILINEAR (1 << 6) |
| 1297 | #define HORIZ_INTERP_MASK (3 << 6) |
| 1298 | #define HORIZ_AUTO_SCALE (1 << 5) |
| 1299 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) |
Zhao Yakui | 3fbe18d | 2009-06-22 15:31:25 +0800 | [diff] [blame] | 1300 | #define PFIT_FILTER_FUZZY (0 << 24) |
| 1301 | #define PFIT_SCALING_AUTO (0 << 26) |
| 1302 | #define PFIT_SCALING_PROGRAMMED (1 << 26) |
| 1303 | #define PFIT_SCALING_PILLAR (2 << 26) |
| 1304 | #define PFIT_SCALING_LETTER (3 << 26) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1305 | #define PFIT_PGM_RATIOS 0x61234 |
| 1306 | #define PFIT_VERT_SCALE_MASK 0xfff00000 |
| 1307 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
Zhao Yakui | 3fbe18d | 2009-06-22 15:31:25 +0800 | [diff] [blame] | 1308 | /* Pre-965 */ |
| 1309 | #define PFIT_VERT_SCALE_SHIFT 20 |
| 1310 | #define PFIT_VERT_SCALE_MASK 0xfff00000 |
| 1311 | #define PFIT_HORIZ_SCALE_SHIFT 4 |
| 1312 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 |
| 1313 | /* 965+ */ |
| 1314 | #define PFIT_VERT_SCALE_SHIFT_965 16 |
| 1315 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 |
| 1316 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 |
| 1317 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff |
| 1318 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1319 | #define PFIT_AUTO_RATIOS 0x61238 |
| 1320 | |
| 1321 | /* Backlight control */ |
| 1322 | #define BLC_PWM_CTL 0x61254 |
| 1323 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
| 1324 | #define BLC_PWM_CTL2 0x61250 /* 965+ only */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 1325 | #define BLM_COMBINATION_MODE (1 << 30) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1326 | /* |
| 1327 | * This is the most significant 15 bits of the number of backlight cycles in a |
| 1328 | * complete cycle of the modulated backlight control. |
| 1329 | * |
| 1330 | * The actual value is this field multiplied by two. |
| 1331 | */ |
| 1332 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
| 1333 | #define BLM_LEGACY_MODE (1 << 16) |
| 1334 | /* |
| 1335 | * This is the number of cycles out of the backlight modulation cycle for which |
| 1336 | * the backlight is on. |
| 1337 | * |
| 1338 | * This field must be no greater than the number of cycles in the complete |
| 1339 | * backlight modulation cycle. |
| 1340 | */ |
| 1341 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
| 1342 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
| 1343 | |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 1344 | #define BLC_HIST_CTL 0x61260 |
| 1345 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1346 | /* TV port control */ |
| 1347 | #define TV_CTL 0x68000 |
| 1348 | /** Enables the TV encoder */ |
| 1349 | # define TV_ENC_ENABLE (1 << 31) |
| 1350 | /** Sources the TV encoder input from pipe B instead of A. */ |
| 1351 | # define TV_ENC_PIPEB_SELECT (1 << 30) |
| 1352 | /** Outputs composite video (DAC A only) */ |
| 1353 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
| 1354 | /** Outputs SVideo video (DAC B/C) */ |
| 1355 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
| 1356 | /** Outputs Component video (DAC A/B/C) */ |
| 1357 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
| 1358 | /** Outputs Composite and SVideo (DAC A/B/C) */ |
| 1359 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
| 1360 | # define TV_TRILEVEL_SYNC (1 << 21) |
| 1361 | /** Enables slow sync generation (945GM only) */ |
| 1362 | # define TV_SLOW_SYNC (1 << 20) |
| 1363 | /** Selects 4x oversampling for 480i and 576p */ |
| 1364 | # define TV_OVERSAMPLE_4X (0 << 18) |
| 1365 | /** Selects 2x oversampling for 720p and 1080i */ |
| 1366 | # define TV_OVERSAMPLE_2X (1 << 18) |
| 1367 | /** Selects no oversampling for 1080p */ |
| 1368 | # define TV_OVERSAMPLE_NONE (2 << 18) |
| 1369 | /** Selects 8x oversampling */ |
| 1370 | # define TV_OVERSAMPLE_8X (3 << 18) |
| 1371 | /** Selects progressive mode rather than interlaced */ |
| 1372 | # define TV_PROGRESSIVE (1 << 17) |
| 1373 | /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
| 1374 | # define TV_PAL_BURST (1 << 16) |
| 1375 | /** Field for setting delay of Y compared to C */ |
| 1376 | # define TV_YC_SKEW_MASK (7 << 12) |
| 1377 | /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
| 1378 | # define TV_ENC_SDP_FIX (1 << 11) |
| 1379 | /** |
| 1380 | * Enables a fix for the 915GM only. |
| 1381 | * |
| 1382 | * Not sure what it does. |
| 1383 | */ |
| 1384 | # define TV_ENC_C0_FIX (1 << 10) |
| 1385 | /** Bits that must be preserved by software */ |
Zhenyu Wang | d2d9f23 | 2009-03-04 19:36:02 +0800 | [diff] [blame] | 1386 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1387 | # define TV_FUSE_STATE_MASK (3 << 4) |
| 1388 | /** Read-only state that reports all features enabled */ |
| 1389 | # define TV_FUSE_STATE_ENABLED (0 << 4) |
| 1390 | /** Read-only state that reports that Macrovision is disabled in hardware*/ |
| 1391 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
| 1392 | /** Read-only state that reports that TV-out is disabled in hardware. */ |
| 1393 | # define TV_FUSE_STATE_DISABLED (2 << 4) |
| 1394 | /** Normal operation */ |
| 1395 | # define TV_TEST_MODE_NORMAL (0 << 0) |
| 1396 | /** Encoder test pattern 1 - combo pattern */ |
| 1397 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) |
| 1398 | /** Encoder test pattern 2 - full screen vertical 75% color bars */ |
| 1399 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) |
| 1400 | /** Encoder test pattern 3 - full screen horizontal 75% color bars */ |
| 1401 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) |
| 1402 | /** Encoder test pattern 4 - random noise */ |
| 1403 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) |
| 1404 | /** Encoder test pattern 5 - linear color ramps */ |
| 1405 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) |
| 1406 | /** |
| 1407 | * This test mode forces the DACs to 50% of full output. |
| 1408 | * |
| 1409 | * This is used for load detection in combination with TVDAC_SENSE_MASK |
| 1410 | */ |
| 1411 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) |
| 1412 | # define TV_TEST_MODE_MASK (7 << 0) |
| 1413 | |
| 1414 | #define TV_DAC 0x68004 |
| 1415 | /** |
| 1416 | * Reports that DAC state change logic has reported change (RO). |
| 1417 | * |
| 1418 | * This gets cleared when TV_DAC_STATE_EN is cleared |
| 1419 | */ |
| 1420 | # define TVDAC_STATE_CHG (1 << 31) |
| 1421 | # define TVDAC_SENSE_MASK (7 << 28) |
| 1422 | /** Reports that DAC A voltage is above the detect threshold */ |
| 1423 | # define TVDAC_A_SENSE (1 << 30) |
| 1424 | /** Reports that DAC B voltage is above the detect threshold */ |
| 1425 | # define TVDAC_B_SENSE (1 << 29) |
| 1426 | /** Reports that DAC C voltage is above the detect threshold */ |
| 1427 | # define TVDAC_C_SENSE (1 << 28) |
| 1428 | /** |
| 1429 | * Enables DAC state detection logic, for load-based TV detection. |
| 1430 | * |
| 1431 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set |
| 1432 | * to off, for load detection to work. |
| 1433 | */ |
| 1434 | # define TVDAC_STATE_CHG_EN (1 << 27) |
| 1435 | /** Sets the DAC A sense value to high */ |
| 1436 | # define TVDAC_A_SENSE_CTL (1 << 26) |
| 1437 | /** Sets the DAC B sense value to high */ |
| 1438 | # define TVDAC_B_SENSE_CTL (1 << 25) |
| 1439 | /** Sets the DAC C sense value to high */ |
| 1440 | # define TVDAC_C_SENSE_CTL (1 << 24) |
| 1441 | /** Overrides the ENC_ENABLE and DAC voltage levels */ |
| 1442 | # define DAC_CTL_OVERRIDE (1 << 7) |
| 1443 | /** Sets the slew rate. Must be preserved in software */ |
| 1444 | # define ENC_TVDAC_SLEW_FAST (1 << 6) |
| 1445 | # define DAC_A_1_3_V (0 << 4) |
| 1446 | # define DAC_A_1_1_V (1 << 4) |
| 1447 | # define DAC_A_0_7_V (2 << 4) |
Ma Ling | cb66c69 | 2009-05-31 16:58:32 +0800 | [diff] [blame] | 1448 | # define DAC_A_MASK (3 << 4) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1449 | # define DAC_B_1_3_V (0 << 2) |
| 1450 | # define DAC_B_1_1_V (1 << 2) |
| 1451 | # define DAC_B_0_7_V (2 << 2) |
Ma Ling | cb66c69 | 2009-05-31 16:58:32 +0800 | [diff] [blame] | 1452 | # define DAC_B_MASK (3 << 2) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1453 | # define DAC_C_1_3_V (0 << 0) |
| 1454 | # define DAC_C_1_1_V (1 << 0) |
| 1455 | # define DAC_C_0_7_V (2 << 0) |
Ma Ling | cb66c69 | 2009-05-31 16:58:32 +0800 | [diff] [blame] | 1456 | # define DAC_C_MASK (3 << 0) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 1457 | |
| 1458 | /** |
| 1459 | * CSC coefficients are stored in a floating point format with 9 bits of |
| 1460 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, |
| 1461 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with |
| 1462 | * -1 (0x3) being the only legal negative value. |
| 1463 | */ |
| 1464 | #define TV_CSC_Y 0x68010 |
| 1465 | # define TV_RY_MASK 0x07ff0000 |
| 1466 | # define TV_RY_SHIFT 16 |
| 1467 | # define TV_GY_MASK 0x00000fff |
| 1468 | # define TV_GY_SHIFT 0 |
| 1469 | |
| 1470 | #define TV_CSC_Y2 0x68014 |
| 1471 | # define TV_BY_MASK 0x07ff0000 |
| 1472 | # define TV_BY_SHIFT 16 |
| 1473 | /** |
| 1474 | * Y attenuation for component video. |
| 1475 | * |
| 1476 | * Stored in 1.9 fixed point. |
| 1477 | */ |
| 1478 | # define TV_AY_MASK 0x000003ff |
| 1479 | # define TV_AY_SHIFT 0 |
| 1480 | |
| 1481 | #define TV_CSC_U 0x68018 |
| 1482 | # define TV_RU_MASK 0x07ff0000 |
| 1483 | # define TV_RU_SHIFT 16 |
| 1484 | # define TV_GU_MASK 0x000007ff |
| 1485 | # define TV_GU_SHIFT 0 |
| 1486 | |
| 1487 | #define TV_CSC_U2 0x6801c |
| 1488 | # define TV_BU_MASK 0x07ff0000 |
| 1489 | # define TV_BU_SHIFT 16 |
| 1490 | /** |
| 1491 | * U attenuation for component video. |
| 1492 | * |
| 1493 | * Stored in 1.9 fixed point. |
| 1494 | */ |
| 1495 | # define TV_AU_MASK 0x000003ff |
| 1496 | # define TV_AU_SHIFT 0 |
| 1497 | |
| 1498 | #define TV_CSC_V 0x68020 |
| 1499 | # define TV_RV_MASK 0x0fff0000 |
| 1500 | # define TV_RV_SHIFT 16 |
| 1501 | # define TV_GV_MASK 0x000007ff |
| 1502 | # define TV_GV_SHIFT 0 |
| 1503 | |
| 1504 | #define TV_CSC_V2 0x68024 |
| 1505 | # define TV_BV_MASK 0x07ff0000 |
| 1506 | # define TV_BV_SHIFT 16 |
| 1507 | /** |
| 1508 | * V attenuation for component video. |
| 1509 | * |
| 1510 | * Stored in 1.9 fixed point. |
| 1511 | */ |
| 1512 | # define TV_AV_MASK 0x000007ff |
| 1513 | # define TV_AV_SHIFT 0 |
| 1514 | |
| 1515 | #define TV_CLR_KNOBS 0x68028 |
| 1516 | /** 2s-complement brightness adjustment */ |
| 1517 | # define TV_BRIGHTNESS_MASK 0xff000000 |
| 1518 | # define TV_BRIGHTNESS_SHIFT 24 |
| 1519 | /** Contrast adjustment, as a 2.6 unsigned floating point number */ |
| 1520 | # define TV_CONTRAST_MASK 0x00ff0000 |
| 1521 | # define TV_CONTRAST_SHIFT 16 |
| 1522 | /** Saturation adjustment, as a 2.6 unsigned floating point number */ |
| 1523 | # define TV_SATURATION_MASK 0x0000ff00 |
| 1524 | # define TV_SATURATION_SHIFT 8 |
| 1525 | /** Hue adjustment, as an integer phase angle in degrees */ |
| 1526 | # define TV_HUE_MASK 0x000000ff |
| 1527 | # define TV_HUE_SHIFT 0 |
| 1528 | |
| 1529 | #define TV_CLR_LEVEL 0x6802c |
| 1530 | /** Controls the DAC level for black */ |
| 1531 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 |
| 1532 | # define TV_BLACK_LEVEL_SHIFT 16 |
| 1533 | /** Controls the DAC level for blanking */ |
| 1534 | # define TV_BLANK_LEVEL_MASK 0x000001ff |
| 1535 | # define TV_BLANK_LEVEL_SHIFT 0 |
| 1536 | |
| 1537 | #define TV_H_CTL_1 0x68030 |
| 1538 | /** Number of pixels in the hsync. */ |
| 1539 | # define TV_HSYNC_END_MASK 0x1fff0000 |
| 1540 | # define TV_HSYNC_END_SHIFT 16 |
| 1541 | /** Total number of pixels minus one in the line (display and blanking). */ |
| 1542 | # define TV_HTOTAL_MASK 0x00001fff |
| 1543 | # define TV_HTOTAL_SHIFT 0 |
| 1544 | |
| 1545 | #define TV_H_CTL_2 0x68034 |
| 1546 | /** Enables the colorburst (needed for non-component color) */ |
| 1547 | # define TV_BURST_ENA (1 << 31) |
| 1548 | /** Offset of the colorburst from the start of hsync, in pixels minus one. */ |
| 1549 | # define TV_HBURST_START_SHIFT 16 |
| 1550 | # define TV_HBURST_START_MASK 0x1fff0000 |
| 1551 | /** Length of the colorburst */ |
| 1552 | # define TV_HBURST_LEN_SHIFT 0 |
| 1553 | # define TV_HBURST_LEN_MASK 0x0001fff |
| 1554 | |
| 1555 | #define TV_H_CTL_3 0x68038 |
| 1556 | /** End of hblank, measured in pixels minus one from start of hsync */ |
| 1557 | # define TV_HBLANK_END_SHIFT 16 |
| 1558 | # define TV_HBLANK_END_MASK 0x1fff0000 |
| 1559 | /** Start of hblank, measured in pixels minus one from start of hsync */ |
| 1560 | # define TV_HBLANK_START_SHIFT 0 |
| 1561 | # define TV_HBLANK_START_MASK 0x0001fff |
| 1562 | |
| 1563 | #define TV_V_CTL_1 0x6803c |
| 1564 | /** XXX */ |
| 1565 | # define TV_NBR_END_SHIFT 16 |
| 1566 | # define TV_NBR_END_MASK 0x07ff0000 |
| 1567 | /** XXX */ |
| 1568 | # define TV_VI_END_F1_SHIFT 8 |
| 1569 | # define TV_VI_END_F1_MASK 0x00003f00 |
| 1570 | /** XXX */ |
| 1571 | # define TV_VI_END_F2_SHIFT 0 |
| 1572 | # define TV_VI_END_F2_MASK 0x0000003f |
| 1573 | |
| 1574 | #define TV_V_CTL_2 0x68040 |
| 1575 | /** Length of vsync, in half lines */ |
| 1576 | # define TV_VSYNC_LEN_MASK 0x07ff0000 |
| 1577 | # define TV_VSYNC_LEN_SHIFT 16 |
| 1578 | /** Offset of the start of vsync in field 1, measured in one less than the |
| 1579 | * number of half lines. |
| 1580 | */ |
| 1581 | # define TV_VSYNC_START_F1_MASK 0x00007f00 |
| 1582 | # define TV_VSYNC_START_F1_SHIFT 8 |
| 1583 | /** |
| 1584 | * Offset of the start of vsync in field 2, measured in one less than the |
| 1585 | * number of half lines. |
| 1586 | */ |
| 1587 | # define TV_VSYNC_START_F2_MASK 0x0000007f |
| 1588 | # define TV_VSYNC_START_F2_SHIFT 0 |
| 1589 | |
| 1590 | #define TV_V_CTL_3 0x68044 |
| 1591 | /** Enables generation of the equalization signal */ |
| 1592 | # define TV_EQUAL_ENA (1 << 31) |
| 1593 | /** Length of vsync, in half lines */ |
| 1594 | # define TV_VEQ_LEN_MASK 0x007f0000 |
| 1595 | # define TV_VEQ_LEN_SHIFT 16 |
| 1596 | /** Offset of the start of equalization in field 1, measured in one less than |
| 1597 | * the number of half lines. |
| 1598 | */ |
| 1599 | # define TV_VEQ_START_F1_MASK 0x0007f00 |
| 1600 | # define TV_VEQ_START_F1_SHIFT 8 |
| 1601 | /** |
| 1602 | * Offset of the start of equalization in field 2, measured in one less than |
| 1603 | * the number of half lines. |
| 1604 | */ |
| 1605 | # define TV_VEQ_START_F2_MASK 0x000007f |
| 1606 | # define TV_VEQ_START_F2_SHIFT 0 |
| 1607 | |
| 1608 | #define TV_V_CTL_4 0x68048 |
| 1609 | /** |
| 1610 | * Offset to start of vertical colorburst, measured in one less than the |
| 1611 | * number of lines from vertical start. |
| 1612 | */ |
| 1613 | # define TV_VBURST_START_F1_MASK 0x003f0000 |
| 1614 | # define TV_VBURST_START_F1_SHIFT 16 |
| 1615 | /** |
| 1616 | * Offset to the end of vertical colorburst, measured in one less than the |
| 1617 | * number of lines from the start of NBR. |
| 1618 | */ |
| 1619 | # define TV_VBURST_END_F1_MASK 0x000000ff |
| 1620 | # define TV_VBURST_END_F1_SHIFT 0 |
| 1621 | |
| 1622 | #define TV_V_CTL_5 0x6804c |
| 1623 | /** |
| 1624 | * Offset to start of vertical colorburst, measured in one less than the |
| 1625 | * number of lines from vertical start. |
| 1626 | */ |
| 1627 | # define TV_VBURST_START_F2_MASK 0x003f0000 |
| 1628 | # define TV_VBURST_START_F2_SHIFT 16 |
| 1629 | /** |
| 1630 | * Offset to the end of vertical colorburst, measured in one less than the |
| 1631 | * number of lines from the start of NBR. |
| 1632 | */ |
| 1633 | # define TV_VBURST_END_F2_MASK 0x000000ff |
| 1634 | # define TV_VBURST_END_F2_SHIFT 0 |
| 1635 | |
| 1636 | #define TV_V_CTL_6 0x68050 |
| 1637 | /** |
| 1638 | * Offset to start of vertical colorburst, measured in one less than the |
| 1639 | * number of lines from vertical start. |
| 1640 | */ |
| 1641 | # define TV_VBURST_START_F3_MASK 0x003f0000 |
| 1642 | # define TV_VBURST_START_F3_SHIFT 16 |
| 1643 | /** |
| 1644 | * Offset to the end of vertical colorburst, measured in one less than the |
| 1645 | * number of lines from the start of NBR. |
| 1646 | */ |
| 1647 | # define TV_VBURST_END_F3_MASK 0x000000ff |
| 1648 | # define TV_VBURST_END_F3_SHIFT 0 |
| 1649 | |
| 1650 | #define TV_V_CTL_7 0x68054 |
| 1651 | /** |
| 1652 | * Offset to start of vertical colorburst, measured in one less than the |
| 1653 | * number of lines from vertical start. |
| 1654 | */ |
| 1655 | # define TV_VBURST_START_F4_MASK 0x003f0000 |
| 1656 | # define TV_VBURST_START_F4_SHIFT 16 |
| 1657 | /** |
| 1658 | * Offset to the end of vertical colorburst, measured in one less than the |
| 1659 | * number of lines from the start of NBR. |
| 1660 | */ |
| 1661 | # define TV_VBURST_END_F4_MASK 0x000000ff |
| 1662 | # define TV_VBURST_END_F4_SHIFT 0 |
| 1663 | |
| 1664 | #define TV_SC_CTL_1 0x68060 |
| 1665 | /** Turns on the first subcarrier phase generation DDA */ |
| 1666 | # define TV_SC_DDA1_EN (1 << 31) |
| 1667 | /** Turns on the first subcarrier phase generation DDA */ |
| 1668 | # define TV_SC_DDA2_EN (1 << 30) |
| 1669 | /** Turns on the first subcarrier phase generation DDA */ |
| 1670 | # define TV_SC_DDA3_EN (1 << 29) |
| 1671 | /** Sets the subcarrier DDA to reset frequency every other field */ |
| 1672 | # define TV_SC_RESET_EVERY_2 (0 << 24) |
| 1673 | /** Sets the subcarrier DDA to reset frequency every fourth field */ |
| 1674 | # define TV_SC_RESET_EVERY_4 (1 << 24) |
| 1675 | /** Sets the subcarrier DDA to reset frequency every eighth field */ |
| 1676 | # define TV_SC_RESET_EVERY_8 (2 << 24) |
| 1677 | /** Sets the subcarrier DDA to never reset the frequency */ |
| 1678 | # define TV_SC_RESET_NEVER (3 << 24) |
| 1679 | /** Sets the peak amplitude of the colorburst.*/ |
| 1680 | # define TV_BURST_LEVEL_MASK 0x00ff0000 |
| 1681 | # define TV_BURST_LEVEL_SHIFT 16 |
| 1682 | /** Sets the increment of the first subcarrier phase generation DDA */ |
| 1683 | # define TV_SCDDA1_INC_MASK 0x00000fff |
| 1684 | # define TV_SCDDA1_INC_SHIFT 0 |
| 1685 | |
| 1686 | #define TV_SC_CTL_2 0x68064 |
| 1687 | /** Sets the rollover for the second subcarrier phase generation DDA */ |
| 1688 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
| 1689 | # define TV_SCDDA2_SIZE_SHIFT 16 |
| 1690 | /** Sets the increent of the second subcarrier phase generation DDA */ |
| 1691 | # define TV_SCDDA2_INC_MASK 0x00007fff |
| 1692 | # define TV_SCDDA2_INC_SHIFT 0 |
| 1693 | |
| 1694 | #define TV_SC_CTL_3 0x68068 |
| 1695 | /** Sets the rollover for the third subcarrier phase generation DDA */ |
| 1696 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
| 1697 | # define TV_SCDDA3_SIZE_SHIFT 16 |
| 1698 | /** Sets the increent of the third subcarrier phase generation DDA */ |
| 1699 | # define TV_SCDDA3_INC_MASK 0x00007fff |
| 1700 | # define TV_SCDDA3_INC_SHIFT 0 |
| 1701 | |
| 1702 | #define TV_WIN_POS 0x68070 |
| 1703 | /** X coordinate of the display from the start of horizontal active */ |
| 1704 | # define TV_XPOS_MASK 0x1fff0000 |
| 1705 | # define TV_XPOS_SHIFT 16 |
| 1706 | /** Y coordinate of the display from the start of vertical active (NBR) */ |
| 1707 | # define TV_YPOS_MASK 0x00000fff |
| 1708 | # define TV_YPOS_SHIFT 0 |
| 1709 | |
| 1710 | #define TV_WIN_SIZE 0x68074 |
| 1711 | /** Horizontal size of the display window, measured in pixels*/ |
| 1712 | # define TV_XSIZE_MASK 0x1fff0000 |
| 1713 | # define TV_XSIZE_SHIFT 16 |
| 1714 | /** |
| 1715 | * Vertical size of the display window, measured in pixels. |
| 1716 | * |
| 1717 | * Must be even for interlaced modes. |
| 1718 | */ |
| 1719 | # define TV_YSIZE_MASK 0x00000fff |
| 1720 | # define TV_YSIZE_SHIFT 0 |
| 1721 | |
| 1722 | #define TV_FILTER_CTL_1 0x68080 |
| 1723 | /** |
| 1724 | * Enables automatic scaling calculation. |
| 1725 | * |
| 1726 | * If set, the rest of the registers are ignored, and the calculated values can |
| 1727 | * be read back from the register. |
| 1728 | */ |
| 1729 | # define TV_AUTO_SCALE (1 << 31) |
| 1730 | /** |
| 1731 | * Disables the vertical filter. |
| 1732 | * |
| 1733 | * This is required on modes more than 1024 pixels wide */ |
| 1734 | # define TV_V_FILTER_BYPASS (1 << 29) |
| 1735 | /** Enables adaptive vertical filtering */ |
| 1736 | # define TV_VADAPT (1 << 28) |
| 1737 | # define TV_VADAPT_MODE_MASK (3 << 26) |
| 1738 | /** Selects the least adaptive vertical filtering mode */ |
| 1739 | # define TV_VADAPT_MODE_LEAST (0 << 26) |
| 1740 | /** Selects the moderately adaptive vertical filtering mode */ |
| 1741 | # define TV_VADAPT_MODE_MODERATE (1 << 26) |
| 1742 | /** Selects the most adaptive vertical filtering mode */ |
| 1743 | # define TV_VADAPT_MODE_MOST (3 << 26) |
| 1744 | /** |
| 1745 | * Sets the horizontal scaling factor. |
| 1746 | * |
| 1747 | * This should be the fractional part of the horizontal scaling factor divided |
| 1748 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: |
| 1749 | * |
| 1750 | * (src width - 1) / ((oversample * dest width) - 1) |
| 1751 | */ |
| 1752 | # define TV_HSCALE_FRAC_MASK 0x00003fff |
| 1753 | # define TV_HSCALE_FRAC_SHIFT 0 |
| 1754 | |
| 1755 | #define TV_FILTER_CTL_2 0x68084 |
| 1756 | /** |
| 1757 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
| 1758 | * |
| 1759 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) |
| 1760 | */ |
| 1761 | # define TV_VSCALE_INT_MASK 0x00038000 |
| 1762 | # define TV_VSCALE_INT_SHIFT 15 |
| 1763 | /** |
| 1764 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
| 1765 | * |
| 1766 | * \sa TV_VSCALE_INT_MASK |
| 1767 | */ |
| 1768 | # define TV_VSCALE_FRAC_MASK 0x00007fff |
| 1769 | # define TV_VSCALE_FRAC_SHIFT 0 |
| 1770 | |
| 1771 | #define TV_FILTER_CTL_3 0x68088 |
| 1772 | /** |
| 1773 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
| 1774 | * |
| 1775 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) |
| 1776 | * |
| 1777 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
| 1778 | */ |
| 1779 | # define TV_VSCALE_IP_INT_MASK 0x00038000 |
| 1780 | # define TV_VSCALE_IP_INT_SHIFT 15 |
| 1781 | /** |
| 1782 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
| 1783 | * |
| 1784 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. |
| 1785 | * |
| 1786 | * \sa TV_VSCALE_IP_INT_MASK |
| 1787 | */ |
| 1788 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff |
| 1789 | # define TV_VSCALE_IP_FRAC_SHIFT 0 |
| 1790 | |
| 1791 | #define TV_CC_CONTROL 0x68090 |
| 1792 | # define TV_CC_ENABLE (1 << 31) |
| 1793 | /** |
| 1794 | * Specifies which field to send the CC data in. |
| 1795 | * |
| 1796 | * CC data is usually sent in field 0. |
| 1797 | */ |
| 1798 | # define TV_CC_FID_MASK (1 << 27) |
| 1799 | # define TV_CC_FID_SHIFT 27 |
| 1800 | /** Sets the horizontal position of the CC data. Usually 135. */ |
| 1801 | # define TV_CC_HOFF_MASK 0x03ff0000 |
| 1802 | # define TV_CC_HOFF_SHIFT 16 |
| 1803 | /** Sets the vertical position of the CC data. Usually 21 */ |
| 1804 | # define TV_CC_LINE_MASK 0x0000003f |
| 1805 | # define TV_CC_LINE_SHIFT 0 |
| 1806 | |
| 1807 | #define TV_CC_DATA 0x68094 |
| 1808 | # define TV_CC_RDY (1 << 31) |
| 1809 | /** Second word of CC data to be transmitted. */ |
| 1810 | # define TV_CC_DATA_2_MASK 0x007f0000 |
| 1811 | # define TV_CC_DATA_2_SHIFT 16 |
| 1812 | /** First word of CC data to be transmitted. */ |
| 1813 | # define TV_CC_DATA_1_MASK 0x0000007f |
| 1814 | # define TV_CC_DATA_1_SHIFT 0 |
| 1815 | |
| 1816 | #define TV_H_LUMA_0 0x68100 |
| 1817 | #define TV_H_LUMA_59 0x681ec |
| 1818 | #define TV_H_CHROMA_0 0x68200 |
| 1819 | #define TV_H_CHROMA_59 0x682ec |
| 1820 | #define TV_V_LUMA_0 0x68300 |
| 1821 | #define TV_V_LUMA_42 0x683a8 |
| 1822 | #define TV_V_CHROMA_0 0x68400 |
| 1823 | #define TV_V_CHROMA_42 0x684a8 |
| 1824 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1825 | /* Display Port */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1826 | #define DP_A 0x64000 /* eDP */ |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1827 | #define DP_B 0x64100 |
| 1828 | #define DP_C 0x64200 |
| 1829 | #define DP_D 0x64300 |
| 1830 | |
| 1831 | #define DP_PORT_EN (1 << 31) |
| 1832 | #define DP_PIPEB_SELECT (1 << 30) |
| 1833 | |
| 1834 | /* Link training mode - select a suitable mode for each stage */ |
| 1835 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) |
| 1836 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) |
| 1837 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) |
| 1838 | #define DP_LINK_TRAIN_OFF (3 << 28) |
| 1839 | #define DP_LINK_TRAIN_MASK (3 << 28) |
| 1840 | #define DP_LINK_TRAIN_SHIFT 28 |
| 1841 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 1842 | /* CPT Link training mode */ |
| 1843 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) |
| 1844 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) |
| 1845 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) |
| 1846 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) |
| 1847 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) |
| 1848 | #define DP_LINK_TRAIN_SHIFT_CPT 8 |
| 1849 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1850 | /* Signal voltages. These are mostly controlled by the other end */ |
| 1851 | #define DP_VOLTAGE_0_4 (0 << 25) |
| 1852 | #define DP_VOLTAGE_0_6 (1 << 25) |
| 1853 | #define DP_VOLTAGE_0_8 (2 << 25) |
| 1854 | #define DP_VOLTAGE_1_2 (3 << 25) |
| 1855 | #define DP_VOLTAGE_MASK (7 << 25) |
| 1856 | #define DP_VOLTAGE_SHIFT 25 |
| 1857 | |
| 1858 | /* Signal pre-emphasis levels, like voltages, the other end tells us what |
| 1859 | * they want |
| 1860 | */ |
| 1861 | #define DP_PRE_EMPHASIS_0 (0 << 22) |
| 1862 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) |
| 1863 | #define DP_PRE_EMPHASIS_6 (2 << 22) |
| 1864 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) |
| 1865 | #define DP_PRE_EMPHASIS_MASK (7 << 22) |
| 1866 | #define DP_PRE_EMPHASIS_SHIFT 22 |
| 1867 | |
| 1868 | /* How many wires to use. I guess 3 was too hard */ |
| 1869 | #define DP_PORT_WIDTH_1 (0 << 19) |
| 1870 | #define DP_PORT_WIDTH_2 (1 << 19) |
| 1871 | #define DP_PORT_WIDTH_4 (3 << 19) |
| 1872 | #define DP_PORT_WIDTH_MASK (7 << 19) |
| 1873 | |
| 1874 | /* Mystic DPCD version 1.1 special mode */ |
| 1875 | #define DP_ENHANCED_FRAMING (1 << 18) |
| 1876 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1877 | /* eDP */ |
| 1878 | #define DP_PLL_FREQ_270MHZ (0 << 16) |
| 1879 | #define DP_PLL_FREQ_160MHZ (1 << 16) |
| 1880 | #define DP_PLL_FREQ_MASK (3 << 16) |
| 1881 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1882 | /** locked once port is enabled */ |
| 1883 | #define DP_PORT_REVERSAL (1 << 15) |
| 1884 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1885 | /* eDP */ |
| 1886 | #define DP_PLL_ENABLE (1 << 14) |
| 1887 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1888 | /** sends the clock on lane 15 of the PEG for debug */ |
| 1889 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
| 1890 | |
| 1891 | #define DP_SCRAMBLING_DISABLE (1 << 12) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1892 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1893 | |
| 1894 | /** limit RGB values to avoid confusing TVs */ |
| 1895 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
| 1896 | |
| 1897 | /** Turn on the audio link */ |
| 1898 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
| 1899 | |
| 1900 | /** vs and hs sync polarity */ |
| 1901 | #define DP_SYNC_VS_HIGH (1 << 4) |
| 1902 | #define DP_SYNC_HS_HIGH (1 << 3) |
| 1903 | |
| 1904 | /** A fantasy */ |
| 1905 | #define DP_DETECTED (1 << 2) |
| 1906 | |
| 1907 | /** The aux channel provides a way to talk to the |
| 1908 | * signal sink for DDC etc. Max packet size supported |
| 1909 | * is 20 bytes in each direction, hence the 5 fixed |
| 1910 | * data registers |
| 1911 | */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1912 | #define DPA_AUX_CH_CTL 0x64010 |
| 1913 | #define DPA_AUX_CH_DATA1 0x64014 |
| 1914 | #define DPA_AUX_CH_DATA2 0x64018 |
| 1915 | #define DPA_AUX_CH_DATA3 0x6401c |
| 1916 | #define DPA_AUX_CH_DATA4 0x64020 |
| 1917 | #define DPA_AUX_CH_DATA5 0x64024 |
| 1918 | |
Keith Packard | 040d87f | 2009-05-30 20:42:33 -0700 | [diff] [blame] | 1919 | #define DPB_AUX_CH_CTL 0x64110 |
| 1920 | #define DPB_AUX_CH_DATA1 0x64114 |
| 1921 | #define DPB_AUX_CH_DATA2 0x64118 |
| 1922 | #define DPB_AUX_CH_DATA3 0x6411c |
| 1923 | #define DPB_AUX_CH_DATA4 0x64120 |
| 1924 | #define DPB_AUX_CH_DATA5 0x64124 |
| 1925 | |
| 1926 | #define DPC_AUX_CH_CTL 0x64210 |
| 1927 | #define DPC_AUX_CH_DATA1 0x64214 |
| 1928 | #define DPC_AUX_CH_DATA2 0x64218 |
| 1929 | #define DPC_AUX_CH_DATA3 0x6421c |
| 1930 | #define DPC_AUX_CH_DATA4 0x64220 |
| 1931 | #define DPC_AUX_CH_DATA5 0x64224 |
| 1932 | |
| 1933 | #define DPD_AUX_CH_CTL 0x64310 |
| 1934 | #define DPD_AUX_CH_DATA1 0x64314 |
| 1935 | #define DPD_AUX_CH_DATA2 0x64318 |
| 1936 | #define DPD_AUX_CH_DATA3 0x6431c |
| 1937 | #define DPD_AUX_CH_DATA4 0x64320 |
| 1938 | #define DPD_AUX_CH_DATA5 0x64324 |
| 1939 | |
| 1940 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) |
| 1941 | #define DP_AUX_CH_CTL_DONE (1 << 30) |
| 1942 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) |
| 1943 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) |
| 1944 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) |
| 1945 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) |
| 1946 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) |
| 1947 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) |
| 1948 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) |
| 1949 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) |
| 1950 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) |
| 1951 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 |
| 1952 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) |
| 1953 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 |
| 1954 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) |
| 1955 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) |
| 1956 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) |
| 1957 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) |
| 1958 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) |
| 1959 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) |
| 1960 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 |
| 1961 | |
| 1962 | /* |
| 1963 | * Computing GMCH M and N values for the Display Port link |
| 1964 | * |
| 1965 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes |
| 1966 | * |
| 1967 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) |
| 1968 | * |
| 1969 | * The GMCH value is used internally |
| 1970 | * |
| 1971 | * bytes_per_pixel is the number of bytes coming out of the plane, |
| 1972 | * which is after the LUTs, so we want the bytes for our color format. |
| 1973 | * For our current usage, this is always 3, one byte for R, G and B. |
| 1974 | */ |
| 1975 | #define PIPEA_GMCH_DATA_M 0x70050 |
| 1976 | #define PIPEB_GMCH_DATA_M 0x71050 |
| 1977 | |
| 1978 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ |
| 1979 | #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) |
| 1980 | #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 |
| 1981 | |
| 1982 | #define PIPE_GMCH_DATA_M_MASK (0xffffff) |
| 1983 | |
| 1984 | #define PIPEA_GMCH_DATA_N 0x70054 |
| 1985 | #define PIPEB_GMCH_DATA_N 0x71054 |
| 1986 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
| 1987 | |
| 1988 | /* |
| 1989 | * Computing Link M and N values for the Display Port link |
| 1990 | * |
| 1991 | * Link M / N = pixel_clock / ls_clk |
| 1992 | * |
| 1993 | * (the DP spec calls pixel_clock the 'strm_clk') |
| 1994 | * |
| 1995 | * The Link value is transmitted in the Main Stream |
| 1996 | * Attributes and VB-ID. |
| 1997 | */ |
| 1998 | |
| 1999 | #define PIPEA_DP_LINK_M 0x70060 |
| 2000 | #define PIPEB_DP_LINK_M 0x71060 |
| 2001 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
| 2002 | |
| 2003 | #define PIPEA_DP_LINK_N 0x70064 |
| 2004 | #define PIPEB_DP_LINK_N 0x71064 |
| 2005 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
| 2006 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2007 | /* Display & cursor control */ |
| 2008 | |
Zhao Yakui | 898822c | 2010-01-04 16:29:30 +0800 | [diff] [blame] | 2009 | /* dithering flag on Ironlake */ |
Adam Jackson | 0a31a44 | 2010-04-19 15:57:25 -0400 | [diff] [blame] | 2010 | #define PIPE_ENABLE_DITHER (1 << 4) |
| 2011 | #define PIPE_DITHER_TYPE_MASK (3 << 2) |
| 2012 | #define PIPE_DITHER_TYPE_SPATIAL (0 << 2) |
| 2013 | #define PIPE_DITHER_TYPE_ST01 (1 << 2) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2014 | /* Pipe A */ |
| 2015 | #define PIPEADSL 0x70000 |
| 2016 | #define PIPEACONF 0x70008 |
| 2017 | #define PIPEACONF_ENABLE (1<<31) |
| 2018 | #define PIPEACONF_DISABLE 0 |
| 2019 | #define PIPEACONF_DOUBLE_WIDE (1<<30) |
| 2020 | #define I965_PIPECONF_ACTIVE (1<<30) |
| 2021 | #define PIPEACONF_SINGLE_WIDE 0 |
| 2022 | #define PIPEACONF_PIPE_UNLOCKED 0 |
| 2023 | #define PIPEACONF_PIPE_LOCKED (1<<25) |
| 2024 | #define PIPEACONF_PALETTE 0 |
| 2025 | #define PIPEACONF_GAMMA (1<<24) |
| 2026 | #define PIPECONF_FORCE_BORDER (1<<25) |
| 2027 | #define PIPECONF_PROGRESSIVE (0 << 21) |
| 2028 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) |
| 2029 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2030 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2031 | #define PIPEASTAT 0x70024 |
| 2032 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
| 2033 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
| 2034 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
| 2035 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
| 2036 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
| 2037 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
| 2038 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
| 2039 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
| 2040 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
| 2041 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
| 2042 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
| 2043 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
| 2044 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
| 2045 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
| 2046 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
| 2047 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
| 2048 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
| 2049 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
| 2050 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
| 2051 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
| 2052 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
| 2053 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) |
| 2054 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
| 2055 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
| 2056 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) |
| 2057 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
| 2058 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ |
| 2059 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
| 2060 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
Zhenyu Wang | 58a2747 | 2009-09-25 08:01:28 +0000 | [diff] [blame] | 2061 | #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ |
| 2062 | #define PIPE_8BPC (0 << 5) |
| 2063 | #define PIPE_10BPC (1 << 5) |
| 2064 | #define PIPE_6BPC (2 << 5) |
| 2065 | #define PIPE_12BPC (3 << 5) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2066 | |
| 2067 | #define DSPARB 0x70030 |
| 2068 | #define DSPARB_CSTART_MASK (0x7f << 7) |
| 2069 | #define DSPARB_CSTART_SHIFT 7 |
| 2070 | #define DSPARB_BSTART_MASK (0x7f) |
| 2071 | #define DSPARB_BSTART_SHIFT 0 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2072 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
| 2073 | #define DSPARB_AEND_SHIFT 0 |
| 2074 | |
| 2075 | #define DSPFW1 0x70034 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2076 | #define DSPFW_SR_SHIFT 23 |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2077 | #define DSPFW_SR_MASK (0x1ff<<23) |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2078 | #define DSPFW_CURSORB_SHIFT 16 |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2079 | #define DSPFW_CURSORB_MASK (0x3f<<16) |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2080 | #define DSPFW_PLANEB_SHIFT 8 |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2081 | #define DSPFW_PLANEB_MASK (0x7f<<8) |
| 2082 | #define DSPFW_PLANEA_MASK (0x7f) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2083 | #define DSPFW2 0x70038 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2084 | #define DSPFW_CURSORA_MASK 0x00003f00 |
Zhao Yakui | 21bd770 | 2010-01-13 14:10:50 +0000 | [diff] [blame] | 2085 | #define DSPFW_CURSORA_SHIFT 8 |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2086 | #define DSPFW_PLANEC_MASK (0x7f) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2087 | #define DSPFW3 0x7003c |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2088 | #define DSPFW_HPLL_SR_EN (1<<31) |
| 2089 | #define DSPFW_CURSOR_SR_SHIFT 24 |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2090 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
Zhao Yakui | d429434 | 2010-03-22 22:45:36 +0800 | [diff] [blame] | 2091 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
| 2092 | #define DSPFW_HPLL_CURSOR_SHIFT 16 |
| 2093 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) |
| 2094 | #define DSPFW_HPLL_SR_MASK (0x1ff) |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2095 | |
| 2096 | /* FIFO watermark sizes etc */ |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2097 | #define G4X_FIFO_LINE_SIZE 64 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2098 | #define I915_FIFO_LINE_SIZE 64 |
| 2099 | #define I830_FIFO_LINE_SIZE 32 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2100 | |
| 2101 | #define G4X_FIFO_SIZE 127 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2102 | #define I945_FIFO_SIZE 127 /* 945 & 965 */ |
| 2103 | #define I915_FIFO_SIZE 95 |
Jesse Barnes | dff33cf | 2009-07-14 10:15:56 -0700 | [diff] [blame] | 2104 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2105 | #define I830_FIFO_SIZE 95 |
Jesse Barnes | 0e442c6 | 2009-10-19 10:09:33 +0900 | [diff] [blame] | 2106 | |
| 2107 | #define G4X_MAX_WM 0x3f |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2108 | #define I915_MAX_WM 0x3f |
| 2109 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2110 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
| 2111 | #define PINEVIEW_FIFO_LINE_SIZE 64 |
| 2112 | #define PINEVIEW_MAX_WM 0x1ff |
| 2113 | #define PINEVIEW_DFT_WM 0x3f |
| 2114 | #define PINEVIEW_DFT_HPLLOFF_WM 0 |
| 2115 | #define PINEVIEW_GUARD_WM 10 |
| 2116 | #define PINEVIEW_CURSOR_FIFO 64 |
| 2117 | #define PINEVIEW_CURSOR_MAX_WM 0x3f |
| 2118 | #define PINEVIEW_CURSOR_DFT_WM 0 |
| 2119 | #define PINEVIEW_CURSOR_GUARD_WM 5 |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 2120 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2121 | |
| 2122 | /* define the Watermark register on Ironlake */ |
| 2123 | #define WM0_PIPEA_ILK 0x45100 |
| 2124 | #define WM0_PIPE_PLANE_MASK (0x7f<<16) |
| 2125 | #define WM0_PIPE_PLANE_SHIFT 16 |
| 2126 | #define WM0_PIPE_SPRITE_MASK (0x3f<<8) |
| 2127 | #define WM0_PIPE_SPRITE_SHIFT 8 |
| 2128 | #define WM0_PIPE_CURSOR_MASK (0x1f) |
| 2129 | |
| 2130 | #define WM0_PIPEB_ILK 0x45104 |
| 2131 | #define WM1_LP_ILK 0x45108 |
| 2132 | #define WM1_LP_SR_EN (1<<31) |
| 2133 | #define WM1_LP_LATENCY_SHIFT 24 |
| 2134 | #define WM1_LP_LATENCY_MASK (0x7f<<24) |
| 2135 | #define WM1_LP_SR_MASK (0x1ff<<8) |
| 2136 | #define WM1_LP_SR_SHIFT 8 |
| 2137 | #define WM1_LP_CURSOR_MASK (0x3f) |
| 2138 | |
| 2139 | /* Memory latency timer register */ |
| 2140 | #define MLTR_ILK 0x11222 |
| 2141 | /* the unit of memory self-refresh latency time is 0.5us */ |
| 2142 | #define ILK_SRLT_MASK 0x3f |
| 2143 | |
| 2144 | /* define the fifo size on Ironlake */ |
| 2145 | #define ILK_DISPLAY_FIFO 128 |
| 2146 | #define ILK_DISPLAY_MAXWM 64 |
| 2147 | #define ILK_DISPLAY_DFTWM 8 |
| 2148 | |
| 2149 | #define ILK_DISPLAY_SR_FIFO 512 |
| 2150 | #define ILK_DISPLAY_MAX_SRWM 0x1ff |
| 2151 | #define ILK_DISPLAY_DFT_SRWM 0x3f |
| 2152 | #define ILK_CURSOR_SR_FIFO 64 |
| 2153 | #define ILK_CURSOR_MAX_SRWM 0x3f |
| 2154 | #define ILK_CURSOR_DFT_SRWM 8 |
| 2155 | |
| 2156 | #define ILK_FIFO_LINE_SIZE 64 |
| 2157 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2158 | /* |
| 2159 | * The two pipe frame counter registers are not synchronized, so |
| 2160 | * reading a stable value is somewhat tricky. The following code |
| 2161 | * should work: |
| 2162 | * |
| 2163 | * do { |
| 2164 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
| 2165 | * PIPE_FRAME_HIGH_SHIFT; |
| 2166 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> |
| 2167 | * PIPE_FRAME_LOW_SHIFT); |
| 2168 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> |
| 2169 | * PIPE_FRAME_HIGH_SHIFT); |
| 2170 | * } while (high1 != high2); |
| 2171 | * frame = (high1 << 8) | low1; |
| 2172 | */ |
| 2173 | #define PIPEAFRAMEHIGH 0x70040 |
| 2174 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
| 2175 | #define PIPE_FRAME_HIGH_SHIFT 0 |
| 2176 | #define PIPEAFRAMEPIXEL 0x70044 |
| 2177 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
| 2178 | #define PIPE_FRAME_LOW_SHIFT 24 |
| 2179 | #define PIPE_PIXEL_MASK 0x00ffffff |
| 2180 | #define PIPE_PIXEL_SHIFT 0 |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 2181 | /* GM45+ just has to be different */ |
| 2182 | #define PIPEA_FRMCOUNT_GM45 0x70040 |
| 2183 | #define PIPEA_FLIPCOUNT_GM45 0x70044 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2184 | |
| 2185 | /* Cursor A & B regs */ |
| 2186 | #define CURACNTR 0x70080 |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 2187 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
| 2188 | #define CURSOR_ENABLE 0x80000000 |
| 2189 | #define CURSOR_GAMMA_ENABLE 0x40000000 |
| 2190 | #define CURSOR_STRIDE_MASK 0x30000000 |
| 2191 | #define CURSOR_FORMAT_SHIFT 24 |
| 2192 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) |
| 2193 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) |
| 2194 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) |
| 2195 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) |
| 2196 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) |
| 2197 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) |
| 2198 | /* New style CUR*CNTR flags */ |
| 2199 | #define CURSOR_MODE 0x27 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2200 | #define CURSOR_MODE_DISABLE 0x00 |
| 2201 | #define CURSOR_MODE_64_32B_AX 0x07 |
| 2202 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 2203 | #define MCURSOR_PIPE_SELECT (1 << 28) |
| 2204 | #define MCURSOR_PIPE_A 0x00 |
| 2205 | #define MCURSOR_PIPE_B (1 << 28) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2206 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
| 2207 | #define CURABASE 0x70084 |
| 2208 | #define CURAPOS 0x70088 |
| 2209 | #define CURSOR_POS_MASK 0x007FF |
| 2210 | #define CURSOR_POS_SIGN 0x8000 |
| 2211 | #define CURSOR_X_SHIFT 0 |
| 2212 | #define CURSOR_Y_SHIFT 16 |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 2213 | #define CURSIZE 0x700a0 |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2214 | #define CURBCNTR 0x700c0 |
| 2215 | #define CURBBASE 0x700c4 |
| 2216 | #define CURBPOS 0x700c8 |
| 2217 | |
| 2218 | /* Display A control */ |
| 2219 | #define DSPACNTR 0x70180 |
| 2220 | #define DISPLAY_PLANE_ENABLE (1<<31) |
| 2221 | #define DISPLAY_PLANE_DISABLE 0 |
| 2222 | #define DISPPLANE_GAMMA_ENABLE (1<<30) |
| 2223 | #define DISPPLANE_GAMMA_DISABLE 0 |
| 2224 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
| 2225 | #define DISPPLANE_8BPP (0x2<<26) |
| 2226 | #define DISPPLANE_15_16BPP (0x4<<26) |
| 2227 | #define DISPPLANE_16BPP (0x5<<26) |
| 2228 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) |
| 2229 | #define DISPPLANE_32BPP (0x7<<26) |
Kristian Høgsberg | a4f45cf | 2009-10-19 14:35:30 -0400 | [diff] [blame] | 2230 | #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2231 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
| 2232 | #define DISPPLANE_STEREO_DISABLE 0 |
| 2233 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) |
| 2234 | #define DISPPLANE_SEL_PIPE_A 0 |
| 2235 | #define DISPPLANE_SEL_PIPE_B (1<<24) |
| 2236 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
| 2237 | #define DISPPLANE_SRC_KEY_DISABLE 0 |
| 2238 | #define DISPPLANE_LINE_DOUBLE (1<<20) |
| 2239 | #define DISPPLANE_NO_LINE_DOUBLE 0 |
| 2240 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 |
| 2241 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2242 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
Jesse Barnes | f544847 | 2009-04-14 14:17:47 -0700 | [diff] [blame] | 2243 | #define DISPPLANE_TILED (1<<10) |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2244 | #define DSPAADDR 0x70184 |
| 2245 | #define DSPASTRIDE 0x70188 |
| 2246 | #define DSPAPOS 0x7018C /* reserved */ |
| 2247 | #define DSPASIZE 0x70190 |
| 2248 | #define DSPASURF 0x7019C /* 965+ only */ |
| 2249 | #define DSPATILEOFF 0x701A4 /* 965+ only */ |
| 2250 | |
| 2251 | /* VBIOS flags */ |
| 2252 | #define SWF00 0x71410 |
| 2253 | #define SWF01 0x71414 |
| 2254 | #define SWF02 0x71418 |
| 2255 | #define SWF03 0x7141c |
| 2256 | #define SWF04 0x71420 |
| 2257 | #define SWF05 0x71424 |
| 2258 | #define SWF06 0x71428 |
| 2259 | #define SWF10 0x70410 |
| 2260 | #define SWF11 0x70414 |
| 2261 | #define SWF14 0x71420 |
| 2262 | #define SWF30 0x72414 |
| 2263 | #define SWF31 0x72418 |
| 2264 | #define SWF32 0x7241c |
| 2265 | |
| 2266 | /* Pipe B */ |
| 2267 | #define PIPEBDSL 0x71000 |
| 2268 | #define PIPEBCONF 0x71008 |
| 2269 | #define PIPEBSTAT 0x71024 |
| 2270 | #define PIPEBFRAMEHIGH 0x71040 |
| 2271 | #define PIPEBFRAMEPIXEL 0x71044 |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 2272 | #define PIPEB_FRMCOUNT_GM45 0x71040 |
| 2273 | #define PIPEB_FLIPCOUNT_GM45 0x71044 |
| 2274 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2275 | |
| 2276 | /* Display B control */ |
| 2277 | #define DSPBCNTR 0x71180 |
| 2278 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
| 2279 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 |
| 2280 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 |
| 2281 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) |
| 2282 | #define DSPBADDR 0x71184 |
| 2283 | #define DSPBSTRIDE 0x71188 |
| 2284 | #define DSPBPOS 0x7118C |
| 2285 | #define DSPBSIZE 0x71190 |
| 2286 | #define DSPBSURF 0x7119C |
| 2287 | #define DSPBTILEOFF 0x711A4 |
| 2288 | |
| 2289 | /* VBIOS regs */ |
| 2290 | #define VGACNTRL 0x71400 |
| 2291 | # define VGA_DISP_DISABLE (1 << 31) |
| 2292 | # define VGA_2X_MODE (1 << 30) |
| 2293 | # define VGA_PIPE_B_SELECT (1 << 29) |
| 2294 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2295 | /* Ironlake */ |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2296 | |
| 2297 | #define CPU_VGACNTRL 0x41000 |
| 2298 | |
| 2299 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 |
| 2300 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) |
| 2301 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) |
| 2302 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) |
| 2303 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) |
| 2304 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) |
| 2305 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) |
| 2306 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) |
| 2307 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) |
| 2308 | |
| 2309 | /* refresh rate hardware control */ |
| 2310 | #define RR_HW_CTL 0x45300 |
| 2311 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff |
| 2312 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 |
| 2313 | |
| 2314 | #define FDI_PLL_BIOS_0 0x46000 |
| 2315 | #define FDI_PLL_BIOS_1 0x46004 |
| 2316 | #define FDI_PLL_BIOS_2 0x46008 |
| 2317 | #define DISPLAY_PORT_PLL_BIOS_0 0x4600c |
| 2318 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
| 2319 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
| 2320 | |
Eric Anholt | 8956c8b | 2010-03-18 13:21:14 -0700 | [diff] [blame] | 2321 | #define PCH_DSPCLK_GATE_D 0x42020 |
| 2322 | # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) |
| 2323 | # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
| 2324 | |
| 2325 | #define PCH_3DCGDIS0 0x46020 |
| 2326 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
| 2327 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
| 2328 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2329 | #define FDI_PLL_FREQ_CTL 0x46030 |
| 2330 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
| 2331 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |
| 2332 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff |
| 2333 | |
| 2334 | |
| 2335 | #define PIPEA_DATA_M1 0x60030 |
| 2336 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
| 2337 | #define TU_SIZE_MASK 0x7e000000 |
| 2338 | #define PIPEA_DATA_M1_OFFSET 0 |
| 2339 | #define PIPEA_DATA_N1 0x60034 |
| 2340 | #define PIPEA_DATA_N1_OFFSET 0 |
| 2341 | |
| 2342 | #define PIPEA_DATA_M2 0x60038 |
| 2343 | #define PIPEA_DATA_M2_OFFSET 0 |
| 2344 | #define PIPEA_DATA_N2 0x6003c |
| 2345 | #define PIPEA_DATA_N2_OFFSET 0 |
| 2346 | |
| 2347 | #define PIPEA_LINK_M1 0x60040 |
| 2348 | #define PIPEA_LINK_M1_OFFSET 0 |
| 2349 | #define PIPEA_LINK_N1 0x60044 |
| 2350 | #define PIPEA_LINK_N1_OFFSET 0 |
| 2351 | |
| 2352 | #define PIPEA_LINK_M2 0x60048 |
| 2353 | #define PIPEA_LINK_M2_OFFSET 0 |
| 2354 | #define PIPEA_LINK_N2 0x6004c |
| 2355 | #define PIPEA_LINK_N2_OFFSET 0 |
| 2356 | |
| 2357 | /* PIPEB timing regs are same start from 0x61000 */ |
| 2358 | |
| 2359 | #define PIPEB_DATA_M1 0x61030 |
| 2360 | #define PIPEB_DATA_M1_OFFSET 0 |
| 2361 | #define PIPEB_DATA_N1 0x61034 |
| 2362 | #define PIPEB_DATA_N1_OFFSET 0 |
| 2363 | |
| 2364 | #define PIPEB_DATA_M2 0x61038 |
| 2365 | #define PIPEB_DATA_M2_OFFSET 0 |
| 2366 | #define PIPEB_DATA_N2 0x6103c |
| 2367 | #define PIPEB_DATA_N2_OFFSET 0 |
| 2368 | |
| 2369 | #define PIPEB_LINK_M1 0x61040 |
| 2370 | #define PIPEB_LINK_M1_OFFSET 0 |
| 2371 | #define PIPEB_LINK_N1 0x61044 |
| 2372 | #define PIPEB_LINK_N1_OFFSET 0 |
| 2373 | |
| 2374 | #define PIPEB_LINK_M2 0x61048 |
| 2375 | #define PIPEB_LINK_M2_OFFSET 0 |
| 2376 | #define PIPEB_LINK_N2 0x6104c |
| 2377 | #define PIPEB_LINK_N2_OFFSET 0 |
| 2378 | |
| 2379 | /* CPU panel fitter */ |
| 2380 | #define PFA_CTL_1 0x68080 |
| 2381 | #define PFB_CTL_1 0x68880 |
| 2382 | #define PF_ENABLE (1<<31) |
Zhenyu Wang | b1f60b7 | 2009-10-19 15:43:49 +0800 | [diff] [blame] | 2383 | #define PF_FILTER_MASK (3<<23) |
| 2384 | #define PF_FILTER_PROGRAMMED (0<<23) |
| 2385 | #define PF_FILTER_MED_3x3 (1<<23) |
| 2386 | #define PF_FILTER_EDGE_ENHANCE (2<<23) |
| 2387 | #define PF_FILTER_EDGE_SOFTEN (3<<23) |
Zhenyu Wang | 249c0e6 | 2009-07-24 01:00:29 +0800 | [diff] [blame] | 2388 | #define PFA_WIN_SZ 0x68074 |
| 2389 | #define PFB_WIN_SZ 0x68874 |
Zhenyu Wang | 8dd81a3 | 2009-09-19 14:54:09 +0800 | [diff] [blame] | 2390 | #define PFA_WIN_POS 0x68070 |
| 2391 | #define PFB_WIN_POS 0x68870 |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2392 | |
| 2393 | /* legacy palette */ |
| 2394 | #define LGC_PALETTE_A 0x4a000 |
| 2395 | #define LGC_PALETTE_B 0x4a800 |
| 2396 | |
| 2397 | /* interrupts */ |
| 2398 | #define DE_MASTER_IRQ_CONTROL (1 << 31) |
| 2399 | #define DE_SPRITEB_FLIP_DONE (1 << 29) |
| 2400 | #define DE_SPRITEA_FLIP_DONE (1 << 28) |
| 2401 | #define DE_PLANEB_FLIP_DONE (1 << 27) |
| 2402 | #define DE_PLANEA_FLIP_DONE (1 << 26) |
| 2403 | #define DE_PCU_EVENT (1 << 25) |
| 2404 | #define DE_GTT_FAULT (1 << 24) |
| 2405 | #define DE_POISON (1 << 23) |
| 2406 | #define DE_PERFORM_COUNTER (1 << 22) |
| 2407 | #define DE_PCH_EVENT (1 << 21) |
| 2408 | #define DE_AUX_CHANNEL_A (1 << 20) |
| 2409 | #define DE_DP_A_HOTPLUG (1 << 19) |
| 2410 | #define DE_GSE (1 << 18) |
| 2411 | #define DE_PIPEB_VBLANK (1 << 15) |
| 2412 | #define DE_PIPEB_EVEN_FIELD (1 << 14) |
| 2413 | #define DE_PIPEB_ODD_FIELD (1 << 13) |
| 2414 | #define DE_PIPEB_LINE_COMPARE (1 << 12) |
| 2415 | #define DE_PIPEB_VSYNC (1 << 11) |
| 2416 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
| 2417 | #define DE_PIPEA_VBLANK (1 << 7) |
| 2418 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
| 2419 | #define DE_PIPEA_ODD_FIELD (1 << 5) |
| 2420 | #define DE_PIPEA_LINE_COMPARE (1 << 4) |
| 2421 | #define DE_PIPEA_VSYNC (1 << 3) |
| 2422 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
| 2423 | |
| 2424 | #define DEISR 0x44000 |
| 2425 | #define DEIMR 0x44004 |
| 2426 | #define DEIIR 0x44008 |
| 2427 | #define DEIER 0x4400c |
| 2428 | |
| 2429 | /* GT interrupt */ |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 2430 | #define GT_PIPE_NOTIFY (1 << 4) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2431 | #define GT_SYNC_STATUS (1 << 2) |
| 2432 | #define GT_USER_INTERRUPT (1 << 0) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2433 | #define GT_BSD_USER_INTERRUPT (1 << 5) |
| 2434 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2435 | |
| 2436 | #define GTISR 0x44010 |
| 2437 | #define GTIMR 0x44014 |
| 2438 | #define GTIIR 0x44018 |
| 2439 | #define GTIER 0x4401c |
| 2440 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2441 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
| 2442 | #define ILK_DPARB_GATE (1<<22) |
| 2443 | #define ILK_VSDPFD_FULL (1<<21) |
| 2444 | #define ILK_DSPCLK_GATE 0x42020 |
| 2445 | #define ILK_DPARB_CLK_GATE (1<<5) |
| 2446 | |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 2447 | #define DISP_ARB_CTL 0x45000 |
| 2448 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 2449 | #define DISP_FBC_WM_DIS (1<<15) |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 2450 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2451 | /* PCH */ |
| 2452 | |
| 2453 | /* south display engine interrupt */ |
| 2454 | #define SDE_CRT_HOTPLUG (1 << 11) |
| 2455 | #define SDE_PORTD_HOTPLUG (1 << 10) |
| 2456 | #define SDE_PORTC_HOTPLUG (1 << 9) |
| 2457 | #define SDE_PORTB_HOTPLUG (1 << 8) |
| 2458 | #define SDE_SDVOB_HOTPLUG (1 << 6) |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 2459 | #define SDE_HOTPLUG_MASK (0xf << 8) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2460 | /* CPT */ |
| 2461 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
| 2462 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
| 2463 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) |
| 2464 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2465 | |
| 2466 | #define SDEISR 0xc4000 |
| 2467 | #define SDEIMR 0xc4004 |
| 2468 | #define SDEIIR 0xc4008 |
| 2469 | #define SDEIER 0xc400c |
| 2470 | |
| 2471 | /* digital port hotplug */ |
| 2472 | #define PCH_PORT_HOTPLUG 0xc4030 |
| 2473 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
| 2474 | #define PORTD_PULSE_DURATION_2ms (0) |
| 2475 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) |
| 2476 | #define PORTD_PULSE_DURATION_6ms (2 << 18) |
| 2477 | #define PORTD_PULSE_DURATION_100ms (3 << 18) |
| 2478 | #define PORTD_HOTPLUG_NO_DETECT (0) |
| 2479 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) |
| 2480 | #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) |
| 2481 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
| 2482 | #define PORTC_PULSE_DURATION_2ms (0) |
| 2483 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) |
| 2484 | #define PORTC_PULSE_DURATION_6ms (2 << 10) |
| 2485 | #define PORTC_PULSE_DURATION_100ms (3 << 10) |
| 2486 | #define PORTC_HOTPLUG_NO_DETECT (0) |
| 2487 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) |
| 2488 | #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) |
| 2489 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
| 2490 | #define PORTB_PULSE_DURATION_2ms (0) |
| 2491 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) |
| 2492 | #define PORTB_PULSE_DURATION_6ms (2 << 2) |
| 2493 | #define PORTB_PULSE_DURATION_100ms (3 << 2) |
| 2494 | #define PORTB_HOTPLUG_NO_DETECT (0) |
| 2495 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) |
| 2496 | #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) |
| 2497 | |
| 2498 | #define PCH_GPIOA 0xc5010 |
| 2499 | #define PCH_GPIOB 0xc5014 |
| 2500 | #define PCH_GPIOC 0xc5018 |
| 2501 | #define PCH_GPIOD 0xc501c |
| 2502 | #define PCH_GPIOE 0xc5020 |
| 2503 | #define PCH_GPIOF 0xc5024 |
| 2504 | |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 2505 | #define PCH_GMBUS0 0xc5100 |
| 2506 | #define PCH_GMBUS1 0xc5104 |
| 2507 | #define PCH_GMBUS2 0xc5108 |
| 2508 | #define PCH_GMBUS3 0xc510c |
| 2509 | #define PCH_GMBUS4 0xc5110 |
| 2510 | #define PCH_GMBUS5 0xc5120 |
| 2511 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2512 | #define PCH_DPLL_A 0xc6014 |
| 2513 | #define PCH_DPLL_B 0xc6018 |
| 2514 | |
| 2515 | #define PCH_FPA0 0xc6040 |
| 2516 | #define PCH_FPA1 0xc6044 |
| 2517 | #define PCH_FPB0 0xc6048 |
| 2518 | #define PCH_FPB1 0xc604c |
| 2519 | |
| 2520 | #define PCH_DPLL_TEST 0xc606c |
| 2521 | |
| 2522 | #define PCH_DREF_CONTROL 0xC6200 |
| 2523 | #define DREF_CONTROL_MASK 0x7fc3 |
| 2524 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) |
| 2525 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) |
| 2526 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) |
| 2527 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) |
| 2528 | #define DREF_SSC_SOURCE_DISABLE (0<<11) |
| 2529 | #define DREF_SSC_SOURCE_ENABLE (2<<11) |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 2530 | #define DREF_SSC_SOURCE_MASK (3<<11) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2531 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
| 2532 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) |
| 2533 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) |
Zhenyu Wang | c038e51 | 2009-10-19 15:43:48 +0800 | [diff] [blame] | 2534 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2535 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
| 2536 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) |
| 2537 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
| 2538 | #define DREF_SSC4_CENTERSPREAD (1<<6) |
| 2539 | #define DREF_SSC1_DISABLE (0<<1) |
| 2540 | #define DREF_SSC1_ENABLE (1<<1) |
| 2541 | #define DREF_SSC4_DISABLE (0) |
| 2542 | #define DREF_SSC4_ENABLE (1) |
| 2543 | |
| 2544 | #define PCH_RAWCLK_FREQ 0xc6204 |
| 2545 | #define FDL_TP1_TIMER_SHIFT 12 |
| 2546 | #define FDL_TP1_TIMER_MASK (3<<12) |
| 2547 | #define FDL_TP2_TIMER_SHIFT 10 |
| 2548 | #define FDL_TP2_TIMER_MASK (3<<10) |
| 2549 | #define RAWCLK_FREQ_MASK 0x3ff |
| 2550 | |
| 2551 | #define PCH_DPLL_TMR_CFG 0xc6208 |
| 2552 | |
| 2553 | #define PCH_SSC4_PARMS 0xc6210 |
| 2554 | #define PCH_SSC4_AUX_PARMS 0xc6214 |
| 2555 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2556 | #define PCH_DPLL_SEL 0xc7000 |
| 2557 | #define TRANSA_DPLL_ENABLE (1<<3) |
| 2558 | #define TRANSA_DPLLB_SEL (1<<0) |
| 2559 | #define TRANSA_DPLLA_SEL 0 |
| 2560 | #define TRANSB_DPLL_ENABLE (1<<7) |
| 2561 | #define TRANSB_DPLLB_SEL (1<<4) |
| 2562 | #define TRANSB_DPLLA_SEL (0) |
| 2563 | #define TRANSC_DPLL_ENABLE (1<<11) |
| 2564 | #define TRANSC_DPLLB_SEL (1<<8) |
| 2565 | #define TRANSC_DPLLA_SEL (0) |
| 2566 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2567 | /* transcoder */ |
| 2568 | |
| 2569 | #define TRANS_HTOTAL_A 0xe0000 |
| 2570 | #define TRANS_HTOTAL_SHIFT 16 |
| 2571 | #define TRANS_HACTIVE_SHIFT 0 |
| 2572 | #define TRANS_HBLANK_A 0xe0004 |
| 2573 | #define TRANS_HBLANK_END_SHIFT 16 |
| 2574 | #define TRANS_HBLANK_START_SHIFT 0 |
| 2575 | #define TRANS_HSYNC_A 0xe0008 |
| 2576 | #define TRANS_HSYNC_END_SHIFT 16 |
| 2577 | #define TRANS_HSYNC_START_SHIFT 0 |
| 2578 | #define TRANS_VTOTAL_A 0xe000c |
| 2579 | #define TRANS_VTOTAL_SHIFT 16 |
| 2580 | #define TRANS_VACTIVE_SHIFT 0 |
| 2581 | #define TRANS_VBLANK_A 0xe0010 |
| 2582 | #define TRANS_VBLANK_END_SHIFT 16 |
| 2583 | #define TRANS_VBLANK_START_SHIFT 0 |
| 2584 | #define TRANS_VSYNC_A 0xe0014 |
| 2585 | #define TRANS_VSYNC_END_SHIFT 16 |
| 2586 | #define TRANS_VSYNC_START_SHIFT 0 |
| 2587 | |
| 2588 | #define TRANSA_DATA_M1 0xe0030 |
| 2589 | #define TRANSA_DATA_N1 0xe0034 |
| 2590 | #define TRANSA_DATA_M2 0xe0038 |
| 2591 | #define TRANSA_DATA_N2 0xe003c |
| 2592 | #define TRANSA_DP_LINK_M1 0xe0040 |
| 2593 | #define TRANSA_DP_LINK_N1 0xe0044 |
| 2594 | #define TRANSA_DP_LINK_M2 0xe0048 |
| 2595 | #define TRANSA_DP_LINK_N2 0xe004c |
| 2596 | |
| 2597 | #define TRANS_HTOTAL_B 0xe1000 |
| 2598 | #define TRANS_HBLANK_B 0xe1004 |
| 2599 | #define TRANS_HSYNC_B 0xe1008 |
| 2600 | #define TRANS_VTOTAL_B 0xe100c |
| 2601 | #define TRANS_VBLANK_B 0xe1010 |
| 2602 | #define TRANS_VSYNC_B 0xe1014 |
| 2603 | |
| 2604 | #define TRANSB_DATA_M1 0xe1030 |
| 2605 | #define TRANSB_DATA_N1 0xe1034 |
| 2606 | #define TRANSB_DATA_M2 0xe1038 |
| 2607 | #define TRANSB_DATA_N2 0xe103c |
| 2608 | #define TRANSB_DP_LINK_M1 0xe1040 |
| 2609 | #define TRANSB_DP_LINK_N1 0xe1044 |
| 2610 | #define TRANSB_DP_LINK_M2 0xe1048 |
| 2611 | #define TRANSB_DP_LINK_N2 0xe104c |
| 2612 | |
| 2613 | #define TRANSACONF 0xf0008 |
| 2614 | #define TRANSBCONF 0xf1008 |
| 2615 | #define TRANS_DISABLE (0<<31) |
| 2616 | #define TRANS_ENABLE (1<<31) |
| 2617 | #define TRANS_STATE_MASK (1<<30) |
| 2618 | #define TRANS_STATE_DISABLE (0<<30) |
| 2619 | #define TRANS_STATE_ENABLE (1<<30) |
| 2620 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) |
| 2621 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) |
| 2622 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) |
| 2623 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) |
| 2624 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
| 2625 | #define TRANS_DP_VIDEO_AUDIO (0<<26) |
| 2626 | #define TRANS_PROGRESSIVE (0<<21) |
| 2627 | #define TRANS_8BPC (0<<5) |
| 2628 | #define TRANS_10BPC (1<<5) |
| 2629 | #define TRANS_6BPC (2<<5) |
| 2630 | #define TRANS_12BPC (3<<5) |
| 2631 | |
| 2632 | #define FDI_RXA_CHICKEN 0xc200c |
| 2633 | #define FDI_RXB_CHICKEN 0xc2010 |
| 2634 | #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) |
| 2635 | |
| 2636 | /* CPU: FDI_TX */ |
| 2637 | #define FDI_TXA_CTL 0x60100 |
| 2638 | #define FDI_TXB_CTL 0x61100 |
| 2639 | #define FDI_TX_DISABLE (0<<31) |
| 2640 | #define FDI_TX_ENABLE (1<<31) |
| 2641 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) |
| 2642 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) |
| 2643 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) |
| 2644 | #define FDI_LINK_TRAIN_NONE (3<<28) |
| 2645 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) |
| 2646 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) |
| 2647 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) |
| 2648 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) |
| 2649 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) |
| 2650 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) |
| 2651 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) |
| 2652 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2653 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
| 2654 | SNB has different settings. */ |
| 2655 | /* SNB A-stepping */ |
| 2656 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
| 2657 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
| 2658 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
| 2659 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
| 2660 | /* SNB B-stepping */ |
| 2661 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) |
| 2662 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) |
| 2663 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) |
| 2664 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) |
| 2665 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2666 | #define FDI_DP_PORT_WIDTH_X1 (0<<19) |
| 2667 | #define FDI_DP_PORT_WIDTH_X2 (1<<19) |
| 2668 | #define FDI_DP_PORT_WIDTH_X3 (2<<19) |
| 2669 | #define FDI_DP_PORT_WIDTH_X4 (3<<19) |
| 2670 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 2671 | /* Ironlake: hardwired to 1 */ |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2672 | #define FDI_TX_PLL_ENABLE (1<<14) |
| 2673 | /* both Tx and Rx */ |
| 2674 | #define FDI_SCRAMBLING_ENABLE (0<<7) |
| 2675 | #define FDI_SCRAMBLING_DISABLE (1<<7) |
| 2676 | |
| 2677 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ |
| 2678 | #define FDI_RXA_CTL 0xf000c |
| 2679 | #define FDI_RXB_CTL 0xf100c |
| 2680 | #define FDI_RX_ENABLE (1<<31) |
| 2681 | #define FDI_RX_DISABLE (0<<31) |
| 2682 | /* train, dp width same as FDI_TX */ |
| 2683 | #define FDI_DP_PORT_WIDTH_X8 (7<<19) |
| 2684 | #define FDI_8BPC (0<<16) |
| 2685 | #define FDI_10BPC (1<<16) |
| 2686 | #define FDI_6BPC (2<<16) |
| 2687 | #define FDI_12BPC (3<<16) |
| 2688 | #define FDI_LINK_REVERSE_OVERWRITE (1<<15) |
| 2689 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
| 2690 | #define FDI_RX_PLL_ENABLE (1<<13) |
| 2691 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) |
| 2692 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) |
| 2693 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) |
| 2694 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) |
| 2695 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) |
| 2696 | #define FDI_SEL_RAWCLK (0<<4) |
| 2697 | #define FDI_SEL_PCDCLK (1<<4) |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2698 | /* CPT */ |
| 2699 | #define FDI_AUTO_TRAINING (1<<10) |
| 2700 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) |
| 2701 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) |
| 2702 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) |
| 2703 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) |
| 2704 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2705 | |
| 2706 | #define FDI_RXA_MISC 0xf0010 |
| 2707 | #define FDI_RXB_MISC 0xf1010 |
| 2708 | #define FDI_RXA_TUSIZE1 0xf0030 |
| 2709 | #define FDI_RXA_TUSIZE2 0xf0038 |
| 2710 | #define FDI_RXB_TUSIZE1 0xf1030 |
| 2711 | #define FDI_RXB_TUSIZE2 0xf1038 |
| 2712 | |
| 2713 | /* FDI_RX interrupt register format */ |
| 2714 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) |
| 2715 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ |
| 2716 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ |
| 2717 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) |
| 2718 | #define FDI_RX_FS_CODE_ERR (1<<6) |
| 2719 | #define FDI_RX_FE_CODE_ERR (1<<5) |
| 2720 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) |
| 2721 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) |
| 2722 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) |
| 2723 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) |
| 2724 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) |
| 2725 | |
| 2726 | #define FDI_RXA_IIR 0xf0014 |
| 2727 | #define FDI_RXA_IMR 0xf0018 |
| 2728 | #define FDI_RXB_IIR 0xf1014 |
| 2729 | #define FDI_RXB_IMR 0xf1018 |
| 2730 | |
| 2731 | #define FDI_PLL_CTL_1 0xfe000 |
| 2732 | #define FDI_PLL_CTL_2 0xfe004 |
| 2733 | |
| 2734 | /* CRT */ |
| 2735 | #define PCH_ADPA 0xe1100 |
| 2736 | #define ADPA_TRANS_SELECT_MASK (1<<30) |
| 2737 | #define ADPA_TRANS_A_SELECT 0 |
| 2738 | #define ADPA_TRANS_B_SELECT (1<<30) |
| 2739 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ |
| 2740 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) |
| 2741 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) |
| 2742 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) |
| 2743 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) |
| 2744 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) |
| 2745 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) |
| 2746 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) |
| 2747 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) |
| 2748 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) |
| 2749 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) |
| 2750 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) |
| 2751 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) |
| 2752 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) |
| 2753 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) |
| 2754 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) |
| 2755 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) |
| 2756 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) |
| 2757 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) |
| 2758 | |
| 2759 | /* or SDVOB */ |
| 2760 | #define HDMIB 0xe1140 |
| 2761 | #define PORT_ENABLE (1 << 31) |
| 2762 | #define TRANSCODER_A (0) |
| 2763 | #define TRANSCODER_B (1 << 30) |
| 2764 | #define COLOR_FORMAT_8bpc (0) |
| 2765 | #define COLOR_FORMAT_12bpc (3 << 26) |
| 2766 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) |
| 2767 | #define SDVO_ENCODING (0) |
| 2768 | #define TMDS_ENCODING (2 << 10) |
| 2769 | #define NULL_PACKET_VSYNC_ENABLE (1 << 9) |
Zhenyu Wang | 467b200 | 2010-05-12 11:02:14 +0800 | [diff] [blame] | 2770 | /* CPT */ |
| 2771 | #define HDMI_MODE_SELECT (1 << 9) |
| 2772 | #define DVI_MODE_SELECT (0) |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2773 | #define SDVOB_BORDER_ENABLE (1 << 7) |
| 2774 | #define AUDIO_ENABLE (1 << 6) |
| 2775 | #define VSYNC_ACTIVE_HIGH (1 << 4) |
| 2776 | #define HSYNC_ACTIVE_HIGH (1 << 3) |
| 2777 | #define PORT_DETECTED (1 << 2) |
| 2778 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2779 | /* PCH SDVOB multiplex with HDMIB */ |
| 2780 | #define PCH_SDVOB HDMIB |
| 2781 | |
Zhenyu Wang | b905505 | 2009-06-05 15:38:38 +0800 | [diff] [blame] | 2782 | #define HDMIC 0xe1150 |
| 2783 | #define HDMID 0xe1160 |
| 2784 | |
| 2785 | #define PCH_LVDS 0xe1180 |
| 2786 | #define LVDS_DETECTED (1 << 1) |
| 2787 | |
| 2788 | #define BLC_PWM_CPU_CTL2 0x48250 |
| 2789 | #define PWM_ENABLE (1 << 31) |
| 2790 | #define PWM_PIPE_A (0 << 29) |
| 2791 | #define PWM_PIPE_B (1 << 29) |
| 2792 | #define BLC_PWM_CPU_CTL 0x48254 |
| 2793 | |
| 2794 | #define BLC_PWM_PCH_CTL1 0xc8250 |
| 2795 | #define PWM_PCH_ENABLE (1 << 31) |
| 2796 | #define PWM_POLARITY_ACTIVE_LOW (1 << 29) |
| 2797 | #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) |
| 2798 | #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) |
| 2799 | #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) |
| 2800 | |
| 2801 | #define BLC_PWM_PCH_CTL2 0xc8254 |
| 2802 | |
| 2803 | #define PCH_PP_STATUS 0xc7200 |
| 2804 | #define PCH_PP_CONTROL 0xc7204 |
| 2805 | #define EDP_FORCE_VDD (1 << 3) |
| 2806 | #define EDP_BLC_ENABLE (1 << 2) |
| 2807 | #define PANEL_POWER_RESET (1 << 1) |
| 2808 | #define PANEL_POWER_OFF (0 << 0) |
| 2809 | #define PANEL_POWER_ON (1 << 0) |
| 2810 | #define PCH_PP_ON_DELAYS 0xc7208 |
| 2811 | #define EDP_PANEL (1 << 30) |
| 2812 | #define PCH_PP_OFF_DELAYS 0xc720c |
| 2813 | #define PCH_PP_DIVISOR 0xc7210 |
| 2814 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2815 | #define PCH_DP_B 0xe4100 |
| 2816 | #define PCH_DPB_AUX_CH_CTL 0xe4110 |
| 2817 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 |
| 2818 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 |
| 2819 | #define PCH_DPB_AUX_CH_DATA3 0xe411c |
| 2820 | #define PCH_DPB_AUX_CH_DATA4 0xe4120 |
| 2821 | #define PCH_DPB_AUX_CH_DATA5 0xe4124 |
| 2822 | |
| 2823 | #define PCH_DP_C 0xe4200 |
| 2824 | #define PCH_DPC_AUX_CH_CTL 0xe4210 |
| 2825 | #define PCH_DPC_AUX_CH_DATA1 0xe4214 |
| 2826 | #define PCH_DPC_AUX_CH_DATA2 0xe4218 |
| 2827 | #define PCH_DPC_AUX_CH_DATA3 0xe421c |
| 2828 | #define PCH_DPC_AUX_CH_DATA4 0xe4220 |
| 2829 | #define PCH_DPC_AUX_CH_DATA5 0xe4224 |
| 2830 | |
| 2831 | #define PCH_DP_D 0xe4300 |
| 2832 | #define PCH_DPD_AUX_CH_CTL 0xe4310 |
| 2833 | #define PCH_DPD_AUX_CH_DATA1 0xe4314 |
| 2834 | #define PCH_DPD_AUX_CH_DATA2 0xe4318 |
| 2835 | #define PCH_DPD_AUX_CH_DATA3 0xe431c |
| 2836 | #define PCH_DPD_AUX_CH_DATA4 0xe4320 |
| 2837 | #define PCH_DPD_AUX_CH_DATA5 0xe4324 |
| 2838 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2839 | /* CPT */ |
| 2840 | #define PORT_TRANS_A_SEL_CPT 0 |
| 2841 | #define PORT_TRANS_B_SEL_CPT (1<<29) |
| 2842 | #define PORT_TRANS_C_SEL_CPT (2<<29) |
| 2843 | #define PORT_TRANS_SEL_MASK (3<<29) |
| 2844 | |
| 2845 | #define TRANS_DP_CTL_A 0xe0300 |
| 2846 | #define TRANS_DP_CTL_B 0xe1300 |
| 2847 | #define TRANS_DP_CTL_C 0xe2300 |
| 2848 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) |
| 2849 | #define TRANS_DP_PORT_SEL_B (0<<29) |
| 2850 | #define TRANS_DP_PORT_SEL_C (1<<29) |
| 2851 | #define TRANS_DP_PORT_SEL_D (2<<29) |
| 2852 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
| 2853 | #define TRANS_DP_AUDIO_ONLY (1<<26) |
| 2854 | #define TRANS_DP_ENH_FRAMING (1<<18) |
| 2855 | #define TRANS_DP_8BPC (0<<9) |
| 2856 | #define TRANS_DP_10BPC (1<<9) |
| 2857 | #define TRANS_DP_6BPC (2<<9) |
| 2858 | #define TRANS_DP_12BPC (3<<9) |
| 2859 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
| 2860 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
| 2861 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
| 2862 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 |
| 2863 | |
| 2864 | /* SNB eDP training params */ |
| 2865 | /* SNB A-stepping */ |
| 2866 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) |
| 2867 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) |
| 2868 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) |
| 2869 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) |
| 2870 | /* SNB B-stepping */ |
| 2871 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) |
| 2872 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) |
| 2873 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) |
| 2874 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) |
| 2875 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
| 2876 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 2877 | #endif /* _I915_REG_H_ */ |