David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "I2C PMIC: %s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/bitops.h> |
| 16 | #include <linux/i2c.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/irqdomain.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of_platform.h> |
| 22 | #include <linux/pinctrl/consumer.h> |
| 23 | #include <linux/regmap.h> |
| 24 | #include <linux/slab.h> |
| 25 | |
| 26 | #define I2C_INTR_STATUS_BASE 0x0550 |
| 27 | #define INT_RT_STS_OFFSET 0x10 |
| 28 | #define INT_SET_TYPE_OFFSET 0x11 |
| 29 | #define INT_POL_HIGH_OFFSET 0x12 |
| 30 | #define INT_POL_LOW_OFFSET 0x13 |
| 31 | #define INT_LATCHED_CLR_OFFSET 0x14 |
| 32 | #define INT_EN_SET_OFFSET 0x15 |
| 33 | #define INT_EN_CLR_OFFSET 0x16 |
| 34 | #define INT_LATCHED_STS_OFFSET 0x18 |
| 35 | #define INT_PENDING_STS_OFFSET 0x19 |
| 36 | #define INT_MID_SEL_OFFSET 0x1A |
| 37 | #define INT_MID_SEL_MASK GENMASK(1, 0) |
| 38 | #define INT_PRIORITY_OFFSET 0x1B |
| 39 | #define INT_PRIORITY_BIT BIT(0) |
| 40 | |
| 41 | enum { |
| 42 | IRQ_SET_TYPE = 0, |
| 43 | IRQ_POL_HIGH, |
| 44 | IRQ_POL_LOW, |
| 45 | IRQ_LATCHED_CLR, /* not needed but makes life easy */ |
| 46 | IRQ_EN_SET, |
| 47 | IRQ_MAX_REGS, |
| 48 | }; |
| 49 | |
| 50 | struct i2c_pmic_periph { |
| 51 | void *data; |
| 52 | u16 addr; |
| 53 | u8 cached[IRQ_MAX_REGS]; |
| 54 | u8 synced[IRQ_MAX_REGS]; |
| 55 | u8 wake; |
| 56 | struct mutex lock; |
| 57 | }; |
| 58 | |
| 59 | struct i2c_pmic { |
| 60 | struct device *dev; |
| 61 | struct regmap *regmap; |
| 62 | struct irq_domain *domain; |
| 63 | struct i2c_pmic_periph *periph; |
| 64 | struct pinctrl *pinctrl; |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 65 | struct mutex irq_complete; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 66 | const char *pinctrl_name; |
| 67 | int num_periphs; |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 68 | int summary_irq; |
| 69 | bool resume_completed; |
| 70 | bool irq_waiting; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | static void i2c_pmic_irq_bus_lock(struct irq_data *d) |
| 74 | { |
| 75 | struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d); |
| 76 | |
| 77 | mutex_lock(&periph->lock); |
| 78 | } |
| 79 | |
| 80 | static void i2c_pmic_sync_type_polarity(struct i2c_pmic *chip, |
| 81 | struct i2c_pmic_periph *periph) |
| 82 | { |
| 83 | int rc; |
| 84 | |
| 85 | /* did any irq type change? */ |
| 86 | if (periph->cached[IRQ_SET_TYPE] ^ periph->synced[IRQ_SET_TYPE]) { |
| 87 | rc = regmap_write(chip->regmap, |
| 88 | periph->addr | INT_SET_TYPE_OFFSET, |
| 89 | periph->cached[IRQ_SET_TYPE]); |
| 90 | if (rc < 0) { |
| 91 | pr_err("Couldn't set periph 0x%04x irqs 0x%02x type rc=%d\n", |
| 92 | periph->addr, periph->cached[IRQ_SET_TYPE], rc); |
| 93 | return; |
| 94 | } |
| 95 | |
| 96 | periph->synced[IRQ_SET_TYPE] = periph->cached[IRQ_SET_TYPE]; |
| 97 | } |
| 98 | |
| 99 | /* did any polarity high change? */ |
| 100 | if (periph->cached[IRQ_POL_HIGH] ^ periph->synced[IRQ_POL_HIGH]) { |
| 101 | rc = regmap_write(chip->regmap, |
| 102 | periph->addr | INT_POL_HIGH_OFFSET, |
| 103 | periph->cached[IRQ_POL_HIGH]); |
| 104 | if (rc < 0) { |
| 105 | pr_err("Couldn't set periph 0x%04x irqs 0x%02x polarity high rc=%d\n", |
| 106 | periph->addr, periph->cached[IRQ_POL_HIGH], rc); |
| 107 | return; |
| 108 | } |
| 109 | |
| 110 | periph->synced[IRQ_POL_HIGH] = periph->cached[IRQ_POL_HIGH]; |
| 111 | } |
| 112 | |
| 113 | /* did any polarity low change? */ |
| 114 | if (periph->cached[IRQ_POL_LOW] ^ periph->synced[IRQ_POL_LOW]) { |
| 115 | rc = regmap_write(chip->regmap, |
| 116 | periph->addr | INT_POL_LOW_OFFSET, |
| 117 | periph->cached[IRQ_POL_LOW]); |
| 118 | if (rc < 0) { |
| 119 | pr_err("Couldn't set periph 0x%04x irqs 0x%02x polarity low rc=%d\n", |
| 120 | periph->addr, periph->cached[IRQ_POL_LOW], rc); |
| 121 | return; |
| 122 | } |
| 123 | |
| 124 | periph->synced[IRQ_POL_LOW] = periph->cached[IRQ_POL_LOW]; |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | static void i2c_pmic_sync_enable(struct i2c_pmic *chip, |
| 129 | struct i2c_pmic_periph *periph) |
| 130 | { |
| 131 | u8 en_set, en_clr; |
| 132 | int rc; |
| 133 | |
| 134 | /* determine which irqs were enabled and which were disabled */ |
| 135 | en_clr = periph->synced[IRQ_EN_SET] & ~periph->cached[IRQ_EN_SET]; |
| 136 | en_set = ~periph->synced[IRQ_EN_SET] & periph->cached[IRQ_EN_SET]; |
| 137 | |
| 138 | /* were any irqs disabled? */ |
| 139 | if (en_clr) { |
| 140 | rc = regmap_write(chip->regmap, |
| 141 | periph->addr | INT_EN_CLR_OFFSET, en_clr); |
| 142 | if (rc < 0) { |
| 143 | pr_err("Couldn't disable periph 0x%04x irqs 0x%02x rc=%d\n", |
| 144 | periph->addr, en_clr, rc); |
| 145 | return; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | /* were any irqs enabled? */ |
| 150 | if (en_set) { |
| 151 | rc = regmap_write(chip->regmap, |
| 152 | periph->addr | INT_EN_SET_OFFSET, en_set); |
| 153 | if (rc < 0) { |
| 154 | pr_err("Couldn't enable periph 0x%04x irqs 0x%02x rc=%d\n", |
| 155 | periph->addr, en_set, rc); |
| 156 | return; |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | /* irq enabled status was written to hardware */ |
| 161 | periph->synced[IRQ_EN_SET] = periph->cached[IRQ_EN_SET]; |
| 162 | } |
| 163 | |
| 164 | static void i2c_pmic_irq_bus_sync_unlock(struct irq_data *d) |
| 165 | { |
| 166 | struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d); |
| 167 | struct i2c_pmic *chip = periph->data; |
| 168 | |
| 169 | i2c_pmic_sync_type_polarity(chip, periph); |
| 170 | i2c_pmic_sync_enable(chip, periph); |
| 171 | mutex_unlock(&periph->lock); |
| 172 | } |
| 173 | |
| 174 | static void i2c_pmic_irq_disable(struct irq_data *d) |
| 175 | { |
| 176 | struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d); |
| 177 | |
| 178 | periph->cached[IRQ_EN_SET] &= ~d->hwirq & 0xFF; |
| 179 | } |
| 180 | |
| 181 | static void i2c_pmic_irq_enable(struct irq_data *d) |
| 182 | { |
| 183 | struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d); |
| 184 | |
| 185 | periph->cached[IRQ_EN_SET] |= d->hwirq & 0xFF; |
| 186 | } |
| 187 | |
| 188 | static int i2c_pmic_irq_set_type(struct irq_data *d, unsigned int irq_type) |
| 189 | { |
| 190 | struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d); |
| 191 | |
| 192 | switch (irq_type) { |
| 193 | case IRQ_TYPE_EDGE_RISING: |
| 194 | periph->cached[IRQ_SET_TYPE] |= d->hwirq & 0xFF; |
| 195 | periph->cached[IRQ_POL_HIGH] |= d->hwirq & 0xFF; |
| 196 | periph->cached[IRQ_POL_LOW] &= ~d->hwirq & 0xFF; |
| 197 | break; |
| 198 | case IRQ_TYPE_EDGE_FALLING: |
| 199 | periph->cached[IRQ_SET_TYPE] |= d->hwirq & 0xFF; |
| 200 | periph->cached[IRQ_POL_HIGH] &= ~d->hwirq & 0xFF; |
| 201 | periph->cached[IRQ_POL_LOW] |= d->hwirq & 0xFF; |
| 202 | break; |
| 203 | case IRQ_TYPE_EDGE_BOTH: |
| 204 | periph->cached[IRQ_SET_TYPE] |= d->hwirq & 0xFF; |
| 205 | periph->cached[IRQ_POL_HIGH] |= d->hwirq & 0xFF; |
| 206 | periph->cached[IRQ_POL_LOW] |= d->hwirq & 0xFF; |
| 207 | break; |
| 208 | case IRQ_TYPE_LEVEL_HIGH: |
| 209 | periph->cached[IRQ_SET_TYPE] &= ~d->hwirq & 0xFF; |
| 210 | periph->cached[IRQ_POL_HIGH] |= d->hwirq & 0xFF; |
| 211 | periph->cached[IRQ_POL_LOW] &= ~d->hwirq & 0xFF; |
| 212 | break; |
| 213 | case IRQ_TYPE_LEVEL_LOW: |
| 214 | periph->cached[IRQ_SET_TYPE] &= ~d->hwirq & 0xFF; |
| 215 | periph->cached[IRQ_POL_HIGH] &= ~d->hwirq & 0xFF; |
| 216 | periph->cached[IRQ_POL_LOW] |= d->hwirq & 0xFF; |
| 217 | break; |
| 218 | default: |
| 219 | pr_err("irq type 0x%04x is not supported\n", irq_type); |
| 220 | return -EINVAL; |
| 221 | } |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | #ifdef CONFIG_PM_SLEEP |
| 227 | static int i2c_pmic_irq_set_wake(struct irq_data *d, unsigned int on) |
| 228 | { |
| 229 | struct i2c_pmic_periph *periph = irq_data_get_irq_chip_data(d); |
| 230 | |
| 231 | if (on) |
| 232 | periph->wake |= d->hwirq & 0xFF; |
| 233 | else |
| 234 | periph->wake &= ~d->hwirq & 0xFF; |
| 235 | |
| 236 | return 0; |
| 237 | } |
| 238 | #else |
| 239 | #define i2c_pmic_irq_set_wake NULL |
| 240 | #endif |
| 241 | |
| 242 | static struct irq_chip i2c_pmic_irq_chip = { |
| 243 | .name = "i2c_pmic_irq_chip", |
| 244 | .irq_bus_lock = i2c_pmic_irq_bus_lock, |
| 245 | .irq_bus_sync_unlock = i2c_pmic_irq_bus_sync_unlock, |
| 246 | .irq_disable = i2c_pmic_irq_disable, |
| 247 | .irq_enable = i2c_pmic_irq_enable, |
| 248 | .irq_set_type = i2c_pmic_irq_set_type, |
| 249 | .irq_set_wake = i2c_pmic_irq_set_wake, |
| 250 | }; |
| 251 | |
| 252 | static struct i2c_pmic_periph *i2c_pmic_find_periph(struct i2c_pmic *chip, |
| 253 | irq_hw_number_t hwirq) |
| 254 | { |
| 255 | int i; |
| 256 | |
| 257 | for (i = 0; i < chip->num_periphs; i++) |
| 258 | if (chip->periph[i].addr == (hwirq & 0xFF00)) |
| 259 | return &chip->periph[i]; |
| 260 | |
| 261 | pr_err_ratelimited("Couldn't find periph struct for hwirq 0x%04lx\n", |
| 262 | hwirq); |
| 263 | return NULL; |
| 264 | } |
| 265 | |
| 266 | static int i2c_pmic_domain_map(struct irq_domain *d, unsigned int virq, |
| 267 | irq_hw_number_t hwirq) |
| 268 | { |
| 269 | struct i2c_pmic *chip = d->host_data; |
| 270 | struct i2c_pmic_periph *periph = i2c_pmic_find_periph(chip, hwirq); |
| 271 | |
| 272 | if (!periph) |
| 273 | return -ENODEV; |
| 274 | |
| 275 | irq_set_chip_data(virq, periph); |
| 276 | irq_set_chip_and_handler(virq, &i2c_pmic_irq_chip, handle_level_irq); |
| 277 | irq_set_nested_thread(virq, 1); |
| 278 | irq_set_noprobe(virq); |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static int i2c_pmic_domain_xlate(struct irq_domain *d, |
| 283 | struct device_node *ctrlr, const u32 *intspec, |
| 284 | unsigned int intsize, unsigned long *out_hwirq, |
| 285 | unsigned int *out_type) |
| 286 | { |
| 287 | if (intsize != 3) |
| 288 | return -EINVAL; |
| 289 | |
| 290 | if (intspec[0] > 0xFF || intspec[1] > 0x7 || |
| 291 | intspec[2] > IRQ_TYPE_SENSE_MASK) |
| 292 | return -EINVAL; |
| 293 | |
| 294 | /* |
| 295 | * Interrupt specifiers are triplets |
| 296 | * <peripheral-address, irq-number, IRQ_TYPE_*> |
| 297 | * |
| 298 | * peripheral-address - The base address of the peripheral |
| 299 | * irq-number - The zero based bit position of the peripheral's |
| 300 | * interrupt registers corresponding to the irq |
| 301 | * where the LSB is 0 and the MSB is 7 |
| 302 | * IRQ_TYPE_* - Please refer to linux/irq.h |
| 303 | */ |
| 304 | *out_hwirq = intspec[0] << 8 | BIT(intspec[1]); |
| 305 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | static const struct irq_domain_ops i2c_pmic_domain_ops = { |
| 311 | .map = i2c_pmic_domain_map, |
| 312 | .xlate = i2c_pmic_domain_xlate, |
| 313 | }; |
| 314 | |
| 315 | static void i2c_pmic_irq_ack_now(struct i2c_pmic *chip, u16 hwirq) |
| 316 | { |
| 317 | int rc; |
| 318 | |
| 319 | rc = regmap_write(chip->regmap, |
| 320 | (hwirq & 0xFF00) | INT_LATCHED_CLR_OFFSET, |
| 321 | hwirq & 0xFF); |
| 322 | if (rc < 0) |
| 323 | pr_err_ratelimited("Couldn't ack 0x%04x rc=%d\n", hwirq, rc); |
| 324 | } |
| 325 | |
| 326 | static void i2c_pmic_irq_disable_now(struct i2c_pmic *chip, u16 hwirq) |
| 327 | { |
| 328 | struct i2c_pmic_periph *periph = i2c_pmic_find_periph(chip, hwirq); |
| 329 | int rc; |
| 330 | |
| 331 | if (!periph) |
| 332 | return; |
| 333 | |
| 334 | mutex_lock(&periph->lock); |
| 335 | periph->cached[IRQ_EN_SET] &= ~hwirq & 0xFF; |
| 336 | |
| 337 | rc = regmap_write(chip->regmap, |
| 338 | (hwirq & 0xFF00) | INT_EN_CLR_OFFSET, |
| 339 | hwirq & 0xFF); |
| 340 | if (rc < 0) { |
| 341 | pr_err_ratelimited("Couldn't disable irq 0x%04x rc=%d\n", |
| 342 | hwirq, rc); |
| 343 | goto unlock; |
| 344 | } |
| 345 | |
| 346 | periph->synced[IRQ_EN_SET] = periph->cached[IRQ_EN_SET]; |
| 347 | |
| 348 | unlock: |
| 349 | mutex_unlock(&periph->lock); |
| 350 | } |
| 351 | |
| 352 | static void i2c_pmic_periph_status_handler(struct i2c_pmic *chip, |
| 353 | u16 periph_address, u8 periph_status) |
| 354 | { |
| 355 | unsigned int hwirq, virq; |
| 356 | int i; |
| 357 | |
| 358 | while (periph_status) { |
| 359 | i = ffs(periph_status) - 1; |
| 360 | periph_status &= ~BIT(i); |
| 361 | hwirq = periph_address | BIT(i); |
| 362 | virq = irq_find_mapping(chip->domain, hwirq); |
| 363 | if (virq == 0) { |
| 364 | pr_err_ratelimited("Couldn't find mapping; disabling 0x%04x\n", |
| 365 | hwirq); |
| 366 | i2c_pmic_irq_disable_now(chip, hwirq); |
| 367 | continue; |
| 368 | } |
| 369 | |
| 370 | handle_nested_irq(virq); |
| 371 | i2c_pmic_irq_ack_now(chip, hwirq); |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | static void i2c_pmic_summary_status_handler(struct i2c_pmic *chip, |
| 376 | struct i2c_pmic_periph *periph, |
| 377 | u8 summary_status) |
| 378 | { |
| 379 | unsigned int periph_status; |
| 380 | int rc, i; |
| 381 | |
| 382 | while (summary_status) { |
| 383 | i = ffs(summary_status) - 1; |
| 384 | summary_status &= ~BIT(i); |
| 385 | |
| 386 | rc = regmap_read(chip->regmap, |
| 387 | periph[i].addr | INT_LATCHED_STS_OFFSET, |
| 388 | &periph_status); |
| 389 | if (rc < 0) { |
| 390 | pr_err_ratelimited("Couldn't read 0x%04x | INT_LATCHED_STS rc=%d\n", |
| 391 | periph[i].addr, rc); |
| 392 | continue; |
| 393 | } |
| 394 | |
| 395 | i2c_pmic_periph_status_handler(chip, periph[i].addr, |
| 396 | periph_status); |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | static irqreturn_t i2c_pmic_irq_handler(int irq, void *dev_id) |
| 401 | { |
| 402 | struct i2c_pmic *chip = dev_id; |
| 403 | struct i2c_pmic_periph *periph; |
| 404 | unsigned int summary_status; |
| 405 | int rc, i; |
| 406 | |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 407 | mutex_lock(&chip->irq_complete); |
| 408 | chip->irq_waiting = true; |
| 409 | if (!chip->resume_completed) { |
| 410 | pr_debug("IRQ triggered before device-resume\n"); |
| 411 | disable_irq_nosync(irq); |
| 412 | mutex_unlock(&chip->irq_complete); |
| 413 | return IRQ_HANDLED; |
| 414 | } |
| 415 | chip->irq_waiting = false; |
| 416 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 417 | for (i = 0; i < DIV_ROUND_UP(chip->num_periphs, BITS_PER_BYTE); i++) { |
| 418 | rc = regmap_read(chip->regmap, I2C_INTR_STATUS_BASE + i, |
| 419 | &summary_status); |
| 420 | if (rc < 0) { |
| 421 | pr_err_ratelimited("Couldn't read I2C_INTR_STATUS%d rc=%d\n", |
| 422 | i, rc); |
| 423 | continue; |
| 424 | } |
| 425 | |
| 426 | if (summary_status == 0) |
| 427 | continue; |
| 428 | |
| 429 | periph = &chip->periph[i * 8]; |
| 430 | i2c_pmic_summary_status_handler(chip, periph, summary_status); |
| 431 | } |
| 432 | |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 433 | mutex_unlock(&chip->irq_complete); |
| 434 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 435 | return IRQ_HANDLED; |
| 436 | } |
| 437 | |
| 438 | static int i2c_pmic_parse_dt(struct i2c_pmic *chip) |
| 439 | { |
| 440 | struct device_node *node = chip->dev->of_node; |
| 441 | int rc, i; |
| 442 | u32 temp; |
| 443 | |
| 444 | if (!node) { |
| 445 | pr_err("missing device tree\n"); |
| 446 | return -EINVAL; |
| 447 | } |
| 448 | |
| 449 | chip->num_periphs = of_property_count_u32_elems(node, |
| 450 | "qcom,periph-map"); |
| 451 | if (chip->num_periphs < 0) { |
| 452 | pr_err("missing qcom,periph-map property rc=%d\n", |
| 453 | chip->num_periphs); |
| 454 | return chip->num_periphs; |
| 455 | } |
| 456 | |
| 457 | if (chip->num_periphs == 0) { |
| 458 | pr_err("qcom,periph-map must contain at least one address\n"); |
| 459 | return -EINVAL; |
| 460 | } |
| 461 | |
| 462 | chip->periph = devm_kcalloc(chip->dev, chip->num_periphs, |
| 463 | sizeof(*chip->periph), GFP_KERNEL); |
| 464 | if (!chip->periph) |
| 465 | return -ENOMEM; |
| 466 | |
| 467 | for (i = 0; i < chip->num_periphs; i++) { |
| 468 | rc = of_property_read_u32_index(node, "qcom,periph-map", |
| 469 | i, &temp); |
| 470 | if (rc < 0) { |
| 471 | pr_err("Couldn't read qcom,periph-map[%d] rc=%d\n", |
| 472 | i, rc); |
| 473 | return rc; |
| 474 | } |
| 475 | |
| 476 | chip->periph[i].addr = (u16)(temp << 8); |
| 477 | chip->periph[i].data = chip; |
| 478 | mutex_init(&chip->periph[i].lock); |
| 479 | } |
| 480 | |
| 481 | of_property_read_string(node, "pinctrl-names", &chip->pinctrl_name); |
| 482 | |
| 483 | return rc; |
| 484 | } |
| 485 | |
| 486 | #define MAX_I2C_RETRIES 3 |
| 487 | static int i2c_pmic_read(struct regmap *map, unsigned int reg, void *val, |
| 488 | size_t val_count) |
| 489 | { |
| 490 | int rc, retries = 0; |
| 491 | |
| 492 | do { |
| 493 | rc = regmap_bulk_read(map, reg, val, val_count); |
| 494 | } while (rc == -ENOTCONN && retries++ < MAX_I2C_RETRIES); |
| 495 | |
| 496 | if (retries > 1) |
| 497 | pr_err("i2c_pmic_read failed for %d retries, rc = %d\n", |
| 498 | retries - 1, rc); |
| 499 | |
| 500 | return rc; |
| 501 | } |
| 502 | |
| 503 | static int i2c_pmic_determine_initial_status(struct i2c_pmic *chip) |
| 504 | { |
| 505 | int rc, i; |
| 506 | |
| 507 | for (i = 0; i < chip->num_periphs; i++) { |
| 508 | rc = i2c_pmic_read(chip->regmap, |
| 509 | chip->periph[i].addr | INT_SET_TYPE_OFFSET, |
| 510 | chip->periph[i].cached, IRQ_MAX_REGS); |
| 511 | if (rc < 0) { |
| 512 | pr_err("Couldn't read irq data rc=%d\n", rc); |
| 513 | return rc; |
| 514 | } |
| 515 | |
| 516 | memcpy(chip->periph[i].synced, chip->periph[i].cached, |
| 517 | IRQ_MAX_REGS * sizeof(*chip->periph[i].synced)); |
| 518 | } |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | static struct regmap_config i2c_pmic_regmap_config = { |
| 524 | .reg_bits = 16, |
| 525 | .val_bits = 8, |
| 526 | .max_register = 0xFFFF, |
| 527 | }; |
| 528 | |
| 529 | static int i2c_pmic_probe(struct i2c_client *client, |
| 530 | const struct i2c_device_id *id) |
| 531 | { |
| 532 | struct i2c_pmic *chip; |
| 533 | int rc = 0; |
| 534 | |
| 535 | chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); |
| 536 | if (!chip) |
| 537 | return -ENOMEM; |
| 538 | |
| 539 | chip->dev = &client->dev; |
| 540 | chip->regmap = devm_regmap_init_i2c(client, &i2c_pmic_regmap_config); |
| 541 | if (!chip->regmap) |
| 542 | return -ENODEV; |
| 543 | |
| 544 | i2c_set_clientdata(client, chip); |
| 545 | if (!of_property_read_bool(chip->dev->of_node, "interrupt-controller")) |
| 546 | goto probe_children; |
| 547 | |
| 548 | chip->domain = irq_domain_add_tree(client->dev.of_node, |
| 549 | &i2c_pmic_domain_ops, chip); |
| 550 | if (!chip->domain) { |
| 551 | rc = -ENOMEM; |
| 552 | goto cleanup; |
| 553 | } |
| 554 | |
| 555 | rc = i2c_pmic_parse_dt(chip); |
| 556 | if (rc < 0) { |
| 557 | pr_err("Couldn't parse device tree rc=%d\n", rc); |
| 558 | goto cleanup; |
| 559 | } |
| 560 | |
| 561 | rc = i2c_pmic_determine_initial_status(chip); |
| 562 | if (rc < 0) { |
| 563 | pr_err("Couldn't determine initial status rc=%d\n", rc); |
| 564 | goto cleanup; |
| 565 | } |
| 566 | |
| 567 | if (chip->pinctrl_name) { |
| 568 | chip->pinctrl = devm_pinctrl_get_select(chip->dev, |
| 569 | chip->pinctrl_name); |
| 570 | if (IS_ERR(chip->pinctrl)) { |
| 571 | pr_err("Couldn't select %s pinctrl rc=%ld\n", |
| 572 | chip->pinctrl_name, PTR_ERR(chip->pinctrl)); |
| 573 | rc = PTR_ERR(chip->pinctrl); |
| 574 | goto cleanup; |
| 575 | } |
| 576 | } |
| 577 | |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 578 | chip->resume_completed = true; |
| 579 | mutex_init(&chip->irq_complete); |
| 580 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 581 | rc = devm_request_threaded_irq(&client->dev, client->irq, NULL, |
| 582 | i2c_pmic_irq_handler, |
| 583 | IRQF_ONESHOT | IRQF_SHARED, |
| 584 | "i2c_pmic_stat_irq", chip); |
| 585 | if (rc < 0) { |
| 586 | pr_err("Couldn't request irq %d rc=%d\n", client->irq, rc); |
| 587 | goto cleanup; |
| 588 | } |
| 589 | |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 590 | chip->summary_irq = client->irq; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 591 | enable_irq_wake(client->irq); |
| 592 | |
| 593 | probe_children: |
| 594 | of_platform_populate(chip->dev->of_node, NULL, NULL, chip->dev); |
| 595 | pr_info("I2C PMIC probe successful\n"); |
| 596 | return rc; |
| 597 | |
| 598 | cleanup: |
| 599 | if (chip->domain) |
| 600 | irq_domain_remove(chip->domain); |
| 601 | i2c_set_clientdata(client, NULL); |
| 602 | return rc; |
| 603 | } |
| 604 | |
| 605 | static int i2c_pmic_remove(struct i2c_client *client) |
| 606 | { |
| 607 | struct i2c_pmic *chip = i2c_get_clientdata(client); |
| 608 | |
| 609 | of_platform_depopulate(chip->dev); |
| 610 | if (chip->domain) |
| 611 | irq_domain_remove(chip->domain); |
| 612 | i2c_set_clientdata(client, NULL); |
| 613 | return 0; |
| 614 | } |
| 615 | |
| 616 | #ifdef CONFIG_PM_SLEEP |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 617 | static int i2c_pmic_suspend_noirq(struct device *dev) |
| 618 | { |
| 619 | struct i2c_pmic *chip = dev_get_drvdata(dev); |
| 620 | |
| 621 | if (chip->irq_waiting) { |
| 622 | pr_err_ratelimited("Aborting suspend, an interrupt was detected while suspending\n"); |
| 623 | return -EBUSY; |
| 624 | } |
| 625 | return 0; |
| 626 | } |
| 627 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 628 | static int i2c_pmic_suspend(struct device *dev) |
| 629 | { |
| 630 | struct i2c_pmic *chip = dev_get_drvdata(dev); |
| 631 | struct i2c_pmic_periph *periph; |
| 632 | int rc = 0, i; |
| 633 | |
| 634 | for (i = 0; i < chip->num_periphs; i++) { |
| 635 | periph = &chip->periph[i]; |
| 636 | |
| 637 | rc = regmap_write(chip->regmap, |
| 638 | periph->addr | INT_EN_CLR_OFFSET, 0xFF); |
| 639 | if (rc < 0) { |
| 640 | pr_err_ratelimited("Couldn't clear 0x%04x irqs rc=%d\n", |
| 641 | periph->addr, rc); |
| 642 | continue; |
| 643 | } |
| 644 | |
| 645 | rc = regmap_write(chip->regmap, |
| 646 | periph->addr | INT_EN_SET_OFFSET, |
| 647 | periph->wake); |
| 648 | if (rc < 0) |
| 649 | pr_err_ratelimited("Couldn't enable 0x%04x wake irqs 0x%02x rc=%d\n", |
| 650 | periph->addr, periph->wake, rc); |
| 651 | } |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 652 | if (!rc) { |
| 653 | mutex_lock(&chip->irq_complete); |
| 654 | chip->resume_completed = false; |
| 655 | mutex_unlock(&chip->irq_complete); |
| 656 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 657 | |
| 658 | return rc; |
| 659 | } |
| 660 | |
| 661 | static int i2c_pmic_resume(struct device *dev) |
| 662 | { |
| 663 | struct i2c_pmic *chip = dev_get_drvdata(dev); |
| 664 | struct i2c_pmic_periph *periph; |
| 665 | int rc = 0, i; |
| 666 | |
| 667 | for (i = 0; i < chip->num_periphs; i++) { |
| 668 | periph = &chip->periph[i]; |
| 669 | |
| 670 | rc = regmap_write(chip->regmap, |
| 671 | periph->addr | INT_EN_CLR_OFFSET, 0xFF); |
| 672 | if (rc < 0) { |
| 673 | pr_err("Couldn't clear 0x%04x irqs rc=%d\n", |
| 674 | periph->addr, rc); |
| 675 | continue; |
| 676 | } |
| 677 | |
| 678 | rc = regmap_write(chip->regmap, |
| 679 | periph->addr | INT_EN_SET_OFFSET, |
| 680 | periph->synced[IRQ_EN_SET]); |
| 681 | if (rc < 0) |
| 682 | pr_err("Couldn't restore 0x%04x synced irqs 0x%02x rc=%d\n", |
| 683 | periph->addr, periph->synced[IRQ_EN_SET], rc); |
| 684 | } |
| 685 | |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 686 | mutex_lock(&chip->irq_complete); |
| 687 | chip->resume_completed = true; |
| 688 | if (chip->irq_waiting) { |
| 689 | mutex_unlock(&chip->irq_complete); |
| 690 | /* irq was pending, call the handler */ |
| 691 | i2c_pmic_irq_handler(chip->summary_irq, chip); |
| 692 | enable_irq(chip->summary_irq); |
| 693 | } else { |
| 694 | mutex_unlock(&chip->irq_complete); |
| 695 | } |
| 696 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 697 | return rc; |
| 698 | } |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 699 | #else |
| 700 | static int i2c_pmic_suspend(struct device *dev) |
| 701 | { |
| 702 | return 0; |
| 703 | } |
| 704 | static int i2c_pmic_resume(struct device *dev) |
| 705 | { |
| 706 | return 0; |
| 707 | } |
| 708 | static int i2c_pmic_suspend_noirq(struct device *dev) |
| 709 | { |
| 710 | return 0 |
| 711 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 712 | #endif |
Anirudh Ghayal | 7a1b440 | 2017-09-12 16:52:28 +0530 | [diff] [blame] | 713 | static const struct dev_pm_ops i2c_pmic_pm_ops = { |
| 714 | .suspend = i2c_pmic_suspend, |
| 715 | .suspend_noirq = i2c_pmic_suspend_noirq, |
| 716 | .resume = i2c_pmic_resume, |
| 717 | }; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 718 | |
| 719 | static const struct of_device_id i2c_pmic_match_table[] = { |
| 720 | { .compatible = "qcom,i2c-pmic", }, |
| 721 | { }, |
| 722 | }; |
| 723 | |
| 724 | static const struct i2c_device_id i2c_pmic_id[] = { |
| 725 | { "i2c-pmic", 0 }, |
| 726 | { }, |
| 727 | }; |
| 728 | MODULE_DEVICE_TABLE(i2c, i2c_pmic_id); |
| 729 | |
| 730 | static struct i2c_driver i2c_pmic_driver = { |
| 731 | .driver = { |
| 732 | .name = "i2c_pmic", |
| 733 | .owner = THIS_MODULE, |
| 734 | .pm = &i2c_pmic_pm_ops, |
| 735 | .of_match_table = i2c_pmic_match_table, |
| 736 | }, |
| 737 | .probe = i2c_pmic_probe, |
| 738 | .remove = i2c_pmic_remove, |
| 739 | .id_table = i2c_pmic_id, |
| 740 | }; |
| 741 | |
| 742 | module_i2c_driver(i2c_pmic_driver); |
| 743 | |
| 744 | MODULE_LICENSE("GPL v2"); |
| 745 | MODULE_ALIAS("i2c:i2c_pmic"); |