Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Intel Management Engine Interface (Intel MEI) Linux driver |
Tomas Winkler | 733ba91 | 2012-02-09 19:25:53 +0200 | [diff] [blame] | 4 | * Copyright (c) 2003-2012, Intel Corporation. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <linux/pci.h> |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 18 | |
| 19 | #include <linux/kthread.h> |
| 20 | #include <linux/interrupt.h> |
Alexander Usyskin | 77537ad | 2016-06-16 17:58:52 +0300 | [diff] [blame] | 21 | #include <linux/pm_runtime.h> |
Tomas Winkler | 47a7380 | 2012-12-25 19:06:03 +0200 | [diff] [blame] | 22 | |
| 23 | #include "mei_dev.h" |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 24 | #include "hbm.h" |
| 25 | |
Tomas Winkler | 6e4cd27 | 2014-03-11 14:49:23 +0200 | [diff] [blame] | 26 | #include "hw-me.h" |
| 27 | #include "hw-me-regs.h" |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 28 | |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 29 | #include "mei-trace.h" |
| 30 | |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 31 | /** |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 32 | * mei_me_reg_read - Reads 32bit data from the mei device |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 33 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 34 | * @hw: the me hardware structure |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 35 | * @offset: offset from which to read the data |
| 36 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 37 | * Return: register value (u32) |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 38 | */ |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 39 | static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 40 | unsigned long offset) |
| 41 | { |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 42 | return ioread32(hw->mem_addr + offset); |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 43 | } |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 44 | |
| 45 | |
| 46 | /** |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 47 | * mei_me_reg_write - Writes 32bit data to the mei device |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 48 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 49 | * @hw: the me hardware structure |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 50 | * @offset: offset from which to write the data |
| 51 | * @value: register value to write (u32) |
| 52 | */ |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 53 | static inline void mei_me_reg_write(const struct mei_me_hw *hw, |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 54 | unsigned long offset, u32 value) |
| 55 | { |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 56 | iowrite32(value, hw->mem_addr + offset); |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | /** |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 60 | * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer |
Tomas Winkler | d025284 | 2013-01-08 23:07:24 +0200 | [diff] [blame] | 61 | * read window register |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 62 | * |
| 63 | * @dev: the device structure |
| 64 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 65 | * Return: ME_CB_RW register value (u32) |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 66 | */ |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 67 | static inline u32 mei_me_mecbrw_read(const struct mei_device *dev) |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 68 | { |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 69 | return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 70 | } |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 71 | |
| 72 | /** |
| 73 | * mei_me_hcbww_write - write 32bit data to the host circular buffer |
| 74 | * |
| 75 | * @dev: the device structure |
| 76 | * @data: 32bit data to be written to the host circular buffer |
| 77 | */ |
| 78 | static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data) |
| 79 | { |
| 80 | mei_me_reg_write(to_me_hw(dev), H_CB_WW, data); |
| 81 | } |
| 82 | |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 83 | /** |
Tomas Winkler | b68301e | 2013-03-27 16:58:29 +0200 | [diff] [blame] | 84 | * mei_me_mecsr_read - Reads 32bit data from the ME CSR |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 85 | * |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 86 | * @dev: the device structure |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 87 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 88 | * Return: ME_CSR_HA register value (u32) |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 89 | */ |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 90 | static inline u32 mei_me_mecsr_read(const struct mei_device *dev) |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 91 | { |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 92 | u32 reg; |
| 93 | |
| 94 | reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); |
| 95 | trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); |
| 96 | |
| 97 | return reg; |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | /** |
Tomas Winkler | d025284 | 2013-01-08 23:07:24 +0200 | [diff] [blame] | 101 | * mei_hcsr_read - Reads 32bit data from the host CSR |
| 102 | * |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 103 | * @dev: the device structure |
Tomas Winkler | d025284 | 2013-01-08 23:07:24 +0200 | [diff] [blame] | 104 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 105 | * Return: H_CSR register value (u32) |
Tomas Winkler | d025284 | 2013-01-08 23:07:24 +0200 | [diff] [blame] | 106 | */ |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 107 | static inline u32 mei_hcsr_read(const struct mei_device *dev) |
Tomas Winkler | d025284 | 2013-01-08 23:07:24 +0200 | [diff] [blame] | 108 | { |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 109 | u32 reg; |
| 110 | |
| 111 | reg = mei_me_reg_read(to_me_hw(dev), H_CSR); |
| 112 | trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); |
| 113 | |
| 114 | return reg; |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | /** |
| 118 | * mei_hcsr_write - writes H_CSR register to the mei device |
| 119 | * |
| 120 | * @dev: the device structure |
| 121 | * @reg: new register value |
| 122 | */ |
| 123 | static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) |
| 124 | { |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 125 | trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 126 | mei_me_reg_write(to_me_hw(dev), H_CSR, reg); |
Tomas Winkler | d025284 | 2013-01-08 23:07:24 +0200 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | /** |
| 130 | * mei_hcsr_set - writes H_CSR register to the mei device, |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 131 | * and ignores the H_IS bit for it is write-one-to-zero. |
| 132 | * |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 133 | * @dev: the device structure |
| 134 | * @reg: new register value |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 135 | */ |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 136 | static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 137 | { |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 138 | reg &= ~H_CSR_IS_MASK; |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 139 | mei_hcsr_write(dev, reg); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 140 | } |
| 141 | |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 142 | /** |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 143 | * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register |
| 144 | * |
| 145 | * @dev: the device structure |
| 146 | * |
| 147 | * Return: H_D0I3C register value (u32) |
| 148 | */ |
| 149 | static inline u32 mei_me_d0i3c_read(const struct mei_device *dev) |
| 150 | { |
| 151 | u32 reg; |
| 152 | |
| 153 | reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); |
Alexander Usyskin | cf094eb | 2015-09-18 00:11:52 +0300 | [diff] [blame] | 154 | trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 155 | |
| 156 | return reg; |
| 157 | } |
| 158 | |
| 159 | /** |
| 160 | * mei_me_d0i3c_write - writes H_D0I3C register to device |
| 161 | * |
| 162 | * @dev: the device structure |
| 163 | * @reg: new register value |
| 164 | */ |
| 165 | static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) |
| 166 | { |
Alexander Usyskin | cf094eb | 2015-09-18 00:11:52 +0300 | [diff] [blame] | 167 | trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 168 | mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); |
| 169 | } |
| 170 | |
| 171 | /** |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 172 | * mei_me_fw_status - read fw status register from pci config space |
| 173 | * |
| 174 | * @dev: mei device |
| 175 | * @fw_status: fw status register values |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 176 | * |
| 177 | * Return: 0 on success, error otherwise |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 178 | */ |
| 179 | static int mei_me_fw_status(struct mei_device *dev, |
| 180 | struct mei_fw_status *fw_status) |
| 181 | { |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 182 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
Tomas Winkler | 4ad96db | 2014-09-29 16:31:45 +0300 | [diff] [blame] | 183 | struct mei_me_hw *hw = to_me_hw(dev); |
| 184 | const struct mei_fw_status *fw_src = &hw->cfg->fw_status; |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 185 | int ret; |
| 186 | int i; |
| 187 | |
| 188 | if (!fw_status) |
| 189 | return -EINVAL; |
| 190 | |
| 191 | fw_status->count = fw_src->count; |
| 192 | for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { |
Tomas Winkler | a96c548 | 2016-02-07 22:46:51 +0200 | [diff] [blame] | 193 | ret = pci_read_config_dword(pdev, fw_src->status[i], |
| 194 | &fw_status->status[i]); |
| 195 | trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", |
| 196 | fw_src->status[i], |
| 197 | fw_status->status[i]); |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 198 | if (ret) |
| 199 | return ret; |
| 200 | } |
| 201 | |
| 202 | return 0; |
| 203 | } |
Tomas Winkler | e7e0c23 | 2013-01-08 23:07:31 +0200 | [diff] [blame] | 204 | |
| 205 | /** |
Masanari Iida | 393b148 | 2013-04-05 01:05:05 +0900 | [diff] [blame] | 206 | * mei_me_hw_config - configure hw dependent settings |
Tomas Winkler | e7e0c23 | 2013-01-08 23:07:31 +0200 | [diff] [blame] | 207 | * |
| 208 | * @dev: mei device |
| 209 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 210 | static void mei_me_hw_config(struct mei_device *dev) |
Tomas Winkler | e7e0c23 | 2013-01-08 23:07:31 +0200 | [diff] [blame] | 211 | { |
Alexander Usyskin | bb9f4d2 | 2015-08-02 22:20:51 +0300 | [diff] [blame] | 212 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 213 | struct mei_me_hw *hw = to_me_hw(dev); |
Alexander Usyskin | bb9f4d2 | 2015-08-02 22:20:51 +0300 | [diff] [blame] | 214 | u32 hcsr, reg; |
| 215 | |
Tomas Winkler | e7e0c23 | 2013-01-08 23:07:31 +0200 | [diff] [blame] | 216 | /* Doesn't change in runtime */ |
Alexander Usyskin | bb9f4d2 | 2015-08-02 22:20:51 +0300 | [diff] [blame] | 217 | hcsr = mei_hcsr_read(dev); |
Tomas Winkler | e7e0c23 | 2013-01-08 23:07:31 +0200 | [diff] [blame] | 218 | dev->hbuf_depth = (hcsr & H_CBD) >> 24; |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 219 | |
Alexander Usyskin | bb9f4d2 | 2015-08-02 22:20:51 +0300 | [diff] [blame] | 220 | reg = 0; |
| 221 | pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); |
Tomas Winkler | a96c548 | 2016-02-07 22:46:51 +0200 | [diff] [blame] | 222 | trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); |
Alexander Usyskin | bb9f4d2 | 2015-08-02 22:20:51 +0300 | [diff] [blame] | 223 | hw->d0i3_supported = |
| 224 | ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK); |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 225 | |
| 226 | hw->pg_state = MEI_PG_OFF; |
| 227 | if (hw->d0i3_supported) { |
| 228 | reg = mei_me_d0i3c_read(dev); |
| 229 | if (reg & H_D0I3C_I3) |
| 230 | hw->pg_state = MEI_PG_ON; |
| 231 | } |
Tomas Winkler | e7e0c23 | 2013-01-08 23:07:31 +0200 | [diff] [blame] | 232 | } |
Tomas Winkler | 964a233 | 2014-03-18 22:51:59 +0200 | [diff] [blame] | 233 | |
| 234 | /** |
| 235 | * mei_me_pg_state - translate internal pg state |
| 236 | * to the mei power gating state |
| 237 | * |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 238 | * @dev: mei device |
| 239 | * |
| 240 | * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise |
Tomas Winkler | 964a233 | 2014-03-18 22:51:59 +0200 | [diff] [blame] | 241 | */ |
| 242 | static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) |
| 243 | { |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 244 | struct mei_me_hw *hw = to_me_hw(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 245 | |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 246 | return hw->pg_state; |
Tomas Winkler | 964a233 | 2014-03-18 22:51:59 +0200 | [diff] [blame] | 247 | } |
| 248 | |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 249 | /** |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 250 | * mei_me_intr_clear - clear and stop interrupts |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 251 | * |
| 252 | * @dev: the device structure |
| 253 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 254 | static void mei_me_intr_clear(struct mei_device *dev) |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 255 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 256 | u32 hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 257 | |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 258 | if (hcsr & H_CSR_IS_MASK) |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 259 | mei_hcsr_write(dev, hcsr); |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 260 | } |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 261 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 262 | * mei_me_intr_enable - enables mei device interrupts |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 263 | * |
| 264 | * @dev: the device structure |
| 265 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 266 | static void mei_me_intr_enable(struct mei_device *dev) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 267 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 268 | u32 hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 269 | |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 270 | hcsr |= H_CSR_IE_MASK; |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 271 | mei_hcsr_set(dev, hcsr); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | /** |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 275 | * mei_me_intr_disable - disables mei device interrupts |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 276 | * |
| 277 | * @dev: the device structure |
| 278 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 279 | static void mei_me_intr_disable(struct mei_device *dev) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 280 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 281 | u32 hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 282 | |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 283 | hcsr &= ~H_CSR_IE_MASK; |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 284 | mei_hcsr_set(dev, hcsr); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 285 | } |
| 286 | |
Tomas Winkler | adfba32 | 2013-01-08 23:07:27 +0200 | [diff] [blame] | 287 | /** |
Tomas Winkler | 68f8ea1 | 2013-03-10 13:56:07 +0200 | [diff] [blame] | 288 | * mei_me_hw_reset_release - release device from the reset |
| 289 | * |
| 290 | * @dev: the device structure |
| 291 | */ |
| 292 | static void mei_me_hw_reset_release(struct mei_device *dev) |
| 293 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 294 | u32 hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 68f8ea1 | 2013-03-10 13:56:07 +0200 | [diff] [blame] | 295 | |
| 296 | hcsr |= H_IG; |
| 297 | hcsr &= ~H_RST; |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 298 | mei_hcsr_set(dev, hcsr); |
Tomas Winkler | b04ada9 | 2014-05-12 12:19:39 +0300 | [diff] [blame] | 299 | |
| 300 | /* complete this write before we set host ready on another CPU */ |
| 301 | mmiowb(); |
Tomas Winkler | 68f8ea1 | 2013-03-10 13:56:07 +0200 | [diff] [blame] | 302 | } |
Tomas Winkler | adfba32 | 2013-01-08 23:07:27 +0200 | [diff] [blame] | 303 | |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 304 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 305 | * mei_me_host_set_ready - enable device |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 306 | * |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 307 | * @dev: mei device |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 308 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 309 | static void mei_me_host_set_ready(struct mei_device *dev) |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 310 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 311 | u32 hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 312 | |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 313 | hcsr |= H_CSR_IE_MASK | H_IG | H_RDY; |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 314 | mei_hcsr_set(dev, hcsr); |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 315 | } |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 316 | |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 317 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 318 | * mei_me_host_is_ready - check whether the host has turned ready |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 319 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 320 | * @dev: mei device |
| 321 | * Return: bool |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 322 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 323 | static bool mei_me_host_is_ready(struct mei_device *dev) |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 324 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 325 | u32 hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 326 | |
Tomas Winkler | 18caeb7 | 2014-11-12 23:42:14 +0200 | [diff] [blame] | 327 | return (hcsr & H_RDY) == H_RDY; |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 328 | } |
| 329 | |
| 330 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 331 | * mei_me_hw_is_ready - check whether the me(hw) has turned ready |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 332 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 333 | * @dev: mei device |
| 334 | * Return: bool |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 335 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 336 | static bool mei_me_hw_is_ready(struct mei_device *dev) |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 337 | { |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 338 | u32 mecsr = mei_me_mecsr_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 339 | |
Tomas Winkler | 18caeb7 | 2014-11-12 23:42:14 +0200 | [diff] [blame] | 340 | return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; |
Tomas Winkler | 115ba28 | 2013-01-08 23:07:29 +0200 | [diff] [blame] | 341 | } |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 342 | |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 343 | /** |
| 344 | * mei_me_hw_ready_wait - wait until the me(hw) has turned ready |
| 345 | * or timeout is reached |
| 346 | * |
| 347 | * @dev: mei device |
| 348 | * Return: 0 on success, error otherwise |
| 349 | */ |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 350 | static int mei_me_hw_ready_wait(struct mei_device *dev) |
| 351 | { |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 352 | mutex_unlock(&dev->device_lock); |
Alexander Usyskin | 2c2b93e | 2014-08-12 20:16:03 +0300 | [diff] [blame] | 353 | wait_event_timeout(dev->wait_hw_ready, |
Tomas Winkler | dab9bf4 | 2013-07-17 15:13:17 +0300 | [diff] [blame] | 354 | dev->recvd_hw_ready, |
Tomas Winkler | 7d93e58 | 2014-01-14 23:10:10 +0200 | [diff] [blame] | 355 | mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 356 | mutex_lock(&dev->device_lock); |
Alexander Usyskin | 2c2b93e | 2014-08-12 20:16:03 +0300 | [diff] [blame] | 357 | if (!dev->recvd_hw_ready) { |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 358 | dev_err(dev->dev, "wait hw ready failed\n"); |
Alexander Usyskin | 2c2b93e | 2014-08-12 20:16:03 +0300 | [diff] [blame] | 359 | return -ETIME; |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 360 | } |
| 361 | |
Alexander Usyskin | 663b7ee | 2015-01-25 23:45:28 +0200 | [diff] [blame] | 362 | mei_me_hw_reset_release(dev); |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 363 | dev->recvd_hw_ready = false; |
| 364 | return 0; |
| 365 | } |
| 366 | |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 367 | /** |
| 368 | * mei_me_hw_start - hw start routine |
| 369 | * |
| 370 | * @dev: mei device |
| 371 | * Return: 0 on success, error otherwise |
| 372 | */ |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 373 | static int mei_me_hw_start(struct mei_device *dev) |
| 374 | { |
| 375 | int ret = mei_me_hw_ready_wait(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 376 | |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 377 | if (ret) |
| 378 | return ret; |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 379 | dev_dbg(dev->dev, "hw is ready\n"); |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 380 | |
| 381 | mei_me_host_set_ready(dev); |
| 382 | return ret; |
| 383 | } |
| 384 | |
| 385 | |
Tomas Winkler | 3a65dd4 | 2012-12-25 19:06:06 +0200 | [diff] [blame] | 386 | /** |
Tomas Winkler | 726917f | 2012-06-25 23:46:28 +0300 | [diff] [blame] | 387 | * mei_hbuf_filled_slots - gets number of device filled buffer slots |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 388 | * |
Sedat Dilek | 7353f85 | 2013-01-17 19:54:15 +0100 | [diff] [blame] | 389 | * @dev: the device structure |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 390 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 391 | * Return: number of filled slots |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 392 | */ |
Tomas Winkler | 726917f | 2012-06-25 23:46:28 +0300 | [diff] [blame] | 393 | static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 394 | { |
Tomas Winkler | 18caeb7 | 2014-11-12 23:42:14 +0200 | [diff] [blame] | 395 | u32 hcsr; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 396 | char read_ptr, write_ptr; |
| 397 | |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 398 | hcsr = mei_hcsr_read(dev); |
Tomas Winkler | 726917f | 2012-06-25 23:46:28 +0300 | [diff] [blame] | 399 | |
Tomas Winkler | 18caeb7 | 2014-11-12 23:42:14 +0200 | [diff] [blame] | 400 | read_ptr = (char) ((hcsr & H_CBRP) >> 8); |
| 401 | write_ptr = (char) ((hcsr & H_CBWP) >> 16); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 402 | |
| 403 | return (unsigned char) (write_ptr - read_ptr); |
| 404 | } |
| 405 | |
| 406 | /** |
Masanari Iida | 393b148 | 2013-04-05 01:05:05 +0900 | [diff] [blame] | 407 | * mei_me_hbuf_is_empty - checks if host buffer is empty. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 408 | * |
| 409 | * @dev: the device structure |
| 410 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 411 | * Return: true if empty, false - otherwise. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 412 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 413 | static bool mei_me_hbuf_is_empty(struct mei_device *dev) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 414 | { |
Tomas Winkler | 726917f | 2012-06-25 23:46:28 +0300 | [diff] [blame] | 415 | return mei_hbuf_filled_slots(dev) == 0; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 416 | } |
| 417 | |
| 418 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 419 | * mei_me_hbuf_empty_slots - counts write empty slots. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 420 | * |
| 421 | * @dev: the device structure |
| 422 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 423 | * Return: -EOVERFLOW if overflow, otherwise empty slots count |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 424 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 425 | static int mei_me_hbuf_empty_slots(struct mei_device *dev) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 426 | { |
Tomas Winkler | 24aadc8 | 2012-06-25 23:46:27 +0300 | [diff] [blame] | 427 | unsigned char filled_slots, empty_slots; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 428 | |
Tomas Winkler | 726917f | 2012-06-25 23:46:28 +0300 | [diff] [blame] | 429 | filled_slots = mei_hbuf_filled_slots(dev); |
Tomas Winkler | 24aadc8 | 2012-06-25 23:46:27 +0300 | [diff] [blame] | 430 | empty_slots = dev->hbuf_depth - filled_slots; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 431 | |
| 432 | /* check for overflow */ |
Tomas Winkler | 24aadc8 | 2012-06-25 23:46:27 +0300 | [diff] [blame] | 433 | if (filled_slots > dev->hbuf_depth) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 434 | return -EOVERFLOW; |
| 435 | |
| 436 | return empty_slots; |
| 437 | } |
| 438 | |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 439 | /** |
| 440 | * mei_me_hbuf_max_len - returns size of hw buffer. |
| 441 | * |
| 442 | * @dev: the device structure |
| 443 | * |
| 444 | * Return: size of hw buffer in bytes |
| 445 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 446 | static size_t mei_me_hbuf_max_len(const struct mei_device *dev) |
| 447 | { |
| 448 | return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); |
| 449 | } |
| 450 | |
| 451 | |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 452 | /** |
Alexander Usyskin | 7ca96aa | 2014-02-19 17:35:49 +0200 | [diff] [blame] | 453 | * mei_me_write_message - writes a message to mei device. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 454 | * |
| 455 | * @dev: the device structure |
Sedat Dilek | 7353f85 | 2013-01-17 19:54:15 +0100 | [diff] [blame] | 456 | * @header: mei HECI header of message |
Tomas Winkler | 438763f | 2012-12-25 19:05:59 +0200 | [diff] [blame] | 457 | * @buf: message payload will be written |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 458 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 459 | * Return: -EIO if write has failed |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 460 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 461 | static int mei_me_write_message(struct mei_device *dev, |
| 462 | struct mei_msg_hdr *header, |
| 463 | unsigned char *buf) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 464 | { |
Tomas Winkler | c8c8d08 | 2013-03-11 18:27:02 +0200 | [diff] [blame] | 465 | unsigned long rem; |
Tomas Winkler | 438763f | 2012-12-25 19:05:59 +0200 | [diff] [blame] | 466 | unsigned long length = header->length; |
Tomas Winkler | 169d133 | 2012-06-19 09:13:35 +0300 | [diff] [blame] | 467 | u32 *reg_buf = (u32 *)buf; |
Tomas Winkler | 88eb99f | 2013-01-08 23:07:30 +0200 | [diff] [blame] | 468 | u32 hcsr; |
Tomas Winkler | c8c8d08 | 2013-03-11 18:27:02 +0200 | [diff] [blame] | 469 | u32 dw_cnt; |
Tomas Winkler | 169d133 | 2012-06-19 09:13:35 +0300 | [diff] [blame] | 470 | int i; |
| 471 | int empty_slots; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 472 | |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 473 | dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 474 | |
Tomas Winkler | 726917f | 2012-06-25 23:46:28 +0300 | [diff] [blame] | 475 | empty_slots = mei_hbuf_empty_slots(dev); |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 476 | dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 477 | |
Tomas Winkler | 7bdf72d | 2012-07-04 19:24:52 +0300 | [diff] [blame] | 478 | dw_cnt = mei_data2slots(length); |
Tomas Winkler | 169d133 | 2012-06-19 09:13:35 +0300 | [diff] [blame] | 479 | if (empty_slots < 0 || dw_cnt > empty_slots) |
Tomas Winkler | 9d09819 | 2014-02-19 17:35:48 +0200 | [diff] [blame] | 480 | return -EMSGSIZE; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 481 | |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 482 | mei_me_hcbww_write(dev, *((u32 *) header)); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 483 | |
Tomas Winkler | 169d133 | 2012-06-19 09:13:35 +0300 | [diff] [blame] | 484 | for (i = 0; i < length / 4; i++) |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 485 | mei_me_hcbww_write(dev, reg_buf[i]); |
Tomas Winkler | 169d133 | 2012-06-19 09:13:35 +0300 | [diff] [blame] | 486 | |
| 487 | rem = length & 0x3; |
| 488 | if (rem > 0) { |
| 489 | u32 reg = 0; |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 490 | |
Tomas Winkler | 169d133 | 2012-06-19 09:13:35 +0300 | [diff] [blame] | 491 | memcpy(®, &buf[length - rem], rem); |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 492 | mei_me_hcbww_write(dev, reg); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 493 | } |
| 494 | |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 495 | hcsr = mei_hcsr_read(dev) | H_IG; |
| 496 | mei_hcsr_set(dev, hcsr); |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 497 | if (!mei_me_hw_is_ready(dev)) |
Tomas Winkler | 1ccb7b6 | 2012-03-14 14:39:42 +0200 | [diff] [blame] | 498 | return -EIO; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 499 | |
Tomas Winkler | 1ccb7b6 | 2012-03-14 14:39:42 +0200 | [diff] [blame] | 500 | return 0; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 504 | * mei_me_count_full_read_slots - counts read full slots. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 505 | * |
| 506 | * @dev: the device structure |
| 507 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 508 | * Return: -EOVERFLOW if overflow, otherwise filled slots count |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 509 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 510 | static int mei_me_count_full_read_slots(struct mei_device *dev) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 511 | { |
Tomas Winkler | 18caeb7 | 2014-11-12 23:42:14 +0200 | [diff] [blame] | 512 | u32 me_csr; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 513 | char read_ptr, write_ptr; |
| 514 | unsigned char buffer_depth, filled_slots; |
| 515 | |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 516 | me_csr = mei_me_mecsr_read(dev); |
Tomas Winkler | 18caeb7 | 2014-11-12 23:42:14 +0200 | [diff] [blame] | 517 | buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); |
| 518 | read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); |
| 519 | write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 520 | filled_slots = (unsigned char) (write_ptr - read_ptr); |
| 521 | |
| 522 | /* check for overflow */ |
| 523 | if (filled_slots > buffer_depth) |
| 524 | return -EOVERFLOW; |
| 525 | |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 526 | dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 527 | return (int)filled_slots; |
| 528 | } |
| 529 | |
| 530 | /** |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 531 | * mei_me_read_slots - reads a message from mei device. |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 532 | * |
| 533 | * @dev: the device structure |
| 534 | * @buffer: message buffer will be written |
| 535 | * @buffer_length: message size will be read |
Alexander Usyskin | ce23139 | 2014-09-29 16:31:50 +0300 | [diff] [blame] | 536 | * |
| 537 | * Return: always 0 |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 538 | */ |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 539 | static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, |
Tomas Winkler | edf1eed | 2012-02-09 19:25:54 +0200 | [diff] [blame] | 540 | unsigned long buffer_length) |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 541 | { |
Tomas Winkler | edf1eed | 2012-02-09 19:25:54 +0200 | [diff] [blame] | 542 | u32 *reg_buf = (u32 *)buffer; |
Tomas Winkler | 88eb99f | 2013-01-08 23:07:30 +0200 | [diff] [blame] | 543 | u32 hcsr; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 544 | |
Tomas Winkler | edf1eed | 2012-02-09 19:25:54 +0200 | [diff] [blame] | 545 | for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 546 | *reg_buf++ = mei_me_mecbrw_read(dev); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 547 | |
| 548 | if (buffer_length > 0) { |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 549 | u32 reg = mei_me_mecbrw_read(dev); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 550 | |
Tomas Winkler | edf1eed | 2012-02-09 19:25:54 +0200 | [diff] [blame] | 551 | memcpy(reg_buf, ®, buffer_length); |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 552 | } |
| 553 | |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 554 | hcsr = mei_hcsr_read(dev) | H_IG; |
| 555 | mei_hcsr_set(dev, hcsr); |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 556 | return 0; |
Oren Weil | 3ce7272 | 2011-05-15 13:43:43 +0300 | [diff] [blame] | 557 | } |
| 558 | |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 559 | /** |
Alexander Usyskin | 2d1995f | 2015-02-10 10:39:34 +0200 | [diff] [blame] | 560 | * mei_me_pg_set - write pg enter register |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 561 | * |
| 562 | * @dev: the device structure |
| 563 | */ |
Alexander Usyskin | 2d1995f | 2015-02-10 10:39:34 +0200 | [diff] [blame] | 564 | static void mei_me_pg_set(struct mei_device *dev) |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 565 | { |
| 566 | struct mei_me_hw *hw = to_me_hw(dev); |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 567 | u32 reg; |
| 568 | |
| 569 | reg = mei_me_reg_read(hw, H_HPG_CSR); |
| 570 | trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 571 | |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 572 | reg |= H_HPG_CSR_PGI; |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 573 | |
| 574 | trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 575 | mei_me_reg_write(hw, H_HPG_CSR, reg); |
| 576 | } |
| 577 | |
| 578 | /** |
Alexander Usyskin | 2d1995f | 2015-02-10 10:39:34 +0200 | [diff] [blame] | 579 | * mei_me_pg_unset - write pg exit register |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 580 | * |
| 581 | * @dev: the device structure |
| 582 | */ |
Alexander Usyskin | 2d1995f | 2015-02-10 10:39:34 +0200 | [diff] [blame] | 583 | static void mei_me_pg_unset(struct mei_device *dev) |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 584 | { |
| 585 | struct mei_me_hw *hw = to_me_hw(dev); |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 586 | u32 reg; |
| 587 | |
| 588 | reg = mei_me_reg_read(hw, H_HPG_CSR); |
| 589 | trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 590 | |
| 591 | WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); |
| 592 | |
| 593 | reg |= H_HPG_CSR_PGIHEXR; |
Tomas Winkler | a0a927d | 2015-02-10 10:39:33 +0200 | [diff] [blame] | 594 | |
| 595 | trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); |
Tomas Winkler | b16c357 | 2014-03-18 22:51:57 +0200 | [diff] [blame] | 596 | mei_me_reg_write(hw, H_HPG_CSR, reg); |
| 597 | } |
| 598 | |
| 599 | /** |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 600 | * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 601 | * |
| 602 | * @dev: the device structure |
| 603 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 604 | * Return: 0 on success an error code otherwise |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 605 | */ |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 606 | static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 607 | { |
| 608 | struct mei_me_hw *hw = to_me_hw(dev); |
| 609 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); |
| 610 | int ret; |
| 611 | |
| 612 | dev->pg_event = MEI_PG_EVENT_WAIT; |
| 613 | |
| 614 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); |
| 615 | if (ret) |
| 616 | return ret; |
| 617 | |
| 618 | mutex_unlock(&dev->device_lock); |
| 619 | wait_event_timeout(dev->wait_pg, |
| 620 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); |
| 621 | mutex_lock(&dev->device_lock); |
| 622 | |
| 623 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { |
Alexander Usyskin | 2d1995f | 2015-02-10 10:39:34 +0200 | [diff] [blame] | 624 | mei_me_pg_set(dev); |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 625 | ret = 0; |
| 626 | } else { |
| 627 | ret = -ETIME; |
| 628 | } |
| 629 | |
| 630 | dev->pg_event = MEI_PG_EVENT_IDLE; |
| 631 | hw->pg_state = MEI_PG_ON; |
| 632 | |
| 633 | return ret; |
| 634 | } |
| 635 | |
| 636 | /** |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 637 | * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 638 | * |
| 639 | * @dev: the device structure |
| 640 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 641 | * Return: 0 on success an error code otherwise |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 642 | */ |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 643 | static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 644 | { |
| 645 | struct mei_me_hw *hw = to_me_hw(dev); |
| 646 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); |
| 647 | int ret; |
| 648 | |
| 649 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) |
| 650 | goto reply; |
| 651 | |
| 652 | dev->pg_event = MEI_PG_EVENT_WAIT; |
| 653 | |
Alexander Usyskin | 2d1995f | 2015-02-10 10:39:34 +0200 | [diff] [blame] | 654 | mei_me_pg_unset(dev); |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 655 | |
| 656 | mutex_unlock(&dev->device_lock); |
| 657 | wait_event_timeout(dev->wait_pg, |
| 658 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); |
| 659 | mutex_lock(&dev->device_lock); |
| 660 | |
| 661 | reply: |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 662 | if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { |
| 663 | ret = -ETIME; |
| 664 | goto out; |
| 665 | } |
| 666 | |
| 667 | dev->pg_event = MEI_PG_EVENT_INTR_WAIT; |
| 668 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); |
| 669 | if (ret) |
| 670 | return ret; |
| 671 | |
| 672 | mutex_unlock(&dev->device_lock); |
| 673 | wait_event_timeout(dev->wait_pg, |
| 674 | dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); |
| 675 | mutex_lock(&dev->device_lock); |
| 676 | |
| 677 | if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED) |
| 678 | ret = 0; |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 679 | else |
| 680 | ret = -ETIME; |
| 681 | |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 682 | out: |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 683 | dev->pg_event = MEI_PG_EVENT_IDLE; |
| 684 | hw->pg_state = MEI_PG_OFF; |
| 685 | |
| 686 | return ret; |
| 687 | } |
| 688 | |
| 689 | /** |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 690 | * mei_me_pg_in_transition - is device now in pg transition |
| 691 | * |
| 692 | * @dev: the device structure |
| 693 | * |
| 694 | * Return: true if in pg transition, false otherwise |
| 695 | */ |
| 696 | static bool mei_me_pg_in_transition(struct mei_device *dev) |
| 697 | { |
| 698 | return dev->pg_event >= MEI_PG_EVENT_WAIT && |
| 699 | dev->pg_event <= MEI_PG_EVENT_INTR_WAIT; |
| 700 | } |
| 701 | |
| 702 | /** |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 703 | * mei_me_pg_is_enabled - detect if PG is supported by HW |
| 704 | * |
| 705 | * @dev: the device structure |
| 706 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 707 | * Return: true is pg supported, false otherwise |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 708 | */ |
| 709 | static bool mei_me_pg_is_enabled(struct mei_device *dev) |
| 710 | { |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 711 | struct mei_me_hw *hw = to_me_hw(dev); |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 712 | u32 reg = mei_me_mecsr_read(dev); |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 713 | |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 714 | if (hw->d0i3_supported) |
| 715 | return true; |
| 716 | |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 717 | if ((reg & ME_PGIC_HRA) == 0) |
| 718 | goto notsupported; |
| 719 | |
Tomas Winkler | bae1cc7 | 2014-08-21 14:29:21 +0300 | [diff] [blame] | 720 | if (!dev->hbm_f_pg_supported) |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 721 | goto notsupported; |
| 722 | |
| 723 | return true; |
| 724 | |
| 725 | notsupported: |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 726 | dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n", |
| 727 | hw->d0i3_supported, |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 728 | !!(reg & ME_PGIC_HRA), |
| 729 | dev->version.major_version, |
| 730 | dev->version.minor_version, |
| 731 | HBM_MAJOR_VERSION_PGI, |
| 732 | HBM_MINOR_VERSION_PGI); |
| 733 | |
| 734 | return false; |
| 735 | } |
| 736 | |
| 737 | /** |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 738 | * mei_me_d0i3_set - write d0i3 register bit on mei device. |
| 739 | * |
| 740 | * @dev: the device structure |
| 741 | * @intr: ask for interrupt |
| 742 | * |
| 743 | * Return: D0I3C register value |
| 744 | */ |
| 745 | static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr) |
| 746 | { |
| 747 | u32 reg = mei_me_d0i3c_read(dev); |
| 748 | |
| 749 | reg |= H_D0I3C_I3; |
| 750 | if (intr) |
| 751 | reg |= H_D0I3C_IR; |
| 752 | else |
| 753 | reg &= ~H_D0I3C_IR; |
| 754 | mei_me_d0i3c_write(dev, reg); |
| 755 | /* read it to ensure HW consistency */ |
| 756 | reg = mei_me_d0i3c_read(dev); |
| 757 | return reg; |
| 758 | } |
| 759 | |
| 760 | /** |
| 761 | * mei_me_d0i3_unset - clean d0i3 register bit on mei device. |
| 762 | * |
| 763 | * @dev: the device structure |
| 764 | * |
| 765 | * Return: D0I3C register value |
| 766 | */ |
| 767 | static u32 mei_me_d0i3_unset(struct mei_device *dev) |
| 768 | { |
| 769 | u32 reg = mei_me_d0i3c_read(dev); |
| 770 | |
| 771 | reg &= ~H_D0I3C_I3; |
| 772 | reg |= H_D0I3C_IR; |
| 773 | mei_me_d0i3c_write(dev, reg); |
| 774 | /* read it to ensure HW consistency */ |
| 775 | reg = mei_me_d0i3c_read(dev); |
| 776 | return reg; |
| 777 | } |
| 778 | |
| 779 | /** |
| 780 | * mei_me_d0i3_enter_sync - perform d0i3 entry procedure |
| 781 | * |
| 782 | * @dev: the device structure |
| 783 | * |
| 784 | * Return: 0 on success an error code otherwise |
| 785 | */ |
| 786 | static int mei_me_d0i3_enter_sync(struct mei_device *dev) |
| 787 | { |
| 788 | struct mei_me_hw *hw = to_me_hw(dev); |
| 789 | unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); |
| 790 | unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); |
| 791 | int ret; |
| 792 | u32 reg; |
| 793 | |
| 794 | reg = mei_me_d0i3c_read(dev); |
| 795 | if (reg & H_D0I3C_I3) { |
| 796 | /* we are in d0i3, nothing to do */ |
| 797 | dev_dbg(dev->dev, "d0i3 set not needed\n"); |
| 798 | ret = 0; |
| 799 | goto on; |
| 800 | } |
| 801 | |
| 802 | /* PGI entry procedure */ |
| 803 | dev->pg_event = MEI_PG_EVENT_WAIT; |
| 804 | |
| 805 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); |
| 806 | if (ret) |
| 807 | /* FIXME: should we reset here? */ |
| 808 | goto out; |
| 809 | |
| 810 | mutex_unlock(&dev->device_lock); |
| 811 | wait_event_timeout(dev->wait_pg, |
| 812 | dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout); |
| 813 | mutex_lock(&dev->device_lock); |
| 814 | |
| 815 | if (dev->pg_event != MEI_PG_EVENT_RECEIVED) { |
| 816 | ret = -ETIME; |
| 817 | goto out; |
| 818 | } |
| 819 | /* end PGI entry procedure */ |
| 820 | |
| 821 | dev->pg_event = MEI_PG_EVENT_INTR_WAIT; |
| 822 | |
| 823 | reg = mei_me_d0i3_set(dev, true); |
| 824 | if (!(reg & H_D0I3C_CIP)) { |
| 825 | dev_dbg(dev->dev, "d0i3 enter wait not needed\n"); |
| 826 | ret = 0; |
| 827 | goto on; |
| 828 | } |
| 829 | |
| 830 | mutex_unlock(&dev->device_lock); |
| 831 | wait_event_timeout(dev->wait_pg, |
| 832 | dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); |
| 833 | mutex_lock(&dev->device_lock); |
| 834 | |
| 835 | if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { |
| 836 | reg = mei_me_d0i3c_read(dev); |
| 837 | if (!(reg & H_D0I3C_I3)) { |
| 838 | ret = -ETIME; |
| 839 | goto out; |
| 840 | } |
| 841 | } |
| 842 | |
| 843 | ret = 0; |
| 844 | on: |
| 845 | hw->pg_state = MEI_PG_ON; |
| 846 | out: |
| 847 | dev->pg_event = MEI_PG_EVENT_IDLE; |
| 848 | dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret); |
| 849 | return ret; |
| 850 | } |
| 851 | |
| 852 | /** |
| 853 | * mei_me_d0i3_enter - perform d0i3 entry procedure |
| 854 | * no hbm PG handshake |
| 855 | * no waiting for confirmation; runs with interrupts |
| 856 | * disabled |
| 857 | * |
| 858 | * @dev: the device structure |
| 859 | * |
| 860 | * Return: 0 on success an error code otherwise |
| 861 | */ |
| 862 | static int mei_me_d0i3_enter(struct mei_device *dev) |
| 863 | { |
| 864 | struct mei_me_hw *hw = to_me_hw(dev); |
| 865 | u32 reg; |
| 866 | |
| 867 | reg = mei_me_d0i3c_read(dev); |
| 868 | if (reg & H_D0I3C_I3) { |
| 869 | /* we are in d0i3, nothing to do */ |
| 870 | dev_dbg(dev->dev, "already d0i3 : set not needed\n"); |
| 871 | goto on; |
| 872 | } |
| 873 | |
| 874 | mei_me_d0i3_set(dev, false); |
| 875 | on: |
| 876 | hw->pg_state = MEI_PG_ON; |
| 877 | dev->pg_event = MEI_PG_EVENT_IDLE; |
| 878 | dev_dbg(dev->dev, "d0i3 enter\n"); |
| 879 | return 0; |
| 880 | } |
| 881 | |
| 882 | /** |
| 883 | * mei_me_d0i3_exit_sync - perform d0i3 exit procedure |
| 884 | * |
| 885 | * @dev: the device structure |
| 886 | * |
| 887 | * Return: 0 on success an error code otherwise |
| 888 | */ |
| 889 | static int mei_me_d0i3_exit_sync(struct mei_device *dev) |
| 890 | { |
| 891 | struct mei_me_hw *hw = to_me_hw(dev); |
| 892 | unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); |
| 893 | int ret; |
| 894 | u32 reg; |
| 895 | |
| 896 | dev->pg_event = MEI_PG_EVENT_INTR_WAIT; |
| 897 | |
| 898 | reg = mei_me_d0i3c_read(dev); |
| 899 | if (!(reg & H_D0I3C_I3)) { |
| 900 | /* we are not in d0i3, nothing to do */ |
| 901 | dev_dbg(dev->dev, "d0i3 exit not needed\n"); |
| 902 | ret = 0; |
| 903 | goto off; |
| 904 | } |
| 905 | |
| 906 | reg = mei_me_d0i3_unset(dev); |
| 907 | if (!(reg & H_D0I3C_CIP)) { |
| 908 | dev_dbg(dev->dev, "d0i3 exit wait not needed\n"); |
| 909 | ret = 0; |
| 910 | goto off; |
| 911 | } |
| 912 | |
| 913 | mutex_unlock(&dev->device_lock); |
| 914 | wait_event_timeout(dev->wait_pg, |
| 915 | dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout); |
| 916 | mutex_lock(&dev->device_lock); |
| 917 | |
| 918 | if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) { |
| 919 | reg = mei_me_d0i3c_read(dev); |
| 920 | if (reg & H_D0I3C_I3) { |
| 921 | ret = -ETIME; |
| 922 | goto out; |
| 923 | } |
| 924 | } |
| 925 | |
| 926 | ret = 0; |
| 927 | off: |
| 928 | hw->pg_state = MEI_PG_OFF; |
| 929 | out: |
| 930 | dev->pg_event = MEI_PG_EVENT_IDLE; |
| 931 | |
| 932 | dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret); |
| 933 | return ret; |
| 934 | } |
| 935 | |
| 936 | /** |
| 937 | * mei_me_pg_legacy_intr - perform legacy pg processing |
| 938 | * in interrupt thread handler |
| 939 | * |
| 940 | * @dev: the device structure |
| 941 | */ |
| 942 | static void mei_me_pg_legacy_intr(struct mei_device *dev) |
| 943 | { |
| 944 | struct mei_me_hw *hw = to_me_hw(dev); |
| 945 | |
| 946 | if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT) |
| 947 | return; |
| 948 | |
| 949 | dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; |
| 950 | hw->pg_state = MEI_PG_OFF; |
| 951 | if (waitqueue_active(&dev->wait_pg)) |
| 952 | wake_up(&dev->wait_pg); |
| 953 | } |
| 954 | |
| 955 | /** |
| 956 | * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler |
| 957 | * |
| 958 | * @dev: the device structure |
| 959 | */ |
| 960 | static void mei_me_d0i3_intr(struct mei_device *dev) |
| 961 | { |
| 962 | struct mei_me_hw *hw = to_me_hw(dev); |
| 963 | |
| 964 | if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT && |
| 965 | (hw->intr_source & H_D0I3C_IS)) { |
| 966 | dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED; |
| 967 | if (hw->pg_state == MEI_PG_ON) { |
| 968 | hw->pg_state = MEI_PG_OFF; |
| 969 | if (dev->hbm_state != MEI_HBM_IDLE) { |
| 970 | /* |
| 971 | * force H_RDY because it could be |
| 972 | * wiped off during PG |
| 973 | */ |
| 974 | dev_dbg(dev->dev, "d0i3 set host ready\n"); |
| 975 | mei_me_host_set_ready(dev); |
| 976 | } |
| 977 | } else { |
| 978 | hw->pg_state = MEI_PG_ON; |
| 979 | } |
| 980 | |
| 981 | wake_up(&dev->wait_pg); |
| 982 | } |
| 983 | |
| 984 | if (hw->pg_state == MEI_PG_ON && (hw->intr_source & H_IS)) { |
| 985 | /* |
| 986 | * HW sent some data and we are in D0i3, so |
| 987 | * we got here because of HW initiated exit from D0i3. |
| 988 | * Start runtime pm resume sequence to exit low power state. |
| 989 | */ |
| 990 | dev_dbg(dev->dev, "d0i3 want resume\n"); |
| 991 | mei_hbm_pg_resume(dev); |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | /** |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 996 | * mei_me_pg_intr - perform pg processing in interrupt thread handler |
| 997 | * |
| 998 | * @dev: the device structure |
| 999 | */ |
| 1000 | static void mei_me_pg_intr(struct mei_device *dev) |
| 1001 | { |
| 1002 | struct mei_me_hw *hw = to_me_hw(dev); |
| 1003 | |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 1004 | if (hw->d0i3_supported) |
| 1005 | mei_me_d0i3_intr(dev); |
| 1006 | else |
| 1007 | mei_me_pg_legacy_intr(dev); |
| 1008 | } |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 1009 | |
Alexander Usyskin | 859ef2f | 2015-08-02 22:20:54 +0300 | [diff] [blame] | 1010 | /** |
| 1011 | * mei_me_pg_enter_sync - perform runtime pm entry procedure |
| 1012 | * |
| 1013 | * @dev: the device structure |
| 1014 | * |
| 1015 | * Return: 0 on success an error code otherwise |
| 1016 | */ |
| 1017 | int mei_me_pg_enter_sync(struct mei_device *dev) |
| 1018 | { |
| 1019 | struct mei_me_hw *hw = to_me_hw(dev); |
| 1020 | |
| 1021 | if (hw->d0i3_supported) |
| 1022 | return mei_me_d0i3_enter_sync(dev); |
| 1023 | else |
| 1024 | return mei_me_pg_legacy_enter_sync(dev); |
| 1025 | } |
| 1026 | |
| 1027 | /** |
| 1028 | * mei_me_pg_exit_sync - perform runtime pm exit procedure |
| 1029 | * |
| 1030 | * @dev: the device structure |
| 1031 | * |
| 1032 | * Return: 0 on success an error code otherwise |
| 1033 | */ |
| 1034 | int mei_me_pg_exit_sync(struct mei_device *dev) |
| 1035 | { |
| 1036 | struct mei_me_hw *hw = to_me_hw(dev); |
| 1037 | |
| 1038 | if (hw->d0i3_supported) |
| 1039 | return mei_me_d0i3_exit_sync(dev); |
| 1040 | else |
| 1041 | return mei_me_pg_legacy_exit_sync(dev); |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 1042 | } |
| 1043 | |
| 1044 | /** |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1045 | * mei_me_hw_reset - resets fw via mei csr register. |
| 1046 | * |
| 1047 | * @dev: the device structure |
| 1048 | * @intr_enable: if interrupt should be enabled after reset. |
| 1049 | * |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1050 | * Return: 0 on success an error code otherwise |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1051 | */ |
| 1052 | static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) |
| 1053 | { |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1054 | struct mei_me_hw *hw = to_me_hw(dev); |
| 1055 | int ret; |
| 1056 | u32 hcsr; |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1057 | |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1058 | if (intr_enable) { |
| 1059 | mei_me_intr_enable(dev); |
| 1060 | if (hw->d0i3_supported) { |
| 1061 | ret = mei_me_d0i3_exit_sync(dev); |
| 1062 | if (ret) |
| 1063 | return ret; |
| 1064 | } |
| 1065 | } |
| 1066 | |
Alexander Usyskin | 77537ad | 2016-06-16 17:58:52 +0300 | [diff] [blame] | 1067 | pm_runtime_set_active(dev->dev); |
| 1068 | |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1069 | hcsr = mei_hcsr_read(dev); |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1070 | /* H_RST may be found lit before reset is started, |
| 1071 | * for example if preceding reset flow hasn't completed. |
| 1072 | * In that case asserting H_RST will be ignored, therefore |
| 1073 | * we need to clean H_RST bit to start a successful reset sequence. |
| 1074 | */ |
| 1075 | if ((hcsr & H_RST) == H_RST) { |
| 1076 | dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); |
| 1077 | hcsr &= ~H_RST; |
| 1078 | mei_hcsr_set(dev, hcsr); |
| 1079 | hcsr = mei_hcsr_read(dev); |
| 1080 | } |
| 1081 | |
| 1082 | hcsr |= H_RST | H_IG | H_CSR_IS_MASK; |
| 1083 | |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1084 | if (!intr_enable) |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1085 | hcsr &= ~H_CSR_IE_MASK; |
| 1086 | |
| 1087 | dev->recvd_hw_ready = false; |
| 1088 | mei_hcsr_write(dev, hcsr); |
| 1089 | |
| 1090 | /* |
| 1091 | * Host reads the H_CSR once to ensure that the |
| 1092 | * posted write to H_CSR completes. |
| 1093 | */ |
| 1094 | hcsr = mei_hcsr_read(dev); |
| 1095 | |
| 1096 | if ((hcsr & H_RST) == 0) |
| 1097 | dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); |
| 1098 | |
| 1099 | if ((hcsr & H_RDY) == H_RDY) |
| 1100 | dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); |
| 1101 | |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1102 | if (!intr_enable) { |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1103 | mei_me_hw_reset_release(dev); |
Alexander Usyskin | b9a1fc9 | 2015-08-02 22:20:56 +0300 | [diff] [blame] | 1104 | if (hw->d0i3_supported) { |
| 1105 | ret = mei_me_d0i3_enter(dev); |
| 1106 | if (ret) |
| 1107 | return ret; |
| 1108 | } |
| 1109 | } |
Alexander Usyskin | ebad6b9 | 2015-08-02 22:20:55 +0300 | [diff] [blame] | 1110 | return 0; |
| 1111 | } |
| 1112 | |
| 1113 | /** |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1114 | * mei_me_irq_quick_handler - The ISR of the MEI device |
| 1115 | * |
| 1116 | * @irq: The irq number |
| 1117 | * @dev_id: pointer to the device structure |
| 1118 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 1119 | * Return: irqreturn_t |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1120 | */ |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1121 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) |
| 1122 | { |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 1123 | struct mei_device *dev = (struct mei_device *)dev_id; |
| 1124 | struct mei_me_hw *hw = to_me_hw(dev); |
| 1125 | u32 hcsr; |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1126 | |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 1127 | hcsr = mei_hcsr_read(dev); |
| 1128 | if (!(hcsr & H_CSR_IS_MASK)) |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1129 | return IRQ_NONE; |
| 1130 | |
Alexander Usyskin | 1fa55b4 | 2015-08-02 22:20:52 +0300 | [diff] [blame] | 1131 | hw->intr_source = hcsr & H_CSR_IS_MASK; |
| 1132 | dev_dbg(dev->dev, "interrupt source 0x%08X.\n", hw->intr_source); |
| 1133 | |
| 1134 | /* clear H_IS and H_D0I3C_IS bits in H_CSR to clear the interrupts */ |
Tomas Winkler | 381a58c | 2015-02-10 10:39:32 +0200 | [diff] [blame] | 1135 | mei_hcsr_write(dev, hcsr); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1136 | |
| 1137 | return IRQ_WAKE_THREAD; |
| 1138 | } |
| 1139 | |
| 1140 | /** |
| 1141 | * mei_me_irq_thread_handler - function called after ISR to handle the interrupt |
| 1142 | * processing. |
| 1143 | * |
| 1144 | * @irq: The irq number |
| 1145 | * @dev_id: pointer to the device structure |
| 1146 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 1147 | * Return: irqreturn_t |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1148 | * |
| 1149 | */ |
| 1150 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) |
| 1151 | { |
| 1152 | struct mei_device *dev = (struct mei_device *) dev_id; |
| 1153 | struct mei_cl_cb complete_list; |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1154 | s32 slots; |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1155 | int rets = 0; |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1156 | |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1157 | dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1158 | /* initialize our complete list */ |
| 1159 | mutex_lock(&dev->device_lock); |
| 1160 | mei_io_list_init(&complete_list); |
| 1161 | |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1162 | /* check if ME wants a reset */ |
Tomas Winkler | 33ec082 | 2014-01-12 00:36:09 +0200 | [diff] [blame] | 1163 | if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1164 | dev_warn(dev->dev, "FW not ready: resetting.\n"); |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1165 | schedule_work(&dev->reset_work); |
| 1166 | goto end; |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1167 | } |
| 1168 | |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 1169 | mei_me_pg_intr(dev); |
| 1170 | |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1171 | /* check if we need to start the dev */ |
| 1172 | if (!mei_host_is_ready(dev)) { |
| 1173 | if (mei_hw_is_ready(dev)) { |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1174 | dev_dbg(dev->dev, "we need to start the dev.\n"); |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 1175 | dev->recvd_hw_ready = true; |
Alexander Usyskin | 2c2b93e | 2014-08-12 20:16:03 +0300 | [diff] [blame] | 1176 | wake_up(&dev->wait_hw_ready); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1177 | } else { |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1178 | dev_dbg(dev->dev, "Spurious Interrupt\n"); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1179 | } |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1180 | goto end; |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1181 | } |
| 1182 | /* check slots available for reading */ |
| 1183 | slots = mei_count_full_read_slots(dev); |
| 1184 | while (slots > 0) { |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1185 | dev_dbg(dev->dev, "slots to read = %08x\n", slots); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1186 | rets = mei_irq_read_handler(dev, &complete_list, &slots); |
Tomas Winkler | b1b94b5 | 2014-03-03 00:21:28 +0200 | [diff] [blame] | 1187 | /* There is a race between ME write and interrupt delivery: |
| 1188 | * Not all data is always available immediately after the |
| 1189 | * interrupt, so try to read again on the next interrupt. |
| 1190 | */ |
| 1191 | if (rets == -ENODATA) |
| 1192 | break; |
| 1193 | |
Tomas Winkler | 33ec082 | 2014-01-12 00:36:09 +0200 | [diff] [blame] | 1194 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1195 | dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", |
Tomas Winkler | b1b94b5 | 2014-03-03 00:21:28 +0200 | [diff] [blame] | 1196 | rets); |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1197 | schedule_work(&dev->reset_work); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1198 | goto end; |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1199 | } |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1200 | } |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1201 | |
Tomas Winkler | 6aae48f | 2014-02-19 17:35:47 +0200 | [diff] [blame] | 1202 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); |
| 1203 | |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 1204 | /* |
| 1205 | * During PG handshake only allowed write is the replay to the |
| 1206 | * PG exit message, so block calling write function |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 1207 | * if the pg event is in PG handshake |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 1208 | */ |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 1209 | if (dev->pg_event != MEI_PG_EVENT_WAIT && |
| 1210 | dev->pg_event != MEI_PG_EVENT_RECEIVED) { |
Tomas Winkler | ba9cdd0 | 2014-03-18 22:52:00 +0200 | [diff] [blame] | 1211 | rets = mei_irq_write_handler(dev, &complete_list); |
| 1212 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); |
| 1213 | } |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1214 | |
Tomas Winkler | 4c6e22b | 2013-03-17 11:41:20 +0200 | [diff] [blame] | 1215 | mei_irq_compl_handler(dev, &complete_list); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1216 | |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1217 | end: |
Tomas Winkler | 2bf94cab | 2014-09-29 16:31:42 +0300 | [diff] [blame] | 1218 | dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); |
Tomas Winkler | 544f946 | 2014-01-08 20:19:21 +0200 | [diff] [blame] | 1219 | mutex_unlock(&dev->device_lock); |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1220 | return IRQ_HANDLED; |
| 1221 | } |
Alexander Usyskin | 04dd366 | 2014-03-31 17:59:23 +0300 | [diff] [blame] | 1222 | |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 1223 | static const struct mei_hw_ops mei_me_hw_ops = { |
| 1224 | |
Tomas Winkler | 1bd30b6 | 2014-09-29 16:31:43 +0300 | [diff] [blame] | 1225 | .fw_status = mei_me_fw_status, |
Tomas Winkler | 964a233 | 2014-03-18 22:51:59 +0200 | [diff] [blame] | 1226 | .pg_state = mei_me_pg_state, |
| 1227 | |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 1228 | .host_is_ready = mei_me_host_is_ready, |
| 1229 | |
| 1230 | .hw_is_ready = mei_me_hw_is_ready, |
| 1231 | .hw_reset = mei_me_hw_reset, |
Tomas Winkler | aafae7e | 2013-03-11 18:27:03 +0200 | [diff] [blame] | 1232 | .hw_config = mei_me_hw_config, |
| 1233 | .hw_start = mei_me_hw_start, |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 1234 | |
Alexander Usyskin | 3dc196e | 2015-06-13 08:51:17 +0300 | [diff] [blame] | 1235 | .pg_in_transition = mei_me_pg_in_transition, |
Tomas Winkler | ee7e5af | 2014-03-18 22:51:58 +0200 | [diff] [blame] | 1236 | .pg_is_enabled = mei_me_pg_is_enabled, |
| 1237 | |
Tomas Winkler | 827eef5 | 2013-02-06 14:06:41 +0200 | [diff] [blame] | 1238 | .intr_clear = mei_me_intr_clear, |
| 1239 | .intr_enable = mei_me_intr_enable, |
| 1240 | .intr_disable = mei_me_intr_disable, |
| 1241 | |
| 1242 | .hbuf_free_slots = mei_me_hbuf_empty_slots, |
| 1243 | .hbuf_is_ready = mei_me_hbuf_is_empty, |
| 1244 | .hbuf_max_len = mei_me_hbuf_max_len, |
| 1245 | |
| 1246 | .write = mei_me_write_message, |
| 1247 | |
| 1248 | .rdbuf_full_slots = mei_me_count_full_read_slots, |
| 1249 | .read_hdr = mei_me_mecbrw_read, |
| 1250 | .read = mei_me_read_slots |
| 1251 | }; |
| 1252 | |
Tomas Winkler | c919951 | 2014-05-13 01:30:54 +0300 | [diff] [blame] | 1253 | static bool mei_me_fw_type_nm(struct pci_dev *pdev) |
| 1254 | { |
| 1255 | u32 reg; |
Tomas Winkler | 92db155 | 2014-09-29 16:31:37 +0300 | [diff] [blame] | 1256 | |
Tomas Winkler | c919951 | 2014-05-13 01:30:54 +0300 | [diff] [blame] | 1257 | pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); |
Tomas Winkler | a96c548 | 2016-02-07 22:46:51 +0200 | [diff] [blame] | 1258 | trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); |
Tomas Winkler | c919951 | 2014-05-13 01:30:54 +0300 | [diff] [blame] | 1259 | /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ |
| 1260 | return (reg & 0x600) == 0x200; |
| 1261 | } |
| 1262 | |
| 1263 | #define MEI_CFG_FW_NM \ |
| 1264 | .quirk_probe = mei_me_fw_type_nm |
| 1265 | |
| 1266 | static bool mei_me_fw_type_sps(struct pci_dev *pdev) |
| 1267 | { |
| 1268 | u32 reg; |
Tomas Winkler | 8c57cac | 2016-07-20 10:24:02 +0300 | [diff] [blame] | 1269 | unsigned int devfn; |
| 1270 | |
| 1271 | /* |
| 1272 | * Read ME FW Status register to check for SPS Firmware |
| 1273 | * The SPS FW is only signaled in pci function 0 |
| 1274 | */ |
| 1275 | devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0); |
| 1276 | pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®); |
Tomas Winkler | a96c548 | 2016-02-07 22:46:51 +0200 | [diff] [blame] | 1277 | trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); |
Tomas Winkler | c919951 | 2014-05-13 01:30:54 +0300 | [diff] [blame] | 1278 | /* if bits [19:16] = 15, running SPS Firmware */ |
| 1279 | return (reg & 0xf0000) == 0xf0000; |
| 1280 | } |
| 1281 | |
| 1282 | #define MEI_CFG_FW_SPS \ |
| 1283 | .quirk_probe = mei_me_fw_type_sps |
| 1284 | |
| 1285 | |
Alexander Usyskin | 8d929d4 | 2014-05-13 01:30:53 +0300 | [diff] [blame] | 1286 | #define MEI_CFG_LEGACY_HFS \ |
| 1287 | .fw_status.count = 0 |
| 1288 | |
| 1289 | #define MEI_CFG_ICH_HFS \ |
| 1290 | .fw_status.count = 1, \ |
| 1291 | .fw_status.status[0] = PCI_CFG_HFS_1 |
| 1292 | |
| 1293 | #define MEI_CFG_PCH_HFS \ |
| 1294 | .fw_status.count = 2, \ |
| 1295 | .fw_status.status[0] = PCI_CFG_HFS_1, \ |
| 1296 | .fw_status.status[1] = PCI_CFG_HFS_2 |
| 1297 | |
Alexander Usyskin | edca5ea | 2014-11-19 17:01:38 +0200 | [diff] [blame] | 1298 | #define MEI_CFG_PCH8_HFS \ |
| 1299 | .fw_status.count = 6, \ |
| 1300 | .fw_status.status[0] = PCI_CFG_HFS_1, \ |
| 1301 | .fw_status.status[1] = PCI_CFG_HFS_2, \ |
| 1302 | .fw_status.status[2] = PCI_CFG_HFS_3, \ |
| 1303 | .fw_status.status[3] = PCI_CFG_HFS_4, \ |
| 1304 | .fw_status.status[4] = PCI_CFG_HFS_5, \ |
| 1305 | .fw_status.status[5] = PCI_CFG_HFS_6 |
Alexander Usyskin | 8d929d4 | 2014-05-13 01:30:53 +0300 | [diff] [blame] | 1306 | |
| 1307 | /* ICH Legacy devices */ |
| 1308 | const struct mei_cfg mei_me_legacy_cfg = { |
| 1309 | MEI_CFG_LEGACY_HFS, |
| 1310 | }; |
| 1311 | |
| 1312 | /* ICH devices */ |
| 1313 | const struct mei_cfg mei_me_ich_cfg = { |
| 1314 | MEI_CFG_ICH_HFS, |
| 1315 | }; |
| 1316 | |
| 1317 | /* PCH devices */ |
| 1318 | const struct mei_cfg mei_me_pch_cfg = { |
| 1319 | MEI_CFG_PCH_HFS, |
| 1320 | }; |
| 1321 | |
Tomas Winkler | c919951 | 2014-05-13 01:30:54 +0300 | [diff] [blame] | 1322 | |
| 1323 | /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ |
| 1324 | const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { |
| 1325 | MEI_CFG_PCH_HFS, |
| 1326 | MEI_CFG_FW_NM, |
| 1327 | }; |
| 1328 | |
Alexander Usyskin | edca5ea | 2014-11-19 17:01:38 +0200 | [diff] [blame] | 1329 | /* PCH8 Lynx Point and newer devices */ |
| 1330 | const struct mei_cfg mei_me_pch8_cfg = { |
| 1331 | MEI_CFG_PCH8_HFS, |
| 1332 | }; |
| 1333 | |
| 1334 | /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ |
| 1335 | const struct mei_cfg mei_me_pch8_sps_cfg = { |
| 1336 | MEI_CFG_PCH8_HFS, |
Tomas Winkler | c919951 | 2014-05-13 01:30:54 +0300 | [diff] [blame] | 1337 | MEI_CFG_FW_SPS, |
| 1338 | }; |
| 1339 | |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1340 | /** |
Masanari Iida | 393b148 | 2013-04-05 01:05:05 +0900 | [diff] [blame] | 1341 | * mei_me_dev_init - allocates and initializes the mei device structure |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1342 | * |
| 1343 | * @pdev: The pci device structure |
Alexander Usyskin | 8d929d4 | 2014-05-13 01:30:53 +0300 | [diff] [blame] | 1344 | * @cfg: per device generation config |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1345 | * |
Alexander Usyskin | a8605ea | 2014-09-29 16:31:49 +0300 | [diff] [blame] | 1346 | * Return: The mei_device_device pointer on success, NULL on failure. |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1347 | */ |
Alexander Usyskin | 8d929d4 | 2014-05-13 01:30:53 +0300 | [diff] [blame] | 1348 | struct mei_device *mei_me_dev_init(struct pci_dev *pdev, |
| 1349 | const struct mei_cfg *cfg) |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1350 | { |
| 1351 | struct mei_device *dev; |
Tomas Winkler | 4ad96db | 2014-09-29 16:31:45 +0300 | [diff] [blame] | 1352 | struct mei_me_hw *hw; |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1353 | |
| 1354 | dev = kzalloc(sizeof(struct mei_device) + |
| 1355 | sizeof(struct mei_me_hw), GFP_KERNEL); |
| 1356 | if (!dev) |
| 1357 | return NULL; |
Tomas Winkler | 4ad96db | 2014-09-29 16:31:45 +0300 | [diff] [blame] | 1358 | hw = to_me_hw(dev); |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1359 | |
Tomas Winkler | 3a7e9b6 | 2014-09-29 16:31:41 +0300 | [diff] [blame] | 1360 | mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); |
Tomas Winkler | 4ad96db | 2014-09-29 16:31:45 +0300 | [diff] [blame] | 1361 | hw->cfg = cfg; |
Tomas Winkler | 52c3456 | 2013-02-06 14:06:40 +0200 | [diff] [blame] | 1362 | return dev; |
| 1363 | } |
Tomas Winkler | 06ecd64 | 2013-02-06 14:06:42 +0200 | [diff] [blame] | 1364 | |