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Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Blackfin power management
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Copyright 2006-2009 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -07005 *
Robin Getz96f10502009-09-24 14:11:24 +00006 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
Bryan Wu1394f032007-05-06 14:50:22 -07009 */
10
Rafael J. Wysocki95d9ffb2007-10-18 03:04:39 -070011#include <linux/suspend.h>
Bryan Wu1394f032007-05-06 14:50:22 -070012#include <linux/sched.h>
13#include <linux/proc_fs.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090014#include <linux/slab.h>
Mike Frysinger1f83b8f2007-07-12 22:58:21 +080015#include <linux/io.h>
16#include <linux/irq.h>
Aaron Wuef7dcaf2014-10-22 13:45:58 +080017#include <linux/delay.h>
Bjorn Helgaas288e6ea2016-02-02 13:53:23 -060018#include <linux/gpio.h>
Bryan Wu1394f032007-05-06 14:50:22 -070019
Yi Lieb7bd9c2009-08-07 01:20:58 +000020#include <asm/cplb.h>
Michael Hennerich1efc80b2008-07-19 16:57:32 +080021#include <asm/dma.h>
22#include <asm/dpmc.h>
Steven Miao93f89512012-05-16 18:26:10 +080023#include <asm/pm.h>
Bryan Wu1394f032007-05-06 14:50:22 -070024
Steven Miao93f89512012-05-16 18:26:10 +080025#ifdef CONFIG_BF60x
26struct bfin_cpu_pm_fns *bfin_cpu_pm;
27#endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +080028
Bryan Wu1394f032007-05-06 14:50:22 -070029void bfin_pm_suspend_standby_enter(void)
30{
Sonic Zhang54e4ff42013-05-30 18:37:28 +080031#if !BFIN_GPIO_PINT
Michael Hennerich1efc80b2008-07-19 16:57:32 +080032 bfin_pm_standby_setup();
Sonic Zhangfb5f0042007-12-23 23:02:13 +080033#endif
Bryan Wu1394f032007-05-06 14:50:22 -070034
Steven Miao93f89512012-05-16 18:26:10 +080035#ifdef CONFIG_BF60x
36 bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
37#else
38# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
39 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
40# else
41 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
42# endif
43#endif
Bryan Wu1394f032007-05-06 14:50:22 -070044
Sonic Zhang54e4ff42013-05-30 18:37:28 +080045#if !BFIN_GPIO_PINT
Steven Miao93f89512012-05-16 18:26:10 +080046 bfin_pm_standby_restore();
47#endif
48
49#ifndef CONFIG_BF60x
Mike Frysingerbe1d8542009-02-04 16:49:45 +080050#ifdef SIC_IWR0
Michael Hennerich56f5f592008-08-06 17:55:32 +080051 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +080052# ifdef SIC_IWR1
Michael Hennerich55546ac2008-08-13 17:41:13 +080053 /* BF52x system reset does not properly reset SIC_IWR1 which
54 * will screw up the bootrom as it relies on MDMA0/1 waking it
55 * up from IDLE instructions. See this report for more info:
56 * http://blackfin.uclinux.org/gf/tracker/4323
57 */
Mike Frysingerb7e11292008-11-18 17:48:22 +080058 if (ANOMALY_05000435)
59 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
60 else
61 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +080062# endif
63# ifdef SIC_IWR2
Michael Hennerich56f5f592008-08-06 17:55:32 +080064 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
Sonic Zhangfb5f0042007-12-23 23:02:13 +080065# endif
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080066#else
Michael Hennerich56f5f592008-08-06 17:55:32 +080067 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080068#endif
Steven Miao93f89512012-05-16 18:26:10 +080069
70#endif
Bryan Wu1394f032007-05-06 14:50:22 -070071}
72
Michael Hennerich1efc80b2008-07-19 16:57:32 +080073int bf53x_suspend_l1_mem(unsigned char *memptr)
74{
Michael Hennerichd1401e12010-06-16 09:12:10 +000075 dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
76 L1_CODE_LENGTH);
77 dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
78 (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
79 dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
Michael Hennerich1efc80b2008-07-19 16:57:32 +080080 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
81 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
82 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
83 L1_SCRATCH_LENGTH);
84
85 return 0;
86}
87
88int bf53x_resume_l1_mem(unsigned char *memptr)
89{
Michael Hennerichd1401e12010-06-16 09:12:10 +000090 dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
91 dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
Michael Hennerich1efc80b2008-07-19 16:57:32 +080092 L1_DATA_A_LENGTH);
Michael Hennerichd1401e12010-06-16 09:12:10 +000093 dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
Michael Hennerich1efc80b2008-07-19 16:57:32 +080094 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
95 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
96 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
97
98 return 0;
99}
100
Jie Zhang41ba6532009-06-16 09:48:33 +0000101#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
Steven Miao93f89512012-05-16 18:26:10 +0800102# ifdef CONFIG_BF60x
103__attribute__((l1_text))
104# endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800105static void flushinv_all_dcache(void)
106{
Steven Miao93f89512012-05-16 18:26:10 +0800107 register u32 way, bank, subbank, set;
108 register u32 status, addr;
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800109 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
110
111 for (bank = 0; bank < 2; ++bank) {
112 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
113 continue;
114
115 for (way = 0; way < 2; ++way)
116 for (subbank = 0; subbank < 4; ++subbank)
117 for (set = 0; set < 64; ++set) {
118
119 bfin_write_DTEST_COMMAND(
120 way << 26 |
121 bank << 23 |
122 subbank << 16 |
123 set << 5
124 );
125 CSYNC();
126 status = bfin_read_DTEST_DATA0();
127
128 /* only worry about valid/dirty entries */
129 if ((status & 0x3) != 0x3)
130 continue;
131
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800132
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800133 /* construct the address using the tag */
134 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
135
136 /* flush it */
137 __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
138 }
139 }
140}
141#endif
142
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800143int bfin_pm_suspend_mem_enter(void)
144{
Steven Miao36855dc2013-11-14 17:41:30 +0800145 int ret;
146#ifndef CONFIG_BF60x
147 int wakeup;
148#endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800149
150 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
151 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
Scott Jiangaefefe92013-09-16 00:53:09 -0400152 GFP_ATOMIC);
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800153
154 if (memptr == NULL) {
155 panic("bf53x_suspend_l1_mem malloc failed");
156 return -ENOMEM;
157 }
158
Steven Miao93f89512012-05-16 18:26:10 +0800159#ifndef CONFIG_BF60x
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800160 wakeup = bfin_read_VR_CTL() & ~FREQ;
161 wakeup |= SCKELOW;
162
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800163#ifdef CONFIG_PM_BFIN_WAKE_PH6
164 wakeup |= PHYWE;
165#endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800166#ifdef CONFIG_PM_BFIN_WAKE_GP
167 wakeup |= GPWE;
168#endif
Steven Miao0fbd88c2012-05-17 17:29:54 +0800169#endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800170
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800171 ret = blackfin_dma_suspend();
172
173 if (ret) {
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800174 kfree(memptr);
175 return ret;
176 }
177
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800178#ifdef CONFIG_GPIO_ADI
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800179 bfin_gpio_pm_hibernate_suspend();
Steven Miaoba4691a2012-06-15 11:40:48 +0800180#endif
Steven Miaod49cdf8402012-06-14 18:04:01 +0800181
Yi Lieb7bd9c2009-08-07 01:20:58 +0000182#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
183 flushinv_all_dcache();
Aaron Wuef7dcaf2014-10-22 13:45:58 +0800184 udelay(1);
Yi Lieb7bd9c2009-08-07 01:20:58 +0000185#endif
186 _disable_dcplb();
187 _disable_icplb();
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800188 bf53x_suspend_l1_mem(memptr);
189
Steven Miao93f89512012-05-16 18:26:10 +0800190#ifndef CONFIG_BF60x
Michael Hennerichd1401e12010-06-16 09:12:10 +0000191 do_hibernate(wakeup | vr_wakeup); /* See you later! */
Steven Miao93f89512012-05-16 18:26:10 +0800192#else
193 bfin_cpu_pm->enter(PM_SUSPEND_MEM);
194#endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800195
196 bf53x_resume_l1_mem(memptr);
197
Yi Lieb7bd9c2009-08-07 01:20:58 +0000198 _enable_icplb();
199 _enable_dcplb();
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800200
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800201#ifdef CONFIG_GPIO_ADI
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800202 bfin_gpio_pm_hibernate_restore();
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800203#endif
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800204 blackfin_dma_resume();
205
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800206 kfree(memptr);
207
208 return 0;
209}
210
Bryan Wu1394f032007-05-06 14:50:22 -0700211/*
Rafael J. Wysockie6c5eb92007-10-18 03:04:41 -0700212 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
213 * state
214 * @state: suspend state we're checking.
Bryan Wu1394f032007-05-06 14:50:22 -0700215 *
216 */
Rafael J. Wysockie6c5eb92007-10-18 03:04:41 -0700217static int bfin_pm_valid(suspend_state_t state)
Bryan Wu1394f032007-05-06 14:50:22 -0700218{
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800219 return (state == PM_SUSPEND_STANDBY
Michael Hennerichb89df502009-03-28 23:14:41 +0800220#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800221 /*
222 * On BF533/2/1:
223 * If we enter Hibernate the SCKE Pin is driven Low,
224 * so that the SDRAM enters Self Refresh Mode.
225 * However when the reset sequence that follows hibernate
226 * state is executed, SCKE is driven High, taking the
227 * SDRAM out of Self Refresh.
228 *
229 * If you reconfigure and access the SDRAM "very quickly",
230 * you are likely to avoid errors, otherwise the SDRAM
231 * start losing its contents.
232 * An external HW workaround is possible using logic gates.
233 */
234 || state == PM_SUSPEND_MEM
235#endif
236 );
Bryan Wu1394f032007-05-06 14:50:22 -0700237}
238
239/*
240 * bfin_pm_enter - Actually enter a sleep state.
241 * @state: State we're entering.
242 *
243 */
244static int bfin_pm_enter(suspend_state_t state)
245{
246 switch (state) {
247 case PM_SUSPEND_STANDBY:
248 bfin_pm_suspend_standby_enter();
249 break;
Bryan Wu9d7b6672007-05-21 18:09:37 +0800250 case PM_SUSPEND_MEM:
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800251 bfin_pm_suspend_mem_enter();
252 break;
Bryan Wu1394f032007-05-06 14:50:22 -0700253 default:
254 return -EINVAL;
255 }
256
257 return 0;
258}
259
Sonic Zhang72b099e2012-05-17 17:33:00 +0800260#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
261void bfin_pm_end(void)
262{
263 u32 cycle, cycle2;
264 u64 usec64;
265 u32 usec;
266
267 __asm__ __volatile__ (
268 "1: %0 = CYCLES2\n"
269 "%1 = CYCLES\n"
270 "%2 = CYCLES2\n"
271 "CC = %2 == %0\n"
272 "if ! CC jump 1b\n"
273 : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
274 );
275
276 usec64 = ((u64)cycle2 << 32) + cycle;
277 do_div(usec64, get_cclk() / USEC_PER_SEC);
278 usec = usec64;
279 if (usec == 0)
280 usec = 1;
281
282 pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
283 usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
284}
285#endif
286
Lionel Debroux2f55ac02010-11-16 14:14:02 +0100287static const struct platform_suspend_ops bfin_pm_ops = {
Bryan Wu1394f032007-05-06 14:50:22 -0700288 .enter = bfin_pm_enter,
Michael Hennerich4bbd10f2007-08-27 17:29:10 +0800289 .valid = bfin_pm_valid,
Sonic Zhang72b099e2012-05-17 17:33:00 +0800290#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
291 .end = bfin_pm_end,
292#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700293};
294
295static int __init bfin_pm_init(void)
296{
Rafael J. Wysocki26398a72007-10-18 03:04:40 -0700297 suspend_set_ops(&bfin_pm_ops);
Bryan Wu1394f032007-05-06 14:50:22 -0700298 return 0;
299}
300
301__initcall(bfin_pm_init);