blob: c25ce5af091addb2f23653feb8fcbac27d5c9180 [file] [log] [blame]
Heiko Stuebner1f629b72013-01-29 10:25:22 -08001/*
2 * S3C24XX IRQ handling
Ben Dooksa21765a2007-02-11 18:31:01 +01003 *
Ben Dookse02f8662009-11-13 22:54:13 +00004 * Copyright (c) 2003-2004 Simtec Electronics
Ben Dooksa21765a2007-02-11 18:31:01 +01005 * Ben Dooks <ben@simtec.co.uk>
Heiko Stuebner1f629b72013-01-29 10:25:22 -08006 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
Ben Dooksa21765a2007-02-11 18:31:01 +01007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Ben Dooksa21765a2007-02-11 18:31:01 +010017*/
18
19#include <linux/init.h>
Heiko Stuebner1f629b72013-01-29 10:25:22 -080020#include <linux/slab.h>
Ben Dooksa21765a2007-02-11 18:31:01 +010021#include <linux/module.h>
Heiko Stuebner1f629b72013-01-29 10:25:22 -080022#include <linux/io.h>
23#include <linux/err.h>
Ben Dooksa21765a2007-02-11 18:31:01 +010024#include <linux/interrupt.h>
25#include <linux/ioport.h>
Kay Sieversedbaa602011-12-21 16:26:03 -080026#include <linux/device.h>
Heiko Stuebner1f629b72013-01-29 10:25:22 -080027#include <linux/irqdomain.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040028#include <linux/irqchip.h>
Linus Torvalds6fa52ed2013-05-04 12:31:18 -070029#include <linux/irqchip/chained_irq.h>
Heiko Stuebnerf0774d42013-04-04 14:55:10 +090030#include <linux/of.h>
31#include <linux/of_irq.h>
32#include <linux/of_address.h>
Ben Dooksa21765a2007-02-11 18:31:01 +010033
Heiko Stuebner17453dd2013-03-07 12:38:25 +090034#include <asm/exception.h>
Ben Dooksa21765a2007-02-11 18:31:01 +010035#include <asm/mach/irq.h>
36
Heiko Stuebner1f629b72013-01-29 10:25:22 -080037#include <mach/regs-irq.h>
38#include <mach/regs-gpio.h>
Ben Dooksa21765a2007-02-11 18:31:01 +010039
Ben Dooksa2b7ba92008-10-07 22:26:09 +010040#include <plat/cpu.h>
Heiko Stuebner1f629b72013-01-29 10:25:22 -080041#include <plat/regs-irqtype.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010042#include <plat/pm.h>
Ben Dooksa21765a2007-02-11 18:31:01 +010043
Heiko Stuebner1f629b72013-01-29 10:25:22 -080044#define S3C_IRQTYPE_NONE 0
45#define S3C_IRQTYPE_EINT 1
46#define S3C_IRQTYPE_EDGE 2
47#define S3C_IRQTYPE_LEVEL 3
Ben Dooksa21765a2007-02-11 18:31:01 +010048
Heiko Stuebner1f629b72013-01-29 10:25:22 -080049struct s3c_irq_data {
50 unsigned int type;
Heiko Stuebnerf5a25522013-04-04 14:53:52 +090051 unsigned long offset;
Heiko Stuebner1f629b72013-01-29 10:25:22 -080052 unsigned long parent_irq;
Ben Dooksa21765a2007-02-11 18:31:01 +010053
Heiko Stuebner1f629b72013-01-29 10:25:22 -080054 /* data gets filled during init */
55 struct s3c_irq_intc *intc;
56 unsigned long sub_bits;
57 struct s3c_irq_intc *sub_intc;
Ben Dooksa21765a2007-02-11 18:31:01 +010058};
59
Heiko Stuebner1f629b72013-01-29 10:25:22 -080060/*
61 * Sructure holding the controller data
62 * @reg_pending register holding pending irqs
63 * @reg_intpnd special register intpnd in main intc
64 * @reg_mask mask register
65 * @domain irq_domain of the controller
66 * @parent parent controller for ext and sub irqs
67 * @irqs irq-data, always s3c_irq_data[32]
68 */
69struct s3c_irq_intc {
70 void __iomem *reg_pending;
71 void __iomem *reg_intpnd;
72 void __iomem *reg_mask;
73 struct irq_domain *domain;
74 struct s3c_irq_intc *parent;
75 struct s3c_irq_data *irqs;
Ben Dooksa21765a2007-02-11 18:31:01 +010076};
77
Heiko Stuebner658dc8f2013-04-04 14:53:49 +090078/*
79 * Array holding pointers to the global controller structs
80 * [0] ... main_intc
81 * [1] ... sub_intc
82 * [2] ... main_intc2 on s3c2416
83 */
84static struct s3c_irq_intc *s3c_intc[3];
85
Heiko Stuebner1f629b72013-01-29 10:25:22 -080086static void s3c_irq_mask(struct irq_data *data)
Ben Dooksa21765a2007-02-11 18:31:01 +010087{
Heiko Stuebnerf5a25522013-04-04 14:53:52 +090088 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
89 struct s3c_irq_intc *intc = irq_data->intc;
Heiko Stuebner1f629b72013-01-29 10:25:22 -080090 struct s3c_irq_intc *parent_intc = intc->parent;
Heiko Stuebner1f629b72013-01-29 10:25:22 -080091 struct s3c_irq_data *parent_data;
Ben Dooksa21765a2007-02-11 18:31:01 +010092 unsigned long mask;
Heiko Stuebner1f629b72013-01-29 10:25:22 -080093 unsigned int irqno;
Ben Dooksa21765a2007-02-11 18:31:01 +010094
Ben Dooks35333282016-06-21 11:20:30 +010095 mask = readl_relaxed(intc->reg_mask);
Heiko Stuebnerf5a25522013-04-04 14:53:52 +090096 mask |= (1UL << irq_data->offset);
Ben Dooks35333282016-06-21 11:20:30 +010097 writel_relaxed(mask, intc->reg_mask);
Ben Dooksa21765a2007-02-11 18:31:01 +010098
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +090099 if (parent_intc) {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800100 parent_data = &parent_intc->irqs[irq_data->parent_irq];
Ben Dooksa21765a2007-02-11 18:31:01 +0100101
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900102 /* check to see if we need to mask the parent IRQ
103 * The parent_irq is always in main_intc, so the hwirq
104 * for find_mapping does not need an offset in any case.
105 */
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800106 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
107 irqno = irq_find_mapping(parent_intc->domain,
108 irq_data->parent_irq);
109 s3c_irq_mask(irq_get_irq_data(irqno));
110 }
Ben Dooksa21765a2007-02-11 18:31:01 +0100111 }
112}
113
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800114static void s3c_irq_unmask(struct irq_data *data)
Ben Dooksa21765a2007-02-11 18:31:01 +0100115{
Heiko Stuebnerf5a25522013-04-04 14:53:52 +0900116 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
117 struct s3c_irq_intc *intc = irq_data->intc;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800118 struct s3c_irq_intc *parent_intc = intc->parent;
Ben Dooksa21765a2007-02-11 18:31:01 +0100119 unsigned long mask;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800120 unsigned int irqno;
Ben Dooksa21765a2007-02-11 18:31:01 +0100121
Ben Dooks35333282016-06-21 11:20:30 +0100122 mask = readl_relaxed(intc->reg_mask);
Heiko Stuebnerf5a25522013-04-04 14:53:52 +0900123 mask &= ~(1UL << irq_data->offset);
Ben Dooks35333282016-06-21 11:20:30 +0100124 writel_relaxed(mask, intc->reg_mask);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800125
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +0900126 if (parent_intc) {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800127 irqno = irq_find_mapping(parent_intc->domain,
128 irq_data->parent_irq);
129 s3c_irq_unmask(irq_get_irq_data(irqno));
130 }
Ben Dooksa21765a2007-02-11 18:31:01 +0100131}
132
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800133static inline void s3c_irq_ack(struct irq_data *data)
Ben Dooksa21765a2007-02-11 18:31:01 +0100134{
Heiko Stuebnerf5a25522013-04-04 14:53:52 +0900135 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
136 struct s3c_irq_intc *intc = irq_data->intc;
137 unsigned long bitval = 1UL << irq_data->offset;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800138
Ben Dooks35333282016-06-21 11:20:30 +0100139 writel_relaxed(bitval, intc->reg_pending);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800140 if (intc->reg_intpnd)
Ben Dooks35333282016-06-21 11:20:30 +0100141 writel_relaxed(bitval, intc->reg_intpnd);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800142}
143
Heiko Stuebnerbd7c0da2013-04-04 14:53:45 +0900144static int s3c_irq_type(struct irq_data *data, unsigned int type)
145{
146 switch (type) {
147 case IRQ_TYPE_NONE:
148 break;
149 case IRQ_TYPE_EDGE_RISING:
150 case IRQ_TYPE_EDGE_FALLING:
151 case IRQ_TYPE_EDGE_BOTH:
152 irq_set_handler(data->irq, handle_edge_irq);
153 break;
154 case IRQ_TYPE_LEVEL_LOW:
155 case IRQ_TYPE_LEVEL_HIGH:
156 irq_set_handler(data->irq, handle_level_irq);
157 break;
158 default:
159 pr_err("No such irq type %d", type);
160 return -EINVAL;
161 }
162
163 return 0;
164}
165
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800166static int s3c_irqext_type_set(void __iomem *gpcon_reg,
167 void __iomem *extint_reg,
168 unsigned long gpcon_offset,
169 unsigned long extint_offset,
170 unsigned int type)
171{
Ben Dooksa21765a2007-02-11 18:31:01 +0100172 unsigned long newvalue = 0, value;
173
Ben Dooksa21765a2007-02-11 18:31:01 +0100174 /* Set the GPIO to external interrupt mode */
Ben Dooks35333282016-06-21 11:20:30 +0100175 value = readl_relaxed(gpcon_reg);
Ben Dooksa21765a2007-02-11 18:31:01 +0100176 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
Ben Dooks35333282016-06-21 11:20:30 +0100177 writel_relaxed(value, gpcon_reg);
Ben Dooksa21765a2007-02-11 18:31:01 +0100178
179 /* Set the external interrupt to pointed trigger type */
180 switch (type)
181 {
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100182 case IRQ_TYPE_NONE:
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800183 pr_warn("No edge setting!\n");
Ben Dooksa21765a2007-02-11 18:31:01 +0100184 break;
185
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100186 case IRQ_TYPE_EDGE_RISING:
Ben Dooksa21765a2007-02-11 18:31:01 +0100187 newvalue = S3C2410_EXTINT_RISEEDGE;
188 break;
189
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100190 case IRQ_TYPE_EDGE_FALLING:
Ben Dooksa21765a2007-02-11 18:31:01 +0100191 newvalue = S3C2410_EXTINT_FALLEDGE;
192 break;
193
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100194 case IRQ_TYPE_EDGE_BOTH:
Ben Dooksa21765a2007-02-11 18:31:01 +0100195 newvalue = S3C2410_EXTINT_BOTHEDGE;
196 break;
197
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100198 case IRQ_TYPE_LEVEL_LOW:
Ben Dooksa21765a2007-02-11 18:31:01 +0100199 newvalue = S3C2410_EXTINT_LOWLEV;
200 break;
201
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100202 case IRQ_TYPE_LEVEL_HIGH:
Ben Dooksa21765a2007-02-11 18:31:01 +0100203 newvalue = S3C2410_EXTINT_HILEV;
204 break;
205
206 default:
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800207 pr_err("No such irq type %d", type);
208 return -EINVAL;
Ben Dooksa21765a2007-02-11 18:31:01 +0100209 }
210
Ben Dooks35333282016-06-21 11:20:30 +0100211 value = readl_relaxed(extint_reg);
Ben Dooksa21765a2007-02-11 18:31:01 +0100212 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
Ben Dooks35333282016-06-21 11:20:30 +0100213 writel_relaxed(value, extint_reg);
Ben Dooksa21765a2007-02-11 18:31:01 +0100214
215 return 0;
216}
217
Heiko Stuebnerdc1a3532013-02-12 14:23:01 -0800218static int s3c_irqext_type(struct irq_data *data, unsigned int type)
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800219{
220 void __iomem *extint_reg;
221 void __iomem *gpcon_reg;
222 unsigned long gpcon_offset, extint_offset;
223
224 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
225 gpcon_reg = S3C2410_GPFCON;
226 extint_reg = S3C24XX_EXTINT0;
227 gpcon_offset = (data->hwirq) * 2;
228 extint_offset = (data->hwirq) * 4;
229 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
230 gpcon_reg = S3C2410_GPGCON;
231 extint_reg = S3C24XX_EXTINT1;
232 gpcon_offset = (data->hwirq - 8) * 2;
233 extint_offset = (data->hwirq - 8) * 4;
234 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
235 gpcon_reg = S3C2410_GPGCON;
236 extint_reg = S3C24XX_EXTINT2;
237 gpcon_offset = (data->hwirq - 8) * 2;
238 extint_offset = (data->hwirq - 16) * 4;
239 } else {
240 return -EINVAL;
241 }
242
243 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
244 extint_offset, type);
245}
246
247static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
248{
249 void __iomem *extint_reg;
250 void __iomem *gpcon_reg;
251 unsigned long gpcon_offset, extint_offset;
252
253 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
254 gpcon_reg = S3C2410_GPFCON;
255 extint_reg = S3C24XX_EXTINT0;
256 gpcon_offset = (data->hwirq) * 2;
257 extint_offset = (data->hwirq) * 4;
258 } else {
259 return -EINVAL;
260 }
261
262 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
263 extint_offset, type);
264}
265
Heiko Stuebnerdc1a3532013-02-12 14:23:01 -0800266static struct irq_chip s3c_irq_chip = {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800267 .name = "s3c",
268 .irq_ack = s3c_irq_ack,
269 .irq_mask = s3c_irq_mask,
270 .irq_unmask = s3c_irq_unmask,
Heiko Stuebnerbd7c0da2013-04-04 14:53:45 +0900271 .irq_set_type = s3c_irq_type,
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800272 .irq_set_wake = s3c_irq_wake
273};
274
Heiko Stuebnerdc1a3532013-02-12 14:23:01 -0800275static struct irq_chip s3c_irq_level_chip = {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800276 .name = "s3c-level",
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_ack = s3c_irq_ack,
Heiko Stuebnerbd7c0da2013-04-04 14:53:45 +0900280 .irq_set_type = s3c_irq_type,
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800281};
282
Ben Dooksa21765a2007-02-11 18:31:01 +0100283static struct irq_chip s3c_irqext_chip = {
284 .name = "s3c-ext",
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800285 .irq_mask = s3c_irq_mask,
286 .irq_unmask = s3c_irq_unmask,
287 .irq_ack = s3c_irq_ack,
Lennert Buytenhek57436c2d2011-01-03 19:15:54 +0900288 .irq_set_type = s3c_irqext_type,
Mark Brownf5aeffb2010-12-02 14:35:38 +0900289 .irq_set_wake = s3c_irqext_wake
Ben Dooksa21765a2007-02-11 18:31:01 +0100290};
291
292static struct irq_chip s3c_irq_eint0t4 = {
293 .name = "s3c-ext0",
Lennert Buytenhek57436c2d2011-01-03 19:15:54 +0900294 .irq_ack = s3c_irq_ack,
295 .irq_mask = s3c_irq_mask,
296 .irq_unmask = s3c_irq_unmask,
297 .irq_set_wake = s3c_irq_wake,
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800298 .irq_set_type = s3c_irqext0_type,
Ben Dooksa21765a2007-02-11 18:31:01 +0100299};
300
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200301static void s3c_irq_demux(struct irq_desc *desc)
Ben Dooksa21765a2007-02-11 18:31:01 +0100302{
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800303 struct irq_chip *chip = irq_desc_get_chip(desc);
Heiko Stuebnerf5a25522013-04-04 14:53:52 +0900304 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900305 struct s3c_irq_intc *intc = irq_data->intc;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800306 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
Thomas Gleixner4df18a62015-07-16 22:39:29 +0200307 unsigned int n, offset, irq;
308 unsigned long src, msk;
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900309
310 /* we're using individual domains for the non-dt case
311 * and one big domain for the dt case where the subintc
312 * starts at hwirq number 32.
313 */
Marc Zyngier5d4c9bc2015-10-13 12:51:29 +0100314 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
Ben Dooksa21765a2007-02-11 18:31:01 +0100315
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800316 chained_irq_enter(chip, desc);
Ben Dooksa21765a2007-02-11 18:31:01 +0100317
Ben Dooks35333282016-06-21 11:20:30 +0100318 src = readl_relaxed(sub_intc->reg_pending);
319 msk = readl_relaxed(sub_intc->reg_mask);
Ben Dooksa21765a2007-02-11 18:31:01 +0100320
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800321 src &= ~msk;
322 src &= irq_data->sub_bits;
Ben Dooksa21765a2007-02-11 18:31:01 +0100323
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800324 while (src) {
325 n = __ffs(src);
326 src &= ~(1 << n);
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900327 irq = irq_find_mapping(sub_intc->domain, offset + n);
328 generic_handle_irq(irq);
Ben Dooksa21765a2007-02-11 18:31:01 +0100329 }
330
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800331 chained_irq_exit(chip, desc);
Ben Dooksa21765a2007-02-11 18:31:01 +0100332}
333
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900334static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900335 struct pt_regs *regs, int intc_offset)
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900336{
337 int pnd;
338 int offset;
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900339
Ben Dooks35333282016-06-21 11:20:30 +0100340 pnd = readl_relaxed(intc->reg_intpnd);
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900341 if (!pnd)
342 return false;
343
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900344 /* non-dt machines use individual domains */
Marc Zyngier5d4c9bc2015-10-13 12:51:29 +0100345 if (!irq_domain_get_of_node(intc->domain))
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900346 intc_offset = 0;
347
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900348 /* We have a problem that the INTOFFSET register does not always
349 * show one interrupt. Occasionally we get two interrupts through
350 * the prioritiser, and this causes the INTOFFSET register to show
351 * what looks like the logical-or of the two interrupt numbers.
352 *
353 * Thanks to Klaus, Shannon, et al for helping to debug this problem
354 */
Ben Dooks35333282016-06-21 11:20:30 +0100355 offset = readl_relaxed(intc->reg_intpnd + 4);
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900356
357 /* Find the bit manually, when the offset is wrong.
358 * The pending register only ever contains the one bit of the next
359 * interrupt to handle.
360 */
361 if (!(pnd & (1 << offset)))
362 offset = __ffs(pnd);
363
Marc Zyngiercf86bfd2014-08-26 11:03:26 +0100364 handle_domain_irq(intc->domain, intc_offset + offset, regs);
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900365 return true;
366}
367
368asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
369{
370 do {
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900371 if (likely(s3c_intc[0]))
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900372 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900373 continue;
374
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900375 if (s3c_intc[2])
Heiko Stuebnerf0774d42013-04-04 14:55:10 +0900376 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900377 continue;
378
379 break;
380 } while (1);
381}
382
Ben Dooks229fd8f2009-08-03 17:26:57 +0100383#ifdef CONFIG_FIQ
384/**
385 * s3c24xx_set_fiq - set the FIQ routing
386 * @irq: IRQ number to route to FIQ on processor.
387 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
388 *
389 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
390 * @on is true, the @irq is checked to see if it can be routed and the
391 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
392 * routing is cleared, regardless of which @irq is specified.
393 */
394int s3c24xx_set_fiq(unsigned int irq, bool on)
395{
396 u32 intmod;
397 unsigned offs;
398
399 if (on) {
400 offs = irq - FIQ_START;
401 if (offs > 31)
402 return -EINVAL;
403
404 intmod = 1 << offs;
405 } else {
406 intmod = 0;
407 }
408
Ben Dooks35333282016-06-21 11:20:30 +0100409 writel_relaxed(intmod, S3C2410_INTMOD);
Ben Dooks229fd8f2009-08-03 17:26:57 +0100410 return 0;
411}
Ben Dooks0f13c822009-12-07 14:51:38 +0000412
413EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
Ben Dooks229fd8f2009-08-03 17:26:57 +0100414#endif
415
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800416static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
417 irq_hw_number_t hw)
418{
419 struct s3c_irq_intc *intc = h->host_data;
420 struct s3c_irq_data *irq_data = &intc->irqs[hw];
421 struct s3c_irq_intc *parent_intc;
422 struct s3c_irq_data *parent_irq_data;
423 unsigned int irqno;
424
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800425 /* attach controller pointer to irq_data */
426 irq_data->intc = intc;
Heiko Stuebnerf5a25522013-04-04 14:53:52 +0900427 irq_data->offset = hw;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800428
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +0900429 parent_intc = intc->parent;
430
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800431 /* set handler and flags */
432 switch (irq_data->type) {
433 case S3C_IRQTYPE_NONE:
434 return 0;
435 case S3C_IRQTYPE_EINT:
Heiko Stuebner1c8408e2013-02-12 10:12:09 -0800436 /* On the S3C2412, the EINT0to3 have a parent irq
437 * but need the s3c_irq_eint0t4 chip
438 */
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +0900439 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800440 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
441 handle_edge_irq);
442 else
443 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
444 handle_edge_irq);
445 break;
446 case S3C_IRQTYPE_EDGE:
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +0900447 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800448 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
449 handle_edge_irq);
450 else
451 irq_set_chip_and_handler(virq, &s3c_irq_chip,
452 handle_edge_irq);
453 break;
454 case S3C_IRQTYPE_LEVEL:
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +0900455 if (parent_intc)
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800456 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
457 handle_level_irq);
458 else
459 irq_set_chip_and_handler(virq, &s3c_irq_chip,
460 handle_level_irq);
461 break;
462 default:
463 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
464 return -EINVAL;
465 }
Heiko Stuebnerf5a25522013-04-04 14:53:52 +0900466
467 irq_set_chip_data(virq, irq_data);
468
Heiko Stuebner0fe3cb12013-03-07 12:38:16 +0900469 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
Heiko Stuebner502a2982013-03-07 12:38:13 +0900470 if (irq_data->parent_irq > 31) {
471 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
472 irq_data->parent_irq);
Rob Herringd17cab42015-08-29 18:01:22 -0500473 return -EINVAL;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800474 }
475
Heiko Stuebner502a2982013-03-07 12:38:13 +0900476 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800477 parent_irq_data->sub_intc = intc;
478 parent_irq_data->sub_bits |= (1UL << hw);
479
480 /* attach the demuxer to the parent irq */
481 irqno = irq_find_mapping(parent_intc->domain,
482 irq_data->parent_irq);
483 if (!irqno) {
484 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
485 irq_data->parent_irq);
Rob Herringd17cab42015-08-29 18:01:22 -0500486 return -EINVAL;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800487 }
488 irq_set_chained_handler(irqno, s3c_irq_demux);
489 }
490
491 return 0;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800492}
493
Krzysztof Kozlowski96009732015-04-27 21:54:24 +0900494static const struct irq_domain_ops s3c24xx_irq_ops = {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800495 .map = s3c24xx_irq_map,
496 .xlate = irq_domain_xlate_twocell,
497};
498
499static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
500{
501 void __iomem *reg_source;
502 unsigned long pend;
503 unsigned long last;
504 int i;
505
506 /* if intpnd is set, read the next pending irq from there */
507 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
508
509 last = 0;
510 for (i = 0; i < 4; i++) {
Ben Dooks35333282016-06-21 11:20:30 +0100511 pend = readl_relaxed(reg_source);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800512
513 if (pend == 0 || pend == last)
514 break;
515
Ben Dooks35333282016-06-21 11:20:30 +0100516 writel_relaxed(pend, intc->reg_pending);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800517 if (intc->reg_intpnd)
Ben Dooks35333282016-06-21 11:20:30 +0100518 writel_relaxed(pend, intc->reg_intpnd);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800519
520 pr_info("irq: clearing pending status %08x\n", (int)pend);
521 last = pend;
522 }
523}
524
Arnd Bergmannbc8fd902013-04-25 16:49:05 +0200525static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800526 struct s3c_irq_data *irq_data,
527 struct s3c_irq_intc *parent,
528 unsigned long address)
529{
530 struct s3c_irq_intc *intc;
531 void __iomem *base = (void *)0xf6000000; /* static mapping */
532 int irq_num;
533 int irq_start;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800534 int ret;
535
536 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
537 if (!intc)
538 return ERR_PTR(-ENOMEM);
539
540 intc->irqs = irq_data;
541
542 if (parent)
543 intc->parent = parent;
544
545 /* select the correct data for the controller.
546 * Need to hard code the irq num start and offset
547 * to preserve the static mapping for now
548 */
549 switch (address) {
550 case 0x4a000000:
551 pr_debug("irq: found main intc\n");
552 intc->reg_pending = base;
553 intc->reg_mask = base + 0x08;
554 intc->reg_intpnd = base + 0x10;
555 irq_num = 32;
556 irq_start = S3C2410_IRQ(0);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800557 break;
558 case 0x4a000018:
559 pr_debug("irq: found subintc\n");
560 intc->reg_pending = base + 0x18;
561 intc->reg_mask = base + 0x1c;
562 irq_num = 29;
563 irq_start = S3C2410_IRQSUB(0);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800564 break;
565 case 0x4a000040:
566 pr_debug("irq: found intc2\n");
567 intc->reg_pending = base + 0x40;
568 intc->reg_mask = base + 0x48;
569 intc->reg_intpnd = base + 0x50;
570 irq_num = 8;
571 irq_start = S3C2416_IRQ(0);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800572 break;
573 case 0x560000a4:
574 pr_debug("irq: found eintc\n");
575 base = (void *)0xfd000000;
576
577 intc->reg_mask = base + 0xa4;
Linus Torvalds6fa52ed2013-05-04 12:31:18 -0700578 intc->reg_pending = base + 0xa8;
Heiko Stuebner5424f212013-02-12 10:12:04 -0800579 irq_num = 24;
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800580 irq_start = S3C2410_IRQ(32);
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800581 break;
582 default:
583 pr_err("irq: unsupported controller address\n");
584 ret = -EINVAL;
585 goto err;
586 }
587
588 /* now that all the data is complete, init the irq-domain */
589 s3c24xx_clear_intc(intc);
590 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
Heiko Stuebner5424f212013-02-12 10:12:04 -0800591 0, &s3c24xx_irq_ops,
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800592 intc);
593 if (!intc->domain) {
594 pr_err("irq: could not create irq-domain\n");
595 ret = -EINVAL;
596 goto err;
597 }
598
Heiko Stuebner17453dd2013-03-07 12:38:25 +0900599 set_handle_irq(s3c24xx_handle_irq);
600
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800601 return intc;
602
603err:
604 kfree(intc);
605 return ERR_PTR(ret);
606}
Ben Dooks229fd8f2009-08-03 17:26:57 +0100607
Arnd Bergmanneb249a12016-01-25 16:58:08 +0100608static struct s3c_irq_data __maybe_unused init_eint[32] = {
Heiko Stuebnerf182aa12013-03-07 12:38:19 +0900609 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
610 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
611 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
612 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
632 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
633};
Ben Dooksa21765a2007-02-11 18:31:01 +0100634
Heiko Stuebnerf182aa12013-03-07 12:38:19 +0900635#ifdef CONFIG_CPU_S3C2410
636static struct s3c_irq_data init_s3c2410base[32] = {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800637 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
638 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
639 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
640 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
641 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
642 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
643 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
644 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
645 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
646 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
647 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
648 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
649 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
650 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
651 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
652 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
654 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
657 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
658 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
659 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
660 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
661 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
662 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
663 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
664 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
665 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
666 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
667 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
668 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
669};
670
Heiko Stuebnerf182aa12013-03-07 12:38:19 +0900671static struct s3c_irq_data init_s3c2410subint[32] = {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
680 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
681 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
682 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
683};
684
Heiko Stuebnerf182aa12013-03-07 12:38:19 +0900685void __init s3c2410_init_irq(void)
Ben Dooksa21765a2007-02-11 18:31:01 +0100686{
Ben Dooks229fd8f2009-08-03 17:26:57 +0100687#ifdef CONFIG_FIQ
Shawn Guobc896632012-06-28 14:42:08 +0800688 init_FIQ(FIQ_START);
Ben Dooks229fd8f2009-08-03 17:26:57 +0100689#endif
690
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900691 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
692 0x4a000000);
693 if (IS_ERR(s3c_intc[0])) {
Heiko Stuebner1f629b72013-01-29 10:25:22 -0800694 pr_err("irq: could not create main interrupt controller\n");
695 return;
Ben Dooksa21765a2007-02-11 18:31:01 +0100696 }
697
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900698 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
699 s3c_intc[0], 0x4a000018);
700 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
Ben Dooksa21765a2007-02-11 18:31:01 +0100701}
Heiko Stuebnerf182aa12013-03-07 12:38:19 +0900702#endif
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800703
Heiko Stuebnerd3d5a2c2013-02-12 10:09:13 -0800704#ifdef CONFIG_CPU_S3C2412
Heiko Stuebner42459442013-02-12 10:09:21 -0800705static struct s3c_irq_data init_s3c2412base[32] = {
Heiko Stuebner1c8408e2013-02-12 10:12:09 -0800706 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
707 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
708 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
709 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
Heiko Stuebner42459442013-02-12 10:09:21 -0800710 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
711 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
712 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
713 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
714 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
715 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
716 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
717 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
718 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
719 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
720 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
721 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
722 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
723 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
724 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
725 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
726 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
727 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
728 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
729 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
730 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
731 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
732 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
733 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
734 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
735 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
736 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
737 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
738};
Heiko Stuebnerd3d5a2c2013-02-12 10:09:13 -0800739
Heiko Stuebner1c8408e2013-02-12 10:12:09 -0800740static struct s3c_irq_data init_s3c2412eint[32] = {
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
764 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
765};
766
Heiko Stuebner42459442013-02-12 10:09:21 -0800767static struct s3c_irq_data init_s3c2412subint[32] = {
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
777 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
778 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
779 { .type = S3C_IRQTYPE_NONE, },
780 { .type = S3C_IRQTYPE_NONE, },
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
782 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
783};
Heiko Stuebnerd3d5a2c2013-02-12 10:09:13 -0800784
Arnd Bergmannbc8fd902013-04-25 16:49:05 +0200785void __init s3c2412_init_irq(void)
Heiko Stuebnerd3d5a2c2013-02-12 10:09:13 -0800786{
Heiko Stuebner42459442013-02-12 10:09:21 -0800787 pr_info("S3C2412: IRQ Support\n");
788
789#ifdef CONFIG_FIQ
790 init_FIQ(FIQ_START);
791#endif
792
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900793 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
794 0x4a000000);
795 if (IS_ERR(s3c_intc[0])) {
Heiko Stuebner42459442013-02-12 10:09:21 -0800796 pr_err("irq: could not create main interrupt controller\n");
797 return;
798 }
799
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900800 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
801 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
802 s3c_intc[0], 0x4a000018);
Heiko Stuebnerd3d5a2c2013-02-12 10:09:13 -0800803}
Heiko Stuebnerd3d5a2c2013-02-12 10:09:13 -0800804#endif
805
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800806#ifdef CONFIG_CPU_S3C2416
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800807static struct s3c_irq_data init_s3c2416base[32] = {
808 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
809 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
810 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
811 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
812 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
813 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
814 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
815 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
816 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
817 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
818 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
819 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
820 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
821 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
822 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
823 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
824 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
826 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
827 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
828 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
829 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
830 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
831 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
832 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
833 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
834 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
835 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
836 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
837 { .type = S3C_IRQTYPE_NONE, },
838 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
839 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800840};
841
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800842static struct s3c_irq_data init_s3c2416subint[32] = {
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
852 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
853 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
854 { .type = S3C_IRQTYPE_NONE }, /* reserved */
855 { .type = S3C_IRQTYPE_NONE }, /* reserved */
856 { .type = S3C_IRQTYPE_NONE }, /* reserved */
857 { .type = S3C_IRQTYPE_NONE }, /* reserved */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
871 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800872};
873
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800874static struct s3c_irq_data init_s3c2416_second[32] = {
875 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
Heiko Stuebner1ebc7e82013-04-04 14:53:41 +0900876 { .type = S3C_IRQTYPE_NONE }, /* reserved */
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800877 { .type = S3C_IRQTYPE_NONE }, /* reserved */
878 { .type = S3C_IRQTYPE_NONE }, /* reserved */
879 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
Heiko Stuebner1ebc7e82013-04-04 14:53:41 +0900880 { .type = S3C_IRQTYPE_NONE }, /* reserved */
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800881 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800882};
883
Heiko Stuebner4a282dd2013-01-29 10:25:22 -0800884void __init s3c2416_init_irq(void)
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800885{
Heiko Stuebner4a282dd2013-01-29 10:25:22 -0800886 pr_info("S3C2416: IRQ Support\n");
887
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800888#ifdef CONFIG_FIQ
889 init_FIQ(FIQ_START);
890#endif
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800891
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900892 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
893 0x4a000000);
894 if (IS_ERR(s3c_intc[0])) {
Heiko Stuebner20f6c782013-01-29 10:25:22 -0800895 pr_err("irq: could not create main interrupt controller\n");
896 return;
897 }
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800898
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900899 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
900 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
901 s3c_intc[0], 0x4a000018);
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800902
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900903 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
904 NULL, 0x4a000040);
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800905}
906
Heiko Stuebneref602eb2013-01-29 10:25:22 -0800907#endif
Heiko Stuebner6b628912013-01-29 10:25:22 -0800908
Heiko Stuebnerf0301672013-02-12 09:59:35 -0800909#ifdef CONFIG_CPU_S3C2440
910static struct s3c_irq_data init_s3c2440base[32] = {
911 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
912 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
913 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
914 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
915 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
916 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
917 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
918 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
919 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
920 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
921 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
923 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
924 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
925 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
926 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
927 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
928 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
929 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
930 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
931 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
932 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
933 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
934 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
935 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
936 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
937 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
938 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
939 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
940 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
941 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
942 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -0800943};
944
Heiko Stuebnerf0301672013-02-12 09:59:35 -0800945static struct s3c_irq_data init_s3c2440subint[32] = {
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
953 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
954 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
955 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
956 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
Heiko Stuebnere2714f72013-04-04 14:53:37 +0900957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
Heiko Stuebnerf0301672013-02-12 09:59:35 -0800959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
960 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
Heiko Stuebner2286cf42013-02-12 09:59:24 -0800961};
962
Heiko Stuebner7cefed52013-02-12 09:59:27 -0800963void __init s3c2440_init_irq(void)
Heiko Stuebner2286cf42013-02-12 09:59:24 -0800964{
Heiko Stuebnerf0301672013-02-12 09:59:35 -0800965 pr_info("S3C2440: IRQ Support\n");
Heiko Stuebner2286cf42013-02-12 09:59:24 -0800966
Heiko Stuebnerf0301672013-02-12 09:59:35 -0800967#ifdef CONFIG_FIQ
968 init_FIQ(FIQ_START);
969#endif
Heiko Stuebnerce6c1642013-02-12 09:59:20 -0800970
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900971 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
972 0x4a000000);
973 if (IS_ERR(s3c_intc[0])) {
Heiko Stuebnerf0301672013-02-12 09:59:35 -0800974 pr_err("irq: could not create main interrupt controller\n");
975 return;
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -0800976 }
Heiko Stuebner7cefed52013-02-12 09:59:27 -0800977
Heiko Stuebner658dc8f2013-04-04 14:53:49 +0900978 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
979 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
980 s3c_intc[0], 0x4a000018);
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -0800981}
Heiko Stuebnerce6c1642013-02-12 09:59:20 -0800982#endif
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -0800983
Heiko Stuebnerce6c1642013-02-12 09:59:20 -0800984#ifdef CONFIG_CPU_S3C2442
Heiko Stuebner70644ad2013-02-12 09:59:31 -0800985static struct s3c_irq_data init_s3c2442base[32] = {
986 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
987 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
988 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
989 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
990 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
991 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
992 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
993 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
994 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
995 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
996 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
997 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
998 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
999 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1000 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1001 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1005 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1008 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1009 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1010 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1013 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1014 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1015 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1016 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1017 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1018};
1019
1020static struct s3c_irq_data init_s3c2442subint[32] = {
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1029 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1030 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1031 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
Heiko Stuebnere2714f72013-04-04 14:53:37 +09001032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1033 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
Heiko Stuebner70644ad2013-02-12 09:59:31 -08001034};
1035
Heiko Stuebnerce6c1642013-02-12 09:59:20 -08001036void __init s3c2442_init_irq(void)
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -08001037{
Heiko Stuebner70644ad2013-02-12 09:59:31 -08001038 pr_info("S3C2442: IRQ Support\n");
Heiko Stuebnerce6c1642013-02-12 09:59:20 -08001039
Heiko Stuebner70644ad2013-02-12 09:59:31 -08001040#ifdef CONFIG_FIQ
1041 init_FIQ(FIQ_START);
1042#endif
Heiko Stuebnerce6c1642013-02-12 09:59:20 -08001043
Heiko Stuebner658dc8f2013-04-04 14:53:49 +09001044 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1045 0x4a000000);
1046 if (IS_ERR(s3c_intc[0])) {
Heiko Stuebner70644ad2013-02-12 09:59:31 -08001047 pr_err("irq: could not create main interrupt controller\n");
1048 return;
Heiko Stuebnerce6c1642013-02-12 09:59:20 -08001049 }
Heiko Stuebner70644ad2013-02-12 09:59:31 -08001050
Heiko Stuebner658dc8f2013-04-04 14:53:49 +09001051 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1052 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1053 s3c_intc[0], 0x4a000018);
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -08001054}
Heiko Stuebnerce6c1642013-02-12 09:59:20 -08001055#endif
Heiko Stuebner6f8d7ea2013-02-12 09:59:17 -08001056
Heiko Stuebner6b628912013-01-29 10:25:22 -08001057#ifdef CONFIG_CPU_S3C2443
Heiko Stuebnerf44ddba2013-01-29 10:25:23 -08001058static struct s3c_irq_data init_s3c2443base[32] = {
1059 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1060 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1061 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1062 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1063 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1064 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1065 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1066 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1067 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1068 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1072 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1073 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1074 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1075 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1077 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1078 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1081 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1082 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1086 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1087 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1088 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1089 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1090 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
Heiko Stuebner6b628912013-01-29 10:25:22 -08001091};
1092
Heiko Stuebner6b628912013-01-29 10:25:22 -08001093
Heiko Stuebnerf44ddba2013-01-29 10:25:23 -08001094static struct s3c_irq_data init_s3c2443subint[32] = {
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1104 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1105 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1108 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1123 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
Heiko Stuebner6b628912013-01-29 10:25:22 -08001124};
1125
Heiko Stuebnerb499b7a2013-01-29 10:25:23 -08001126void __init s3c2443_init_irq(void)
Heiko Stuebner6b628912013-01-29 10:25:22 -08001127{
Heiko Stuebnerb499b7a2013-01-29 10:25:23 -08001128 pr_info("S3C2443: IRQ Support\n");
1129
Heiko Stuebnerf44ddba2013-01-29 10:25:23 -08001130#ifdef CONFIG_FIQ
1131 init_FIQ(FIQ_START);
1132#endif
Heiko Stuebner6b628912013-01-29 10:25:22 -08001133
Heiko Stuebner658dc8f2013-04-04 14:53:49 +09001134 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1135 0x4a000000);
1136 if (IS_ERR(s3c_intc[0])) {
Heiko Stuebnerf44ddba2013-01-29 10:25:23 -08001137 pr_err("irq: could not create main interrupt controller\n");
1138 return;
1139 }
Heiko Stuebner6b628912013-01-29 10:25:22 -08001140
Heiko Stuebner658dc8f2013-04-04 14:53:49 +09001141 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1142 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1143 s3c_intc[0], 0x4a000018);
Heiko Stuebner6b628912013-01-29 10:25:22 -08001144}
Heiko Stuebner6b628912013-01-29 10:25:22 -08001145#endif
Heiko Stuebnerf0774d42013-04-04 14:55:10 +09001146
1147#ifdef CONFIG_OF
1148static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1149 irq_hw_number_t hw)
1150{
1151 unsigned int ctrl_num = hw / 32;
1152 unsigned int intc_hw = hw % 32;
1153 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1154 struct s3c_irq_intc *parent_intc = intc->parent;
1155 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1156
1157 /* attach controller pointer to irq_data */
1158 irq_data->intc = intc;
1159 irq_data->offset = intc_hw;
1160
1161 if (!parent_intc)
1162 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1163 else
1164 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1165 handle_edge_irq);
1166
1167 irq_set_chip_data(virq, irq_data);
1168
Heiko Stuebnerf0774d42013-04-04 14:55:10 +09001169 return 0;
1170}
1171
1172/* Translate our of irq notation
1173 * format: <ctrl_num ctrl_irq parent_irq type>
1174 */
1175static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1176 const u32 *intspec, unsigned int intsize,
1177 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1178{
1179 struct s3c_irq_intc *intc;
1180 struct s3c_irq_intc *parent_intc;
1181 struct s3c_irq_data *irq_data;
1182 struct s3c_irq_data *parent_irq_data;
1183 int irqno;
1184
1185 if (WARN_ON(intsize < 4))
1186 return -EINVAL;
1187
1188 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1189 pr_err("controller number %d invalid\n", intspec[0]);
1190 return -EINVAL;
1191 }
1192 intc = s3c_intc[intspec[0]];
1193
1194 *out_hwirq = intspec[0] * 32 + intspec[2];
1195 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1196
1197 parent_intc = intc->parent;
1198 if (parent_intc) {
1199 irq_data = &intc->irqs[intspec[2]];
1200 irq_data->parent_irq = intspec[1];
1201 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1202 parent_irq_data->sub_intc = intc;
1203 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1204
1205 /* parent_intc is always s3c_intc[0], so no offset */
1206 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1207 if (irqno < 0) {
1208 pr_err("irq: could not map parent interrupt\n");
1209 return irqno;
1210 }
1211
1212 irq_set_chained_handler(irqno, s3c_irq_demux);
1213 }
1214
1215 return 0;
1216}
1217
Krzysztof Kozlowski96009732015-04-27 21:54:24 +09001218static const struct irq_domain_ops s3c24xx_irq_ops_of = {
Heiko Stuebnerf0774d42013-04-04 14:55:10 +09001219 .map = s3c24xx_irq_map_of,
1220 .xlate = s3c24xx_irq_xlate_of,
1221};
1222
1223struct s3c24xx_irq_of_ctrl {
1224 char *name;
1225 unsigned long offset;
1226 struct s3c_irq_intc **handle;
1227 struct s3c_irq_intc **parent;
1228 struct irq_domain_ops *ops;
1229};
1230
1231static int __init s3c_init_intc_of(struct device_node *np,
1232 struct device_node *interrupt_parent,
1233 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1234{
1235 struct s3c_irq_intc *intc;
1236 struct s3c24xx_irq_of_ctrl *ctrl;
1237 struct irq_domain *domain;
1238 void __iomem *reg_base;
1239 int i;
1240
1241 reg_base = of_iomap(np, 0);
1242 if (!reg_base) {
1243 pr_err("irq-s3c24xx: could not map irq registers\n");
1244 return -EINVAL;
1245 }
1246
1247 domain = irq_domain_add_linear(np, num_ctrl * 32,
1248 &s3c24xx_irq_ops_of, NULL);
1249 if (!domain) {
1250 pr_err("irq: could not create irq-domain\n");
1251 return -EINVAL;
1252 }
1253
1254 for (i = 0; i < num_ctrl; i++) {
1255 ctrl = &s3c_ctrl[i];
1256
1257 pr_debug("irq: found controller %s\n", ctrl->name);
1258
1259 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1260 if (!intc)
1261 return -ENOMEM;
1262
1263 intc->domain = domain;
1264 intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
1265 GFP_KERNEL);
1266 if (!intc->irqs) {
1267 kfree(intc);
1268 return -ENOMEM;
1269 }
1270
1271 if (ctrl->parent) {
1272 intc->reg_pending = reg_base + ctrl->offset;
1273 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1274
1275 if (*(ctrl->parent)) {
1276 intc->parent = *(ctrl->parent);
1277 } else {
1278 pr_warn("irq: parent of %s missing\n",
1279 ctrl->name);
1280 kfree(intc->irqs);
1281 kfree(intc);
1282 continue;
1283 }
1284 } else {
1285 intc->reg_pending = reg_base + ctrl->offset;
1286 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1287 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1288 }
1289
1290 s3c24xx_clear_intc(intc);
1291 s3c_intc[i] = intc;
1292 }
1293
1294 set_handle_irq(s3c24xx_handle_irq);
1295
1296 return 0;
1297}
1298
1299static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1300 {
1301 .name = "intc",
1302 .offset = 0,
1303 }, {
1304 .name = "subintc",
1305 .offset = 0x18,
1306 .parent = &s3c_intc[0],
1307 }
1308};
1309
1310int __init s3c2410_init_intc_of(struct device_node *np,
Rob Herring4f410832014-05-12 11:35:52 -05001311 struct device_node *interrupt_parent)
Heiko Stuebnerf0774d42013-04-04 14:55:10 +09001312{
1313 return s3c_init_intc_of(np, interrupt_parent,
1314 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1315}
1316IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1317
1318static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1319 {
1320 .name = "intc",
1321 .offset = 0,
1322 }, {
1323 .name = "subintc",
1324 .offset = 0x18,
1325 .parent = &s3c_intc[0],
1326 }, {
1327 .name = "intc2",
1328 .offset = 0x40,
1329 }
1330};
1331
1332int __init s3c2416_init_intc_of(struct device_node *np,
Rob Herring4f410832014-05-12 11:35:52 -05001333 struct device_node *interrupt_parent)
Heiko Stuebnerf0774d42013-04-04 14:55:10 +09001334{
1335 return s3c_init_intc_of(np, interrupt_parent,
1336 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
1337}
1338IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
1339#endif