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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Sergei Shtylyovb4e44362007-10-11 23:53:58 +02002 * linux/drivers/ide/pci/hpt366.c Version 1.13 Sep 29, 2007
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov38b66f82007-04-20 22:16:58 +02007 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
13 *
Alan Coxb39b01f2005-06-27 15:24:27 -070014 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080015 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070020 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 * Note that final HPT370 support was done by force extraction of GPL.
22 *
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
37 *
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
43 *
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
46 *
47 * On hpt366:
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
51 *
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * keeping me sane.
56 * Alan Cox <alan@redhat.com>
57 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080058 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010063 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080067 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080070 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020071 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
72 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080073 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080075 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
76 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010077 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
78 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010079 * - prefix the driver startup messages with the real chip name
80 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020081 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010082 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010083 * - cache offset of the channel's misc. control registers (MCRs) being used
84 * throughout the driver
85 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010087 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010088 * - move all the interrupt twiddling code from the speedproc handlers into
89 * init_hwif_hpt366(), also grouping all the DMA related code together there
90 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
91 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
92 * when setting an UltraDMA mode
93 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
94 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010095 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010096 * - switch to using the enumeration type to differ between the numerous chip
97 * variants, matching PCI device/revision ID with the chip type early, at the
98 * init_setup stage
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
100 * stop duplicating it for each channel by storing the pointer in the pci_dev
101 * structure: first, at the init_setup stage, point it to a static "template"
102 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200103 * UltraDMA mode, and the chip settings table pointer filled, then, at the
104 * init_chipset stage, allocate per-chip instance and fill it with the rest
105 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * frequency
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200110 * anything newer than HPT370/A (except HPT374 that is not capable of this
111 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
113 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100114 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
115 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200116 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200117 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100118 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 */
120
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121#include <linux/types.h>
122#include <linux/module.h>
123#include <linux/kernel.h>
124#include <linux/delay.h>
125#include <linux/timer.h>
126#include <linux/mm.h>
127#include <linux/ioport.h>
128#include <linux/blkdev.h>
129#include <linux/hdreg.h>
130
131#include <linux/interrupt.h>
132#include <linux/pci.h>
133#include <linux/init.h>
134#include <linux/ide.h>
135
136#include <asm/uaccess.h>
137#include <asm/io.h>
138#include <asm/irq.h>
139
140/* various tuning parameters */
141#define HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800142#undef HPT_DELAY_INTERRUPT
143#define HPT_SERIALIZE_IO 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144
145static const char *quirk_drives[] = {
146 "QUANTUM FIREBALLlct08 08",
147 "QUANTUM FIREBALLP KA6.4",
148 "QUANTUM FIREBALLP LM20.4",
149 "QUANTUM FIREBALLP LM20.5",
150 NULL
151};
152
153static const char *bad_ata100_5[] = {
154 "IBM-DTLA-307075",
155 "IBM-DTLA-307060",
156 "IBM-DTLA-307045",
157 "IBM-DTLA-307030",
158 "IBM-DTLA-307020",
159 "IBM-DTLA-307015",
160 "IBM-DTLA-305040",
161 "IBM-DTLA-305030",
162 "IBM-DTLA-305020",
163 "IC35L010AVER07-0",
164 "IC35L020AVER07-0",
165 "IC35L030AVER07-0",
166 "IC35L040AVER07-0",
167 "IC35L060AVER07-0",
168 "WDC AC310200R",
169 NULL
170};
171
172static const char *bad_ata66_4[] = {
173 "IBM-DTLA-307075",
174 "IBM-DTLA-307060",
175 "IBM-DTLA-307045",
176 "IBM-DTLA-307030",
177 "IBM-DTLA-307020",
178 "IBM-DTLA-307015",
179 "IBM-DTLA-305040",
180 "IBM-DTLA-305030",
181 "IBM-DTLA-305020",
182 "IC35L010AVER07-0",
183 "IC35L020AVER07-0",
184 "IC35L030AVER07-0",
185 "IC35L040AVER07-0",
186 "IC35L060AVER07-0",
187 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200188 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 NULL
190};
191
192static const char *bad_ata66_3[] = {
193 "WDC AC310200R",
194 NULL
195};
196
197static const char *bad_ata33[] = {
198 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
199 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
200 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
201 "Maxtor 90510D4",
202 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
203 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
204 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
205 NULL
206};
207
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800208static u8 xfer_speeds[] = {
209 XFER_UDMA_6,
210 XFER_UDMA_5,
211 XFER_UDMA_4,
212 XFER_UDMA_3,
213 XFER_UDMA_2,
214 XFER_UDMA_1,
215 XFER_UDMA_0,
216
217 XFER_MW_DMA_2,
218 XFER_MW_DMA_1,
219 XFER_MW_DMA_0,
220
221 XFER_PIO_4,
222 XFER_PIO_3,
223 XFER_PIO_2,
224 XFER_PIO_1,
225 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226};
227
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800228/* Key for bus clock timings
229 * 36x 37x
230 * bits bits
231 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
232 * cycles = value + 1
233 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
234 * cycles = value + 1
235 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
236 * register access.
237 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
238 * register access.
239 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
240 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
241 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
242 * MW DMA xfer.
243 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
244 * task file register access.
245 * 28 28 UDMA enable.
246 * 29 29 DMA enable.
247 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
248 * PIO xfer.
249 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800252static u32 forty_base_hpt36x[] = {
253 /* XFER_UDMA_6 */ 0x900fd943,
254 /* XFER_UDMA_5 */ 0x900fd943,
255 /* XFER_UDMA_4 */ 0x900fd943,
256 /* XFER_UDMA_3 */ 0x900ad943,
257 /* XFER_UDMA_2 */ 0x900bd943,
258 /* XFER_UDMA_1 */ 0x9008d943,
259 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800261 /* XFER_MW_DMA_2 */ 0xa008d943,
262 /* XFER_MW_DMA_1 */ 0xa010d955,
263 /* XFER_MW_DMA_0 */ 0xa010d9fc,
264
265 /* XFER_PIO_4 */ 0xc008d963,
266 /* XFER_PIO_3 */ 0xc010d974,
267 /* XFER_PIO_2 */ 0xc010d997,
268 /* XFER_PIO_1 */ 0xc010d9c7,
269 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270};
271
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800272static u32 thirty_three_base_hpt36x[] = {
273 /* XFER_UDMA_6 */ 0x90c9a731,
274 /* XFER_UDMA_5 */ 0x90c9a731,
275 /* XFER_UDMA_4 */ 0x90c9a731,
276 /* XFER_UDMA_3 */ 0x90cfa731,
277 /* XFER_UDMA_2 */ 0x90caa731,
278 /* XFER_UDMA_1 */ 0x90cba731,
279 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800281 /* XFER_MW_DMA_2 */ 0xa0c8a731,
282 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
283 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800285 /* XFER_PIO_4 */ 0xc0c8a731,
286 /* XFER_PIO_3 */ 0xc0c8a742,
287 /* XFER_PIO_2 */ 0xc0d0a753,
288 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
289 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290};
291
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800292static u32 twenty_five_base_hpt36x[] = {
293 /* XFER_UDMA_6 */ 0x90c98521,
294 /* XFER_UDMA_5 */ 0x90c98521,
295 /* XFER_UDMA_4 */ 0x90c98521,
296 /* XFER_UDMA_3 */ 0x90cf8521,
297 /* XFER_UDMA_2 */ 0x90cf8521,
298 /* XFER_UDMA_1 */ 0x90cb8521,
299 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800301 /* XFER_MW_DMA_2 */ 0xa0ca8521,
302 /* XFER_MW_DMA_1 */ 0xa0ca8532,
303 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800305 /* XFER_PIO_4 */ 0xc0ca8521,
306 /* XFER_PIO_3 */ 0xc0ca8532,
307 /* XFER_PIO_2 */ 0xc0ca8542,
308 /* XFER_PIO_1 */ 0xc0d08572,
309 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310};
311
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800312static u32 thirty_three_base_hpt37x[] = {
313 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
314 /* XFER_UDMA_5 */ 0x12446231,
315 /* XFER_UDMA_4 */ 0x12446231,
316 /* XFER_UDMA_3 */ 0x126c6231,
317 /* XFER_UDMA_2 */ 0x12486231,
318 /* XFER_UDMA_1 */ 0x124c6233,
319 /* XFER_UDMA_0 */ 0x12506297,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800321 /* XFER_MW_DMA_2 */ 0x22406c31,
322 /* XFER_MW_DMA_1 */ 0x22406c33,
323 /* XFER_MW_DMA_0 */ 0x22406c97,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800325 /* XFER_PIO_4 */ 0x06414e31,
326 /* XFER_PIO_3 */ 0x06414e42,
327 /* XFER_PIO_2 */ 0x06414e53,
328 /* XFER_PIO_1 */ 0x06814e93,
329 /* XFER_PIO_0 */ 0x06814ea7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330};
331
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800332static u32 fifty_base_hpt37x[] = {
333 /* XFER_UDMA_6 */ 0x12848242,
334 /* XFER_UDMA_5 */ 0x12848242,
335 /* XFER_UDMA_4 */ 0x12ac8242,
336 /* XFER_UDMA_3 */ 0x128c8242,
337 /* XFER_UDMA_2 */ 0x120c8242,
338 /* XFER_UDMA_1 */ 0x12148254,
339 /* XFER_UDMA_0 */ 0x121882ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800341 /* XFER_MW_DMA_2 */ 0x22808242,
342 /* XFER_MW_DMA_1 */ 0x22808254,
343 /* XFER_MW_DMA_0 */ 0x228082ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800345 /* XFER_PIO_4 */ 0x0a81f442,
346 /* XFER_PIO_3 */ 0x0a81f443,
347 /* XFER_PIO_2 */ 0x0a81f454,
348 /* XFER_PIO_1 */ 0x0ac1f465,
349 /* XFER_PIO_0 */ 0x0ac1f48a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350};
351
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800352static u32 sixty_six_base_hpt37x[] = {
353 /* XFER_UDMA_6 */ 0x1c869c62,
354 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
355 /* XFER_UDMA_4 */ 0x1c8a9c62,
356 /* XFER_UDMA_3 */ 0x1c8e9c62,
357 /* XFER_UDMA_2 */ 0x1c929c62,
358 /* XFER_UDMA_1 */ 0x1c9a9c62,
359 /* XFER_UDMA_0 */ 0x1c829c62,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800361 /* XFER_MW_DMA_2 */ 0x2c829c62,
362 /* XFER_MW_DMA_1 */ 0x2c829c66,
363 /* XFER_MW_DMA_0 */ 0x2c829d2e,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800365 /* XFER_PIO_4 */ 0x0c829c62,
366 /* XFER_PIO_3 */ 0x0c829c84,
367 /* XFER_PIO_2 */ 0x0c829ca6,
368 /* XFER_PIO_1 */ 0x0d029d26,
369 /* XFER_PIO_0 */ 0x0d029d5e
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370};
371
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372#define HPT366_DEBUG_DRIVE_INFO 0
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100373#define HPT371_ALLOW_ATA133_6 1
374#define HPT302_ALLOW_ATA133_6 1
375#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100376#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377#define HPT366_ALLOW_ATA66_4 1
378#define HPT366_ALLOW_ATA66_3 1
379#define HPT366_MAX_DEVS 8
380
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100381/* Supported ATA clock frequencies */
382enum ata_clock {
383 ATA_CLOCK_25MHZ,
384 ATA_CLOCK_33MHZ,
385 ATA_CLOCK_40MHZ,
386 ATA_CLOCK_50MHZ,
387 ATA_CLOCK_66MHZ,
388 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700389};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390
Alan Coxb39b01f2005-06-27 15:24:27 -0700391/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100392 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700393 */
394
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100395struct hpt_info {
396 u8 chip_type; /* Chip type */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200397 u8 max_ultra; /* Max. UltraDMA mode allowed */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100398 u8 dpll_clk; /* DPLL clock in MHz */
399 u8 pci_clk; /* PCI clock in MHz */
400 u32 **settings; /* Chipset settings table */
401};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100402
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100403/* Supported HighPoint chips */
404enum {
405 HPT36x,
406 HPT370,
407 HPT370A,
408 HPT374,
409 HPT372,
410 HPT372A,
411 HPT302,
412 HPT371,
413 HPT372N,
414 HPT302N,
415 HPT371N
416};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100418static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
419 twenty_five_base_hpt36x,
420 thirty_three_base_hpt36x,
421 forty_base_hpt36x,
422 NULL,
423 NULL
424};
425
426static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
427 NULL,
428 thirty_three_base_hpt37x,
429 NULL,
430 fifty_base_hpt37x,
431 sixty_six_base_hpt37x
432};
433
434static struct hpt_info hpt36x __devinitdata = {
435 .chip_type = HPT36x,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200436 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100437 .dpll_clk = 0, /* no DPLL */
438 .settings = hpt36x_settings
439};
440
441static struct hpt_info hpt370 __devinitdata = {
442 .chip_type = HPT370,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200443 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100444 .dpll_clk = 48,
445 .settings = hpt37x_settings
446};
447
448static struct hpt_info hpt370a __devinitdata = {
449 .chip_type = HPT370A,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200450 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100451 .dpll_clk = 48,
452 .settings = hpt37x_settings
453};
454
455static struct hpt_info hpt374 __devinitdata = {
456 .chip_type = HPT374,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200457 .max_ultra = 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100458 .dpll_clk = 48,
459 .settings = hpt37x_settings
460};
461
462static struct hpt_info hpt372 __devinitdata = {
463 .chip_type = HPT372,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200464 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100465 .dpll_clk = 55,
466 .settings = hpt37x_settings
467};
468
469static struct hpt_info hpt372a __devinitdata = {
470 .chip_type = HPT372A,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200471 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100472 .dpll_clk = 66,
473 .settings = hpt37x_settings
474};
475
476static struct hpt_info hpt302 __devinitdata = {
477 .chip_type = HPT302,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200478 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100479 .dpll_clk = 66,
480 .settings = hpt37x_settings
481};
482
483static struct hpt_info hpt371 __devinitdata = {
484 .chip_type = HPT371,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200485 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100486 .dpll_clk = 66,
487 .settings = hpt37x_settings
488};
489
490static struct hpt_info hpt372n __devinitdata = {
491 .chip_type = HPT372N,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200492 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100493 .dpll_clk = 77,
494 .settings = hpt37x_settings
495};
496
497static struct hpt_info hpt302n __devinitdata = {
498 .chip_type = HPT302N,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200499 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100500 .dpll_clk = 77,
Sergei Shtylyov38b66f82007-04-20 22:16:58 +0200501 .settings = hpt37x_settings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100502};
503
504static struct hpt_info hpt371n __devinitdata = {
505 .chip_type = HPT371N,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200506 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100507 .dpll_clk = 77,
508 .settings = hpt37x_settings
509};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100511static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512{
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100513 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100515 while (*list)
516 if (!strcmp(*list++,id->model))
517 return 1;
518 return 0;
519}
Alan Coxb39b01f2005-06-27 15:24:27 -0700520
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200522 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
523 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200525
526static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527{
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200528 ide_hwif_t *hwif = HWIF(drive);
529 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
530 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200532 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200533 case HPT36x:
534 if (!HPT366_ALLOW_ATA66_4 ||
535 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200536 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100537
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200538 if (!HPT366_ALLOW_ATA66_3 ||
539 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200540 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200541 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200542 case HPT370:
543 if (!HPT370_ALLOW_ATA100_5 ||
544 check_in_drive_list(drive, bad_ata100_5))
545 mask = ATA_UDMA4;
546 break;
547 case HPT370A:
548 if (!HPT370_ALLOW_ATA100_5 ||
549 check_in_drive_list(drive, bad_ata100_5))
550 return ATA_UDMA4;
551 case HPT372 :
552 case HPT372A:
553 case HPT372N:
554 case HPT374 :
555 if (ide_dev_is_sata(drive->id))
556 mask &= ~0x0e;
557 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200558 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200559 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200561
562 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563}
564
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200565static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
566{
567 ide_hwif_t *hwif = HWIF(drive);
568 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
569
570 switch (info->chip_type) {
571 case HPT372 :
572 case HPT372A:
573 case HPT372N:
574 case HPT374 :
575 if (ide_dev_is_sata(drive->id))
576 return 0x00;
577 /* Fall thru */
578 default:
579 return 0x07;
580 }
581}
582
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100583static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800585 int i;
586
587 /*
588 * Lookup the transfer mode table to get the index into
589 * the timing table.
590 *
591 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
592 */
593 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
594 if (xfer_speeds[i] == speed)
595 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100596 /*
597 * NOTE: info->settings only points to the pointer
598 * to the list of the actual register values
599 */
600 return (*info->settings)[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601}
602
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200603static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100605 ide_hwif_t *hwif = HWIF(drive);
606 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100607 struct hpt_info *info = pci_get_drvdata(dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100608 u8 itr_addr = drive->dn ? 0x44 : 0x40;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100609 u32 old_itr = 0;
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200610 u32 itr_mask, new_itr;
611
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200612 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
613 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
614
615 new_itr = get_speed_setting(speed, info);
Alan Coxb39b01f2005-06-27 15:24:27 -0700616
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100618 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
619 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100621 pci_read_config_dword(dev, itr_addr, &old_itr);
622 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
623 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100625 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626}
627
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200628static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100630 ide_hwif_t *hwif = HWIF(drive);
631 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100632 struct hpt_info *info = pci_get_drvdata(dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100633 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100634 u32 old_itr = 0;
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200635 u32 itr_mask, new_itr;
636
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200637 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
638 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
639
640 new_itr = get_speed_setting(speed, info);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100642 pci_read_config_dword(dev, itr_addr, &old_itr);
643 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644
Alan Coxb39b01f2005-06-27 15:24:27 -0700645 if (speed < XFER_MW_DMA_0)
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100646 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
647 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648}
649
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200650static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100652 ide_hwif_t *hwif = HWIF(drive);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100653 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100655 if (info->chip_type >= HPT370)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200656 hpt37x_set_mode(drive, speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 else /* hpt368: hpt_minimum_revision(dev, 2) */
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200658 hpt36x_set_mode(drive, speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659}
660
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200661static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662{
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200663 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664}
665
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100666static int hpt3xx_quirkproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667{
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100668 struct hd_driveid *id = drive->id;
669 const char **list = quirk_drives;
670
671 while (*list)
672 if (strstr(id->model, *list++))
673 return 1;
674 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675}
676
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100677static void hpt3xx_intrproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100679 ide_hwif_t *hwif = HWIF(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680
681 if (drive->quirk_list)
682 return;
683 /* drives in the quirk_list may not like intr setups/cleanups */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100684 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685}
686
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100687static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100689 ide_hwif_t *hwif = HWIF(drive);
690 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100691 struct hpt_info *info = pci_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
693 if (drive->quirk_list) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100694 if (info->chip_type >= HPT370) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100695 u8 scr1 = 0;
696
697 pci_read_config_byte(dev, 0x5a, &scr1);
698 if (((scr1 & 0x10) >> 4) != mask) {
699 if (mask)
700 scr1 |= 0x10;
701 else
702 scr1 &= ~0x10;
703 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 }
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100705 } else {
706 if (mask)
707 disable_irq(hwif->irq);
708 else
709 enable_irq (hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 }
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100711 } else
712 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
713 IDE_CONTROL_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714}
715
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100716static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 drive->init_speed = 0;
719
Bartlomiej Zolnierkiewicz29e744d2007-05-10 00:01:09 +0200720 if (ide_tune_dma(drive))
Bartlomiej Zolnierkiewicz3608b5d2007-02-17 02:40:26 +0100721 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722
Bartlomiej Zolnierkiewiczd8f44692007-02-17 02:40:25 +0100723 if (ide_use_fast_pio(drive))
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200724 ide_set_max_pio(drive);
Bartlomiej Zolnierkiewiczd8f44692007-02-17 02:40:25 +0100725
Bartlomiej Zolnierkiewicz3608b5d2007-02-17 02:40:26 +0100726 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727}
728
729/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100730 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 * by HighPoint|Triones Technologies, Inc.
732 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200733static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100735 struct pci_dev *dev = HWIF(drive)->pci_dev;
736 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100738 pci_read_config_byte(dev, 0x50, &mcr1);
739 pci_read_config_byte(dev, 0x52, &mcr3);
740 pci_read_config_byte(dev, 0x5a, &scr1);
741 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
742 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
743 if (scr1 & 0x10)
744 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200745 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746}
747
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100748static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100750 ide_hwif_t *hwif = HWIF(drive);
751
752 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 udelay(10);
754}
755
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100756static void hpt370_irq_timeout(ide_drive_t *drive)
757{
758 ide_hwif_t *hwif = HWIF(drive);
759 u16 bfifo = 0;
760 u8 dma_cmd;
761
762 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
763 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
764
765 /* get DMA command mode */
766 dma_cmd = hwif->INB(hwif->dma_command);
767 /* stop DMA */
768 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
769 hpt370_clear_engine(drive);
770}
771
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772static void hpt370_ide_dma_start(ide_drive_t *drive)
773{
774#ifdef HPT_RESET_STATE_ENGINE
775 hpt370_clear_engine(drive);
776#endif
777 ide_dma_start(drive);
778}
779
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100780static int hpt370_ide_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781{
782 ide_hwif_t *hwif = HWIF(drive);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100783 u8 dma_stat = hwif->INB(hwif->dma_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784
785 if (dma_stat & 0x01) {
786 /* wait a little */
787 udelay(20);
788 dma_stat = hwif->INB(hwif->dma_status);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100789 if (dma_stat & 0x01)
790 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 return __ide_dma_end(drive);
793}
794
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200795static void hpt370_dma_timeout(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796{
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100797 hpt370_irq_timeout(drive);
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200798 ide_dma_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799}
800
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801/* returns 1 if DMA IRQ issued, 0 otherwise */
802static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
803{
804 ide_hwif_t *hwif = HWIF(drive);
805 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100806 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100808 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 if (bfifo & 0x1FF) {
810// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
811 return 0;
812 }
813
Bartlomiej Zolnierkiewicz0ecdca22007-02-17 02:40:25 +0100814 dma_stat = inb(hwif->dma_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 /* return 1 if INTR asserted */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100816 if (dma_stat & 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 return 1;
818
819 if (!drive->waiting_for_dma)
820 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
821 drive->name, __FUNCTION__);
822 return 0;
823}
824
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100825static int hpt374_ide_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 ide_hwif_t *hwif = HWIF(drive);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100828 struct pci_dev *dev = hwif->pci_dev;
829 u8 mcr = 0, mcr_addr = hwif->select_data;
830 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100832 pci_read_config_byte(dev, 0x6a, &bwsr);
833 pci_read_config_byte(dev, mcr_addr, &mcr);
834 if (bwsr & mask)
835 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 return __ide_dma_end(drive);
837}
838
839/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800840 * hpt3xxn_set_clock - perform clock switching dance
841 * @hwif: hwif to switch
842 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800844 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800846
847static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100849 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800850
851 if ((scr2 & 0x7f) == mode)
852 return;
853
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854 /* Tristate the bus */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100855 hwif->OUTB(0x80, hwif->dma_master + 0x73);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800856 hwif->OUTB(0x80, hwif->dma_master + 0x77);
857
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 /* Switch clock and reset channels */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800859 hwif->OUTB(mode, hwif->dma_master + 0x7b);
860 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
861
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100862 /*
863 * Reset the state machines.
864 * NOTE: avoid accidentally enabling the disabled channels.
865 */
866 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
867 hwif->dma_master + 0x70);
868 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
869 hwif->dma_master + 0x74);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800870
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 /* Complete reset */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800872 hwif->OUTB(0x00, hwif->dma_master + 0x79);
873
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 /* Reconnect channels to bus */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100875 hwif->OUTB(0x00, hwif->dma_master + 0x73);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800876 hwif->OUTB(0x00, hwif->dma_master + 0x77);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877}
878
879/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800880 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 * @drive: drive for command
882 * @rq: block request structure
883 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800884 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700885 * We need it because of the clock switching.
886 */
887
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800888static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100890 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891}
892
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893/*
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800894 * Set/get power state for a drive.
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100895 * NOTE: affects both drives on each channel.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 *
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800897 * When we turn the power back on, we need to re-initialize things.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 */
899#define TRISTATE_BIT 0x8000
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800900
901static int hpt3xx_busproc(ide_drive_t *drive, int state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100903 ide_hwif_t *hwif = HWIF(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100905 u8 mcr_addr = hwif->select_data + 2;
906 u8 resetmask = hwif->channel ? 0x80 : 0x40;
907 u8 bsr2 = 0;
908 u16 mcr = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909
910 hwif->bus_state = state;
911
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800912 /* Grab the status. */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100913 pci_read_config_word(dev, mcr_addr, &mcr);
914 pci_read_config_byte(dev, 0x59, &bsr2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800916 /*
917 * Set the state. We don't set it if we don't need to do so.
918 * Make sure that the drive knows that it has failed if it's off.
919 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 switch (state) {
921 case BUSSTATE_ON:
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100922 if (!(bsr2 & resetmask))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700923 return 0;
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800924 hwif->drives[0].failures = hwif->drives[1].failures = 0;
925
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100926 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
927 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800928 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929 case BUSSTATE_OFF:
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100930 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 return 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100932 mcr &= ~TRISTATE_BIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 break;
934 case BUSSTATE_TRISTATE:
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100935 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936 return 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100937 mcr |= TRISTATE_BIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 break;
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800939 default:
940 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942
Sergei Shtylyov33b18a62006-12-13 00:35:50 -0800943 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
944 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
945
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100946 pci_write_config_word(dev, mcr_addr, mcr);
947 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700948 return 0;
949}
950
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100951/**
952 * hpt37x_calibrate_dpll - calibrate the DPLL
953 * @dev: PCI device
954 *
955 * Perform a calibration cycle on the DPLL.
956 * Returns 1 if this succeeds
957 */
958static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100960 u32 dpll = (f_high << 16) | f_low | 0x100;
961 u8 scr2;
962 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700963
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100964 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700965
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100966 /* Wait for oscillator ready */
967 for(i = 0; i < 0x5000; ++i) {
968 udelay(50);
969 pci_read_config_byte(dev, 0x5b, &scr2);
970 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700971 break;
972 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100973 /* See if it stays ready (we'll just bail out if it's not yet) */
974 for(i = 0; i < 0x1000; ++i) {
975 pci_read_config_byte(dev, 0x5b, &scr2);
976 /* DPLL destabilized? */
977 if(!(scr2 & 0x80))
978 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100979 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100980 /* Turn off tuning, we have the DPLL set */
981 pci_read_config_dword (dev, 0x5c, &dpll);
982 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
983 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700984}
985
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
987{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100988 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
989 unsigned long io_base = pci_resource_start(dev, 4);
990 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200991 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100992 enum ata_clock clock;
993
994 if (info == NULL) {
995 printk(KERN_ERR "%s: out of memory!\n", name);
996 return -ENOMEM;
997 }
998
999 /*
1000 * Copy everything from a static "template" structure
1001 * to just allocated per-chip hpt_info structure.
1002 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001003 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
1004 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001005
Alan Coxb39b01f2005-06-27 15:24:27 -07001006 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1007 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1008 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1009 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001011 /*
1012 * First, try to estimate the PCI clock frequency...
1013 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001014 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001015 u8 scr1 = 0;
1016 u16 f_cnt = 0;
1017 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -07001018
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001019 /* Interrupt force enable. */
1020 pci_read_config_byte(dev, 0x5a, &scr1);
1021 if (scr1 & 0x10)
1022 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001023
1024 /*
1025 * HighPoint does this for HPT372A.
1026 * NOTE: This register is only writeable via I/O space.
1027 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001028 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001029 outb(0x0e, io_base + 0x9c);
1030
1031 /*
1032 * Default to PCI clock. Make sure MA15/16 are set to output
1033 * to prevent drives having problems with 40-pin cables.
1034 */
1035 pci_write_config_byte(dev, 0x5b, 0x23);
1036
1037 /*
1038 * We'll have to read f_CNT value in order to determine
1039 * the PCI clock frequency according to the following ratio:
1040 *
1041 * f_CNT = Fpci * 192 / Fdpll
1042 *
1043 * First try reading the register in which the HighPoint BIOS
1044 * saves f_CNT value before reprogramming the DPLL from its
1045 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001046 *
Sergei Shtylyov72931362007-09-11 22:28:35 +02001047 * NOTE: This register is only accessible via I/O space;
1048 * HPT374 BIOS only saves it for the function 0, so we have to
1049 * always read it from there -- no need to check the result of
1050 * pci_get_slot() for the function 0 as the whole device has
1051 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001052 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001053 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1054 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1055 dev->devfn - 1);
1056 unsigned long io_base = pci_resource_start(dev1, 4);
1057
1058 temp = inl(io_base + 0x90);
1059 pci_dev_put(dev1);
1060 } else
1061 temp = inl(io_base + 0x90);
1062
1063 /*
1064 * In case the signature check fails, we'll have to
1065 * resort to reading the f_CNT register itself in hopes
1066 * that nobody has touched the DPLL yet...
1067 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001068 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1069 int i;
1070
1071 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1072 name);
1073
1074 /* Calculate the average value of f_CNT. */
1075 for (temp = i = 0; i < 128; i++) {
1076 pci_read_config_word(dev, 0x78, &f_cnt);
1077 temp += f_cnt & 0x1ff;
1078 mdelay(1);
1079 }
1080 f_cnt = temp / 128;
1081 } else
1082 f_cnt = temp & 0x1ff;
1083
1084 dpll_clk = info->dpll_clk;
1085 pci_clk = (f_cnt * dpll_clk) / 192;
1086
1087 /* Clamp PCI clock to bands. */
1088 if (pci_clk < 40)
1089 pci_clk = 33;
1090 else if(pci_clk < 45)
1091 pci_clk = 40;
1092 else if(pci_clk < 55)
1093 pci_clk = 50;
1094 else
1095 pci_clk = 66;
1096
1097 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1098 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1099 } else {
1100 u32 itr1 = 0;
1101
1102 pci_read_config_dword(dev, 0x40, &itr1);
1103
1104 /* Detect PCI clock by looking at cmd_high_time. */
1105 switch((itr1 >> 8) & 0x07) {
1106 case 0x09:
1107 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001108 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001109 case 0x05:
1110 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001111 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001112 case 0x07:
1113 default:
1114 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001115 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001116 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001117 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001119 /* Let's assume we'll use PCI clock for the ATA clock... */
1120 switch (pci_clk) {
1121 case 25:
1122 clock = ATA_CLOCK_25MHZ;
1123 break;
1124 case 33:
1125 default:
1126 clock = ATA_CLOCK_33MHZ;
1127 break;
1128 case 40:
1129 clock = ATA_CLOCK_40MHZ;
1130 break;
1131 case 50:
1132 clock = ATA_CLOCK_50MHZ;
1133 break;
1134 case 66:
1135 clock = ATA_CLOCK_66MHZ;
1136 break;
1137 }
1138
1139 /*
1140 * Only try the DPLL if we don't have a table for the PCI clock that
1141 * we are running at for HPT370/A, always use it for anything newer...
1142 *
1143 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1144 * We also don't like using the DPLL because this causes glitches
1145 * on PRST-/SRST- when the state engine gets reset...
1146 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001147 if (chip_type >= HPT374 || info->settings[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001148 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1149 int adjust;
1150
1151 /*
1152 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1153 * supported/enabled, use 50 MHz DPLL clock otherwise...
1154 */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001155 if (info->max_ultra == 6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001156 dpll_clk = 66;
1157 clock = ATA_CLOCK_66MHZ;
1158 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1159 dpll_clk = 50;
1160 clock = ATA_CLOCK_50MHZ;
1161 }
1162
1163 if (info->settings[clock] == NULL) {
1164 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1165 kfree(info);
1166 return -EIO;
1167 }
1168
1169 /* Select the DPLL clock. */
1170 pci_write_config_byte(dev, 0x5b, 0x21);
1171
1172 /*
1173 * Adjust the DPLL based upon PCI clock, enable it,
1174 * and wait for stabilization...
1175 */
1176 f_low = (pci_clk * 48) / dpll_clk;
1177
1178 for (adjust = 0; adjust < 8; adjust++) {
1179 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1180 break;
1181
1182 /*
1183 * See if it'll settle at a fractionally different clock
1184 */
1185 if (adjust & 1)
1186 f_low -= adjust >> 1;
1187 else
1188 f_low += adjust >> 1;
1189 }
1190 if (adjust == 8) {
1191 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1192 kfree(info);
1193 return -EIO;
1194 }
1195
1196 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1197 } else {
1198 /* Mark the fact that we're not using the DPLL. */
1199 dpll_clk = 0;
1200
1201 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1202 }
1203
1204 /*
1205 * Advance the table pointer to a slot which points to the list
1206 * of the register values settings matching the clock being used.
1207 */
1208 info->settings += clock;
1209
1210 /* Store the clock frequencies. */
1211 info->dpll_clk = dpll_clk;
1212 info->pci_clk = pci_clk;
1213
1214 /* Point to this chip's own instance of the hpt_info structure. */
1215 pci_set_drvdata(dev, info);
1216
Sergei Shtylyov72931362007-09-11 22:28:35 +02001217 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001218 u8 mcr1, mcr4;
1219
1220 /*
1221 * Reset the state engines.
1222 * NOTE: Avoid accidentally enabling the disabled channels.
1223 */
1224 pci_read_config_byte (dev, 0x50, &mcr1);
1225 pci_read_config_byte (dev, 0x54, &mcr4);
1226 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1227 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1228 udelay(100);
1229 }
1230
1231 /*
1232 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1233 * the MISC. register to stretch the UltraDMA Tss timing.
1234 * NOTE: This register is only writeable via I/O space.
1235 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001236 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001237
1238 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1239
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 return dev->irq;
1241}
1242
1243static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1244{
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001245 struct pci_dev *dev = hwif->pci_dev;
1246 struct hpt_info *info = pci_get_drvdata(dev);
1247 int serialize = HPT_SERIALIZE_IO;
1248 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1249 u8 chip_type = info->chip_type;
1250 u8 new_mcr, old_mcr = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001251
1252 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001253 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001254
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +02001255 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +02001256 hwif->set_dma_mode = &hpt3xx_set_mode;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001257 hwif->quirkproc = &hpt3xx_quirkproc;
1258 hwif->intrproc = &hpt3xx_intrproc;
1259 hwif->maskproc = &hpt3xx_maskproc;
1260 hwif->busproc = &hpt3xx_busproc;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001261
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001262 hwif->udma_filter = &hpt3xx_udma_filter;
Sergei Shtylyovb4e44362007-10-11 23:53:58 +02001263 hwif->mdma_filter = &hpt3xx_mdma_filter;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001264
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001265 /*
1266 * HPT3xxN chips have some complications:
1267 *
1268 * - on 33 MHz PCI we must clock switch
1269 * - on 66 MHz PCI we must NOT use the PCI clock
1270 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001271 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001272 /*
1273 * Clock is shared between the channels,
1274 * so we'll have to serialize them... :-(
1275 */
1276 serialize = 1;
1277 hwif->rw_disk = &hpt3xxn_rw_disk;
1278 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001280 /* Serialize access to this device if needed */
1281 if (serialize && hwif->mate)
1282 hwif->serialized = hwif->mate->serialized = 1;
1283
1284 /*
1285 * Disable the "fast interrupt" prediction. Don't hold off
1286 * on interrupts. (== 0x01 despite what the docs say)
1287 */
1288 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1289
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001290 if (info->chip_type >= HPT374)
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001291 new_mcr = old_mcr & ~0x07;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001292 else if (info->chip_type >= HPT370) {
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001293 new_mcr = old_mcr;
1294 new_mcr &= ~0x02;
1295
1296#ifdef HPT_DELAY_INTERRUPT
1297 new_mcr &= ~0x01;
1298#else
1299 new_mcr |= 0x01;
1300#endif
1301 } else /* HPT366 and HPT368 */
1302 new_mcr = old_mcr & ~0x80;
1303
1304 if (new_mcr != old_mcr)
1305 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1306
1307 if (!hwif->dma_base) {
1308 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1309 return;
1310 }
1311
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001312 hwif->ultra_mask = hwif->cds->udma_mask;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001313 hwif->mwdma_mask = 0x07;
1314
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315 /*
1316 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001317 * address lines to access an external EEPROM. To read valid
Linus Torvalds1da177e2005-04-16 15:20:36 -07001318 * cable detect state the pins must be enabled as inputs.
1319 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001320 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321 /*
1322 * HPT374 PCI function 1
1323 * - set bit 15 of reg 0x52 to enable TCBLID as input
1324 * - set bit 15 of reg 0x56 to enable FCBLID as input
1325 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001326 u8 mcr_addr = hwif->select_data + 2;
1327 u16 mcr;
1328
1329 pci_read_config_word (dev, mcr_addr, &mcr);
1330 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001331 /* now read cable id register */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001332 pci_read_config_byte (dev, 0x5a, &scr1);
1333 pci_write_config_word(dev, mcr_addr, mcr);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001334 } else if (chip_type >= HPT370) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001335 /*
1336 * HPT370/372 and 374 pcifn 0
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001337 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
Linus Torvalds1da177e2005-04-16 15:20:36 -07001338 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001339 u8 scr2 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001341 pci_read_config_byte (dev, 0x5b, &scr2);
1342 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1343 /* now read cable id register */
1344 pci_read_config_byte (dev, 0x5a, &scr1);
1345 pci_write_config_byte(dev, 0x5b, scr2);
1346 } else
1347 pci_read_config_byte (dev, 0x5a, &scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +02001349 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1350 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001352 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001354 if (chip_type >= HPT374) {
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001355 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1356 hwif->ide_dma_end = &hpt374_ide_dma_end;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001357 } else if (chip_type >= HPT370) {
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001358 hwif->dma_start = &hpt370_ide_dma_start;
1359 hwif->ide_dma_end = &hpt370_ide_dma_end;
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +02001360 hwif->dma_timeout = &hpt370_dma_timeout;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001361 } else
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001362 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001363
1364 if (!noautodma)
1365 hwif->autodma = 1;
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001366 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367}
1368
1369static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1370{
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001371 struct pci_dev *dev = hwif->pci_dev;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001372 u8 masterdma = 0, slavedma = 0;
1373 u8 dma_new = 0, dma_old = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 unsigned long flags;
1375
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001376 dma_old = hwif->INB(dmabase + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
1378 local_irq_save(flags);
1379
1380 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001381 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1382 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001383
1384 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001385 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001386 if (dma_new != dma_old)
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001387 hwif->OUTB(dma_new, dmabase + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388
1389 local_irq_restore(flags);
1390
1391 ide_setup_dma(hwif, dmabase, 8);
1392}
1393
1394static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1395{
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001396 struct pci_dev *dev2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397
1398 if (PCI_FUNC(dev->devfn) & 1)
1399 return -ENODEV;
1400
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001401 pci_set_drvdata(dev, &hpt374);
1402
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001403 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1404 int ret;
1405
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001406 pci_set_drvdata(dev2, &hpt374);
1407
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001408 if (dev2->irq != dev->irq) {
1409 /* FIXME: we need a core pci_set_interrupt() */
1410 dev2->irq = dev->irq;
1411 printk(KERN_WARNING "%s: PCI config space interrupt "
1412 "fixed.\n", d->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 }
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001414 ret = ide_setup_pci_devices(dev, dev2, d);
1415 if (ret < 0)
1416 pci_dev_put(dev2);
1417 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418 }
1419 return ide_setup_pci_device(dev, d);
1420}
1421
Sergei Shtylyov90778572007-02-07 18:17:51 +01001422static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001423{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001424 pci_set_drvdata(dev, &hpt372n);
1425
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426 return ide_setup_pci_device(dev, d);
1427}
1428
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001429static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1430{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001431 struct hpt_info *info;
Auke Kok44c10132007-06-08 15:46:36 -07001432 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001433
Auke Kok44c10132007-06-08 15:46:36 -07001434 if (dev->revision > 1) {
Sergei Shtylyov90778572007-02-07 18:17:51 +01001435 d->name = "HPT371N";
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001436
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001437 info = &hpt371n;
1438 } else
1439 info = &hpt371;
1440
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001441 /*
1442 * HPT371 chips physically have only one channel, the secondary one,
1443 * but the primary channel registers do exist! Go figure...
1444 * So, we manually disable the non-existing channel here
1445 * (if the BIOS hasn't done this already).
1446 */
1447 pci_read_config_byte(dev, 0x50, &mcr1);
1448 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001449 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1450
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001451 pci_set_drvdata(dev, info);
1452
Sergei Shtylyov90778572007-02-07 18:17:51 +01001453 return ide_setup_pci_device(dev, d);
1454}
1455
1456static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1457{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001458 struct hpt_info *info;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001459
Auke Kok44c10132007-06-08 15:46:36 -07001460 if (dev->revision > 1) {
Sergei Shtylyov90778572007-02-07 18:17:51 +01001461 d->name = "HPT372N";
1462
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001463 info = &hpt372n;
1464 } else
1465 info = &hpt372a;
1466 pci_set_drvdata(dev, info);
1467
Sergei Shtylyov90778572007-02-07 18:17:51 +01001468 return ide_setup_pci_device(dev, d);
1469}
1470
1471static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1472{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001473 struct hpt_info *info;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001474
Auke Kok44c10132007-06-08 15:46:36 -07001475 if (dev->revision > 1) {
Sergei Shtylyov90778572007-02-07 18:17:51 +01001476 d->name = "HPT302N";
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001477
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001478 info = &hpt302n;
1479 } else
1480 info = &hpt302;
1481 pci_set_drvdata(dev, info);
1482
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001483 return ide_setup_pci_device(dev, d);
1484}
1485
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1487{
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001488 struct pci_dev *dev2;
Auke Kok44c10132007-06-08 15:46:36 -07001489 u8 rev = dev->revision;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001490 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1491 "HPT370", "HPT370A", "HPT372",
1492 "HPT372N" };
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001493 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1494 &hpt370, &hpt370a, &hpt372,
1495 &hpt372n };
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496
1497 if (PCI_FUNC(dev->devfn) & 1)
1498 return -ENODEV;
1499
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001500 switch (rev) {
1501 case 0:
1502 case 1:
1503 case 2:
1504 /*
1505 * HPT36x chips have one channel per function and have
1506 * both channel enable bits located differently and visible
1507 * to both functions -- really stupid design decision... :-(
1508 * Bit 4 is for the primary channel, bit 5 for the secondary.
1509 */
Bartlomiej Zolnierkiewicza5d8c5c2007-07-20 01:11:55 +02001510 d->host_flags |= IDE_HFLAG_SINGLE;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001511 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1512
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001513 d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ?
1514 ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001515 break;
1516 case 3:
1517 case 4:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001518 d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001519 break;
1520 default:
Sergei Shtylyove139b0b2007-02-07 18:17:37 +01001521 rev = 6;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001522 /* fall thru */
1523 case 5:
1524 case 6:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001525 d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001526 break;
1527 }
1528
Sergei Shtylyov90778572007-02-07 18:17:51 +01001529 d->name = chipset_names[rev];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001531 pci_set_drvdata(dev, info[rev]);
1532
Sergei Shtylyov90778572007-02-07 18:17:51 +01001533 if (rev > 2)
1534 goto init_single;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001536 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
Sergei Shtylyov96dcc082007-07-03 22:28:35 +02001537 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001538 int ret;
1539
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001540 pci_set_drvdata(dev2, info[rev]);
1541
Sergei Shtylyov96dcc082007-07-03 22:28:35 +02001542 /*
1543 * Now we'll have to force both channels enabled if
1544 * at least one of them has been enabled by BIOS...
1545 */
1546 pci_read_config_byte(dev, 0x50, &mcr1);
1547 if (mcr1 & 0x30)
1548 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1549
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001550 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1551 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1552 if (pin1 != pin2 && dev->irq == dev2->irq) {
1553 d->bootable = ON_BOARD;
1554 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1555 d->name, pin1, pin2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556 }
Sergei Shtylyovb4586712007-02-07 18:17:54 +01001557 ret = ide_setup_pci_devices(dev, dev2, d);
1558 if (ret < 0)
1559 pci_dev_put(dev2);
1560 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001561 }
1562init_single:
1563 return ide_setup_pci_device(dev, d);
1564}
1565
1566static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1567 { /* 0 */
1568 .name = "HPT366",
1569 .init_setup = init_setup_hpt366,
1570 .init_chipset = init_chipset_hpt366,
1571 .init_hwif = init_hwif_hpt366,
1572 .init_dma = init_dma_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 .autodma = AUTODMA,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001574 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575 .bootable = OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001576 .extra = 240,
1577 .pio_mask = ATA_PIO4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578 },{ /* 1 */
1579 .name = "HPT372A",
Sergei Shtylyov90778572007-02-07 18:17:51 +01001580 .init_setup = init_setup_hpt372a,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581 .init_chipset = init_chipset_hpt366,
1582 .init_hwif = init_hwif_hpt366,
1583 .init_dma = init_dma_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584 .autodma = AUTODMA,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001585 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001586 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587 .bootable = OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001588 .extra = 240,
1589 .pio_mask = ATA_PIO4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001590 },{ /* 2 */
1591 .name = "HPT302",
Sergei Shtylyov90778572007-02-07 18:17:51 +01001592 .init_setup = init_setup_hpt302,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593 .init_chipset = init_chipset_hpt366,
1594 .init_hwif = init_hwif_hpt366,
1595 .init_dma = init_dma_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596 .autodma = AUTODMA,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001597 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001598 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599 .bootable = OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001600 .extra = 240,
1601 .pio_mask = ATA_PIO4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001602 },{ /* 3 */
1603 .name = "HPT371",
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001604 .init_setup = init_setup_hpt371,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001605 .init_chipset = init_chipset_hpt366,
1606 .init_hwif = init_hwif_hpt366,
1607 .init_dma = init_dma_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608 .autodma = AUTODMA,
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001609 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001610 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 .bootable = OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001612 .extra = 240,
1613 .pio_mask = ATA_PIO4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614 },{ /* 4 */
1615 .name = "HPT374",
1616 .init_setup = init_setup_hpt374,
1617 .init_chipset = init_chipset_hpt366,
1618 .init_hwif = init_hwif_hpt366,
1619 .init_dma = init_dma_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620 .autodma = AUTODMA,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001621 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001622 .udma_mask = ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001623 .bootable = OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001624 .extra = 240,
1625 .pio_mask = ATA_PIO4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 },{ /* 5 */
1627 .name = "HPT372N",
Sergei Shtylyov90778572007-02-07 18:17:51 +01001628 .init_setup = init_setup_hpt372n,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 .init_hwif = init_hwif_hpt366,
1631 .init_dma = init_dma_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001632 .autodma = AUTODMA,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001633 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001634 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001635 .bootable = OFF_BOARD,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001636 .extra = 240,
1637 .pio_mask = ATA_PIO4,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638 }
1639};
1640
1641/**
1642 * hpt366_init_one - called when an HPT366 is found
1643 * @dev: the hpt366 device
1644 * @id: the matching pci id
1645 *
1646 * Called when the PCI registration layer (or the IDE initialization)
1647 * finds a device matching our IDE device tables.
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -08001648 *
1649 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1650 * structure depending on the chip's revision, we'd better pass a local
1651 * copy down the call chain...
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001653static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1654{
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -08001655 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -08001657 return d.init_setup(dev, &d);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658}
1659
1660static struct pci_device_id hpt366_pci_tbl[] = {
1661 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1662 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1663 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1664 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1665 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1666 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1667 { 0, },
1668};
1669MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1670
1671static struct pci_driver driver = {
1672 .name = "HPT366_IDE",
1673 .id_table = hpt366_pci_tbl,
1674 .probe = hpt366_init_one,
1675};
1676
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001677static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678{
1679 return ide_pci_register_driver(&driver);
1680}
1681
1682module_init(hpt366_ide_init);
1683
1684MODULE_AUTHOR("Andre Hedrick");
1685MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1686MODULE_LICENSE("GPL");