Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 33 | #include <uapi/drm/i915_drm.h> |
| 34 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 35 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 37 | #include "intel_ringbuffer.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 38 | #include <linux/io-mapping.h> |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 39 | #include <linux/i2c.h> |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 40 | #include <linux/i2c-algo-bit.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 41 | #include <drm/intel-gtt.h> |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 42 | #include <linux/backlight.h> |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 43 | #include <linux/intel-iommu.h> |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 44 | #include <linux/kref.h> |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 45 | #include <linux/pm_qos.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 46 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | /* General customization: |
| 48 | */ |
| 49 | |
| 50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 51 | |
| 52 | #define DRIVER_NAME "i915" |
| 53 | #define DRIVER_DESC "Intel Graphics" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 54 | #define DRIVER_DATE "20080730" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 56 | enum pipe { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 57 | INVALID_PIPE = -1, |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 58 | PIPE_A = 0, |
| 59 | PIPE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 60 | PIPE_C, |
| 61 | I915_MAX_PIPES |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 62 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 63 | #define pipe_name(p) ((p) + 'A') |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 64 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 65 | enum transcoder { |
| 66 | TRANSCODER_A = 0, |
| 67 | TRANSCODER_B, |
| 68 | TRANSCODER_C, |
| 69 | TRANSCODER_EDP = 0xF, |
| 70 | }; |
| 71 | #define transcoder_name(t) ((t) + 'A') |
| 72 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 73 | enum plane { |
| 74 | PLANE_A = 0, |
| 75 | PLANE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 76 | PLANE_C, |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 77 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 78 | #define plane_name(p) ((p) + 'A') |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 79 | |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 80 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
| 81 | |
Eugeni Dodonov | 2b13952 | 2012-03-29 12:32:22 -0300 | [diff] [blame] | 82 | enum port { |
| 83 | PORT_A = 0, |
| 84 | PORT_B, |
| 85 | PORT_C, |
| 86 | PORT_D, |
| 87 | PORT_E, |
| 88 | I915_MAX_PORTS |
| 89 | }; |
| 90 | #define port_name(p) ((p) + 'A') |
| 91 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 92 | #define I915_NUM_PHYS_VLV 1 |
| 93 | |
| 94 | enum dpio_channel { |
| 95 | DPIO_CH0, |
| 96 | DPIO_CH1 |
| 97 | }; |
| 98 | |
| 99 | enum dpio_phy { |
| 100 | DPIO_PHY0, |
| 101 | DPIO_PHY1 |
| 102 | }; |
| 103 | |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 104 | enum intel_display_power_domain { |
| 105 | POWER_DOMAIN_PIPE_A, |
| 106 | POWER_DOMAIN_PIPE_B, |
| 107 | POWER_DOMAIN_PIPE_C, |
| 108 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
| 109 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
| 110 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
| 111 | POWER_DOMAIN_TRANSCODER_A, |
| 112 | POWER_DOMAIN_TRANSCODER_B, |
| 113 | POWER_DOMAIN_TRANSCODER_C, |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 114 | POWER_DOMAIN_TRANSCODER_EDP, |
Ville Syrjälä | cdf8dd7 | 2013-09-16 17:38:30 +0300 | [diff] [blame] | 115 | POWER_DOMAIN_VGA, |
Imre Deak | fbeeaa2 | 2013-11-25 17:15:28 +0200 | [diff] [blame] | 116 | POWER_DOMAIN_AUDIO, |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 117 | POWER_DOMAIN_INIT, |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 118 | |
| 119 | POWER_DOMAIN_NUM, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 120 | }; |
| 121 | |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 122 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 123 | |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 124 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
| 125 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
| 126 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 127 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
| 128 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
| 129 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 130 | |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 131 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 132 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 133 | BIT(POWER_DOMAIN_TRANSCODER_EDP)) |
Paulo Zanoni | 6745a2c | 2013-11-02 21:07:34 -0700 | [diff] [blame] | 134 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 135 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 136 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
| 137 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 138 | |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 139 | enum hpd_pin { |
| 140 | HPD_NONE = 0, |
| 141 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
| 142 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
| 143 | HPD_CRT, |
| 144 | HPD_SDVO_B, |
| 145 | HPD_SDVO_C, |
| 146 | HPD_PORT_B, |
| 147 | HPD_PORT_C, |
| 148 | HPD_PORT_D, |
| 149 | HPD_NUM_PINS |
| 150 | }; |
| 151 | |
Chris Wilson | 2a2d548 | 2012-12-03 11:49:06 +0000 | [diff] [blame] | 152 | #define I915_GEM_GPU_DOMAINS \ |
| 153 | (I915_GEM_DOMAIN_RENDER | \ |
| 154 | I915_GEM_DOMAIN_SAMPLER | \ |
| 155 | I915_GEM_DOMAIN_COMMAND | \ |
| 156 | I915_GEM_DOMAIN_INSTRUCTION | \ |
| 157 | I915_GEM_DOMAIN_VERTEX) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 158 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 159 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 160 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 161 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
| 162 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
| 163 | if ((intel_encoder)->base.crtc == (__crtc)) |
| 164 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 165 | struct drm_i915_private; |
| 166 | |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 167 | enum intel_dpll_id { |
| 168 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
| 169 | /* real shared dpll ids must be >= 0 */ |
| 170 | DPLL_ID_PCH_PLL_A, |
| 171 | DPLL_ID_PCH_PLL_B, |
| 172 | }; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 173 | #define I915_NUM_PLLS 2 |
| 174 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 175 | struct intel_dpll_hw_state { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 176 | uint32_t dpll; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 177 | uint32_t dpll_md; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 178 | uint32_t fp0; |
| 179 | uint32_t fp1; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 180 | }; |
| 181 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 182 | struct intel_shared_dpll { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | int refcount; /* count of number of CRTCs sharing this PLL */ |
| 184 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 185 | bool on; /* is the PLL actually active? Disabled during modeset */ |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 186 | const char *name; |
| 187 | /* should match the index in the dev_priv->shared_dplls array */ |
| 188 | enum intel_dpll_id id; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 189 | struct intel_dpll_hw_state hw_state; |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 190 | void (*mode_set)(struct drm_i915_private *dev_priv, |
| 191 | struct intel_shared_dpll *pll); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 192 | void (*enable)(struct drm_i915_private *dev_priv, |
| 193 | struct intel_shared_dpll *pll); |
| 194 | void (*disable)(struct drm_i915_private *dev_priv, |
| 195 | struct intel_shared_dpll *pll); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 196 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 197 | struct intel_shared_dpll *pll, |
| 198 | struct intel_dpll_hw_state *hw_state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 201 | /* Used by dp and fdi links */ |
| 202 | struct intel_link_m_n { |
| 203 | uint32_t tu; |
| 204 | uint32_t gmch_m; |
| 205 | uint32_t gmch_n; |
| 206 | uint32_t link_m; |
| 207 | uint32_t link_n; |
| 208 | }; |
| 209 | |
| 210 | void intel_link_compute_m_n(int bpp, int nlanes, |
| 211 | int pixel_clock, int link_clock, |
| 212 | struct intel_link_m_n *m_n); |
| 213 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 214 | struct intel_ddi_plls { |
| 215 | int spll_refcount; |
| 216 | int wrpll1_refcount; |
| 217 | int wrpll2_refcount; |
| 218 | }; |
| 219 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | /* Interface history: |
| 221 | * |
| 222 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 223 | * 1.2: Add Power Management |
| 224 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 225 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 226 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 227 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 228 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | */ |
| 230 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 231 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | #define DRIVER_PATCHLEVEL 0 |
| 233 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 234 | #define WATCH_LISTS 0 |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 235 | #define WATCH_GTT 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 236 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 237 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 238 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 239 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 240 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 241 | |
| 242 | struct drm_i915_gem_phys_object { |
| 243 | int id; |
| 244 | struct page **page_list; |
| 245 | drm_dma_handle_t *handle; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 246 | struct drm_i915_gem_object *cur_obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 247 | }; |
| 248 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 249 | struct opregion_header; |
| 250 | struct opregion_acpi; |
| 251 | struct opregion_swsci; |
| 252 | struct opregion_asle; |
| 253 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 254 | struct intel_opregion { |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 255 | struct opregion_header __iomem *header; |
| 256 | struct opregion_acpi __iomem *acpi; |
| 257 | struct opregion_swsci __iomem *swsci; |
Jani Nikula | ebde53c | 2013-09-02 10:38:59 +0300 | [diff] [blame] | 258 | u32 swsci_gbda_sub_functions; |
| 259 | u32 swsci_sbcb_sub_functions; |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 260 | struct opregion_asle __iomem *asle; |
| 261 | void __iomem *vbt; |
Chris Wilson | 01fe9db | 2011-01-16 19:37:30 +0000 | [diff] [blame] | 262 | u32 __iomem *lid_state; |
Jani Nikula | 91a60f2 | 2013-10-31 18:55:48 +0200 | [diff] [blame] | 263 | struct work_struct asle_work; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 264 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 265 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 266 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 267 | struct intel_overlay; |
| 268 | struct intel_overlay_error_state; |
| 269 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 270 | struct drm_i915_master_private { |
| 271 | drm_local_map_t *sarea; |
| 272 | struct _drm_i915_sarea *sarea_priv; |
| 273 | }; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 274 | #define I915_FENCE_REG_NONE -1 |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 275 | #define I915_MAX_NUM_FENCES 32 |
| 276 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
| 277 | #define I915_MAX_NUM_FENCE_BITS 6 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 278 | |
| 279 | struct drm_i915_fence_reg { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 280 | struct list_head lru_list; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 281 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 282 | int pin_count; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 283 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 284 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 285 | struct sdvo_device_mapping { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 286 | u8 initialized; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 287 | u8 dvo_port; |
| 288 | u8 slave_addr; |
| 289 | u8 dvo_wiring; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 290 | u8 i2c_pin; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 291 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 292 | }; |
| 293 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 294 | struct intel_display_error_state; |
| 295 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 296 | struct drm_i915_error_state { |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 297 | struct kref ref; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 298 | u32 eir; |
| 299 | u32 pgtbl_er; |
Ben Widawsky | be998e2 | 2012-04-26 16:03:00 -0700 | [diff] [blame] | 300 | u32 ier; |
Ben Widawsky | b9a3906 | 2012-06-04 14:42:52 -0700 | [diff] [blame] | 301 | u32 ccid; |
Chris Wilson | 0f3b684 | 2013-01-15 12:05:55 +0000 | [diff] [blame] | 302 | u32 derrmr; |
| 303 | u32 forcewake; |
Ben Widawsky | 9574b3f | 2012-04-26 16:03:01 -0700 | [diff] [blame] | 304 | bool waiting[I915_NUM_RINGS]; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 305 | u32 pipestat[I915_MAX_PIPES]; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 306 | u32 tail[I915_NUM_RINGS]; |
| 307 | u32 head[I915_NUM_RINGS]; |
Chris Wilson | 0f3b684 | 2013-01-15 12:05:55 +0000 | [diff] [blame] | 308 | u32 ctl[I915_NUM_RINGS]; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 309 | u32 ipeir[I915_NUM_RINGS]; |
| 310 | u32 ipehr[I915_NUM_RINGS]; |
| 311 | u32 instdone[I915_NUM_RINGS]; |
| 312 | u32 acthd[I915_NUM_RINGS]; |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 313 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
Chris Wilson | df2b23d | 2012-11-27 17:06:54 +0000 | [diff] [blame] | 314 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 315 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
Daniel Vetter | 7e3b873 | 2012-02-01 22:26:45 +0100 | [diff] [blame] | 316 | /* our own tracking of ring head and tail */ |
| 317 | u32 cpu_ring_head[I915_NUM_RINGS]; |
| 318 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
Chris Wilson | 1d8f38f | 2010-10-29 19:00:51 +0100 | [diff] [blame] | 319 | u32 error; /* gen6+ */ |
Ben Widawsky | 71e172e | 2012-08-20 16:15:13 -0700 | [diff] [blame] | 320 | u32 err_int; /* gen7 */ |
Chris Wilson | 94e39e2 | 2013-10-30 09:28:22 +0000 | [diff] [blame] | 321 | u32 bbstate[I915_NUM_RINGS]; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 322 | u32 instpm[I915_NUM_RINGS]; |
| 323 | u32 instps[I915_NUM_RINGS]; |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 324 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
Daniel Vetter | d27b1e0 | 2011-12-14 13:57:01 +0100 | [diff] [blame] | 325 | u32 seqno[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 326 | u64 bbaddr; |
Daniel Vetter | 33f3f51 | 2011-12-14 13:57:39 +0100 | [diff] [blame] | 327 | u32 fault_reg[I915_NUM_RINGS]; |
| 328 | u32 done_reg; |
Daniel Vetter | c1cd90e | 2011-12-14 13:57:02 +0100 | [diff] [blame] | 329 | u32 faddr[I915_NUM_RINGS]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 330 | u64 fence[I915_MAX_NUM_FENCES]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 331 | struct timeval time; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 332 | struct drm_i915_error_ring { |
| 333 | struct drm_i915_error_object { |
| 334 | int page_count; |
| 335 | u32 gtt_offset; |
| 336 | u32 *pages[0]; |
Ben Widawsky | 8c123e5 | 2013-03-04 17:00:29 -0800 | [diff] [blame] | 337 | } *ringbuffer, *batchbuffer, *ctx; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 338 | struct drm_i915_error_request { |
| 339 | long jiffies; |
| 340 | u32 seqno; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 341 | u32 tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 342 | } *requests; |
| 343 | int num_requests; |
| 344 | } ring[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 345 | struct drm_i915_error_buffer { |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 346 | u32 size; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 347 | u32 name; |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 348 | u32 rseqno, wseqno; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 349 | u32 gtt_offset; |
| 350 | u32 read_domains; |
| 351 | u32 write_domain; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 352 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 353 | s32 pinned:2; |
| 354 | u32 tiling:2; |
| 355 | u32 dirty:1; |
| 356 | u32 purgeable:1; |
Daniel Vetter | 5d1333f | 2012-02-16 11:03:29 +0100 | [diff] [blame] | 357 | s32 ring:4; |
Chris Wilson | f56383c | 2013-09-25 10:23:19 +0100 | [diff] [blame] | 358 | u32 cache_level:3; |
Ben Widawsky | 95f5301 | 2013-07-31 17:00:15 -0700 | [diff] [blame] | 359 | } **active_bo, **pinned_bo; |
| 360 | u32 *active_bo_count, *pinned_bo_count; |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 361 | struct intel_overlay_error_state *overlay; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 362 | struct intel_display_error_state *display; |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 363 | int hangcheck_score[I915_NUM_RINGS]; |
| 364 | enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 365 | }; |
| 366 | |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 367 | struct intel_connector; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 368 | struct intel_crtc_config; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 369 | struct intel_crtc; |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 370 | struct intel_limit; |
| 371 | struct dpll; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 372 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 373 | struct drm_i915_display_funcs { |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 374 | bool (*fbc_enabled)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 375 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
| 376 | void (*disable_fbc)(struct drm_device *dev); |
| 377 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 378 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 379 | /** |
| 380 | * find_dpll() - Find the best values for the PLL |
| 381 | * @limit: limits for the PLL |
| 382 | * @crtc: current CRTC |
| 383 | * @target: target frequency in kHz |
| 384 | * @refclk: reference clock frequency in kHz |
| 385 | * @match_clock: if provided, @best_clock P divider must |
| 386 | * match the P divider from @match_clock |
| 387 | * used for LVDS downclocking |
| 388 | * @best_clock: best PLL values found |
| 389 | * |
| 390 | * Returns true on success, false on failure. |
| 391 | */ |
| 392 | bool (*find_dpll)(const struct intel_limit *limit, |
| 393 | struct drm_crtc *crtc, |
| 394 | int target, int refclk, |
| 395 | struct dpll *match_clock, |
| 396 | struct dpll *best_clock); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 397 | void (*update_wm)(struct drm_crtc *crtc); |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 398 | void (*update_sprite_wm)(struct drm_plane *plane, |
| 399 | struct drm_crtc *crtc, |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 400 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 401 | bool enable, bool scaled); |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 402 | void (*modeset_global_resources)(struct drm_device *dev); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 403 | /* Returns the active state of the crtc, and if the crtc is active, |
| 404 | * fills out the pipe-config with the hw state. */ |
| 405 | bool (*get_pipe_config)(struct intel_crtc *, |
| 406 | struct intel_crtc_config *); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 407 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 408 | int x, int y, |
| 409 | struct drm_framebuffer *old_fb); |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 410 | void (*crtc_enable)(struct drm_crtc *crtc); |
| 411 | void (*crtc_disable)(struct drm_crtc *crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 412 | void (*off)(struct drm_crtc *crtc); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 413 | void (*write_eld)(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 414 | struct drm_crtc *crtc, |
| 415 | struct drm_display_mode *mode); |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 416 | void (*fdi_link_train)(struct drm_crtc *crtc); |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 417 | void (*init_clock_gating)(struct drm_device *dev); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 418 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
| 419 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 420 | struct drm_i915_gem_object *obj, |
| 421 | uint32_t flags); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 422 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 423 | int x, int y); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 424 | void (*hpd_irq_setup)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 425 | /* clock updates for mode set */ |
| 426 | /* cursor updates */ |
| 427 | /* render clock increase/decrease */ |
| 428 | /* display clock increase/decrease */ |
| 429 | /* pll clock increase/decrease */ |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 430 | |
| 431 | int (*setup_backlight)(struct intel_connector *connector); |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 432 | uint32_t (*get_backlight)(struct intel_connector *connector); |
| 433 | void (*set_backlight)(struct intel_connector *connector, |
| 434 | uint32_t level); |
| 435 | void (*disable_backlight)(struct intel_connector *connector); |
| 436 | void (*enable_backlight)(struct intel_connector *connector); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 437 | }; |
| 438 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 439 | struct intel_uncore_funcs { |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 440 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
| 441 | int fw_engine); |
| 442 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
| 443 | int fw_engine); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 444 | |
| 445 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 446 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 447 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 448 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 449 | |
| 450 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
| 451 | uint8_t val, bool trace); |
| 452 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
| 453 | uint16_t val, bool trace); |
| 454 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
| 455 | uint32_t val, bool trace); |
| 456 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
| 457 | uint64_t val, bool trace); |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 458 | }; |
| 459 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 460 | struct intel_uncore { |
| 461 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
| 462 | |
| 463 | struct intel_uncore_funcs funcs; |
| 464 | |
| 465 | unsigned fifo_count; |
| 466 | unsigned forcewake_count; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 467 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 468 | unsigned fw_rendercount; |
| 469 | unsigned fw_mediacount; |
| 470 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 471 | struct delayed_work force_wake_work; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 472 | }; |
| 473 | |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 474 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
| 475 | func(is_mobile) sep \ |
| 476 | func(is_i85x) sep \ |
| 477 | func(is_i915g) sep \ |
| 478 | func(is_i945gm) sep \ |
| 479 | func(is_g33) sep \ |
| 480 | func(need_gfx_hws) sep \ |
| 481 | func(is_g4x) sep \ |
| 482 | func(is_pineview) sep \ |
| 483 | func(is_broadwater) sep \ |
| 484 | func(is_crestline) sep \ |
| 485 | func(is_ivybridge) sep \ |
| 486 | func(is_valleyview) sep \ |
| 487 | func(is_haswell) sep \ |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 488 | func(is_preliminary) sep \ |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 489 | func(has_fbc) sep \ |
| 490 | func(has_pipe_cxsr) sep \ |
| 491 | func(has_hotplug) sep \ |
| 492 | func(cursor_needs_physical) sep \ |
| 493 | func(has_overlay) sep \ |
| 494 | func(overlay_needs_physical) sep \ |
| 495 | func(supports_tv) sep \ |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 496 | func(has_llc) sep \ |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 497 | func(has_ddi) sep \ |
| 498 | func(has_fpga_dbg) |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 499 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 500 | #define DEFINE_FLAG(name) u8 name:1 |
| 501 | #define SEP_SEMICOLON ; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 502 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 503 | struct intel_device_info { |
Ville Syrjälä | 10fce67 | 2013-01-24 15:29:28 +0200 | [diff] [blame] | 504 | u32 display_mmio_offset; |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 505 | u8 num_pipes:3; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 506 | u8 gen; |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 507 | u8 ring_mask; /* Rings supported by the HW */ |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 508 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 509 | }; |
| 510 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 511 | #undef DEFINE_FLAG |
| 512 | #undef SEP_SEMICOLON |
| 513 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 514 | enum i915_cache_level { |
| 515 | I915_CACHE_NONE = 0, |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 516 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
| 517 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
| 518 | caches, eg sampler/render caches, and the |
| 519 | large Last-Level-Cache. LLC is coherent with |
| 520 | the CPU, but L3 is only visible to the GPU. */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 521 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 522 | }; |
| 523 | |
Kenneth Graunke | 2d04bef | 2013-04-22 00:53:49 -0700 | [diff] [blame] | 524 | typedef uint32_t gen6_gtt_pte_t; |
| 525 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 526 | /** |
| 527 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
| 528 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
| 529 | * object into/from the address space. |
| 530 | * |
| 531 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
| 532 | * will always be <= an objects lifetime. So object refcounting should cover us. |
| 533 | */ |
| 534 | struct i915_vma { |
| 535 | struct drm_mm_node node; |
| 536 | struct drm_i915_gem_object *obj; |
| 537 | struct i915_address_space *vm; |
| 538 | |
| 539 | /** This object's place on the active/inactive lists */ |
| 540 | struct list_head mm_list; |
| 541 | |
| 542 | struct list_head vma_link; /* Link in the object's VMA list */ |
| 543 | |
| 544 | /** This vma's place in the batchbuffer or on the eviction list */ |
| 545 | struct list_head exec_list; |
| 546 | |
| 547 | /** |
| 548 | * Used for performing relocations during execbuffer insertion. |
| 549 | */ |
| 550 | struct hlist_node exec_node; |
| 551 | unsigned long exec_handle; |
| 552 | struct drm_i915_gem_exec_object2 *exec_entry; |
| 553 | |
| 554 | /** |
| 555 | * How many users have pinned this object in GTT space. The following |
| 556 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 557 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 558 | * times for the same batchbuffer), and the framebuffer code. When |
| 559 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 560 | * pinned per crtc. |
| 561 | * |
| 562 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 563 | * bits with absolutely no headroom. So use 4 bits. */ |
| 564 | unsigned int pin_count:4; |
| 565 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
| 566 | |
| 567 | /** Unmap an object from an address space. This usually consists of |
| 568 | * setting the valid PTE entries to a reserved scratch page. */ |
| 569 | void (*unbind_vma)(struct i915_vma *vma); |
| 570 | /* Map an object into an address space with the given cache flags. */ |
| 571 | #define GLOBAL_BIND (1<<0) |
| 572 | void (*bind_vma)(struct i915_vma *vma, |
| 573 | enum i915_cache_level cache_level, |
| 574 | u32 flags); |
| 575 | }; |
| 576 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 577 | struct i915_address_space { |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 578 | struct drm_mm mm; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 579 | struct drm_device *dev; |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 580 | struct list_head global_link; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 581 | unsigned long start; /* Start offset always 0 for dri2 */ |
| 582 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
| 583 | |
| 584 | struct { |
| 585 | dma_addr_t addr; |
| 586 | struct page *page; |
| 587 | } scratch; |
| 588 | |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 589 | /** |
| 590 | * List of objects currently involved in rendering. |
| 591 | * |
| 592 | * Includes buffers having the contents of their GPU caches |
| 593 | * flushed, not necessarily primitives. last_rendering_seqno |
| 594 | * represents when the rendering involved will be completed. |
| 595 | * |
| 596 | * A reference is held on the buffer while on this list. |
| 597 | */ |
| 598 | struct list_head active_list; |
| 599 | |
| 600 | /** |
| 601 | * LRU list of objects which are not in the ringbuffer and |
| 602 | * are ready to unbind, but are still in the GTT. |
| 603 | * |
| 604 | * last_rendering_seqno is 0 while an object is in this list. |
| 605 | * |
| 606 | * A reference is not held on the buffer while on this list, |
| 607 | * as merely being GTT-bound shouldn't prevent its being |
| 608 | * freed, and we'll pull it off the list in the free path. |
| 609 | */ |
| 610 | struct list_head inactive_list; |
| 611 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 612 | /* FIXME: Need a more generic return type */ |
| 613 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 614 | enum i915_cache_level level, |
| 615 | bool valid); /* Create a valid PTE */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 616 | void (*clear_range)(struct i915_address_space *vm, |
| 617 | unsigned int first_entry, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 618 | unsigned int num_entries, |
| 619 | bool use_scratch); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 620 | void (*insert_entries)(struct i915_address_space *vm, |
| 621 | struct sg_table *st, |
| 622 | unsigned int first_entry, |
| 623 | enum i915_cache_level cache_level); |
| 624 | void (*cleanup)(struct i915_address_space *vm); |
| 625 | }; |
| 626 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 627 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
| 628 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
| 629 | * collateral associated with any va->pa translations GEN hardware also has a |
| 630 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
| 631 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
| 632 | * the spec. |
| 633 | */ |
| 634 | struct i915_gtt { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 635 | struct i915_address_space base; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 636 | size_t stolen_size; /* Total size of stolen memory */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 637 | |
| 638 | unsigned long mappable_end; /* End offset that we can CPU map */ |
| 639 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
| 640 | phys_addr_t mappable_base; /* PA of our GMADR */ |
| 641 | |
| 642 | /** "Graphics Stolen Memory" holds the global PTEs */ |
| 643 | void __iomem *gsm; |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 644 | |
| 645 | bool do_idle_maps; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 646 | |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 647 | int mtrr; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 648 | |
| 649 | /* global gtt ops */ |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 650 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 651 | size_t *stolen, phys_addr_t *mappable_base, |
| 652 | unsigned long *mappable_end); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 653 | }; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 654 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 655 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 656 | struct i915_hw_ppgtt { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 657 | struct i915_address_space base; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 658 | unsigned num_pd_entries; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 659 | union { |
| 660 | struct page **pt_pages; |
| 661 | struct page *gen8_pt_pages; |
| 662 | }; |
| 663 | struct page *pd_pages; |
| 664 | int num_pd_pages; |
| 665 | int num_pt_pages; |
| 666 | union { |
| 667 | uint32_t pd_offset; |
| 668 | dma_addr_t pd_dma_addr[4]; |
| 669 | }; |
| 670 | union { |
| 671 | dma_addr_t *pt_dma_addr; |
| 672 | dma_addr_t *gen8_pt_dma_addr[4]; |
| 673 | }; |
Ben Widawsky | a3d67d2 | 2013-12-06 14:11:06 -0800 | [diff] [blame^] | 674 | |
| 675 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 676 | }; |
| 677 | |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 678 | struct i915_ctx_hang_stats { |
| 679 | /* This context had batch pending when hang was declared */ |
| 680 | unsigned batch_pending; |
| 681 | |
| 682 | /* This context had batch active when hang was declared */ |
| 683 | unsigned batch_active; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 684 | |
| 685 | /* Time when this context was last blamed for a GPU reset */ |
| 686 | unsigned long guilty_ts; |
| 687 | |
| 688 | /* This context is banned to submit more work */ |
| 689 | bool banned; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 690 | }; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 691 | |
| 692 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
| 693 | #define DEFAULT_CONTEXT_ID 0 |
| 694 | struct i915_hw_context { |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 695 | struct kref ref; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 696 | int id; |
Ben Widawsky | e055684 | 2012-06-04 14:42:46 -0700 | [diff] [blame] | 697 | bool is_initialized; |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 698 | uint8_t remap_slice; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 699 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | 0009e46 | 2013-12-06 14:11:02 -0800 | [diff] [blame] | 700 | struct intel_ring_buffer *last_ring; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 701 | struct drm_i915_gem_object *obj; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 702 | struct i915_ctx_hang_stats hang_stats; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 703 | |
| 704 | struct list_head link; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 705 | }; |
| 706 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 707 | struct i915_fbc { |
| 708 | unsigned long size; |
| 709 | unsigned int fb_id; |
| 710 | enum plane plane; |
| 711 | int y; |
| 712 | |
| 713 | struct drm_mm_node *compressed_fb; |
| 714 | struct drm_mm_node *compressed_llb; |
| 715 | |
| 716 | struct intel_fbc_work { |
| 717 | struct delayed_work work; |
| 718 | struct drm_crtc *crtc; |
| 719 | struct drm_framebuffer *fb; |
| 720 | int interval; |
| 721 | } *fbc_work; |
| 722 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 723 | enum no_fbc_reason { |
| 724 | FBC_OK, /* FBC is enabled */ |
| 725 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 726 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
| 727 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
| 728 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 729 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 730 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 731 | FBC_NOT_TILED, /* buffer not tiled */ |
| 732 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
| 733 | FBC_MODULE_PARAM, |
| 734 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
| 735 | } no_fbc_reason; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 736 | }; |
| 737 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 738 | struct i915_psr { |
| 739 | bool sink_support; |
| 740 | bool source_ok; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 741 | }; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 742 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 743 | enum intel_pch { |
Paulo Zanoni | f035083 | 2012-07-03 18:48:16 -0300 | [diff] [blame] | 744 | PCH_NONE = 0, /* No PCH present */ |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 745 | PCH_IBX, /* Ibexpeak PCH */ |
| 746 | PCH_CPT, /* Cougarpoint PCH */ |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 747 | PCH_LPT, /* Lynxpoint PCH */ |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 748 | PCH_NOP, |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 749 | }; |
| 750 | |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 751 | enum intel_sbi_destination { |
| 752 | SBI_ICLK, |
| 753 | SBI_MPHY, |
| 754 | }; |
| 755 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 756 | #define QUIRK_PIPEA_FORCE (1<<0) |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 757 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 758 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 759 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 760 | struct intel_fbdev; |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 761 | struct intel_fbc_work; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 762 | |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 763 | struct intel_gmbus { |
| 764 | struct i2c_adapter adapter; |
Chris Wilson | f2ce9fa | 2012-11-10 15:58:21 +0000 | [diff] [blame] | 765 | u32 force_bit; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 766 | u32 reg0; |
Daniel Vetter | 36c785f | 2012-02-14 22:37:22 +0100 | [diff] [blame] | 767 | u32 gpio_reg; |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 768 | struct i2c_algo_bit_data bit_algo; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 769 | struct drm_i915_private *dev_priv; |
| 770 | }; |
| 771 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 772 | struct i915_suspend_saved_registers { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 773 | u8 saveLBB; |
| 774 | u32 saveDSPACNTR; |
| 775 | u32 saveDSPBCNTR; |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 776 | u32 saveDSPARB; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 777 | u32 savePIPEACONF; |
| 778 | u32 savePIPEBCONF; |
| 779 | u32 savePIPEASRC; |
| 780 | u32 savePIPEBSRC; |
| 781 | u32 saveFPA0; |
| 782 | u32 saveFPA1; |
| 783 | u32 saveDPLL_A; |
| 784 | u32 saveDPLL_A_MD; |
| 785 | u32 saveHTOTAL_A; |
| 786 | u32 saveHBLANK_A; |
| 787 | u32 saveHSYNC_A; |
| 788 | u32 saveVTOTAL_A; |
| 789 | u32 saveVBLANK_A; |
| 790 | u32 saveVSYNC_A; |
| 791 | u32 saveBCLRPAT_A; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 792 | u32 saveTRANSACONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 793 | u32 saveTRANS_HTOTAL_A; |
| 794 | u32 saveTRANS_HBLANK_A; |
| 795 | u32 saveTRANS_HSYNC_A; |
| 796 | u32 saveTRANS_VTOTAL_A; |
| 797 | u32 saveTRANS_VBLANK_A; |
| 798 | u32 saveTRANS_VSYNC_A; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 799 | u32 savePIPEASTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 800 | u32 saveDSPASTRIDE; |
| 801 | u32 saveDSPASIZE; |
| 802 | u32 saveDSPAPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 803 | u32 saveDSPAADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 804 | u32 saveDSPASURF; |
| 805 | u32 saveDSPATILEOFF; |
| 806 | u32 savePFIT_PGM_RATIOS; |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 807 | u32 saveBLC_HIST_CTL; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 808 | u32 saveBLC_PWM_CTL; |
| 809 | u32 saveBLC_PWM_CTL2; |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame] | 810 | u32 saveBLC_HIST_CTL_B; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 811 | u32 saveBLC_CPU_PWM_CTL; |
| 812 | u32 saveBLC_CPU_PWM_CTL2; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 813 | u32 saveFPB0; |
| 814 | u32 saveFPB1; |
| 815 | u32 saveDPLL_B; |
| 816 | u32 saveDPLL_B_MD; |
| 817 | u32 saveHTOTAL_B; |
| 818 | u32 saveHBLANK_B; |
| 819 | u32 saveHSYNC_B; |
| 820 | u32 saveVTOTAL_B; |
| 821 | u32 saveVBLANK_B; |
| 822 | u32 saveVSYNC_B; |
| 823 | u32 saveBCLRPAT_B; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 824 | u32 saveTRANSBCONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 825 | u32 saveTRANS_HTOTAL_B; |
| 826 | u32 saveTRANS_HBLANK_B; |
| 827 | u32 saveTRANS_HSYNC_B; |
| 828 | u32 saveTRANS_VTOTAL_B; |
| 829 | u32 saveTRANS_VBLANK_B; |
| 830 | u32 saveTRANS_VSYNC_B; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 831 | u32 savePIPEBSTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 832 | u32 saveDSPBSTRIDE; |
| 833 | u32 saveDSPBSIZE; |
| 834 | u32 saveDSPBPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 835 | u32 saveDSPBADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 836 | u32 saveDSPBSURF; |
| 837 | u32 saveDSPBTILEOFF; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 838 | u32 saveVGA0; |
| 839 | u32 saveVGA1; |
| 840 | u32 saveVGA_PD; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 841 | u32 saveVGACNTRL; |
| 842 | u32 saveADPA; |
| 843 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 844 | u32 savePP_ON_DELAYS; |
| 845 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 846 | u32 saveDVOA; |
| 847 | u32 saveDVOB; |
| 848 | u32 saveDVOC; |
| 849 | u32 savePP_ON; |
| 850 | u32 savePP_OFF; |
| 851 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 852 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 853 | u32 savePFIT_CONTROL; |
| 854 | u32 save_palette_a[256]; |
| 855 | u32 save_palette_b[256]; |
Jesse Barnes | 06027f9 | 2009-10-05 13:47:26 -0700 | [diff] [blame] | 856 | u32 saveDPFC_CB_BASE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 857 | u32 saveFBC_CFB_BASE; |
| 858 | u32 saveFBC_LL_BASE; |
| 859 | u32 saveFBC_CONTROL; |
| 860 | u32 saveFBC_CONTROL2; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 861 | u32 saveIER; |
| 862 | u32 saveIIR; |
| 863 | u32 saveIMR; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 864 | u32 saveDEIER; |
| 865 | u32 saveDEIMR; |
| 866 | u32 saveGTIER; |
| 867 | u32 saveGTIMR; |
| 868 | u32 saveFDI_RXA_IMR; |
| 869 | u32 saveFDI_RXB_IMR; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 870 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 871 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 872 | u32 saveSWF0[16]; |
| 873 | u32 saveSWF1[16]; |
| 874 | u32 saveSWF2[3]; |
| 875 | u8 saveMSR; |
| 876 | u8 saveSR[8]; |
Jesse Barnes | 123f794 | 2008-02-07 11:15:20 -0800 | [diff] [blame] | 877 | u8 saveGR[25]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 878 | u8 saveAR_INDEX; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 879 | u8 saveAR[21]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 880 | u8 saveDACMASK; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 881 | u8 saveCR[37]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 882 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 883 | u32 saveCURACNTR; |
| 884 | u32 saveCURAPOS; |
| 885 | u32 saveCURABASE; |
| 886 | u32 saveCURBCNTR; |
| 887 | u32 saveCURBPOS; |
| 888 | u32 saveCURBBASE; |
| 889 | u32 saveCURSIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 890 | u32 saveDP_B; |
| 891 | u32 saveDP_C; |
| 892 | u32 saveDP_D; |
| 893 | u32 savePIPEA_GMCH_DATA_M; |
| 894 | u32 savePIPEB_GMCH_DATA_M; |
| 895 | u32 savePIPEA_GMCH_DATA_N; |
| 896 | u32 savePIPEB_GMCH_DATA_N; |
| 897 | u32 savePIPEA_DP_LINK_M; |
| 898 | u32 savePIPEB_DP_LINK_M; |
| 899 | u32 savePIPEA_DP_LINK_N; |
| 900 | u32 savePIPEB_DP_LINK_N; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 901 | u32 saveFDI_RXA_CTL; |
| 902 | u32 saveFDI_TXA_CTL; |
| 903 | u32 saveFDI_RXB_CTL; |
| 904 | u32 saveFDI_TXB_CTL; |
| 905 | u32 savePFA_CTL_1; |
| 906 | u32 savePFB_CTL_1; |
| 907 | u32 savePFA_WIN_SZ; |
| 908 | u32 savePFB_WIN_SZ; |
| 909 | u32 savePFA_WIN_POS; |
| 910 | u32 savePFB_WIN_POS; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 911 | u32 savePCH_DREF_CONTROL; |
| 912 | u32 saveDISP_ARB_CTL; |
| 913 | u32 savePIPEA_DATA_M1; |
| 914 | u32 savePIPEA_DATA_N1; |
| 915 | u32 savePIPEA_LINK_M1; |
| 916 | u32 savePIPEA_LINK_N1; |
| 917 | u32 savePIPEB_DATA_M1; |
| 918 | u32 savePIPEB_DATA_N1; |
| 919 | u32 savePIPEB_LINK_M1; |
| 920 | u32 savePIPEB_LINK_N1; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 921 | u32 saveMCHBAR_RENDER_STANDBY; |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 922 | u32 savePCH_PORT_HOTPLUG; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 923 | }; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 924 | |
| 925 | struct intel_gen6_power_mgmt { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 926 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 927 | struct work_struct work; |
| 928 | u32 pm_iir; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 929 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 930 | /* The below variables an all the rps hw state are protected by |
| 931 | * dev->struct mutext. */ |
| 932 | u8 cur_delay; |
| 933 | u8 min_delay; |
| 934 | u8 max_delay; |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 935 | u8 rpe_delay; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 936 | u8 rp1_delay; |
| 937 | u8 rp0_delay; |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 938 | u8 hw_max; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 939 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 940 | int last_adj; |
| 941 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
| 942 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 943 | bool enabled; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 944 | struct delayed_work delayed_resume_work; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 945 | |
| 946 | /* |
| 947 | * Protects RPS/RC6 register access and PCU communication. |
| 948 | * Must be taken after struct_mutex if nested. |
| 949 | */ |
| 950 | struct mutex hw_lock; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 951 | }; |
| 952 | |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 953 | /* defined intel_pm.c */ |
| 954 | extern spinlock_t mchdev_lock; |
| 955 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 956 | struct intel_ilk_power_mgmt { |
| 957 | u8 cur_delay; |
| 958 | u8 min_delay; |
| 959 | u8 max_delay; |
| 960 | u8 fmax; |
| 961 | u8 fstart; |
| 962 | |
| 963 | u64 last_count1; |
| 964 | unsigned long last_time1; |
| 965 | unsigned long chipset_power; |
| 966 | u64 last_count2; |
| 967 | struct timespec last_time2; |
| 968 | unsigned long gfx_power; |
| 969 | u8 corr; |
| 970 | |
| 971 | int c_m; |
| 972 | int r_t; |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 973 | |
| 974 | struct drm_i915_gem_object *pwrctx; |
| 975 | struct drm_i915_gem_object *renderctx; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 976 | }; |
| 977 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 978 | /* Power well structure for haswell */ |
| 979 | struct i915_power_well { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 980 | const char *name; |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 981 | bool always_on; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 982 | /* power well enable/disable usage count */ |
| 983 | int count; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 984 | unsigned long domains; |
| 985 | void *data; |
| 986 | void (*set)(struct drm_device *dev, struct i915_power_well *power_well, |
| 987 | bool enable); |
| 988 | bool (*is_enabled)(struct drm_device *dev, |
| 989 | struct i915_power_well *power_well); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 990 | }; |
| 991 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 992 | struct i915_power_domains { |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 993 | /* |
| 994 | * Power wells needed for initialization at driver init and suspend |
| 995 | * time are on. They are kept on until after the first modeset. |
| 996 | */ |
| 997 | bool init_power_on; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 998 | int power_well_count; |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 999 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1000 | struct mutex lock; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 1001 | int domain_use_count[POWER_DOMAIN_NUM]; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1002 | struct i915_power_well *power_wells; |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1003 | }; |
| 1004 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1005 | struct i915_dri1_state { |
| 1006 | unsigned allow_batchbuffer : 1; |
| 1007 | u32 __iomem *gfx_hws_cpu_addr; |
| 1008 | |
| 1009 | unsigned int cpp; |
| 1010 | int back_offset; |
| 1011 | int front_offset; |
| 1012 | int current_page; |
| 1013 | int page_flipping; |
| 1014 | |
| 1015 | uint32_t counter; |
| 1016 | }; |
| 1017 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 1018 | struct i915_ums_state { |
| 1019 | /** |
| 1020 | * Flag if the X Server, and thus DRM, is not currently in |
| 1021 | * control of the device. |
| 1022 | * |
| 1023 | * This is set between LeaveVT and EnterVT. It needs to be |
| 1024 | * replaced with a semaphore. It also needs to be |
| 1025 | * transitioned away from for kernel modesetting. |
| 1026 | */ |
| 1027 | int mm_suspended; |
| 1028 | }; |
| 1029 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1030 | #define MAX_L3_SLICES 2 |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1031 | struct intel_l3_parity { |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1032 | u32 *remap_info[MAX_L3_SLICES]; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1033 | struct work_struct error_work; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1034 | int which_slice; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1035 | }; |
| 1036 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1037 | struct i915_gem_mm { |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1038 | /** Memory allocator for GTT stolen memory */ |
| 1039 | struct drm_mm stolen; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1040 | /** List of all objects in gtt_space. Used to restore gtt |
| 1041 | * mappings on resume */ |
| 1042 | struct list_head bound_list; |
| 1043 | /** |
| 1044 | * List of objects which are not bound to the GTT (thus |
| 1045 | * are idle and not used by the GPU) but still have |
| 1046 | * (presumably uncached) pages still attached. |
| 1047 | */ |
| 1048 | struct list_head unbound_list; |
| 1049 | |
| 1050 | /** Usable portion of the GTT for GEM */ |
| 1051 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
| 1052 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1053 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
| 1054 | struct i915_hw_ppgtt *aliasing_ppgtt; |
| 1055 | |
| 1056 | struct shrinker inactive_shrinker; |
| 1057 | bool shrinker_no_lock_stealing; |
| 1058 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1059 | /** LRU list of objects with fence regs on them. */ |
| 1060 | struct list_head fence_list; |
| 1061 | |
| 1062 | /** |
| 1063 | * We leave the user IRQ off as much as possible, |
| 1064 | * but this means that requests will finish and never |
| 1065 | * be retired once the system goes idle. Set a timer to |
| 1066 | * fire periodically while the ring is running. When it |
| 1067 | * fires, go retire requests. |
| 1068 | */ |
| 1069 | struct delayed_work retire_work; |
| 1070 | |
| 1071 | /** |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1072 | * When we detect an idle GPU, we want to turn on |
| 1073 | * powersaving features. So once we see that there |
| 1074 | * are no more requests outstanding and no more |
| 1075 | * arrive within a small period of time, we fire |
| 1076 | * off the idle_work. |
| 1077 | */ |
| 1078 | struct delayed_work idle_work; |
| 1079 | |
| 1080 | /** |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1081 | * Are we in a non-interruptible section of code like |
| 1082 | * modesetting? |
| 1083 | */ |
| 1084 | bool interruptible; |
| 1085 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1086 | /** Bit 6 swizzling required for X tiling */ |
| 1087 | uint32_t bit_6_swizzle_x; |
| 1088 | /** Bit 6 swizzling required for Y tiling */ |
| 1089 | uint32_t bit_6_swizzle_y; |
| 1090 | |
| 1091 | /* storage for physical objects */ |
| 1092 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
| 1093 | |
| 1094 | /* accounting, useful for userland debugging */ |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 1095 | spinlock_t object_stat_lock; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1096 | size_t object_memory; |
| 1097 | u32 object_count; |
| 1098 | }; |
| 1099 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1100 | struct drm_i915_error_state_buf { |
| 1101 | unsigned bytes; |
| 1102 | unsigned size; |
| 1103 | int err; |
| 1104 | u8 *buf; |
| 1105 | loff_t start; |
| 1106 | loff_t pos; |
| 1107 | }; |
| 1108 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 1109 | struct i915_error_state_file_priv { |
| 1110 | struct drm_device *dev; |
| 1111 | struct drm_i915_error_state *error; |
| 1112 | }; |
| 1113 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1114 | struct i915_gpu_error { |
| 1115 | /* For hangcheck timer */ |
| 1116 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
| 1117 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 1118 | /* Hang gpu twice in this window and your context gets banned */ |
| 1119 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
| 1120 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1121 | struct timer_list hangcheck_timer; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1122 | |
| 1123 | /* For reset and error_state handling. */ |
| 1124 | spinlock_t lock; |
| 1125 | /* Protected by the above dev->gpu_error.lock. */ |
| 1126 | struct drm_i915_error_state *first_error; |
| 1127 | struct work_struct work; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1128 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1129 | |
| 1130 | unsigned long missed_irq_rings; |
| 1131 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1132 | /** |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1133 | * State variable controlling the reset flow and count |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1134 | * |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1135 | * This is a counter which gets incremented when reset is triggered, |
| 1136 | * and again when reset has been handled. So odd values (lowest bit set) |
| 1137 | * means that reset is in progress and even values that |
| 1138 | * (reset_counter >> 1):th reset was successfully completed. |
| 1139 | * |
| 1140 | * If reset is not completed succesfully, the I915_WEDGE bit is |
| 1141 | * set meaning that hardware is terminally sour and there is no |
| 1142 | * recovery. All waiters on the reset_queue will be woken when |
| 1143 | * that happens. |
| 1144 | * |
| 1145 | * This counter is used by the wait_seqno code to notice that reset |
| 1146 | * event happened and it needs to restart the entire ioctl (since most |
| 1147 | * likely the seqno it waited for won't ever signal anytime soon). |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1148 | * |
| 1149 | * This is important for lock-free wait paths, where no contended lock |
| 1150 | * naturally enforces the correct ordering between the bail-out of the |
| 1151 | * waiter and the gpu reset work code. |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1152 | */ |
| 1153 | atomic_t reset_counter; |
| 1154 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1155 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1156 | #define I915_WEDGED (1 << 31) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1157 | |
| 1158 | /** |
| 1159 | * Waitqueue to signal when the reset has completed. Used by clients |
| 1160 | * that wait for dev_priv->mm.wedged to settle. |
| 1161 | */ |
| 1162 | wait_queue_head_t reset_queue; |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1163 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1164 | /* For gpu hang simulation. */ |
| 1165 | unsigned int stop_rings; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1166 | |
| 1167 | /* For missed irq/seqno simulation. */ |
| 1168 | unsigned int test_irq_rings; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1169 | }; |
| 1170 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1171 | enum modeset_restore { |
| 1172 | MODESET_ON_LID_OPEN, |
| 1173 | MODESET_DONE, |
| 1174 | MODESET_SUSPENDED, |
| 1175 | }; |
| 1176 | |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1177 | struct ddi_vbt_port_info { |
| 1178 | uint8_t hdmi_level_shift; |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 1179 | |
| 1180 | uint8_t supports_dvi:1; |
| 1181 | uint8_t supports_hdmi:1; |
| 1182 | uint8_t supports_dp:1; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1183 | }; |
| 1184 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1185 | struct intel_vbt_data { |
| 1186 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 1187 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
| 1188 | |
| 1189 | /* Feature bits */ |
| 1190 | unsigned int int_tv_support:1; |
| 1191 | unsigned int lvds_dither:1; |
| 1192 | unsigned int lvds_vbt:1; |
| 1193 | unsigned int int_crt_support:1; |
| 1194 | unsigned int lvds_use_ssc:1; |
| 1195 | unsigned int display_clock_mode:1; |
| 1196 | unsigned int fdi_rx_polarity_inverted:1; |
| 1197 | int lvds_ssc_freq; |
| 1198 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
| 1199 | |
| 1200 | /* eDP */ |
| 1201 | int edp_rate; |
| 1202 | int edp_lanes; |
| 1203 | int edp_preemphasis; |
| 1204 | int edp_vswing; |
| 1205 | bool edp_initialized; |
| 1206 | bool edp_support; |
| 1207 | int edp_bpp; |
| 1208 | struct edp_power_seq edp_pps; |
| 1209 | |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 1210 | /* MIPI DSI */ |
| 1211 | struct { |
| 1212 | u16 panel_id; |
| 1213 | } dsi; |
| 1214 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1215 | int crt_ddc_pin; |
| 1216 | |
| 1217 | int child_dev_num; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 1218 | union child_device_config *child_dev; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1219 | |
| 1220 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1221 | }; |
| 1222 | |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 1223 | enum intel_ddb_partitioning { |
| 1224 | INTEL_DDB_PART_1_2, |
| 1225 | INTEL_DDB_PART_5_6, /* IVB+ */ |
| 1226 | }; |
| 1227 | |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 1228 | struct intel_wm_level { |
| 1229 | bool enable; |
| 1230 | uint32_t pri_val; |
| 1231 | uint32_t spr_val; |
| 1232 | uint32_t cur_val; |
| 1233 | uint32_t fbc_val; |
| 1234 | }; |
| 1235 | |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1236 | struct hsw_wm_values { |
| 1237 | uint32_t wm_pipe[3]; |
| 1238 | uint32_t wm_lp[3]; |
| 1239 | uint32_t wm_lp_spr[3]; |
| 1240 | uint32_t wm_linetime[3]; |
| 1241 | bool enable_fbc_wm; |
| 1242 | enum intel_ddb_partitioning partitioning; |
| 1243 | }; |
| 1244 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1245 | /* |
| 1246 | * This struct tracks the state needed for the Package C8+ feature. |
| 1247 | * |
| 1248 | * Package states C8 and deeper are really deep PC states that can only be |
| 1249 | * reached when all the devices on the system allow it, so even if the graphics |
| 1250 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 1251 | * states. |
| 1252 | * |
| 1253 | * Our driver only allows PC8+ when all the outputs are disabled, the power well |
| 1254 | * is disabled and the GPU is idle. When these conditions are met, we manually |
| 1255 | * do the other conditions: disable the interrupts, clocks and switch LCPLL |
| 1256 | * refclk to Fclk. |
| 1257 | * |
| 1258 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 1259 | * the state of some registers, so when we come back from PC8+ we need to |
| 1260 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 1261 | * need to take care of the registers kept by RC6. |
| 1262 | * |
| 1263 | * The interrupt disabling is part of the requirements. We can only leave the |
| 1264 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we |
| 1265 | * can lock the machine. |
| 1266 | * |
| 1267 | * Ideally every piece of our code that needs PC8+ disabled would call |
| 1268 | * hsw_disable_package_c8, which would increment disable_count and prevent the |
| 1269 | * system from reaching PC8+. But we don't have a symmetric way to do this for |
| 1270 | * everything, so we have the requirements_met and gpu_idle variables. When we |
| 1271 | * switch requirements_met or gpu_idle to true we decrease disable_count, and |
| 1272 | * increase it in the opposite case. The requirements_met variable is true when |
| 1273 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle |
| 1274 | * variable is true when the GPU is idle. |
| 1275 | * |
| 1276 | * In addition to everything, we only actually enable PC8+ if disable_count |
| 1277 | * stays at zero for at least some seconds. This is implemented with the |
| 1278 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of |
| 1279 | * consecutive times when all screens are disabled and some background app |
| 1280 | * queries the state of our connectors, or we have some application constantly |
| 1281 | * waking up to use the GPU. Only after the enable_work function actually |
| 1282 | * enables PC8+ the "enable" variable will become true, which means that it can |
| 1283 | * be false even if disable_count is 0. |
| 1284 | * |
| 1285 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
| 1286 | * goes back to false exactly before we reenable the IRQs. We use this variable |
| 1287 | * to check if someone is trying to enable/disable IRQs while they're supposed |
| 1288 | * to be disabled. This shouldn't happen and we'll print some error messages in |
| 1289 | * case it happens, but if it actually happens we'll also update the variables |
| 1290 | * inside struct regsave so when we restore the IRQs they will contain the |
| 1291 | * latest expected values. |
| 1292 | * |
| 1293 | * For more, read "Display Sequences for Package C8" on our documentation. |
| 1294 | */ |
| 1295 | struct i915_package_c8 { |
| 1296 | bool requirements_met; |
| 1297 | bool gpu_idle; |
| 1298 | bool irqs_disabled; |
| 1299 | /* Only true after the delayed work task actually enables it. */ |
| 1300 | bool enabled; |
| 1301 | int disable_count; |
| 1302 | struct mutex lock; |
| 1303 | struct delayed_work enable_work; |
| 1304 | |
| 1305 | struct { |
| 1306 | uint32_t deimr; |
| 1307 | uint32_t sdeimr; |
| 1308 | uint32_t gtimr; |
| 1309 | uint32_t gtier; |
| 1310 | uint32_t gen6_pmimr; |
| 1311 | } regsave; |
| 1312 | }; |
| 1313 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1314 | enum intel_pipe_crc_source { |
| 1315 | INTEL_PIPE_CRC_SOURCE_NONE, |
| 1316 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
| 1317 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
| 1318 | INTEL_PIPE_CRC_SOURCE_PF, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1319 | INTEL_PIPE_CRC_SOURCE_PIPE, |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 1320 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
| 1321 | INTEL_PIPE_CRC_SOURCE_TV, |
| 1322 | INTEL_PIPE_CRC_SOURCE_DP_B, |
| 1323 | INTEL_PIPE_CRC_SOURCE_DP_C, |
| 1324 | INTEL_PIPE_CRC_SOURCE_DP_D, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 1325 | INTEL_PIPE_CRC_SOURCE_AUTO, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1326 | INTEL_PIPE_CRC_SOURCE_MAX, |
| 1327 | }; |
| 1328 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1329 | struct intel_pipe_crc_entry { |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1330 | uint32_t frame; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1331 | uint32_t crc[5]; |
| 1332 | }; |
| 1333 | |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1334 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1335 | struct intel_pipe_crc { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1336 | spinlock_t lock; |
| 1337 | bool opened; /* exclusive access to the result file */ |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 1338 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1339 | enum intel_pipe_crc_source source; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1340 | int head, tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1341 | wait_queue_head_t wq; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1342 | }; |
| 1343 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1344 | typedef struct drm_i915_private { |
| 1345 | struct drm_device *dev; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1346 | struct kmem_cache *slab; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1347 | |
| 1348 | const struct intel_device_info *info; |
| 1349 | |
| 1350 | int relative_constants_mode; |
| 1351 | |
| 1352 | void __iomem *regs; |
| 1353 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1354 | struct intel_uncore uncore; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1355 | |
| 1356 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
| 1357 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1358 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1359 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
| 1360 | * controller on different i2c buses. */ |
| 1361 | struct mutex gmbus_mutex; |
| 1362 | |
| 1363 | /** |
| 1364 | * Base address of the gmbus and gpio block. |
| 1365 | */ |
| 1366 | uint32_t gpio_mmio_base; |
| 1367 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1368 | wait_queue_head_t gmbus_wait_queue; |
| 1369 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1370 | struct pci_dev *bridge_dev; |
| 1371 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1372 | uint32_t last_seqno, next_seqno; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1373 | |
| 1374 | drm_dma_handle_t *status_page_dmah; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1375 | struct resource mch_res; |
| 1376 | |
| 1377 | atomic_t irq_received; |
| 1378 | |
| 1379 | /* protects the irq masks */ |
| 1380 | spinlock_t irq_lock; |
| 1381 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1382 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
| 1383 | struct pm_qos_request pm_qos; |
| 1384 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1385 | /* DPIO indirect register protection */ |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1386 | struct mutex dpio_lock; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1387 | |
| 1388 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1389 | union { |
| 1390 | u32 irq_mask; |
| 1391 | u32 de_irq_mask[I915_MAX_PIPES]; |
| 1392 | }; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1393 | u32 gt_irq_mask; |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 1394 | u32 pm_irq_mask; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1395 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1396 | struct work_struct hotplug_work; |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1397 | bool enable_hotplug_processing; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1398 | struct { |
| 1399 | unsigned long hpd_last_jiffies; |
| 1400 | int hpd_cnt; |
| 1401 | enum { |
| 1402 | HPD_ENABLED = 0, |
| 1403 | HPD_DISABLED = 1, |
| 1404 | HPD_MARK_DISABLED = 2 |
| 1405 | } hpd_mark; |
| 1406 | } hpd_stats[HPD_NUM_PINS]; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1407 | u32 hpd_event_bits; |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 1408 | struct timer_list hotplug_reenable_timer; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1409 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1410 | int num_plane; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1411 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1412 | struct i915_fbc fbc; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1413 | struct intel_opregion opregion; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1414 | struct intel_vbt_data vbt; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1415 | |
| 1416 | /* overlay */ |
| 1417 | struct intel_overlay *overlay; |
Ville Syrjälä | 2c6602d | 2013-02-08 23:13:35 +0200 | [diff] [blame] | 1418 | unsigned int sprite_scaling_enabled; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1419 | |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 1420 | /* backlight registers and fields in struct intel_panel */ |
| 1421 | spinlock_t backlight_lock; |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 1422 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1423 | /* LVDS info */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1424 | bool no_aux_handshake; |
| 1425 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1426 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
| 1427 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 1428 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 1429 | |
| 1430 | unsigned int fsb_freq, mem_freq, is_ddr3; |
| 1431 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1432 | /** |
| 1433 | * wq - Driver workqueue for GEM. |
| 1434 | * |
| 1435 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
| 1436 | * locks, for otherwise the flushing done in the pageflip code will |
| 1437 | * result in deadlocks. |
| 1438 | */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1439 | struct workqueue_struct *wq; |
| 1440 | |
| 1441 | /* Display functions */ |
| 1442 | struct drm_i915_display_funcs display; |
| 1443 | |
| 1444 | /* PCH chipset type */ |
| 1445 | enum intel_pch pch_type; |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 1446 | unsigned short pch_id; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1447 | |
| 1448 | unsigned long quirks; |
| 1449 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1450 | enum modeset_restore modeset_restore; |
| 1451 | struct mutex modeset_restore_lock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1452 | |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 1453 | struct list_head vm_list; /* Global list of all address spaces */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1454 | struct i915_gtt gtt; /* VMA representing the global address space */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1455 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1456 | struct i915_gem_mm mm; |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1457 | |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1458 | /* Kernel Modesetting */ |
| 1459 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 1460 | struct sdvo_device_mapping sdvo_mappings[2]; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1461 | |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 1462 | struct drm_crtc *plane_to_crtc_mapping[3]; |
| 1463 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1464 | wait_queue_head_t pending_flip_queue; |
| 1465 | |
Daniel Vetter | c459787 | 2013-10-21 21:04:07 +0200 | [diff] [blame] | 1466 | #ifdef CONFIG_DEBUG_FS |
| 1467 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
| 1468 | #endif |
| 1469 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1470 | int num_shared_dpll; |
| 1471 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1472 | struct intel_ddi_plls ddi_plls; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1473 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1474 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1475 | /* Reclocking support */ |
| 1476 | bool render_reclock_avail; |
| 1477 | bool lvds_downclock_avail; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 1478 | /* indicates the reduced downclock for LVDS*/ |
| 1479 | int lvds_downclock; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1480 | u16 orig_clock; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1481 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1482 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1483 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1484 | struct intel_l3_parity l3_parity; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1485 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 1486 | /* Cannot be determined by PCIID. You must always read a register. */ |
| 1487 | size_t ellc_size; |
| 1488 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1489 | /* gen6+ rps state */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1490 | struct intel_gen6_power_mgmt rps; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1491 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1492 | /* ilk-only ips/rps state. Everything in here is protected by the global |
| 1493 | * mchdev_lock in intel_pm.c */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1494 | struct intel_ilk_power_mgmt ips; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1495 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1496 | struct i915_power_domains power_domains; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1497 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1498 | struct i915_psr psr; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1499 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1500 | struct i915_gpu_error gpu_error; |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 1501 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 1502 | struct drm_i915_gem_object *vlv_pctx; |
| 1503 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1504 | #ifdef CONFIG_DRM_I915_FBDEV |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 1505 | /* list of fbdev register on this device */ |
| 1506 | struct intel_fbdev *fbdev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1507 | #endif |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1508 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1509 | /* |
| 1510 | * The console may be contended at resume, but we don't |
| 1511 | * want it to block on it. |
| 1512 | */ |
| 1513 | struct work_struct console_resume_work; |
| 1514 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1515 | struct drm_property *broadcast_rgb_property; |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1516 | struct drm_property *force_audio_property; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1517 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1518 | uint32_t hw_context_size; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1519 | struct list_head context_list; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1520 | |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 1521 | u32 fdi_rx_config; |
Paulo Zanoni | 68d18ad | 2012-12-01 12:04:26 -0200 | [diff] [blame] | 1522 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1523 | struct i915_suspend_saved_registers regfile; |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1524 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1525 | struct { |
| 1526 | /* |
| 1527 | * Raw watermark latency values: |
| 1528 | * in 0.1us units for WM0, |
| 1529 | * in 0.5us units for WM1+. |
| 1530 | */ |
| 1531 | /* primary */ |
| 1532 | uint16_t pri_latency[5]; |
| 1533 | /* sprite */ |
| 1534 | uint16_t spr_latency[5]; |
| 1535 | /* cursor */ |
| 1536 | uint16_t cur_latency[5]; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1537 | |
| 1538 | /* current hardware state */ |
| 1539 | struct hsw_wm_values hw; |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1540 | } wm; |
| 1541 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1542 | struct i915_package_c8 pc8; |
| 1543 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1544 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
| 1545 | * here! */ |
| 1546 | struct i915_dri1_state dri1; |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 1547 | /* Old ums support infrastructure, same warning applies. */ |
| 1548 | struct i915_ums_state ums; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1549 | } drm_i915_private_t; |
| 1550 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1551 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
| 1552 | { |
| 1553 | return dev->dev_private; |
| 1554 | } |
| 1555 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1556 | /* Iterate over initialised rings */ |
| 1557 | #define for_each_ring(ring__, dev_priv__, i__) \ |
| 1558 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
| 1559 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
| 1560 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 1561 | enum hdmi_force_audio { |
| 1562 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
| 1563 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
| 1564 | HDMI_AUDIO_AUTO, /* trust EDID */ |
| 1565 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
| 1566 | }; |
| 1567 | |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 1568 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1569 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1570 | struct drm_i915_gem_object_ops { |
| 1571 | /* Interface between the GEM object and its backing storage. |
| 1572 | * get_pages() is called once prior to the use of the associated set |
| 1573 | * of pages before to binding them into the GTT, and put_pages() is |
| 1574 | * called after we no longer need them. As we expect there to be |
| 1575 | * associated cost with migrating pages between the backing storage |
| 1576 | * and making them available for the GPU (e.g. clflush), we may hold |
| 1577 | * onto the pages after they are no longer referenced by the GPU |
| 1578 | * in case they may be used again shortly (for example migrating the |
| 1579 | * pages to a different memory domain within the GTT). put_pages() |
| 1580 | * will therefore most likely be called when the object itself is |
| 1581 | * being released or under memory pressure (where we attempt to |
| 1582 | * reap pages for the shrinker). |
| 1583 | */ |
| 1584 | int (*get_pages)(struct drm_i915_gem_object *); |
| 1585 | void (*put_pages)(struct drm_i915_gem_object *); |
| 1586 | }; |
| 1587 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1588 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 1589 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1590 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1591 | const struct drm_i915_gem_object_ops *ops; |
| 1592 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 1593 | /** List of VMAs backed by this object */ |
| 1594 | struct list_head vma_list; |
| 1595 | |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 1596 | /** Stolen memory for this object, instead of being backed by shmem. */ |
| 1597 | struct drm_mm_node *stolen; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1598 | struct list_head global_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1599 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1600 | struct list_head ring_list; |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 1601 | /** Used in execbuf to temporarily hold a ref */ |
| 1602 | struct list_head obj_exec_link; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1603 | |
| 1604 | /** |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1605 | * This is set if the object is on the active lists (has pending |
| 1606 | * rendering and so a non-zero seqno), and is not set if it i s on |
| 1607 | * inactive (ready to be unbound) list. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1608 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1609 | unsigned int active:1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1610 | |
| 1611 | /** |
| 1612 | * This is set if the object has been written to since last bound |
| 1613 | * to the GTT |
| 1614 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1615 | unsigned int dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1616 | |
| 1617 | /** |
| 1618 | * Fence register bits (if any) for this object. Will be set |
| 1619 | * as needed when mapped into the GTT. |
| 1620 | * Protected by dev->struct_mutex. |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1621 | */ |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1622 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1623 | |
| 1624 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1625 | * Advice: are the backing pages purgeable? |
| 1626 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1627 | unsigned int madv:2; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1628 | |
| 1629 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1630 | * Current tiling mode for the object. |
| 1631 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1632 | unsigned int tiling_mode:2; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 1633 | /** |
| 1634 | * Whether the tiling parameters for the currently associated fence |
| 1635 | * register have changed. Note that for the purposes of tracking |
| 1636 | * tiling changes we also treat the unfenced register, the register |
| 1637 | * slot that the object occupies whilst it executes a fenced |
| 1638 | * command (such as BLT on gen2/3), as a "fence". |
| 1639 | */ |
| 1640 | unsigned int fence_dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1641 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1642 | /** |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1643 | * Is the object at the current location in the gtt mappable and |
| 1644 | * fenceable? Used to avoid costly recalculations. |
| 1645 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1646 | unsigned int map_and_fenceable:1; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1647 | |
| 1648 | /** |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1649 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 1650 | * mappable by accident). Track pin and fault separate for a more |
| 1651 | * accurate mappable working set. |
| 1652 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1653 | unsigned int fault_mappable:1; |
| 1654 | unsigned int pin_mappable:1; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 1655 | unsigned int pin_display:1; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1656 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1657 | /* |
| 1658 | * Is the GPU currently using a fence to access this buffer, |
| 1659 | */ |
| 1660 | unsigned int pending_fenced_gpu_access:1; |
| 1661 | unsigned int fenced_gpu_access:1; |
| 1662 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 1663 | unsigned int cache_level:3; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 1664 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1665 | unsigned int has_aliasing_ppgtt_mapping:1; |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1666 | unsigned int has_global_gtt_mapping:1; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1667 | unsigned int has_dma_mapping:1; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1668 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1669 | struct sg_table *pages; |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1670 | int pages_pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1671 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1672 | /* prime dma-buf support */ |
Dave Airlie | 9a70cc2 | 2012-05-22 13:09:21 +0100 | [diff] [blame] | 1673 | void *dma_buf_vmapping; |
| 1674 | int vmapping_count; |
| 1675 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1676 | struct intel_ring_buffer *ring; |
| 1677 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 1678 | /** Breadcrumb of last rendering to the buffer. */ |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1679 | uint32_t last_read_seqno; |
| 1680 | uint32_t last_write_seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1681 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
| 1682 | uint32_t last_fenced_seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1683 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1684 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1685 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 1687 | /** References from framebuffers, locks out tiling changes. */ |
| 1688 | unsigned long framebuffer_references; |
| 1689 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1690 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 1691 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1692 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1693 | /** User space pin count and filp owning the pin */ |
Daniel Vetter | aa5f802 | 2013-10-10 14:46:37 +0200 | [diff] [blame] | 1694 | unsigned long user_pin_count; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1695 | struct drm_file *pin_filp; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1696 | |
| 1697 | /** for phy allocated objects */ |
| 1698 | struct drm_i915_gem_phys_object *phys_obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1699 | }; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1700 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1701 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 1702 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1703 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1704 | /** |
| 1705 | * Request queue structure. |
| 1706 | * |
| 1707 | * The request queue allows us to note sequence numbers that have been emitted |
| 1708 | * and may be associated with active buffers to be retired. |
| 1709 | * |
| 1710 | * By keeping this list, we can avoid having to do questionable |
| 1711 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 1712 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 1713 | */ |
| 1714 | struct drm_i915_gem_request { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1715 | /** On Which ring this request was generated */ |
| 1716 | struct intel_ring_buffer *ring; |
| 1717 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1718 | /** GEM sequence number associated with this request. */ |
| 1719 | uint32_t seqno; |
| 1720 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 1721 | /** Position in the ringbuffer of the start of the request */ |
| 1722 | u32 head; |
| 1723 | |
| 1724 | /** Position in the ringbuffer of the end of the request */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1725 | u32 tail; |
| 1726 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 1727 | /** Context related to this request */ |
| 1728 | struct i915_hw_context *ctx; |
| 1729 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 1730 | /** Batch buffer related to this request if any */ |
| 1731 | struct drm_i915_gem_object *batch_obj; |
| 1732 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1733 | /** Time at which this request was emitted, in jiffies. */ |
| 1734 | unsigned long emitted_jiffies; |
| 1735 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1736 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1737 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1738 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1739 | struct drm_i915_file_private *file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1740 | /** file_priv list entry for this request */ |
| 1741 | struct list_head client_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1742 | }; |
| 1743 | |
| 1744 | struct drm_i915_file_private { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1745 | struct drm_i915_private *dev_priv; |
| 1746 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1747 | struct { |
Luis R. Rodriguez | 99057c8 | 2012-11-29 12:45:06 -0800 | [diff] [blame] | 1748 | spinlock_t lock; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1749 | struct list_head request_list; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1750 | struct delayed_work idle_work; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1751 | } mm; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 1752 | struct idr context_idr; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 1753 | |
| 1754 | struct i915_ctx_hang_stats hang_stats; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1755 | atomic_t rps_wait_boost; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1756 | }; |
| 1757 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1758 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1759 | |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1760 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
| 1761 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1762 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1763 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1764 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1765 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
| 1766 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1767 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 1768 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 1769 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1770 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1771 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1772 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
| 1773 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1774 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 1775 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1776 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
Jesse Barnes | 4b65177 | 2011-04-28 14:33:09 -0700 | [diff] [blame] | 1777 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1778 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
| 1779 | (dev)->pdev->device == 0x0152 || \ |
| 1780 | (dev)->pdev->device == 0x015a) |
| 1781 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ |
| 1782 | (dev)->pdev->device == 0x0106 || \ |
| 1783 | (dev)->pdev->device == 0x010A) |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 1784 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 1785 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
Paulo Zanoni | 4e8058a | 2013-11-02 21:07:31 -0700 | [diff] [blame] | 1786 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1787 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
Paulo Zanoni | ed1c9e2 | 2013-08-12 14:34:08 -0300 | [diff] [blame] | 1788 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1789 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 1790 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
| 1791 | (((dev)->pdev->device & 0xf) == 0x2 || \ |
| 1792 | ((dev)->pdev->device & 0xf) == 0x6 || \ |
| 1793 | ((dev)->pdev->device & 0xf) == 0xe)) |
| 1794 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1795 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 1796 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 1797 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1798 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 1799 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1800 | |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1801 | /* |
| 1802 | * The genX designation typically refers to the render engine, so render |
| 1803 | * capability related checks should use IS_GEN, while display and other checks |
| 1804 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
| 1805 | * chips, etc.). |
| 1806 | */ |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1807 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 1808 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 1809 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 1810 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 1811 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1812 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
Ben Widawsky | d298084 | 2013-11-02 21:06:59 -0700 | [diff] [blame] | 1813 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1814 | |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 1815 | #define RENDER_RING (1<<RCS) |
| 1816 | #define BSD_RING (1<<VCS) |
| 1817 | #define BLT_RING (1<<BCS) |
| 1818 | #define VEBOX_RING (1<<VECS) |
| 1819 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
| 1820 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
| 1821 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 1822 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 1823 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1824 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 1825 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1826 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
Jesse Barnes | 9355360 | 2012-06-15 11:55:23 -0700 | [diff] [blame] | 1827 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1828 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1829 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1830 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 1831 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1832 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
| 1833 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
| 1834 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1835 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 1836 | * rows, which changed the alignment requirements and fence programming. |
| 1837 | */ |
| 1838 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 1839 | IS_I915GM(dev))) |
| 1840 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 1841 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 1842 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1843 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 1844 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1845 | |
| 1846 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 1847 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
| 1848 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1849 | |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 1850 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 1851 | |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 1852 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 1853 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
Ben Widawsky | ed8546a | 2013-11-04 22:45:05 -0800 | [diff] [blame] | 1854 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 7c6c265 | 2013-11-18 18:32:37 -0800 | [diff] [blame] | 1855 | #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1856 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 1857 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
| 1858 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 1859 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 1860 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
| 1861 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
| 1862 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
| 1863 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1864 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 1865 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1866 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 1867 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 1868 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
Paulo Zanoni | 45e6e3a | 2012-07-03 15:57:32 -0300 | [diff] [blame] | 1869 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1870 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1871 | /* DPF == dynamic parity feature */ |
| 1872 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 1873 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 1874 | |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 1875 | #define GT_FREQUENCY_MULTIPLIER 50 |
| 1876 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1877 | #include "i915_trace.h" |
| 1878 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 1879 | extern const struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 1880 | extern int i915_max_ioctl; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1881 | extern unsigned int i915_fbpercrtc __always_unused; |
| 1882 | extern int i915_panel_ignore_lid __read_mostly; |
| 1883 | extern unsigned int i915_powersave __read_mostly; |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 1884 | extern int i915_semaphores __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1885 | extern unsigned int i915_lvds_downclock __read_mostly; |
Takashi Iwai | 121d527 | 2012-03-20 13:07:06 +0100 | [diff] [blame] | 1886 | extern int i915_lvds_channel_mode __read_mostly; |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 1887 | extern int i915_panel_use_ssc __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1888 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 1889 | extern int i915_enable_rc6 __read_mostly; |
Keith Packard | 4415e63 | 2011-11-09 09:57:50 -0800 | [diff] [blame] | 1890 | extern int i915_enable_fbc __read_mostly; |
Ben Widawsky | a35d9d3 | 2011-07-13 14:38:17 -0700 | [diff] [blame] | 1891 | extern bool i915_enable_hangcheck __read_mostly; |
Daniel Vetter | 650dc07 | 2012-04-02 10:08:35 +0200 | [diff] [blame] | 1892 | extern int i915_enable_ppgtt __read_mostly; |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1893 | extern int i915_enable_psr __read_mostly; |
Rodrigo Vivi | 0a3af26 | 2012-10-15 17:16:23 -0300 | [diff] [blame] | 1894 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
Paulo Zanoni | 2124b72 | 2013-03-22 14:07:23 -0300 | [diff] [blame] | 1895 | extern int i915_disable_power_well __read_mostly; |
Paulo Zanoni | 3c4ca58 | 2013-05-31 16:33:23 -0300 | [diff] [blame] | 1896 | extern int i915_enable_ips __read_mostly; |
Jesse Barnes | 2385bdf | 2013-06-26 01:38:15 +0300 | [diff] [blame] | 1897 | extern bool i915_fastboot __read_mostly; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1898 | extern int i915_enable_pc8 __read_mostly; |
Paulo Zanoni | 9005874 | 2013-08-19 13:18:11 -0300 | [diff] [blame] | 1899 | extern int i915_pc8_timeout __read_mostly; |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1900 | extern bool i915_prefault_disable __read_mostly; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 1901 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1902 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 1903 | extern int i915_resume(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 1904 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 1905 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 1906 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1907 | /* i915_dma.c */ |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 1908 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1909 | extern void i915_kernel_lost_context(struct drm_device * dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 1910 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 1911 | extern int i915_driver_unload(struct drm_device *); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1912 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1913 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 1914 | extern void i915_driver_preclose(struct drm_device *dev, |
| 1915 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1916 | extern void i915_driver_postclose(struct drm_device *dev, |
| 1917 | struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 1918 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1919 | #ifdef CONFIG_COMPAT |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1920 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 1921 | unsigned long arg); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1922 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1923 | extern int i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1924 | struct drm_clip_rect *box, |
| 1925 | int DR1, int DR4); |
Ben Widawsky | 8e96d9c | 2012-06-04 14:42:56 -0700 | [diff] [blame] | 1926 | extern int intel_gpu_reset(struct drm_device *dev); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 1927 | extern int i915_reset(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 1928 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 1929 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 1930 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 1931 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 1932 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1933 | extern void intel_console_resume(struct work_struct *work); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 1934 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1935 | /* i915_irq.c */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 1936 | void i915_queue_hangcheck(struct drm_device *dev); |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1937 | void i915_handle_error(struct drm_device *dev, bool wedged); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1938 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1939 | extern void intel_irq_init(struct drm_device *dev); |
Ben Widawsky | e1b4d30 | 2013-07-30 16:27:57 -0700 | [diff] [blame] | 1940 | extern void intel_pm_init(struct drm_device *dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 1941 | extern void intel_hpd_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1942 | extern void intel_pm_init(struct drm_device *dev); |
| 1943 | |
| 1944 | extern void intel_uncore_sanitize(struct drm_device *dev); |
| 1945 | extern void intel_uncore_early_sanitize(struct drm_device *dev); |
| 1946 | extern void intel_uncore_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1947 | extern void intel_uncore_check_errors(struct drm_device *dev); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 1948 | extern void intel_uncore_fini(struct drm_device *dev); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1949 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1950 | void |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 1951 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1952 | |
| 1953 | void |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 1954 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1955 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1956 | /* i915_gem.c */ |
| 1957 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 1958 | struct drm_file *file_priv); |
| 1959 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1960 | struct drm_file *file_priv); |
| 1961 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1962 | struct drm_file *file_priv); |
| 1963 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1964 | struct drm_file *file_priv); |
| 1965 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1966 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1967 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1968 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1969 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1970 | struct drm_file *file_priv); |
| 1971 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1972 | struct drm_file *file_priv); |
| 1973 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1974 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 1975 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1976 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1977 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1978 | struct drm_file *file_priv); |
| 1979 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1980 | struct drm_file *file_priv); |
| 1981 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1982 | struct drm_file *file_priv); |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 1983 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 1984 | struct drm_file *file); |
| 1985 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 1986 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1987 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 1988 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1989 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 1990 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1991 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 1992 | struct drm_file *file_priv); |
| 1993 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 1994 | struct drm_file *file_priv); |
| 1995 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 1996 | struct drm_file *file_priv); |
| 1997 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 1998 | struct drm_file *file_priv); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 1999 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 2000 | struct drm_file *file_priv); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2001 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
| 2002 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2003 | void i915_gem_load(struct drm_device *dev); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 2004 | void *i915_gem_object_alloc(struct drm_device *dev); |
| 2005 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2006 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 2007 | const struct drm_i915_gem_object_ops *ops); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2008 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 2009 | size_t size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2010 | void i915_gem_free_object(struct drm_gem_object *obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2011 | void i915_gem_vma_destroy(struct i915_vma *vma); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 2012 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2013 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2014 | struct i915_address_space *vm, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2015 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2016 | bool map_and_fenceable, |
| 2017 | bool nonblocking); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2018 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2019 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
| 2020 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2021 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2022 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2023 | void i915_gem_lastclose(struct drm_device *dev); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2024 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2025 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2026 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
| 2027 | { |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2028 | struct sg_page_iter sg_iter; |
Chris Wilson | 1cf8378 | 2012-10-10 12:11:52 +0100 | [diff] [blame] | 2029 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2030 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2031 | return sg_page_iter_page(&sg_iter); |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2032 | |
| 2033 | return NULL; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2034 | } |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2035 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
| 2036 | { |
| 2037 | BUG_ON(obj->pages == NULL); |
| 2038 | obj->pages_pin_count++; |
| 2039 | } |
| 2040 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
| 2041 | { |
| 2042 | BUG_ON(obj->pages_pin_count == 0); |
| 2043 | obj->pages_pin_count--; |
| 2044 | } |
| 2045 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2046 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2047 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2048 | struct intel_ring_buffer *to); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2049 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2050 | struct intel_ring_buffer *ring); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2051 | int i915_gem_dumb_create(struct drm_file *file_priv, |
| 2052 | struct drm_device *dev, |
| 2053 | struct drm_mode_create_dumb *args); |
| 2054 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
| 2055 | uint32_t handle, uint64_t *offset); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2056 | /** |
| 2057 | * Returns true if seq1 is later than seq2. |
| 2058 | */ |
| 2059 | static inline bool |
| 2060 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 2061 | { |
| 2062 | return (int32_t)(seq1 - seq2) >= 0; |
| 2063 | } |
| 2064 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2065 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
| 2066 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2067 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2068 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2069 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2070 | static inline bool |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2071 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 2072 | { |
| 2073 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2074 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2075 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2076 | return true; |
| 2077 | } else |
| 2078 | return false; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2079 | } |
| 2080 | |
| 2081 | static inline void |
| 2082 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 2083 | { |
| 2084 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2085 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | b8c3af7 | 2013-06-12 11:29:47 +0100 | [diff] [blame] | 2086 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2087 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 2088 | } |
| 2089 | } |
| 2090 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2091 | bool i915_gem_retire_requests(struct drm_device *dev); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2092 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2093 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 2094 | bool interruptible); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2095 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
| 2096 | { |
| 2097 | return unlikely(atomic_read(&error->reset_counter) |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2098 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2099 | } |
| 2100 | |
| 2101 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
| 2102 | { |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2103 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
| 2104 | } |
| 2105 | |
| 2106 | static inline u32 i915_reset_count(struct i915_gpu_error *error) |
| 2107 | { |
| 2108 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2109 | } |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2110 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2111 | void i915_gem_reset(struct drm_device *dev); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 2112 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2113 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 2114 | int __must_check i915_gem_init(struct drm_device *dev); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2115 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 2116 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2117 | void i915_gem_init_swizzling(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2118 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2119 | int __must_check i915_gpu_idle(struct drm_device *dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 2120 | int __must_check i915_gem_suspend(struct drm_device *dev); |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2121 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 2122 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2123 | struct drm_i915_gem_object *batch_obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2124 | u32 *seqno); |
| 2125 | #define i915_add_request(ring, seqno) \ |
Dan Carpenter | 854c94a | 2013-06-18 10:29:58 +0300 | [diff] [blame] | 2126 | __i915_add_request(ring, NULL, NULL, seqno) |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2127 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
| 2128 | uint32_t seqno); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2129 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2130 | int __must_check |
| 2131 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 2132 | bool write); |
| 2133 | int __must_check |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 2134 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
| 2135 | int __must_check |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2136 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2137 | u32 alignment, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2138 | struct intel_ring_buffer *pipelined); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2139 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2140 | int i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2141 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 2142 | int id, |
| 2143 | int align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2144 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2145 | struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2146 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2147 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2148 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2149 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2150 | uint32_t |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 2151 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
| 2152 | uint32_t |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2153 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 2154 | int tiling_mode, bool fenced); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2155 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2156 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2157 | enum i915_cache_level cache_level); |
| 2158 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2159 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
| 2160 | struct dma_buf *dma_buf); |
| 2161 | |
| 2162 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
| 2163 | struct drm_gem_object *gem_obj, int flags); |
| 2164 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2165 | void i915_gem_restore_fences(struct drm_device *dev); |
| 2166 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2167 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 2168 | struct i915_address_space *vm); |
| 2169 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
| 2170 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 2171 | struct i915_address_space *vm); |
| 2172 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 2173 | struct i915_address_space *vm); |
| 2174 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 2175 | struct i915_address_space *vm); |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 2176 | struct i915_vma * |
| 2177 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 2178 | struct i915_address_space *vm); |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2179 | |
| 2180 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2181 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
| 2182 | struct i915_vma *vma; |
| 2183 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 2184 | if (vma->pin_count > 0) |
| 2185 | return true; |
| 2186 | return false; |
| 2187 | } |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2188 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2189 | /* Some GGTT VM helpers */ |
| 2190 | #define obj_to_ggtt(obj) \ |
| 2191 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
| 2192 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
| 2193 | { |
| 2194 | struct i915_address_space *ggtt = |
| 2195 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
| 2196 | return vm == ggtt; |
| 2197 | } |
| 2198 | |
| 2199 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
| 2200 | { |
| 2201 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); |
| 2202 | } |
| 2203 | |
| 2204 | static inline unsigned long |
| 2205 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) |
| 2206 | { |
| 2207 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); |
| 2208 | } |
| 2209 | |
| 2210 | static inline unsigned long |
| 2211 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
| 2212 | { |
| 2213 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); |
| 2214 | } |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2215 | |
| 2216 | static inline int __must_check |
| 2217 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
| 2218 | uint32_t alignment, |
| 2219 | bool map_and_fenceable, |
| 2220 | bool nonblocking) |
| 2221 | { |
| 2222 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, |
| 2223 | map_and_fenceable, nonblocking); |
| 2224 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2225 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2226 | /* i915_gem_context.c */ |
Ben Widawsky | 8245be3 | 2013-11-06 13:56:29 -0200 | [diff] [blame] | 2227 | int __must_check i915_gem_context_init(struct drm_device *dev); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2228 | void i915_gem_context_fini(struct drm_device *dev); |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2229 | void i915_gem_context_reset(struct drm_device *dev); |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 2230 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 2231 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2232 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
Ben Widawsky | e055684 | 2012-06-04 14:42:46 -0700 | [diff] [blame] | 2233 | int i915_switch_context(struct intel_ring_buffer *ring, |
| 2234 | struct drm_file *file, int to_id); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2235 | void i915_gem_context_free(struct kref *ctx_ref); |
| 2236 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) |
| 2237 | { |
| 2238 | kref_get(&ctx->ref); |
| 2239 | } |
| 2240 | |
| 2241 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) |
| 2242 | { |
| 2243 | kref_put(&ctx->ref, i915_gem_context_free); |
| 2244 | } |
| 2245 | |
Mika Kuoppala | c0bb617 | 2013-06-12 12:35:29 +0300 | [diff] [blame] | 2246 | struct i915_ctx_hang_stats * __must_check |
Chris Wilson | 11fa338 | 2013-07-03 17:22:06 +0300 | [diff] [blame] | 2247 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
Mika Kuoppala | c0bb617 | 2013-06-12 12:35:29 +0300 | [diff] [blame] | 2248 | struct drm_file *file, |
| 2249 | u32 id); |
Ben Widawsky | 8462481 | 2012-06-04 14:42:54 -0700 | [diff] [blame] | 2250 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 2251 | struct drm_file *file); |
| 2252 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 2253 | struct drm_file *file); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2254 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 2255 | /* i915_gem_gtt.c */ |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 2256 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 2257 | void i915_check_and_clear_faults(struct drm_device *dev); |
| 2258 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 2259 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2260 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2261 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 2262 | void i915_gem_init_global_gtt(struct drm_device *dev); |
| 2263 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
| 2264 | unsigned long mappable_end, unsigned long end); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2265 | int i915_gem_gtt_init(struct drm_device *dev); |
Ben Widawsky | d09105c | 2012-11-15 12:06:09 -0800 | [diff] [blame] | 2266 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2267 | { |
| 2268 | if (INTEL_INFO(dev)->gen < 6) |
| 2269 | intel_gtt_chipset_flush(); |
| 2270 | } |
| 2271 | |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 2272 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2273 | /* i915_gem_evict.c */ |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 2274 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
| 2275 | struct i915_address_space *vm, |
| 2276 | int min_size, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2277 | unsigned alignment, |
| 2278 | unsigned cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2279 | bool mappable, |
| 2280 | bool nonblock); |
Ben Widawsky | 68c8c17 | 2013-09-11 14:57:50 -0700 | [diff] [blame] | 2281 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2282 | int i915_gem_evict_everything(struct drm_device *dev); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2283 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2284 | /* i915_gem_stolen.c */ |
| 2285 | int i915_gem_init_stolen(struct drm_device *dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 2286 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
| 2287 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2288 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2289 | struct drm_i915_gem_object * |
| 2290 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
Chris Wilson | 866d12b | 2013-02-19 13:31:37 -0800 | [diff] [blame] | 2291 | struct drm_i915_gem_object * |
| 2292 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
| 2293 | u32 stolen_offset, |
| 2294 | u32 gtt_offset, |
| 2295 | u32 size); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2296 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2297 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2298 | /* i915_gem_tiling.c */ |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 2299 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 2300 | { |
| 2301 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
| 2302 | |
| 2303 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 2304 | obj->tiling_mode != I915_TILING_NONE; |
| 2305 | } |
| 2306 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2307 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2308 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 2309 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2310 | |
| 2311 | /* i915_gem_debug.c */ |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2312 | #if WATCH_LISTS |
| 2313 | int i915_verify_lists(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2314 | #else |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2315 | #define i915_verify_lists(dev) 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2316 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2317 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2318 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2319 | int i915_debugfs_init(struct drm_minor *minor); |
| 2320 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 2321 | #ifdef CONFIG_DEBUG_FS |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2322 | void intel_display_crc_init(struct drm_device *dev); |
| 2323 | #else |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 2324 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2325 | #endif |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 2326 | |
| 2327 | /* i915_gpu_error.c */ |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2328 | __printf(2, 3) |
| 2329 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 2330 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
| 2331 | const struct i915_error_state_file_priv *error); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 2332 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
| 2333 | size_t count, loff_t pos); |
| 2334 | static inline void i915_error_state_buf_release( |
| 2335 | struct drm_i915_error_state_buf *eb) |
| 2336 | { |
| 2337 | kfree(eb->buf); |
| 2338 | } |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 2339 | void i915_capture_error_state(struct drm_device *dev); |
| 2340 | void i915_error_state_get(struct drm_device *dev, |
| 2341 | struct i915_error_state_file_priv *error_priv); |
| 2342 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
| 2343 | void i915_destroy_error_state(struct drm_device *dev); |
| 2344 | |
| 2345 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
| 2346 | const char *i915_cache_level_str(int type); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2347 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 2348 | /* i915_suspend.c */ |
| 2349 | extern int i915_save_state(struct drm_device *dev); |
| 2350 | extern int i915_restore_state(struct drm_device *dev); |
| 2351 | |
Daniel Vetter | d8157a3 | 2013-01-25 17:53:20 +0100 | [diff] [blame] | 2352 | /* i915_ums.c */ |
| 2353 | void i915_save_display_reg(struct drm_device *dev); |
| 2354 | void i915_restore_display_reg(struct drm_device *dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2355 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 2356 | /* i915_sysfs.c */ |
| 2357 | void i915_setup_sysfs(struct drm_device *dev_priv); |
| 2358 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
| 2359 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2360 | /* intel_i2c.c */ |
| 2361 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 2362 | extern void intel_teardown_gmbus(struct drm_device *dev); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 2363 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 2364 | { |
Daniel Kurtz | 2ed06c9 | 2012-03-28 02:36:15 +0800 | [diff] [blame] | 2365 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 2366 | } |
| 2367 | |
| 2368 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
| 2369 | struct drm_i915_private *dev_priv, unsigned port); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2370 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 2371 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 2372 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
Chris Wilson | b8232e9 | 2010-09-28 16:41:32 +0100 | [diff] [blame] | 2373 | { |
| 2374 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 2375 | } |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2376 | extern void intel_i2c_reset(struct drm_device *dev); |
| 2377 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2378 | /* intel_opregion.c */ |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2379 | struct intel_encoder; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2380 | extern int intel_opregion_setup(struct drm_device *dev); |
| 2381 | #ifdef CONFIG_ACPI |
| 2382 | extern void intel_opregion_init(struct drm_device *dev); |
| 2383 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2384 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2385 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
| 2386 | bool enable); |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 2387 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
| 2388 | pci_power_t state); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 2389 | #else |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2390 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 2391 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2392 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2393 | static inline int |
| 2394 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
| 2395 | { |
| 2396 | return 0; |
| 2397 | } |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 2398 | static inline int |
| 2399 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
| 2400 | { |
| 2401 | return 0; |
| 2402 | } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 2403 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 2404 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 2405 | /* intel_acpi.c */ |
| 2406 | #ifdef CONFIG_ACPI |
| 2407 | extern void intel_register_dsm_handler(void); |
| 2408 | extern void intel_unregister_dsm_handler(void); |
| 2409 | #else |
| 2410 | static inline void intel_register_dsm_handler(void) { return; } |
| 2411 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 2412 | #endif /* CONFIG_ACPI */ |
| 2413 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2414 | /* modesetting */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 2415 | extern void intel_modeset_init_hw(struct drm_device *dev); |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 2416 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2417 | extern void intel_modeset_init(struct drm_device *dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 2418 | extern void intel_modeset_gem_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2419 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2420 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 2421 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 2422 | bool force_restore); |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 2423 | extern void i915_redisable_vga(struct drm_device *dev); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 2424 | extern bool intel_fbc_enabled(struct drm_device *dev); |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 2425 | extern void intel_disable_fbc(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2426 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 2427 | extern void intel_init_pch_refclk(struct drm_device *dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 2428 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2429 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
| 2430 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); |
| 2431 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2432 | extern void intel_detect_pch(struct drm_device *dev); |
| 2433 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 2434 | extern int intel_enable_rc6(const struct drm_device *dev); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 2435 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2436 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 2437 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
| 2438 | struct drm_file *file); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 2439 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
| 2440 | struct drm_file *file); |
Jesse Barnes | 575155a | 2012-03-28 13:39:37 -0700 | [diff] [blame] | 2441 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 2442 | /* overlay */ |
| 2443 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2444 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
| 2445 | struct intel_overlay_error_state *error); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 2446 | |
| 2447 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2448 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 2449 | struct drm_device *dev, |
| 2450 | struct intel_display_error_state *error); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 2451 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 2452 | /* On SNB platform, before reading ring registers forcewake bit |
| 2453 | * must be set to prevent GT core from power down and stale values being |
| 2454 | * returned. |
| 2455 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 2456 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
| 2457 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 2458 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 2459 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
| 2460 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 2461 | |
| 2462 | /* intel_sideband.c */ |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 2463 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
| 2464 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
| 2465 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 2466 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2467 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2468 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2469 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2470 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2471 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jesse Barnes | f341915 | 2013-11-04 11:52:44 -0800 | [diff] [blame] | 2472 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2473 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 2474 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2475 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2476 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
| 2477 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 2478 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 2479 | enum intel_sbi_destination destination); |
| 2480 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 2481 | enum intel_sbi_destination destination); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2482 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 2483 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
| 2484 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 2485 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 2486 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
| 2487 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); |
| 2488 | |
| 2489 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
| 2490 | (((reg) >= 0x2000 && (reg) < 0x4000) ||\ |
| 2491 | ((reg) >= 0x5000 && (reg) < 0x8000) ||\ |
| 2492 | ((reg) >= 0xB000 && (reg) < 0x12000) ||\ |
| 2493 | ((reg) >= 0x2E000 && (reg) < 0x30000)) |
| 2494 | |
| 2495 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ |
| 2496 | (((reg) >= 0x12000 && (reg) < 0x14000) ||\ |
| 2497 | ((reg) >= 0x22000 && (reg) < 0x24000) ||\ |
| 2498 | ((reg) >= 0x30000 && (reg) < 0x40000)) |
| 2499 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 2500 | #define FORCEWAKE_RENDER (1 << 0) |
| 2501 | #define FORCEWAKE_MEDIA (1 << 1) |
| 2502 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) |
| 2503 | |
| 2504 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2505 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
| 2506 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2507 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2508 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
| 2509 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
| 2510 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
| 2511 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2512 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2513 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
| 2514 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
| 2515 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
| 2516 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2517 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2518 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
| 2519 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2520 | |
| 2521 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 2522 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 2523 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2524 | /* "Broadcast RGB" property */ |
| 2525 | #define INTEL_BROADCAST_RGB_AUTO 0 |
| 2526 | #define INTEL_BROADCAST_RGB_FULL 1 |
| 2527 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 2528 | |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 2529 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
| 2530 | { |
| 2531 | if (HAS_PCH_SPLIT(dev)) |
| 2532 | return CPU_VGACNTRL; |
| 2533 | else if (IS_VALLEYVIEW(dev)) |
| 2534 | return VLV_VGACNTRL; |
| 2535 | else |
| 2536 | return VGACNTRL; |
| 2537 | } |
| 2538 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 2539 | static inline void __user *to_user_ptr(u64 address) |
| 2540 | { |
| 2541 | return (void __user *)(uintptr_t)address; |
| 2542 | } |
| 2543 | |
Imre Deak | df97729 | 2013-05-21 20:03:17 +0300 | [diff] [blame] | 2544 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
| 2545 | { |
| 2546 | unsigned long j = msecs_to_jiffies(m); |
| 2547 | |
| 2548 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2549 | } |
| 2550 | |
| 2551 | static inline unsigned long |
| 2552 | timespec_to_jiffies_timeout(const struct timespec *value) |
| 2553 | { |
| 2554 | unsigned long j = timespec_to_jiffies(value); |
| 2555 | |
| 2556 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2557 | } |
| 2558 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2559 | #endif |