Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/io.h> |
| 15 | #include "kgsl.h" |
| 16 | #include "adreno.h" |
| 17 | #include "kgsl_snapshot.h" |
| 18 | #include "a4xx_reg.h" |
| 19 | #include "adreno_snapshot.h" |
| 20 | #include "adreno_a4xx.h" |
| 21 | |
| 22 | /* |
| 23 | * Set of registers to dump for A4XX on snapshot. |
| 24 | * Registers in pairs - first value is the start offset, second |
| 25 | * is the stop offset (inclusive) |
| 26 | */ |
| 27 | |
| 28 | static const unsigned int a4xx_registers[] = { |
| 29 | /* RBBM */ |
| 30 | 0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026, |
| 31 | 0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066, |
| 32 | 0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF, |
| 33 | /* CP */ |
| 34 | 0x0200, 0x0226, 0x0228, 0x0233, 0x0240, 0x0258, 0x04C0, 0x04D0, |
| 35 | 0x04D2, 0x04DD, 0x0500, 0x050B, 0x0578, 0x058F, |
| 36 | /* VSC */ |
| 37 | 0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51, |
| 38 | /* GRAS */ |
| 39 | 0x0C80, 0x0C81, 0x0C88, 0x0C8F, |
| 40 | /* RB */ |
| 41 | 0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2, |
| 42 | /* PC */ |
| 43 | 0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23, |
| 44 | /* VFD */ |
| 45 | 0x0E40, 0x0E4A, |
| 46 | /* VPC */ |
| 47 | 0x0E60, 0x0E61, 0x0E63, 0x0E68, |
| 48 | /* UCHE */ |
| 49 | 0x0E80, 0x0E84, 0x0E88, 0x0E95, |
| 50 | /* GRAS CTX 0 */ |
| 51 | 0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E, |
| 52 | /* PC CTX 0 */ |
| 53 | 0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7, |
| 54 | /* VFD CTX 0 */ |
| 55 | 0x2200, 0x2204, 0x2208, 0x22A9, |
| 56 | /* GRAS CTX 1 */ |
| 57 | 0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E, |
| 58 | /* PC CTX 1 */ |
| 59 | 0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7, |
| 60 | /* VFD CTX 1 */ |
| 61 | 0x2600, 0x2604, 0x2608, 0x26A9, |
| 62 | }; |
| 63 | |
| 64 | static const unsigned int a4xx_sp_tp_registers[] = { |
| 65 | /* SP */ |
| 66 | 0x0EC0, 0x0ECF, |
| 67 | /* TPL1 */ |
| 68 | 0x0F00, 0x0F0B, |
| 69 | /* SP CTX 0 */ |
| 70 | 0x22C0, 0x22C1, 0x22C4, 0x22E5, 0x22E8, 0x22F8, 0x2300, 0x2306, |
| 71 | 0x230C, 0x2312, 0x2318, 0x2339, 0x2340, 0x2360, |
| 72 | /* TPL1 CTX 0 */ |
| 73 | 0x2380, 0x2382, 0x2384, 0x238F, 0x23A0, 0x23A6, |
| 74 | /* SP CTX 1 */+ |
| 75 | 0x26C0, 0x26C1, 0x26C4, 0x26E5, 0x26E8, 0x26F8, 0x2700, 0x2706, |
| 76 | 0x270C, 0x2712, 0x2718, 0x2739, 0x2740, 0x2760, |
| 77 | /* TPL1 CTX 1 */ |
| 78 | 0x2780, 0x2782, 0x2784, 0x278F, 0x27A0, 0x27A6, |
| 79 | }; |
| 80 | |
| 81 | static const unsigned int a4xx_ppd_registers[] = { |
| 82 | /* V2 Thresholds */ |
| 83 | 0x01B2, 0x01B5, |
| 84 | /* Control and Status */ |
| 85 | 0x01B9, 0x01BE, |
| 86 | }; |
| 87 | |
| 88 | static const unsigned int a4xx_xpu_registers[] = { |
| 89 | /* XPU */ |
| 90 | 0x2C00, 0x2C01, 0x2C10, 0x2C10, 0x2C12, 0x2C16, 0x2C1D, 0x2C20, |
| 91 | 0x2C28, 0x2C28, 0x2C30, 0x2C30, 0x2C32, 0x2C36, 0x2C40, 0x2C40, |
| 92 | 0x2C50, 0x2C50, 0x2C52, 0x2C56, 0x2C80, 0x2C80, 0x2C94, 0x2C95, |
| 93 | }; |
| 94 | |
| 95 | static const unsigned int a4xx_vbif_ver_20000000_registers[] = { |
| 96 | /* VBIF version 0x20000000 & IOMMU V1 */ |
| 97 | 0x3000, 0x3007, 0x300C, 0x3014, 0x3018, 0x301D, 0x3020, 0x3022, |
| 98 | 0x3024, 0x3026, 0x3028, 0x302A, 0x302C, 0x302D, 0x3030, 0x3031, |
| 99 | 0x3034, 0x3036, 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, |
| 100 | 0x3049, 0x3049, 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, |
| 101 | 0x306C, 0x306D, 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, |
| 102 | 0x3098, 0x3098, 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, |
| 103 | 0x30D0, 0x30D0, 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, |
| 104 | 0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, |
| 105 | 0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x330C, 0x330C, |
| 106 | 0x3310, 0x3310, 0x3400, 0x3401, 0x3410, 0x3410, 0x3412, 0x3416, |
| 107 | 0x341D, 0x3420, 0x3428, 0x3428, 0x3430, 0x3430, 0x3432, 0x3436, |
| 108 | 0x3440, 0x3440, 0x3450, 0x3450, 0x3452, 0x3456, 0x3480, 0x3480, |
| 109 | 0x3494, 0x3495, 0x4000, 0x4000, 0x4002, 0x4002, 0x4004, 0x4004, |
| 110 | 0x4008, 0x400A, 0x400C, 0x400D, 0x400F, 0x4012, 0x4014, 0x4016, |
| 111 | 0x401D, 0x401D, 0x4020, 0x4027, 0x4060, 0x4062, 0x4200, 0x4200, |
| 112 | 0x4300, 0x4300, 0x4400, 0x4400, 0x4500, 0x4500, 0x4800, 0x4802, |
| 113 | 0x480F, 0x480F, 0x4811, 0x4811, 0x4813, 0x4813, 0x4815, 0x4816, |
| 114 | 0x482B, 0x482B, 0x4857, 0x4857, 0x4883, 0x4883, 0x48AF, 0x48AF, |
| 115 | 0x48C5, 0x48C5, 0x48E5, 0x48E5, 0x4905, 0x4905, 0x4925, 0x4925, |
| 116 | 0x4945, 0x4945, 0x4950, 0x4950, 0x495B, 0x495B, 0x4980, 0x498E, |
| 117 | 0x4B00, 0x4B00, 0x4C00, 0x4C00, 0x4D00, 0x4D00, 0x4E00, 0x4E00, |
| 118 | 0x4E80, 0x4E80, 0x4F00, 0x4F00, 0x4F08, 0x4F08, 0x4F10, 0x4F10, |
| 119 | 0x4F18, 0x4F18, 0x4F20, 0x4F20, 0x4F30, 0x4F30, 0x4F60, 0x4F60, |
| 120 | 0x4F80, 0x4F81, 0x4F88, 0x4F89, 0x4FEE, 0x4FEE, 0x4FF3, 0x4FF3, |
| 121 | 0x6000, 0x6001, 0x6008, 0x600F, 0x6014, 0x6016, 0x6018, 0x601B, |
| 122 | 0x61FD, 0x61FD, 0x623C, 0x623C, 0x6380, 0x6380, 0x63A0, 0x63A0, |
| 123 | 0x63C0, 0x63C1, 0x63C8, 0x63C9, 0x63D0, 0x63D4, 0x63D6, 0x63D6, |
| 124 | 0x63EE, 0x63EE, 0x6400, 0x6401, 0x6408, 0x640F, 0x6414, 0x6416, |
| 125 | 0x6418, 0x641B, 0x65FD, 0x65FD, 0x663C, 0x663C, 0x6780, 0x6780, |
| 126 | 0x67A0, 0x67A0, 0x67C0, 0x67C1, 0x67C8, 0x67C9, 0x67D0, 0x67D4, |
| 127 | 0x67D6, 0x67D6, 0x67EE, 0x67EE, |
| 128 | }; |
| 129 | |
| 130 | static const unsigned int a4xx_vbif_ver_20020000_registers[] = { |
| 131 | 0x3000, 0x3007, 0x300C, 0x3014, 0x3018, 0x301D, 0x3020, 0x3022, |
| 132 | 0x3024, 0x3026, 0x3028, 0x302A, 0x302C, 0x302D, 0x3030, 0x3031, |
| 133 | 0x3034, 0x3036, 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, |
| 134 | 0x3049, 0x3049, 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, |
| 135 | 0x306C, 0x306D, 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, |
| 136 | 0x3098, 0x3098, 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, |
| 137 | 0x30D0, 0x30D0, 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, |
| 138 | 0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, |
| 139 | 0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x4800, 0x4802, |
| 140 | 0x480F, 0x480F, 0x4811, 0x4811, 0x4813, 0x4813, 0x4815, 0x4816, |
| 141 | 0x482B, 0x482B, 0x4857, 0x4857, 0x4883, 0x4883, 0x48AF, 0x48AF, |
| 142 | 0x48C5, 0x48C5, 0x48E5, 0x48E5, 0x4905, 0x4905, 0x4925, 0x4925, |
| 143 | 0x4945, 0x4945, 0x4950, 0x4950, 0x495B, 0x495B, 0x4980, 0x498E, |
| 144 | 0x4C00, 0x4C00, 0x4D00, 0x4D00, 0x4E00, 0x4E00, 0x4E80, 0x4E80, |
| 145 | 0x4F00, 0x4F00, 0x4F08, 0x4F08, 0x4F10, 0x4F10, 0x4F18, 0x4F18, |
| 146 | 0x4F20, 0x4F20, 0x4F30, 0x4F30, 0x4F60, 0x4F60, 0x4F80, 0x4F81, |
| 147 | 0x4F88, 0x4F89, 0x4FEE, 0x4FEE, 0x4FF3, 0x4FF3, 0x6000, 0x6001, |
| 148 | 0x6008, 0x600F, 0x6014, 0x6016, 0x6018, 0x601B, 0x61FD, 0x61FD, |
| 149 | 0x623C, 0x623C, 0x6380, 0x6380, 0x63A0, 0x63A0, 0x63C0, 0x63C1, |
| 150 | 0x63C8, 0x63C9, 0x63D0, 0x63D4, 0x63D6, 0x63D6, 0x63EE, 0x63EE, |
| 151 | 0x6400, 0x6401, 0x6408, 0x640F, 0x6414, 0x6416, 0x6418, 0x641B, |
| 152 | 0x65FD, 0x65FD, 0x663C, 0x663C, 0x6780, 0x6780, 0x67A0, 0x67A0, |
| 153 | 0x67C0, 0x67C1, 0x67C8, 0x67C9, 0x67D0, 0x67D4, 0x67D6, 0x67D6, |
| 154 | 0x67EE, 0x67EE, |
| 155 | }; |
| 156 | |
| 157 | static const unsigned int a4xx_vbif_ver_20050000_registers[] = { |
| 158 | /* VBIF version 0x20050000 and 0x20090000 */ |
| 159 | 0x3000, 0x3007, 0x302C, 0x302C, 0x3030, 0x3030, 0x3034, 0x3036, |
| 160 | 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, 0x3049, 0x3049, |
| 161 | 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, 0x306C, 0x306D, |
| 162 | 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, 0x3098, 0x3098, |
| 163 | 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, 0x30D0, 0x30D0, |
| 164 | 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, 0x3108, 0x3108, |
| 165 | 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, 0x3124, 0x3125, |
| 166 | 0x3129, 0x3129, 0x340C, 0x340C, 0x3410, 0x3410, |
| 167 | }; |
| 168 | |
| 169 | static const struct adreno_vbif_snapshot_registers |
| 170 | a4xx_vbif_snapshot_registers[] = { |
| 171 | { 0x20000000, 0xFFFF0000, a4xx_vbif_ver_20000000_registers, |
| 172 | ARRAY_SIZE(a4xx_vbif_ver_20000000_registers)/2}, |
| 173 | { 0x20020000, 0xFFFF0000, a4xx_vbif_ver_20020000_registers, |
| 174 | ARRAY_SIZE(a4xx_vbif_ver_20020000_registers)/2}, |
| 175 | { 0x20050000, 0xFFFF0000, a4xx_vbif_ver_20050000_registers, |
| 176 | ARRAY_SIZE(a4xx_vbif_ver_20050000_registers)/2}, |
| 177 | { 0x20070000, 0xFFFF0000, a4xx_vbif_ver_20020000_registers, |
| 178 | ARRAY_SIZE(a4xx_vbif_ver_20020000_registers)/2}, |
| 179 | { 0x20090000, 0xFFFF0000, a4xx_vbif_ver_20050000_registers, |
| 180 | ARRAY_SIZE(a4xx_vbif_ver_20050000_registers)/2}, |
| 181 | }; |
| 182 | |
| 183 | #define A4XX_NUM_SHADER_BANKS 4 |
| 184 | #define A405_NUM_SHADER_BANKS 1 |
| 185 | /* Shader memory size in words */ |
| 186 | #define A4XX_SHADER_MEMORY_SIZE 0x4000 |
| 187 | |
| 188 | static const struct adreno_debugbus_block a4xx_debugbus_blocks[] = { |
| 189 | { A4XX_RBBM_DEBBUS_CP_ID, 0x100, }, |
| 190 | { A4XX_RBBM_DEBBUS_RBBM_ID, 0x100, }, |
| 191 | { A4XX_RBBM_DEBBUS_VBIF_ID, 0x100, }, |
| 192 | { A4XX_RBBM_DEBBUS_HLSQ_ID, 0x100, }, |
| 193 | { A4XX_RBBM_DEBBUS_UCHE_ID, 0x100, }, |
| 194 | { A4XX_RBBM_DEBBUS_DPM_ID, 0x100, }, |
| 195 | { A4XX_RBBM_DEBBUS_TESS_ID, 0x100, }, |
| 196 | { A4XX_RBBM_DEBBUS_PC_ID, 0x100, }, |
| 197 | { A4XX_RBBM_DEBBUS_VFD_ID, 0x100, }, |
| 198 | { A4XX_RBBM_DEBBUS_VPC_ID, 0x100, }, |
| 199 | { A4XX_RBBM_DEBBUS_TSE_ID, 0x100, }, |
| 200 | { A4XX_RBBM_DEBBUS_RAS_ID, 0x100, }, |
| 201 | { A4XX_RBBM_DEBBUS_VSC_ID, 0x100, }, |
| 202 | { A4XX_RBBM_DEBBUS_COM_ID, 0x100, }, |
| 203 | { A4XX_RBBM_DEBBUS_DCOM_ID, 0x100, }, |
| 204 | { A4XX_RBBM_DEBBUS_SP_0_ID, 0x100, }, |
| 205 | { A4XX_RBBM_DEBBUS_TPL1_0_ID, 0x100, }, |
| 206 | { A4XX_RBBM_DEBBUS_RB_0_ID, 0x100, }, |
| 207 | { A4XX_RBBM_DEBBUS_MARB_0_ID, 0x100 }, |
| 208 | }; |
| 209 | |
| 210 | static const struct adreno_debugbus_block a420_debugbus_blocks[] = { |
| 211 | { A4XX_RBBM_DEBBUS_SP_1_ID, 0x100, }, |
| 212 | { A4XX_RBBM_DEBBUS_SP_2_ID, 0x100, }, |
| 213 | { A4XX_RBBM_DEBBUS_SP_3_ID, 0x100, }, |
| 214 | { A4XX_RBBM_DEBBUS_TPL1_1_ID, 0x100, }, |
| 215 | { A4XX_RBBM_DEBBUS_TPL1_2_ID, 0x100, }, |
| 216 | { A4XX_RBBM_DEBBUS_TPL1_3_ID, 0x100, }, |
| 217 | { A4XX_RBBM_DEBBUS_RB_1_ID, 0x100, }, |
| 218 | { A4XX_RBBM_DEBBUS_RB_2_ID, 0x100, }, |
| 219 | { A4XX_RBBM_DEBBUS_RB_3_ID, 0x100, }, |
| 220 | { A4XX_RBBM_DEBBUS_MARB_1_ID, 0x100, }, |
| 221 | { A4XX_RBBM_DEBBUS_MARB_2_ID, 0x100, }, |
| 222 | { A4XX_RBBM_DEBBUS_MARB_3_ID, 0x100, }, |
| 223 | { A4XX_RBBM_DEBBUS_CCU_0_ID, 0x100, }, |
| 224 | { A4XX_RBBM_DEBBUS_CCU_1_ID, 0x100, }, |
| 225 | { A4XX_RBBM_DEBBUS_CCU_2_ID, 0x100, }, |
| 226 | { A4XX_RBBM_DEBBUS_CCU_3_ID, 0x100, }, |
| 227 | }; |
| 228 | |
| 229 | /** |
| 230 | * a4xx_snapshot_shader_memory - Helper function to dump the GPU shader |
| 231 | * memory to the snapshot buffer. |
| 232 | * @device: GPU device whose shader memory is to be dumped |
| 233 | * @buf: Pointer to binary snapshot data blob being made |
| 234 | * @remain: Number of remaining bytes in the snapshot blob |
| 235 | * @priv: Unused parameter |
| 236 | * |
| 237 | */ |
| 238 | static size_t a4xx_snapshot_shader_memory(struct kgsl_device *device, |
| 239 | u8 *buf, size_t remain, void *priv) |
| 240 | { |
| 241 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 242 | struct kgsl_snapshot_debug *header = (struct kgsl_snapshot_debug *)buf; |
| 243 | unsigned int i, j; |
| 244 | unsigned int *data = (unsigned int *)(buf + sizeof(*header)); |
| 245 | unsigned int shader_read_len = A4XX_SHADER_MEMORY_SIZE; |
| 246 | unsigned int shader_banks = A4XX_NUM_SHADER_BANKS; |
| 247 | |
| 248 | if (shader_read_len > (device->shader_mem_len >> 2)) |
| 249 | shader_read_len = (device->shader_mem_len >> 2); |
| 250 | |
| 251 | if (adreno_is_a405(adreno_dev)) |
| 252 | shader_banks = A405_NUM_SHADER_BANKS; |
| 253 | |
| 254 | if (remain < DEBUG_SECTION_SZ(shader_read_len * |
| 255 | shader_banks)) { |
| 256 | SNAPSHOT_ERR_NOMEM(device, "SHADER MEMORY"); |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | header->type = SNAPSHOT_DEBUG_SHADER_MEMORY; |
| 261 | header->size = shader_read_len * shader_banks; |
| 262 | |
| 263 | /* Map shader memory to kernel, for dumping */ |
| 264 | if (device->shader_mem_virt == NULL) |
| 265 | device->shader_mem_virt = devm_ioremap(device->dev, |
| 266 | device->shader_mem_phys, |
| 267 | device->shader_mem_len); |
| 268 | |
| 269 | if (device->shader_mem_virt == NULL) { |
| 270 | KGSL_DRV_ERR(device, |
| 271 | "Unable to map shader memory region\n"); |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | for (j = 0; j < shader_banks; j++) { |
| 276 | unsigned int val; |
| 277 | /* select the SPTP */ |
| 278 | kgsl_regread(device, A4XX_HLSQ_SPTP_RDSEL, &val); |
| 279 | val &= ~0x3; |
| 280 | val |= j; |
| 281 | kgsl_regwrite(device, A4XX_HLSQ_SPTP_RDSEL, val); |
| 282 | /* Now, dump shader memory to snapshot */ |
| 283 | for (i = 0; i < shader_read_len; i++) |
| 284 | adreno_shadermem_regread(device, i, |
| 285 | &data[i + j * shader_read_len]); |
| 286 | } |
| 287 | |
| 288 | |
| 289 | return DEBUG_SECTION_SZ(shader_read_len * shader_banks); |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * a4xx_rbbm_debug_bus_read() - Read data from trace bus |
| 294 | * @device: Device whose data bus is read |
| 295 | * @block_id: Trace bus block ID |
| 296 | * @index: Index of data to read |
| 297 | * @val: Output parameter where data is read |
| 298 | */ |
| 299 | static void a4xx_rbbm_debug_bus_read(struct kgsl_device *device, |
| 300 | unsigned int block_id, unsigned int index, unsigned int *val) |
| 301 | { |
| 302 | unsigned int reg = 0; |
| 303 | |
| 304 | reg |= (block_id << A4XX_RBBM_CFG_DEBBUS_SEL_PING_BLK_SEL_SHIFT); |
| 305 | reg |= (index << A4XX_RBBM_CFG_DEBBUS_SEL_PING_INDEX_SHIFT); |
| 306 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_SEL_A, reg); |
| 307 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_SEL_B, reg); |
| 308 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_SEL_C, reg); |
| 309 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_SEL_D, reg); |
| 310 | |
| 311 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_IDX, 0x3020000); |
| 312 | kgsl_regread(device, A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4, val); |
| 313 | val++; |
| 314 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_IDX, 0x1000000); |
| 315 | kgsl_regread(device, A4XX_RBBM_CFG_DEBBUS_TRACE_BUF4, val); |
| 316 | } |
| 317 | |
| 318 | /* |
| 319 | * a4xx_snapshot_vbif_debugbus() - Dump the VBIF debug data |
| 320 | * @device: Device pointer for which the debug data is dumped |
| 321 | * @buf: Pointer to the memory where the data is dumped |
| 322 | * @remain: Amount of bytes remaining in snapshot |
| 323 | * @priv: Pointer to debug bus block |
| 324 | * |
| 325 | * Returns the number of bytes dumped |
| 326 | */ |
| 327 | static size_t a4xx_snapshot_vbif_debugbus(struct kgsl_device *device, |
| 328 | u8 *buf, size_t remain, void *priv) |
| 329 | { |
| 330 | struct kgsl_snapshot_debugbus *header = |
| 331 | (struct kgsl_snapshot_debugbus *)buf; |
| 332 | struct adreno_debugbus_block *block = priv; |
| 333 | int i, j; |
| 334 | /* |
| 335 | * Total number of VBIF data words considering 3 sections: |
| 336 | * 2 arbiter blocks of 16 words |
| 337 | * 5 AXI XIN blocks of 4 dwords each |
| 338 | * 5 core clock side XIN blocks of 5 dwords each |
| 339 | */ |
| 340 | unsigned int dwords = (16 * A4XX_NUM_AXI_ARB_BLOCKS) + |
| 341 | (4 * A4XX_NUM_XIN_BLOCKS) + (5 * A4XX_NUM_XIN_BLOCKS); |
| 342 | unsigned int *data = (unsigned int *)(buf + sizeof(*header)); |
| 343 | size_t size; |
| 344 | unsigned int reg_clk; |
| 345 | |
| 346 | size = (dwords * sizeof(unsigned int)) + sizeof(*header); |
| 347 | |
| 348 | if (remain < size) { |
| 349 | SNAPSHOT_ERR_NOMEM(device, "DEBUGBUS"); |
| 350 | return 0; |
| 351 | } |
| 352 | header->id = block->block_id; |
| 353 | header->count = dwords; |
| 354 | |
| 355 | kgsl_regread(device, A4XX_VBIF_CLKON, ®_clk); |
| 356 | kgsl_regwrite(device, A4XX_VBIF_CLKON, reg_clk | |
| 357 | (A4XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK << |
| 358 | A4XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT)); |
| 359 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS1_CTRL0, 0); |
| 360 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS_OUT_CTRL, |
| 361 | (A4XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK << |
| 362 | A4XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT)); |
| 363 | for (i = 0; i < A4XX_NUM_AXI_ARB_BLOCKS; i++) { |
| 364 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS2_CTRL0, |
| 365 | (1 << (i + 16))); |
| 366 | for (j = 0; j < 16; j++) { |
| 367 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS2_CTRL1, |
| 368 | ((j & A4XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK) |
| 369 | << A4XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT)); |
| 370 | kgsl_regread(device, A4XX_VBIF_TEST_BUS_OUT, |
| 371 | data); |
| 372 | data++; |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | /* XIN blocks AXI side */ |
| 377 | for (i = 0; i < A4XX_NUM_XIN_BLOCKS; i++) { |
| 378 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS2_CTRL0, 1 << i); |
| 379 | for (j = 0; j < 4; j++) { |
| 380 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS2_CTRL1, |
| 381 | ((j & A4XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK) |
| 382 | << A4XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT)); |
| 383 | kgsl_regread(device, A4XX_VBIF_TEST_BUS_OUT, |
| 384 | data); |
| 385 | data++; |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | /* XIN blocks core clock side */ |
| 390 | for (i = 0; i < A4XX_NUM_XIN_BLOCKS; i++) { |
| 391 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS1_CTRL0, 1 << i); |
| 392 | for (j = 0; j < 5; j++) { |
| 393 | kgsl_regwrite(device, A4XX_VBIF_TEST_BUS1_CTRL1, |
| 394 | ((j & A4XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK) |
| 395 | << A4XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT)); |
| 396 | kgsl_regread(device, A4XX_VBIF_TEST_BUS_OUT, |
| 397 | data); |
| 398 | data++; |
| 399 | } |
| 400 | } |
| 401 | /* restore the clock of VBIF */ |
| 402 | kgsl_regwrite(device, A4XX_VBIF_CLKON, reg_clk); |
| 403 | return size; |
| 404 | } |
| 405 | |
| 406 | /* |
| 407 | * a4xx_snapshot_debugbus_block() - Capture debug data for a gpu block |
| 408 | * @device: Pointer to device |
| 409 | * @buf: Memory where data is captured |
| 410 | * @remain: Number of bytes left in snapshot |
| 411 | * @priv: Pointer to debug bus block |
| 412 | * |
| 413 | * Returns the number of bytes written |
| 414 | */ |
| 415 | static size_t a4xx_snapshot_debugbus_block(struct kgsl_device *device, |
| 416 | u8 *buf, size_t remain, void *priv) |
| 417 | { |
| 418 | struct kgsl_snapshot_debugbus *header = |
| 419 | (struct kgsl_snapshot_debugbus *)buf; |
| 420 | struct adreno_debugbus_block *block = priv; |
| 421 | int i; |
| 422 | unsigned int *data = (unsigned int *)(buf + sizeof(*header)); |
| 423 | unsigned int dwords; |
| 424 | size_t size; |
| 425 | |
| 426 | dwords = block->dwords; |
| 427 | |
| 428 | /* For a4xx each debug bus data unit is 2 DWRODS */ |
| 429 | size = (dwords * sizeof(unsigned int) * 2) + sizeof(*header); |
| 430 | |
| 431 | if (remain < size) { |
| 432 | SNAPSHOT_ERR_NOMEM(device, "DEBUGBUS"); |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | header->id = block->block_id; |
| 437 | header->count = dwords * 2; |
| 438 | |
| 439 | for (i = 0; i < dwords; i++) |
| 440 | a4xx_rbbm_debug_bus_read(device, block->block_id, i, |
| 441 | &data[i*2]); |
| 442 | |
| 443 | return size; |
| 444 | } |
| 445 | |
| 446 | /* |
| 447 | * a4xx_snapshot_debugbus() - Capture debug bus data |
| 448 | * @device: The device for which data is captured |
| 449 | * @snapshot: Pointer to the snapshot instance |
| 450 | */ |
| 451 | static void a4xx_snapshot_debugbus(struct kgsl_device *device, |
| 452 | struct kgsl_snapshot *snapshot) |
| 453 | { |
| 454 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 455 | int i; |
| 456 | |
| 457 | kgsl_regwrite(device, A4XX_RBBM_CFG_DEBBUS_CTLM, |
| 458 | 0xf << A4XX_RBBM_CFG_DEBBUS_CTLT_ENABLE_SHIFT); |
| 459 | |
| 460 | for (i = 0; i < ARRAY_SIZE(a4xx_debugbus_blocks); i++) { |
| 461 | if (A4XX_RBBM_DEBBUS_VBIF_ID == |
| 462 | a4xx_debugbus_blocks[i].block_id) |
| 463 | kgsl_snapshot_add_section(device, |
| 464 | KGSL_SNAPSHOT_SECTION_DEBUGBUS, |
| 465 | snapshot, a4xx_snapshot_vbif_debugbus, |
| 466 | (void *) &a4xx_debugbus_blocks[i]); |
| 467 | else |
| 468 | kgsl_snapshot_add_section(device, |
| 469 | KGSL_SNAPSHOT_SECTION_DEBUGBUS, |
| 470 | snapshot, a4xx_snapshot_debugbus_block, |
| 471 | (void *) &a4xx_debugbus_blocks[i]); |
| 472 | } |
| 473 | |
| 474 | if (!adreno_is_a405(adreno_dev)) { |
| 475 | for (i = 0; i < ARRAY_SIZE(a420_debugbus_blocks); i++) |
| 476 | kgsl_snapshot_add_section(device, |
| 477 | KGSL_SNAPSHOT_SECTION_DEBUGBUS, |
| 478 | snapshot, a4xx_snapshot_debugbus_block, |
| 479 | (void *) &a420_debugbus_blocks[i]); |
| 480 | |
| 481 | } |
| 482 | } |
| 483 | |
| 484 | static void a4xx_reset_hlsq(struct kgsl_device *device) |
| 485 | { |
| 486 | unsigned int val, dummy = 0; |
| 487 | |
| 488 | /* reset cp */ |
| 489 | kgsl_regwrite(device, A4XX_RBBM_BLOCK_SW_RESET_CMD, 1 << 20); |
| 490 | kgsl_regread(device, A4XX_RBBM_BLOCK_SW_RESET_CMD, &dummy); |
| 491 | |
| 492 | /* reset hlsq */ |
| 493 | kgsl_regwrite(device, A4XX_RBBM_BLOCK_SW_RESET_CMD, 1 << 25); |
| 494 | kgsl_regread(device, A4XX_RBBM_BLOCK_SW_RESET_CMD, &dummy); |
| 495 | |
| 496 | /* clear reset bits */ |
| 497 | kgsl_regwrite(device, A4XX_RBBM_BLOCK_SW_RESET_CMD, 0); |
| 498 | kgsl_regread(device, A4XX_RBBM_BLOCK_SW_RESET_CMD, &dummy); |
| 499 | |
| 500 | |
| 501 | /* set HLSQ_TIMEOUT_THRESHOLD.cycle_timeout_limit_sp to 26 */ |
| 502 | kgsl_regread(device, A4XX_HLSQ_TIMEOUT_THRESHOLD, &val); |
| 503 | val &= (0x1F << 24); |
| 504 | val |= (26 << 24); |
| 505 | kgsl_regwrite(device, A4XX_HLSQ_TIMEOUT_THRESHOLD, val); |
| 506 | } |
| 507 | |
| 508 | /* |
| 509 | * a4xx_snapshot() - A4XX GPU snapshot function |
| 510 | * @adreno_dev: Device being snapshotted |
| 511 | * @snapshot: Pointer to the snapshot instance |
| 512 | * |
| 513 | * This is where all of the A4XX specific bits and pieces are grabbed |
| 514 | * into the snapshot memory |
| 515 | */ |
| 516 | void a4xx_snapshot(struct adreno_device *adreno_dev, |
| 517 | struct kgsl_snapshot *snapshot) |
| 518 | { |
| 519 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 520 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 521 | struct adreno_snapshot_data *snap_data = gpudev->snapshot_data; |
| 522 | |
| 523 | /* Disable SP clock gating for the debug bus to work */ |
| 524 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP0, 0); |
| 525 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP1, 0); |
| 526 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP2, 0); |
| 527 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP3, 0); |
| 528 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP0, 0); |
| 529 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP1, 0); |
| 530 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP2, 0); |
| 531 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP3, 0); |
| 532 | |
| 533 | /* Disable top level clock gating the debug bus to work */ |
| 534 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0); |
| 535 | kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2, 0); |
| 536 | |
| 537 | /* Master set of (non debug) registers */ |
| 538 | |
| 539 | SNAPSHOT_REGISTERS(device, snapshot, a4xx_registers); |
| 540 | |
| 541 | if (adreno_is_a430(adreno_dev)) |
| 542 | SNAPSHOT_REGISTERS(device, snapshot, a4xx_sp_tp_registers); |
| 543 | |
| 544 | if (adreno_is_a420(adreno_dev)) |
| 545 | SNAPSHOT_REGISTERS(device, snapshot, a4xx_xpu_registers); |
| 546 | |
| 547 | if (adreno_is_a430v2(adreno_dev)) |
| 548 | SNAPSHOT_REGISTERS(device, snapshot, a4xx_ppd_registers); |
| 549 | |
| 550 | adreno_snapshot_vbif_registers(device, snapshot, |
| 551 | a4xx_vbif_snapshot_registers, |
| 552 | ARRAY_SIZE(a4xx_vbif_snapshot_registers)); |
| 553 | |
| 554 | kgsl_snapshot_indexed_registers(device, snapshot, |
| 555 | A4XX_CP_STATE_DEBUG_INDEX, A4XX_CP_STATE_DEBUG_DATA, |
| 556 | 0, snap_data->sect_sizes->cp_pfp); |
| 557 | |
| 558 | /* CP_ME indexed registers */ |
| 559 | kgsl_snapshot_indexed_registers(device, snapshot, |
| 560 | A4XX_CP_ME_CNTL, A4XX_CP_ME_STATUS, 64, 44); |
| 561 | |
| 562 | /* VPC memory */ |
| 563 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 564 | snapshot, adreno_snapshot_vpc_memory, |
| 565 | &snap_data->sect_sizes->vpc_mem); |
| 566 | |
| 567 | /* CP MEQ */ |
| 568 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 569 | snapshot, adreno_snapshot_cp_meq, |
| 570 | &snap_data->sect_sizes->cp_meq); |
| 571 | |
| 572 | /* CP PFP and PM4 */ |
| 573 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 574 | snapshot, adreno_snapshot_cp_pfp_ram, NULL); |
| 575 | |
| 576 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 577 | snapshot, adreno_snapshot_cp_pm4_ram, NULL); |
| 578 | |
| 579 | /* CP ROQ */ |
| 580 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 581 | snapshot, adreno_snapshot_cp_roq, |
| 582 | &snap_data->sect_sizes->roq); |
| 583 | |
| 584 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 585 | snapshot, adreno_snapshot_cp_merciu, |
| 586 | &snap_data->sect_sizes->cp_merciu); |
| 587 | |
| 588 | /* Debug bus */ |
| 589 | a4xx_snapshot_debugbus(device, snapshot); |
| 590 | |
| 591 | if (!adreno_is_a430(adreno_dev)) { |
| 592 | a4xx_reset_hlsq(device); |
| 593 | SNAPSHOT_REGISTERS(device, snapshot, a4xx_sp_tp_registers); |
| 594 | } |
| 595 | |
| 596 | /* Shader working/shadow memory */ |
| 597 | kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, |
| 598 | snapshot, a4xx_snapshot_shader_memory, |
| 599 | &snap_data->sect_sizes->shader_mem); |
| 600 | } |