Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | #include <asm/atomic.h> |
| 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
| 72 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 73 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 74 | #include "radeon_mode.h" |
| 75 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Modules parameters. |
| 79 | */ |
| 80 | extern int radeon_no_wb; |
| 81 | extern int radeon_modeset; |
| 82 | extern int radeon_dynclks; |
| 83 | extern int radeon_r4xx_atom; |
| 84 | extern int radeon_agpmode; |
| 85 | extern int radeon_vram_limit; |
| 86 | extern int radeon_gart_size; |
| 87 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 88 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 90 | extern int radeon_tv; |
Alex Deucher | b27b637 | 2009-12-09 17:44:25 -0500 | [diff] [blame] | 91 | extern int radeon_new_pll; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 92 | extern int radeon_dynpm; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 93 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 94 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 95 | extern int radeon_hw_i2c; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 99 | * symbol; |
| 100 | */ |
| 101 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 102 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 103 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | #define RADEON_IB_POOL_SIZE 16 |
| 105 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
| 106 | #define RADEONFB_CONN_LIMIT 4 |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 107 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | /* |
| 110 | * Errata workarounds. |
| 111 | */ |
| 112 | enum radeon_pll_errata { |
| 113 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 114 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 115 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 116 | }; |
| 117 | |
| 118 | |
| 119 | struct radeon_device; |
| 120 | |
| 121 | |
| 122 | /* |
| 123 | * BIOS. |
| 124 | */ |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 125 | #define ATRM_BIOS_PAGE 4096 |
| 126 | |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 127 | #if defined(CONFIG_VGA_SWITCHEROO) |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 128 | bool radeon_atrm_supported(struct pci_dev *pdev); |
| 129 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 130 | #else |
| 131 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
| 132 | { |
| 133 | return false; |
| 134 | } |
| 135 | |
| 136 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
| 137 | return -EINVAL; |
| 138 | } |
| 139 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 140 | bool radeon_get_bios(struct radeon_device *rdev); |
| 141 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * Dummy page |
| 145 | */ |
| 146 | struct radeon_dummy_page { |
| 147 | struct page *page; |
| 148 | dma_addr_t addr; |
| 149 | }; |
| 150 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 151 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 152 | |
| 153 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 154 | /* |
| 155 | * Clocks |
| 156 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | struct radeon_clock { |
| 158 | struct radeon_pll p1pll; |
| 159 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 160 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | struct radeon_pll spll; |
| 162 | struct radeon_pll mpll; |
| 163 | /* 10 Khz units */ |
| 164 | uint32_t default_mclk; |
| 165 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 166 | uint32_t default_dispclk; |
| 167 | uint32_t dp_extclk; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 168 | }; |
| 169 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 170 | /* |
| 171 | * Power management |
| 172 | */ |
| 173 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 174 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 175 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 176 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 177 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Alex Deucher | bae6b562 | 2010-04-22 13:38:05 -0400 | [diff] [blame] | 178 | bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); |
| 179 | void radeon_sync_with_vblank(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 180 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | /* |
| 182 | * Fences. |
| 183 | */ |
| 184 | struct radeon_fence_driver { |
| 185 | uint32_t scratch_reg; |
| 186 | atomic_t seq; |
| 187 | uint32_t last_seq; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 188 | unsigned long last_jiffies; |
| 189 | unsigned long last_timeout; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 190 | wait_queue_head_t queue; |
| 191 | rwlock_t lock; |
| 192 | struct list_head created; |
| 193 | struct list_head emited; |
| 194 | struct list_head signaled; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 195 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | struct radeon_fence { |
| 199 | struct radeon_device *rdev; |
| 200 | struct kref kref; |
| 201 | struct list_head list; |
| 202 | /* protected by radeon_fence.lock */ |
| 203 | uint32_t seq; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | bool emited; |
| 205 | bool signaled; |
| 206 | }; |
| 207 | |
| 208 | int radeon_fence_driver_init(struct radeon_device *rdev); |
| 209 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
| 210 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
| 211 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
| 212 | void radeon_fence_process(struct radeon_device *rdev); |
| 213 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 214 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
| 215 | int radeon_fence_wait_next(struct radeon_device *rdev); |
| 216 | int radeon_fence_wait_last(struct radeon_device *rdev); |
| 217 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 218 | void radeon_fence_unref(struct radeon_fence **fence); |
| 219 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 220 | /* |
| 221 | * Tiling registers |
| 222 | */ |
| 223 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 224 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 225 | }; |
| 226 | |
| 227 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | |
| 229 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 230 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 231 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 232 | struct radeon_mman { |
| 233 | struct ttm_bo_global_ref bo_global_ref; |
| 234 | struct ttm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 235 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 236 | bool mem_global_referenced; |
| 237 | bool initialized; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 238 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 240 | struct radeon_bo { |
| 241 | /* Protected by gem.mutex */ |
| 242 | struct list_head list; |
| 243 | /* Protected by tbo.reserved */ |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 244 | u32 placements[3]; |
| 245 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 246 | struct ttm_buffer_object tbo; |
| 247 | struct ttm_bo_kmap_obj kmap; |
| 248 | unsigned pin_count; |
| 249 | void *kptr; |
| 250 | u32 tiling_flags; |
| 251 | u32 pitch; |
| 252 | int surface_reg; |
| 253 | /* Constant after initialization */ |
| 254 | struct radeon_device *rdev; |
| 255 | struct drm_gem_object *gobj; |
| 256 | }; |
| 257 | |
| 258 | struct radeon_bo_list { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 259 | struct list_head list; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 260 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 261 | uint64_t gpu_offset; |
| 262 | unsigned rdomain; |
| 263 | unsigned wdomain; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 264 | u32 tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | }; |
| 266 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 267 | /* |
| 268 | * GEM objects. |
| 269 | */ |
| 270 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 271 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 272 | struct list_head objects; |
| 273 | }; |
| 274 | |
| 275 | int radeon_gem_init(struct radeon_device *rdev); |
| 276 | void radeon_gem_fini(struct radeon_device *rdev); |
| 277 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 278 | int alignment, int initial_domain, |
| 279 | bool discardable, bool kernel, |
| 280 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
| 282 | uint64_t *gpu_addr); |
| 283 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
| 284 | |
| 285 | |
| 286 | /* |
| 287 | * GART structures, functions & helpers |
| 288 | */ |
| 289 | struct radeon_mc; |
| 290 | |
| 291 | struct radeon_gart_table_ram { |
| 292 | volatile uint32_t *ptr; |
| 293 | }; |
| 294 | |
| 295 | struct radeon_gart_table_vram { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 296 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 297 | volatile uint32_t *ptr; |
| 298 | }; |
| 299 | |
| 300 | union radeon_gart_table { |
| 301 | struct radeon_gart_table_ram ram; |
| 302 | struct radeon_gart_table_vram vram; |
| 303 | }; |
| 304 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 305 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 306 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 307 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 308 | struct radeon_gart { |
| 309 | dma_addr_t table_addr; |
| 310 | unsigned num_gpu_pages; |
| 311 | unsigned num_cpu_pages; |
| 312 | unsigned table_size; |
| 313 | union radeon_gart_table table; |
| 314 | struct page **pages; |
| 315 | dma_addr_t *pages_addr; |
| 316 | bool ready; |
| 317 | }; |
| 318 | |
| 319 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 320 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 321 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 322 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
| 323 | int radeon_gart_init(struct radeon_device *rdev); |
| 324 | void radeon_gart_fini(struct radeon_device *rdev); |
| 325 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 326 | int pages); |
| 327 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
| 328 | int pages, struct page **pagelist); |
| 329 | |
| 330 | |
| 331 | /* |
| 332 | * GPU MC structures, functions & helpers |
| 333 | */ |
| 334 | struct radeon_mc { |
| 335 | resource_size_t aper_size; |
| 336 | resource_size_t aper_base; |
| 337 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 338 | /* for some chips with <= 32MB we need to lie |
| 339 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 340 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 341 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 342 | u64 gtt_size; |
| 343 | u64 gtt_start; |
| 344 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 345 | u64 vram_start; |
| 346 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 347 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 348 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 349 | int vram_mtrr; |
| 350 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 351 | bool igp_sideport_enabled; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 352 | }; |
| 353 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 354 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 355 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | |
| 357 | /* |
| 358 | * GPU scratch registers structures, functions & helpers |
| 359 | */ |
| 360 | struct radeon_scratch { |
| 361 | unsigned num_reg; |
| 362 | bool free[32]; |
| 363 | uint32_t reg[32]; |
| 364 | }; |
| 365 | |
| 366 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 367 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 368 | |
| 369 | |
| 370 | /* |
| 371 | * IRQS. |
| 372 | */ |
| 373 | struct radeon_irq { |
| 374 | bool installed; |
| 375 | bool sw_int; |
| 376 | /* FIXME: use a define max crtc rather than hardcode it */ |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 377 | bool crtc_vblank_int[6]; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 378 | wait_queue_head_t vblank_queue; |
Alex Deucher | b500f68 | 2009-12-03 13:08:53 -0500 | [diff] [blame] | 379 | /* FIXME: use defines for max hpd/dacs */ |
| 380 | bool hpd[6]; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 381 | bool gui_idle; |
| 382 | bool gui_idle_acked; |
| 383 | wait_queue_head_t idle_queue; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 384 | /* FIXME: use defines for max HDMI blocks */ |
| 385 | bool hdmi[2]; |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 386 | spinlock_t sw_lock; |
| 387 | int sw_refcount; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 388 | }; |
| 389 | |
| 390 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 391 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 392 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
| 393 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 394 | |
| 395 | /* |
| 396 | * CP & ring. |
| 397 | */ |
| 398 | struct radeon_ib { |
| 399 | struct list_head list; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 400 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 401 | uint64_t gpu_addr; |
| 402 | struct radeon_fence *fence; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 403 | uint32_t *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 404 | uint32_t length_dw; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 405 | bool free; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 406 | }; |
| 407 | |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 408 | /* |
| 409 | * locking - |
| 410 | * mutex protects scheduled_ibs, ready, alloc_bm |
| 411 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 412 | struct radeon_ib_pool { |
| 413 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 414 | struct radeon_bo *robj; |
Jerome Glisse | 9f93ed3 | 2010-01-28 18:22:31 +0100 | [diff] [blame] | 415 | struct list_head bogus_ib; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 416 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 417 | bool ready; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 418 | unsigned head_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 419 | }; |
| 420 | |
| 421 | struct radeon_cp { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 422 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 423 | volatile uint32_t *ring; |
| 424 | unsigned rptr; |
| 425 | unsigned wptr; |
| 426 | unsigned wptr_old; |
| 427 | unsigned ring_size; |
| 428 | unsigned ring_free_dw; |
| 429 | int count_dw; |
| 430 | uint64_t gpu_addr; |
| 431 | uint32_t align_mask; |
| 432 | uint32_t ptr_mask; |
| 433 | struct mutex mutex; |
| 434 | bool ready; |
| 435 | }; |
| 436 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 437 | /* |
| 438 | * R6xx+ IH ring |
| 439 | */ |
| 440 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 441 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 442 | volatile uint32_t *ring; |
| 443 | unsigned rptr; |
| 444 | unsigned wptr; |
| 445 | unsigned wptr_old; |
| 446 | unsigned ring_size; |
| 447 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 448 | uint32_t ptr_mask; |
| 449 | spinlock_t lock; |
| 450 | bool enabled; |
| 451 | }; |
| 452 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 453 | struct r600_blit { |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 454 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 455 | struct radeon_bo *shader_obj; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 456 | u64 shader_gpu_addr; |
| 457 | u32 vs_offset, ps_offset; |
| 458 | u32 state_offset; |
| 459 | u32 state_len; |
| 460 | u32 vb_used, vb_total; |
| 461 | struct radeon_ib *vb_ib; |
| 462 | }; |
| 463 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 464 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
| 465 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
| 466 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| 467 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 468 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
| 469 | int radeon_ib_test(struct radeon_device *rdev); |
Jerome Glisse | 9f93ed3 | 2010-01-28 18:22:31 +0100 | [diff] [blame] | 470 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 471 | /* Ring access between begin & end cannot sleep */ |
| 472 | void radeon_ring_free_size(struct radeon_device *rdev); |
| 473 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
| 474 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
| 475 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
| 476 | int radeon_ring_test(struct radeon_device *rdev); |
| 477 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 478 | void radeon_ring_fini(struct radeon_device *rdev); |
| 479 | |
| 480 | |
| 481 | /* |
| 482 | * CS. |
| 483 | */ |
| 484 | struct radeon_cs_reloc { |
| 485 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 486 | struct radeon_bo *robj; |
| 487 | struct radeon_bo_list lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 488 | uint32_t handle; |
| 489 | uint32_t flags; |
| 490 | }; |
| 491 | |
| 492 | struct radeon_cs_chunk { |
| 493 | uint32_t chunk_id; |
| 494 | uint32_t length_dw; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 495 | int kpage_idx[2]; |
| 496 | uint32_t *kpage[2]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 497 | uint32_t *kdata; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 498 | void __user *user_ptr; |
| 499 | int last_copied_page; |
| 500 | int last_page_index; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 501 | }; |
| 502 | |
| 503 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 504 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 505 | struct radeon_device *rdev; |
| 506 | struct drm_file *filp; |
| 507 | /* chunks */ |
| 508 | unsigned nchunks; |
| 509 | struct radeon_cs_chunk *chunks; |
| 510 | uint64_t *chunks_array; |
| 511 | /* IB */ |
| 512 | unsigned idx; |
| 513 | /* relocations */ |
| 514 | unsigned nrelocs; |
| 515 | struct radeon_cs_reloc *relocs; |
| 516 | struct radeon_cs_reloc **relocs_ptr; |
| 517 | struct list_head validated; |
| 518 | /* indices of various chunks */ |
| 519 | int chunk_ib_idx; |
| 520 | int chunk_relocs_idx; |
| 521 | struct radeon_ib *ib; |
| 522 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 523 | unsigned family; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 524 | int parser_error; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 525 | }; |
| 526 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 527 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
| 528 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
| 529 | |
| 530 | |
| 531 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| 532 | { |
| 533 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| 534 | u32 pg_idx, pg_offset; |
| 535 | u32 idx_value = 0; |
| 536 | int new_page; |
| 537 | |
| 538 | pg_idx = (idx * 4) / PAGE_SIZE; |
| 539 | pg_offset = (idx * 4) % PAGE_SIZE; |
| 540 | |
| 541 | if (ibc->kpage_idx[0] == pg_idx) |
| 542 | return ibc->kpage[0][pg_offset/4]; |
| 543 | if (ibc->kpage_idx[1] == pg_idx) |
| 544 | return ibc->kpage[1][pg_offset/4]; |
| 545 | |
| 546 | new_page = radeon_cs_update_pages(p, pg_idx); |
| 547 | if (new_page < 0) { |
| 548 | p->parser_error = new_page; |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
| 553 | return idx_value; |
| 554 | } |
| 555 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 556 | struct radeon_cs_packet { |
| 557 | unsigned idx; |
| 558 | unsigned type; |
| 559 | unsigned reg; |
| 560 | unsigned opcode; |
| 561 | int count; |
| 562 | unsigned one_reg_wr; |
| 563 | }; |
| 564 | |
| 565 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 566 | struct radeon_cs_packet *pkt, |
| 567 | unsigned idx, unsigned reg); |
| 568 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 569 | struct radeon_cs_packet *pkt); |
| 570 | |
| 571 | |
| 572 | /* |
| 573 | * AGP |
| 574 | */ |
| 575 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 576 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 577 | void radeon_agp_fini(struct radeon_device *rdev); |
| 578 | |
| 579 | |
| 580 | /* |
| 581 | * Writeback |
| 582 | */ |
| 583 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 584 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 585 | volatile uint32_t *wb; |
| 586 | uint64_t gpu_addr; |
| 587 | }; |
| 588 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 589 | /** |
| 590 | * struct radeon_pm - power management datas |
| 591 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 592 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 593 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 594 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 595 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 596 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 597 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 598 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 599 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
| 600 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
| 601 | * @needed_bandwidth: current bandwidth needs |
| 602 | * |
| 603 | * It keeps track of various data needed to take powermanagement decision. |
| 604 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
| 605 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 606 | * (type of memory, bus size, efficiency, ...) |
| 607 | */ |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 608 | enum radeon_pm_state { |
| 609 | PM_STATE_DISABLED, |
| 610 | PM_STATE_MINIMUM, |
| 611 | PM_STATE_PAUSED, |
| 612 | PM_STATE_ACTIVE |
| 613 | }; |
| 614 | enum radeon_pm_action { |
| 615 | PM_ACTION_NONE, |
| 616 | PM_ACTION_MINIMUM, |
| 617 | PM_ACTION_DOWNCLOCK, |
Alex Deucher | 58e21df | 2010-03-22 13:31:08 -0400 | [diff] [blame] | 618 | PM_ACTION_UPCLOCK, |
| 619 | PM_ACTION_DEFAULT |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 620 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 621 | |
| 622 | enum radeon_voltage_type { |
| 623 | VOLTAGE_NONE = 0, |
| 624 | VOLTAGE_GPIO, |
| 625 | VOLTAGE_VDDC, |
| 626 | VOLTAGE_SW |
| 627 | }; |
| 628 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 629 | enum radeon_pm_state_type { |
| 630 | POWER_STATE_TYPE_DEFAULT, |
| 631 | POWER_STATE_TYPE_POWERSAVE, |
| 632 | POWER_STATE_TYPE_BATTERY, |
| 633 | POWER_STATE_TYPE_BALANCED, |
| 634 | POWER_STATE_TYPE_PERFORMANCE, |
| 635 | }; |
| 636 | |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 637 | enum radeon_pm_clock_mode_type { |
| 638 | POWER_MODE_TYPE_DEFAULT, |
| 639 | POWER_MODE_TYPE_LOW, |
| 640 | POWER_MODE_TYPE_MID, |
| 641 | POWER_MODE_TYPE_HIGH, |
| 642 | }; |
| 643 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 644 | struct radeon_voltage { |
| 645 | enum radeon_voltage_type type; |
| 646 | /* gpio voltage */ |
| 647 | struct radeon_gpio_rec gpio; |
| 648 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 649 | bool active_high; /* voltage drop is active when bit is high */ |
| 650 | /* VDDC voltage */ |
| 651 | u8 vddc_id; /* index into vddc voltage table */ |
| 652 | u8 vddci_id; /* index into vddci voltage table */ |
| 653 | bool vddci_enabled; |
| 654 | /* r6xx+ sw */ |
| 655 | u32 voltage; |
| 656 | }; |
| 657 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 658 | struct radeon_pm_clock_info { |
| 659 | /* memory clock */ |
| 660 | u32 mclk; |
| 661 | /* engine clock */ |
| 662 | u32 sclk; |
| 663 | /* voltage info */ |
| 664 | struct radeon_voltage voltage; |
| 665 | /* standardized clock flags - not sure we'll need these */ |
| 666 | u32 flags; |
| 667 | }; |
| 668 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 669 | /* state flags */ |
| 670 | #define RADEON_PM_SINGLE_DISPLAY_ONLY (1 << 0) |
| 671 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 672 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 673 | enum radeon_pm_state_type type; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 674 | /* XXX: use a define for num clock modes */ |
| 675 | struct radeon_pm_clock_info clock_info[8]; |
| 676 | /* number of valid clock modes in this power state */ |
| 677 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 678 | struct radeon_pm_clock_info *default_clock_mode; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 679 | /* standardized state flags */ |
| 680 | u32 flags; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 681 | u32 misc; /* vbios specific flags */ |
| 682 | u32 misc2; /* vbios specific flags */ |
| 683 | int pcie_lanes; /* pcie lanes */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 684 | }; |
| 685 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 686 | /* |
| 687 | * Some modes are overclocked by very low value, accept them |
| 688 | */ |
| 689 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 690 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 691 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 692 | struct mutex mutex; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 693 | struct delayed_work idle_work; |
| 694 | enum radeon_pm_state state; |
| 695 | enum radeon_pm_action planned_action; |
| 696 | unsigned long action_timeout; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 697 | bool can_upclock; |
| 698 | bool can_downclock; |
| 699 | u32 active_crtcs; |
| 700 | int active_crtc_count; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 701 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 702 | bool vblank_sync; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 703 | bool gui_idle; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 704 | fixed20_12 max_bandwidth; |
| 705 | fixed20_12 igp_sideport_mclk; |
| 706 | fixed20_12 igp_system_mclk; |
| 707 | fixed20_12 igp_ht_link_clk; |
| 708 | fixed20_12 igp_ht_link_width; |
| 709 | fixed20_12 k8_bandwidth; |
| 710 | fixed20_12 sideport_bandwidth; |
| 711 | fixed20_12 ht_bandwidth; |
| 712 | fixed20_12 core_bandwidth; |
| 713 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 714 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 715 | fixed20_12 needed_bandwidth; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 716 | /* XXX: use a define for num power modes */ |
| 717 | struct radeon_power_state power_state[8]; |
| 718 | /* number of valid power states */ |
| 719 | int num_power_states; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 720 | int current_power_state_index; |
| 721 | int current_clock_mode_index; |
| 722 | int requested_power_state_index; |
| 723 | int requested_clock_mode_index; |
| 724 | int default_power_state_index; |
| 725 | u32 current_sclk; |
| 726 | u32 current_mclk; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 727 | struct radeon_i2c_chan *i2c_bus; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 728 | }; |
| 729 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 730 | |
| 731 | /* |
| 732 | * Benchmarking |
| 733 | */ |
| 734 | void radeon_benchmark(struct radeon_device *rdev); |
| 735 | |
| 736 | |
| 737 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 738 | * Testing |
| 739 | */ |
| 740 | void radeon_test_moves(struct radeon_device *rdev); |
| 741 | |
| 742 | |
| 743 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 744 | * Debugfs |
| 745 | */ |
| 746 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 747 | struct drm_info_list *files, |
| 748 | unsigned nfiles); |
| 749 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 750 | |
| 751 | |
| 752 | /* |
| 753 | * ASIC specific functions. |
| 754 | */ |
| 755 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 756 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 757 | void (*fini)(struct radeon_device *rdev); |
| 758 | int (*resume)(struct radeon_device *rdev); |
| 759 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 760 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 761 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 762 | int (*asic_reset)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 763 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 764 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 765 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 766 | void (*cp_fini)(struct radeon_device *rdev); |
| 767 | void (*cp_disable)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 768 | void (*cp_commit)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 769 | void (*ring_start)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 770 | int (*ring_test)(struct radeon_device *rdev); |
| 771 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 772 | int (*irq_set)(struct radeon_device *rdev); |
| 773 | int (*irq_process)(struct radeon_device *rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 774 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 775 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| 776 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 777 | int (*copy_blit)(struct radeon_device *rdev, |
| 778 | uint64_t src_offset, |
| 779 | uint64_t dst_offset, |
| 780 | unsigned num_pages, |
| 781 | struct radeon_fence *fence); |
| 782 | int (*copy_dma)(struct radeon_device *rdev, |
| 783 | uint64_t src_offset, |
| 784 | uint64_t dst_offset, |
| 785 | unsigned num_pages, |
| 786 | struct radeon_fence *fence); |
| 787 | int (*copy)(struct radeon_device *rdev, |
| 788 | uint64_t src_offset, |
| 789 | uint64_t dst_offset, |
| 790 | unsigned num_pages, |
| 791 | struct radeon_fence *fence); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 792 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 793 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 794 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 795 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 796 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 797 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 798 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 799 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
| 800 | uint32_t tiling_flags, uint32_t pitch, |
| 801 | uint32_t offset, uint32_t obj_size); |
Daniel Vetter | 9479c54 | 2010-03-11 21:19:16 +0000 | [diff] [blame] | 802 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 803 | void (*bandwidth_update)(struct radeon_device *rdev); |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 804 | void (*hpd_init)(struct radeon_device *rdev); |
| 805 | void (*hpd_fini)(struct radeon_device *rdev); |
| 806 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 807 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 808 | /* ioctl hw specific callback. Some hw might want to perform special |
| 809 | * operation on specific ioctl. For instance on wait idle some hw |
| 810 | * might want to perform and HDP flush through MMIO as it seems that |
| 811 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 812 | * through ring. |
| 813 | */ |
| 814 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 815 | bool (*gui_idle)(struct radeon_device *rdev); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 816 | void (*get_power_state)(struct radeon_device *rdev, enum radeon_pm_action action); |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame^] | 817 | void (*set_power_state)(struct radeon_device *rdev, bool static_switch); |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 818 | void (*pm_misc)(struct radeon_device *rdev); |
| 819 | void (*pm_prepare)(struct radeon_device *rdev); |
| 820 | void (*pm_finish)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 821 | }; |
| 822 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 823 | /* |
| 824 | * Asic structures |
| 825 | */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 826 | struct r100_gpu_lockup { |
| 827 | unsigned long last_jiffies; |
| 828 | u32 last_cp_rptr; |
| 829 | }; |
| 830 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 831 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 832 | const unsigned *reg_safe_bm; |
| 833 | unsigned reg_safe_bm_size; |
| 834 | u32 hdp_cntl; |
| 835 | struct r100_gpu_lockup lockup; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 836 | }; |
| 837 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 838 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 839 | const unsigned *reg_safe_bm; |
| 840 | unsigned reg_safe_bm_size; |
| 841 | u32 resync_scratch; |
| 842 | u32 hdp_cntl; |
| 843 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 844 | }; |
| 845 | |
| 846 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 847 | unsigned max_pipes; |
| 848 | unsigned max_tile_pipes; |
| 849 | unsigned max_simds; |
| 850 | unsigned max_backends; |
| 851 | unsigned max_gprs; |
| 852 | unsigned max_threads; |
| 853 | unsigned max_stack_entries; |
| 854 | unsigned max_hw_contexts; |
| 855 | unsigned max_gs_threads; |
| 856 | unsigned sx_max_export_size; |
| 857 | unsigned sx_max_export_pos_size; |
| 858 | unsigned sx_max_export_smx_size; |
| 859 | unsigned sq_num_cf_insts; |
| 860 | unsigned tiling_nbanks; |
| 861 | unsigned tiling_npipes; |
| 862 | unsigned tiling_group_size; |
| 863 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 864 | }; |
| 865 | |
| 866 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 867 | unsigned max_pipes; |
| 868 | unsigned max_tile_pipes; |
| 869 | unsigned max_simds; |
| 870 | unsigned max_backends; |
| 871 | unsigned max_gprs; |
| 872 | unsigned max_threads; |
| 873 | unsigned max_stack_entries; |
| 874 | unsigned max_hw_contexts; |
| 875 | unsigned max_gs_threads; |
| 876 | unsigned sx_max_export_size; |
| 877 | unsigned sx_max_export_pos_size; |
| 878 | unsigned sx_max_export_smx_size; |
| 879 | unsigned sq_num_cf_insts; |
| 880 | unsigned sx_num_of_sets; |
| 881 | unsigned sc_prim_fifo_size; |
| 882 | unsigned sc_hiz_tile_fifo_size; |
| 883 | unsigned sc_earlyz_tile_fifo_fize; |
| 884 | unsigned tiling_nbanks; |
| 885 | unsigned tiling_npipes; |
| 886 | unsigned tiling_group_size; |
| 887 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 888 | }; |
| 889 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 890 | struct evergreen_asic { |
| 891 | unsigned num_ses; |
| 892 | unsigned max_pipes; |
| 893 | unsigned max_tile_pipes; |
| 894 | unsigned max_simds; |
| 895 | unsigned max_backends; |
| 896 | unsigned max_gprs; |
| 897 | unsigned max_threads; |
| 898 | unsigned max_stack_entries; |
| 899 | unsigned max_hw_contexts; |
| 900 | unsigned max_gs_threads; |
| 901 | unsigned sx_max_export_size; |
| 902 | unsigned sx_max_export_pos_size; |
| 903 | unsigned sx_max_export_smx_size; |
| 904 | unsigned sq_num_cf_insts; |
| 905 | unsigned sx_num_of_sets; |
| 906 | unsigned sc_prim_fifo_size; |
| 907 | unsigned sc_hiz_tile_fifo_size; |
| 908 | unsigned sc_earlyz_tile_fifo_size; |
| 909 | unsigned tiling_nbanks; |
| 910 | unsigned tiling_npipes; |
| 911 | unsigned tiling_group_size; |
| 912 | }; |
| 913 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 914 | union radeon_asic_config { |
| 915 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 916 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 917 | struct r600_asic r600; |
| 918 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 919 | struct evergreen_asic evergreen; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 920 | }; |
| 921 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 922 | /* |
| 923 | * asic initizalization from radeon_asic.c |
| 924 | */ |
| 925 | void radeon_agp_disable(struct radeon_device *rdev); |
| 926 | int radeon_asic_init(struct radeon_device *rdev); |
| 927 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 928 | |
| 929 | /* |
| 930 | * IOCTL. |
| 931 | */ |
| 932 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 933 | struct drm_file *filp); |
| 934 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 935 | struct drm_file *filp); |
| 936 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 937 | struct drm_file *file_priv); |
| 938 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 939 | struct drm_file *file_priv); |
| 940 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 941 | struct drm_file *file_priv); |
| 942 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 943 | struct drm_file *file_priv); |
| 944 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 945 | struct drm_file *filp); |
| 946 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 947 | struct drm_file *filp); |
| 948 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 949 | struct drm_file *filp); |
| 950 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 951 | struct drm_file *filp); |
| 952 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 953 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 954 | struct drm_file *filp); |
| 955 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 956 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 957 | |
| 958 | |
| 959 | /* |
| 960 | * Core structure, functions and helpers. |
| 961 | */ |
| 962 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 963 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 964 | |
| 965 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 966 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 967 | struct drm_device *ddev; |
| 968 | struct pci_dev *pdev; |
| 969 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 970 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 971 | enum radeon_family family; |
| 972 | unsigned long flags; |
| 973 | int usec_timeout; |
| 974 | enum radeon_pll_errata pll_errata; |
| 975 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 976 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 977 | int disp_priority; |
| 978 | /* BIOS */ |
| 979 | uint8_t *bios; |
| 980 | bool is_atom_bios; |
| 981 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 982 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 983 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 984 | resource_size_t rmmio_base; |
| 985 | resource_size_t rmmio_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 986 | void *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 987 | radeon_rreg_t mc_rreg; |
| 988 | radeon_wreg_t mc_wreg; |
| 989 | radeon_rreg_t pll_rreg; |
| 990 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 991 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 992 | radeon_rreg_t pciep_rreg; |
| 993 | radeon_wreg_t pciep_wreg; |
| 994 | struct radeon_clock clock; |
| 995 | struct radeon_mc mc; |
| 996 | struct radeon_gart gart; |
| 997 | struct radeon_mode_info mode_info; |
| 998 | struct radeon_scratch scratch; |
| 999 | struct radeon_mman mman; |
| 1000 | struct radeon_fence_driver fence_drv; |
| 1001 | struct radeon_cp cp; |
| 1002 | struct radeon_ib_pool ib_pool; |
| 1003 | struct radeon_irq irq; |
| 1004 | struct radeon_asic *asic; |
| 1005 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1006 | struct radeon_pm pm; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1007 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1008 | struct mutex cs_mutex; |
| 1009 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1010 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1011 | bool gpu_lockup; |
| 1012 | bool shutdown; |
| 1013 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1014 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1015 | bool accel_working; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1016 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1017 | const struct firmware *me_fw; /* all family ME firmware */ |
| 1018 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1019 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1020 | struct r600_blit r600_blit; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 1021 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1022 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1023 | struct workqueue_struct *wq; |
| 1024 | struct work_struct hotplug_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1025 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1026 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1027 | |
| 1028 | /* audio stuff */ |
| 1029 | struct timer_list audio_timer; |
| 1030 | int audio_channels; |
| 1031 | int audio_rate; |
| 1032 | int audio_bits_per_sample; |
| 1033 | uint8_t audio_status_bits; |
| 1034 | uint8_t audio_category_code; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1035 | |
| 1036 | bool powered_down; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1037 | }; |
| 1038 | |
| 1039 | int radeon_device_init(struct radeon_device *rdev, |
| 1040 | struct drm_device *ddev, |
| 1041 | struct pci_dev *pdev, |
| 1042 | uint32_t flags); |
| 1043 | void radeon_device_fini(struct radeon_device *rdev); |
| 1044 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 1045 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1046 | /* r600 blit */ |
| 1047 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
| 1048 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
| 1049 | void r600_kms_blit_copy(struct radeon_device *rdev, |
| 1050 | u64 src_gpu_addr, u64 dst_gpu_addr, |
| 1051 | int size_bytes); |
| 1052 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1053 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1054 | { |
Alex Deucher | 07bec2d | 2010-01-13 19:09:12 -0500 | [diff] [blame] | 1055 | if (reg < rdev->rmmio_size) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1056 | return readl(((void __iomem *)rdev->rmmio) + reg); |
| 1057 | else { |
| 1058 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 1059 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 1060 | } |
| 1061 | } |
| 1062 | |
| 1063 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1064 | { |
Alex Deucher | 07bec2d | 2010-01-13 19:09:12 -0500 | [diff] [blame] | 1065 | if (reg < rdev->rmmio_size) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1066 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| 1067 | else { |
| 1068 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| 1069 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| 1070 | } |
| 1071 | } |
| 1072 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1073 | /* |
| 1074 | * Cast helper |
| 1075 | */ |
| 1076 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1077 | |
| 1078 | /* |
| 1079 | * Registers read & write functions. |
| 1080 | */ |
| 1081 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
| 1082 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1083 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1084 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1085 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1086 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1087 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1088 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 1089 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 1090 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 1091 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1092 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 1093 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Rafał Miłecki | aa5120d | 2010-02-18 20:24:28 +0000 | [diff] [blame] | 1094 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
| 1095 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1096 | #define WREG32_P(reg, val, mask) \ |
| 1097 | do { \ |
| 1098 | uint32_t tmp_ = RREG32(reg); \ |
| 1099 | tmp_ &= (mask); \ |
| 1100 | tmp_ |= ((val) & ~(mask)); \ |
| 1101 | WREG32(reg, tmp_); \ |
| 1102 | } while (0) |
| 1103 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1104 | do { \ |
| 1105 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1106 | tmp_ &= (mask); \ |
| 1107 | tmp_ |= ((val) & ~(mask)); \ |
| 1108 | WREG32_PLL(reg, tmp_); \ |
| 1109 | } while (0) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1110 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1111 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1112 | /* |
| 1113 | * Indirect registers accessor |
| 1114 | */ |
| 1115 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1116 | { |
| 1117 | uint32_t r; |
| 1118 | |
| 1119 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1120 | r = RREG32(RADEON_PCIE_DATA); |
| 1121 | return r; |
| 1122 | } |
| 1123 | |
| 1124 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1125 | { |
| 1126 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1127 | WREG32(RADEON_PCIE_DATA, (v)); |
| 1128 | } |
| 1129 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1130 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1131 | |
| 1132 | |
| 1133 | /* |
| 1134 | * ASICs helpers. |
| 1135 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 1136 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 1137 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1138 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 1139 | (rdev->family == CHIP_RV200) || \ |
| 1140 | (rdev->family == CHIP_RS100) || \ |
| 1141 | (rdev->family == CHIP_RS200) || \ |
| 1142 | (rdev->family == CHIP_RV250) || \ |
| 1143 | (rdev->family == CHIP_RV280) || \ |
| 1144 | (rdev->family == CHIP_RS300)) |
| 1145 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 1146 | (rdev->family == CHIP_RV350) || \ |
| 1147 | (rdev->family == CHIP_R350) || \ |
| 1148 | (rdev->family == CHIP_RV380) || \ |
| 1149 | (rdev->family == CHIP_R420) || \ |
| 1150 | (rdev->family == CHIP_R423) || \ |
| 1151 | (rdev->family == CHIP_RV410) || \ |
| 1152 | (rdev->family == CHIP_RS400) || \ |
| 1153 | (rdev->family == CHIP_RS480)) |
| 1154 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
| 1155 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 1156 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1157 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1158 | |
| 1159 | /* |
| 1160 | * BIOS helpers. |
| 1161 | */ |
| 1162 | #define RBIOS8(i) (rdev->bios[i]) |
| 1163 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1164 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1165 | |
| 1166 | int radeon_combios_init(struct radeon_device *rdev); |
| 1167 | void radeon_combios_fini(struct radeon_device *rdev); |
| 1168 | int radeon_atombios_init(struct radeon_device *rdev); |
| 1169 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 1170 | |
| 1171 | |
| 1172 | /* |
| 1173 | * RING helpers. |
| 1174 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1175 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| 1176 | { |
| 1177 | #if DRM_DEBUG_CODE |
| 1178 | if (rdev->cp.count_dw <= 0) { |
| 1179 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 1180 | } |
| 1181 | #endif |
| 1182 | rdev->cp.ring[rdev->cp.wptr++] = v; |
| 1183 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
| 1184 | rdev->cp.count_dw--; |
| 1185 | rdev->cp.ring_free_dw--; |
| 1186 | } |
| 1187 | |
| 1188 | |
| 1189 | /* |
| 1190 | * ASICs macro. |
| 1191 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1192 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1193 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1194 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1195 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1196 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1197 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1198 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1199 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1200 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 1201 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1202 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1203 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1204 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
| 1205 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1206 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 1207 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 1208 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1209 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| 1210 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| 1211 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| 1212 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1213 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1214 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1215 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
Rafał Miłecki | 93e7de7 | 2009-11-04 23:34:10 +0100 | [diff] [blame] | 1216 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 1217 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1218 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| 1219 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1220 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
| 1221 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1222 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 1223 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
| 1224 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
| 1225 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
| 1226 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 1227 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1228 | #define radeon_get_power_state(rdev, a) (rdev)->asic->get_power_state((rdev), (a)) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame^] | 1229 | #define radeon_set_power_state(rdev, s) (rdev)->asic->set_power_state((rdev), (s)) |
| 1230 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
| 1231 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) |
| 1232 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1233 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1234 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1235 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1236 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1237 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1238 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 1239 | extern void radeon_gart_restore(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1240 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1241 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1242 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1243 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1244 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1245 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1246 | extern int radeon_clocks_init(struct radeon_device *rdev); |
| 1247 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
| 1248 | extern void radeon_scratch_init(struct radeon_device *rdev); |
| 1249 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1250 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1251 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1252 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 1253 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 1254 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1255 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 1256 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1257 | extern int radeon_resume_kms(struct drm_device *dev); |
| 1258 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1259 | |
Jerome Glisse | a18d7ea | 2009-09-09 22:23:27 +0200 | [diff] [blame] | 1260 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1261 | extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
| 1262 | extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1263 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 1264 | /* rv200,rv250,rv280 */ |
| 1265 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1266 | |
| 1267 | /* r300,r350,rv350,rv370,rv380 */ |
| 1268 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 1269 | extern void r300_mc_program(struct radeon_device *rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1270 | extern void r300_mc_init(struct radeon_device *rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1271 | extern void r300_clock_startup(struct radeon_device *rdev); |
| 1272 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1273 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
| 1274 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
| 1275 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1276 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
Jerome Glisse | a18d7ea | 2009-09-09 22:23:27 +0200 | [diff] [blame] | 1277 | |
Jerome Glisse | 905b682 | 2009-09-09 22:24:20 +0200 | [diff] [blame] | 1278 | /* r420,r423,rv410 */ |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1279 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 1280 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1281 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1282 | extern void r420_pipes_init(struct radeon_device *rdev); |
Jerome Glisse | 905b682 | 2009-09-09 22:24:20 +0200 | [diff] [blame] | 1283 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1284 | /* rv515 */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1285 | struct rv515_mc_save { |
| 1286 | u32 d1vga_control; |
| 1287 | u32 d2vga_control; |
| 1288 | u32 vga_render_control; |
| 1289 | u32 vga_hdp_control; |
| 1290 | u32 d1crtc_control; |
| 1291 | u32 d2crtc_control; |
| 1292 | }; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1293 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1294 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
| 1295 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 1296 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
| 1297 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
| 1298 | extern void rv515_clock_startup(struct radeon_device *rdev); |
| 1299 | extern void rv515_debugfs(struct radeon_device *rdev); |
| 1300 | extern int rv515_suspend(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1301 | |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 1302 | /* rs400 */ |
| 1303 | extern int rs400_gart_init(struct radeon_device *rdev); |
| 1304 | extern int rs400_gart_enable(struct radeon_device *rdev); |
| 1305 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
| 1306 | extern void rs400_gart_disable(struct radeon_device *rdev); |
| 1307 | extern void rs400_gart_fini(struct radeon_device *rdev); |
| 1308 | |
| 1309 | /* rs600 */ |
| 1310 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 1311 | extern int rs600_irq_set(struct radeon_device *rdev); |
| 1312 | extern void rs600_irq_disable(struct radeon_device *rdev); |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 1313 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1314 | /* rs690, rs740 */ |
| 1315 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 1316 | struct drm_display_mode *mode1, |
| 1317 | struct drm_display_mode *mode2); |
| 1318 | |
| 1319 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1320 | extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1321 | extern bool r600_card_posted(struct radeon_device *rdev); |
| 1322 | extern void r600_cp_stop(struct radeon_device *rdev); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1323 | extern int r600_cp_start(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1324 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 1325 | extern int r600_cp_resume(struct radeon_device *rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 1326 | extern void r600_cp_fini(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1327 | extern int r600_count_pipe_bits(uint32_t val); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1328 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1329 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1330 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 1331 | extern int r600_ib_test(struct radeon_device *rdev); |
| 1332 | extern int r600_ring_test(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1333 | extern void r600_wb_fini(struct radeon_device *rdev); |
Jerome Glisse | 81cc35b | 2009-10-01 18:02:12 +0200 | [diff] [blame] | 1334 | extern int r600_wb_enable(struct radeon_device *rdev); |
| 1335 | extern void r600_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1336 | extern void r600_scratch_init(struct radeon_device *rdev); |
| 1337 | extern int r600_blit_init(struct radeon_device *rdev); |
| 1338 | extern void r600_blit_fini(struct radeon_device *rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1339 | extern int r600_init_microcode(struct radeon_device *rdev); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1340 | extern int r600_asic_reset(struct radeon_device *rdev); |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1341 | /* r600 irq */ |
| 1342 | extern int r600_irq_init(struct radeon_device *rdev); |
| 1343 | extern void r600_irq_fini(struct radeon_device *rdev); |
| 1344 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 1345 | extern int r600_irq_set(struct radeon_device *rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 1346 | extern void r600_irq_suspend(struct radeon_device *rdev); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 1347 | extern void r600_disable_interrupts(struct radeon_device *rdev); |
| 1348 | extern void r600_rlc_stop(struct radeon_device *rdev); |
Jerome Glisse | 0c45249 | 2010-01-15 14:44:37 +0100 | [diff] [blame] | 1349 | /* r600 audio */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1350 | extern int r600_audio_init(struct radeon_device *rdev); |
| 1351 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); |
| 1352 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 1353 | extern int r600_audio_channels(struct radeon_device *rdev); |
| 1354 | extern int r600_audio_bits_per_sample(struct radeon_device *rdev); |
| 1355 | extern int r600_audio_rate(struct radeon_device *rdev); |
| 1356 | extern uint8_t r600_audio_status_bits(struct radeon_device *rdev); |
| 1357 | extern uint8_t r600_audio_category_code(struct radeon_device *rdev); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 1358 | extern void r600_audio_schedule_polling(struct radeon_device *rdev); |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 1359 | extern void r600_audio_enable_polling(struct drm_encoder *encoder); |
| 1360 | extern void r600_audio_disable_polling(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1361 | extern void r600_audio_fini(struct radeon_device *rdev); |
| 1362 | extern void r600_hdmi_init(struct drm_encoder *encoder); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 1363 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
| 1364 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1365 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
| 1366 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 1367 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1368 | |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1369 | extern void r700_cp_stop(struct radeon_device *rdev); |
| 1370 | extern void r700_cp_fini(struct radeon_device *rdev); |
Alex Deucher | 0ca2ab5 | 2010-02-26 13:57:45 -0500 | [diff] [blame] | 1371 | extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 1372 | extern int evergreen_irq_set(struct radeon_device *rdev); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1373 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1374 | /* evergreen */ |
| 1375 | struct evergreen_mc_save { |
| 1376 | u32 vga_control[6]; |
| 1377 | u32 vga_render_control; |
| 1378 | u32 vga_hdp_control; |
| 1379 | u32 crtc_control[6]; |
| 1380 | }; |
| 1381 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1382 | #include "radeon_object.h" |
| 1383 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1384 | #endif |