Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 28 | #include <linux/cpufreq.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "intel_drv.h" |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 31 | #include "../../../platform/x86/intel_ips.h" |
| 32 | #include <linux/module.h> |
Paulo Zanoni | f9dcb0d | 2013-12-11 18:50:10 -0200 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Damien Lespiau | f4db932 | 2013-06-24 22:59:50 +0100 | [diff] [blame] | 34 | #include <drm/i915_powerwell.h> |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 36 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 37 | /** |
| 38 | * RC6 is a special power stage which allows the GPU to enter an very |
| 39 | * low-voltage mode when idle, using down to 0V while at this stage. This |
| 40 | * stage is entered automatically when the GPU is idle when RC6 support is |
| 41 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
| 42 | * |
| 43 | * There are different RC6 modes available in Intel GPU, which differentiate |
| 44 | * among each other with the latency required to enter and leave RC6 and |
| 45 | * voltage consumed by the GPU in different states. |
| 46 | * |
| 47 | * The combination of the following flags define which states GPU is allowed |
| 48 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
| 49 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
| 50 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
| 51 | * which brings the most power savings; deeper states save more power, but |
| 52 | * require higher latency to switch to and wake up. |
| 53 | */ |
| 54 | #define INTEL_RC6_ENABLE (1<<0) |
| 55 | #define INTEL_RC6p_ENABLE (1<<1) |
| 56 | #define INTEL_RC6pp_ENABLE (1<<2) |
| 57 | |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 58 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
| 59 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
| 60 | * during in-memory transfers and, therefore, reduce the power packet. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 61 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 62 | * The benefits of FBC are mostly visible with solid backgrounds and |
| 63 | * variation-less patterns. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 64 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 65 | * FBC-related functionality can be enabled by the means of the |
| 66 | * i915.i915_enable_fbc parameter |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 67 | */ |
| 68 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 69 | static void i8xx_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 70 | { |
| 71 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 72 | u32 fbc_ctl; |
| 73 | |
| 74 | /* Disable compression */ |
| 75 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 76 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 77 | return; |
| 78 | |
| 79 | fbc_ctl &= ~FBC_CTL_EN; |
| 80 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 81 | |
| 82 | /* Wait for compressing bit to clear */ |
| 83 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
| 84 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 85 | return; |
| 86 | } |
| 87 | |
| 88 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 89 | } |
| 90 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 91 | static void i8xx_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 92 | { |
| 93 | struct drm_device *dev = crtc->dev; |
| 94 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 95 | struct drm_framebuffer *fb = crtc->primary->fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 96 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 97 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 98 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 99 | int cfb_pitch; |
Ville Syrjälä | 7f2cf22 | 2014-01-23 16:49:11 +0200 | [diff] [blame] | 100 | int i; |
Ville Syrjälä | 159f987 | 2013-11-28 17:29:57 +0200 | [diff] [blame] | 101 | u32 fbc_ctl; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 102 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 103 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 104 | if (fb->pitches[0] < cfb_pitch) |
| 105 | cfb_pitch = fb->pitches[0]; |
| 106 | |
Ville Syrjälä | 42a430f | 2013-11-28 17:29:56 +0200 | [diff] [blame] | 107 | /* FBC_CTL wants 32B or 64B units */ |
| 108 | if (IS_GEN2(dev)) |
| 109 | cfb_pitch = (cfb_pitch / 32) - 1; |
| 110 | else |
| 111 | cfb_pitch = (cfb_pitch / 64) - 1; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 112 | |
| 113 | /* Clear old tags */ |
| 114 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 115 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 116 | |
Ville Syrjälä | 159f987 | 2013-11-28 17:29:57 +0200 | [diff] [blame] | 117 | if (IS_GEN4(dev)) { |
| 118 | u32 fbc_ctl2; |
| 119 | |
| 120 | /* Set it up... */ |
| 121 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
Ville Syrjälä | 7f2cf22 | 2014-01-23 16:49:11 +0200 | [diff] [blame] | 122 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
Ville Syrjälä | 159f987 | 2013-11-28 17:29:57 +0200 | [diff] [blame] | 123 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 124 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 125 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 126 | |
| 127 | /* enable it... */ |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 128 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 129 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; |
| 130 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 131 | if (IS_I945GM(dev)) |
| 132 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
| 133 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 134 | fbc_ctl |= obj->fence_reg; |
| 135 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 136 | |
Ville Syrjälä | 5cd5410 | 2014-01-23 16:49:16 +0200 | [diff] [blame] | 137 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 138 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 139 | } |
| 140 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 141 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 142 | { |
| 143 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 144 | |
| 145 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 146 | } |
| 147 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 148 | static void g4x_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 149 | { |
| 150 | struct drm_device *dev = crtc->dev; |
| 151 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 152 | struct drm_framebuffer *fb = crtc->primary->fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 153 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 154 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 156 | u32 dpfc_ctl; |
| 157 | |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 158 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
| 159 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 160 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 161 | else |
| 162 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 163 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 164 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 165 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 166 | |
| 167 | /* enable it... */ |
Ville Syrjälä | fe74c1a | 2014-01-23 16:49:13 +0200 | [diff] [blame] | 168 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 169 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 170 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 171 | } |
| 172 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 173 | static void g4x_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 174 | { |
| 175 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 176 | u32 dpfc_ctl; |
| 177 | |
| 178 | /* Disable compression */ |
| 179 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 180 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 181 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 182 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 183 | |
| 184 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 185 | } |
| 186 | } |
| 187 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 188 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 189 | { |
| 190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 191 | |
| 192 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 193 | } |
| 194 | |
| 195 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
| 196 | { |
| 197 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 198 | u32 blt_ecoskpd; |
| 199 | |
| 200 | /* Make sure blitter notifies FBC of writes */ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 201 | |
| 202 | /* Blitter is part of Media powerwell on VLV. No impact of |
| 203 | * his param in other platforms for now */ |
| 204 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 205 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 206 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
| 207 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
| 208 | GEN6_BLITTER_LOCK_SHIFT; |
| 209 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 210 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
| 211 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 212 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
| 213 | GEN6_BLITTER_LOCK_SHIFT); |
| 214 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 215 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 216 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 217 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 218 | } |
| 219 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 220 | static void ironlake_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 221 | { |
| 222 | struct drm_device *dev = crtc->dev; |
| 223 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 224 | struct drm_framebuffer *fb = crtc->primary->fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 225 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 226 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 228 | u32 dpfc_ctl; |
| 229 | |
Ville Syrjälä | 46f3dab | 2014-01-23 16:49:14 +0200 | [diff] [blame] | 230 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 231 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 232 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 233 | else |
| 234 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
Ville Syrjälä | d629336 | 2013-11-21 21:29:45 +0200 | [diff] [blame] | 235 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
| 236 | if (IS_GEN5(dev)) |
| 237 | dpfc_ctl |= obj->fence_reg; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 238 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 239 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 240 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 241 | /* enable it... */ |
| 242 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 243 | |
| 244 | if (IS_GEN6(dev)) { |
| 245 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 246 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 247 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 248 | sandybridge_blit_fbc_update(dev); |
| 249 | } |
| 250 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 251 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 252 | } |
| 253 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 254 | static void ironlake_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 255 | { |
| 256 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 257 | u32 dpfc_ctl; |
| 258 | |
| 259 | /* Disable compression */ |
| 260 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 261 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 262 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 263 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 264 | |
| 265 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 266 | } |
| 267 | } |
| 268 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 269 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 270 | { |
| 271 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 272 | |
| 273 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 274 | } |
| 275 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 276 | static void gen7_enable_fbc(struct drm_crtc *crtc) |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 277 | { |
| 278 | struct drm_device *dev = crtc->dev; |
| 279 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 280 | struct drm_framebuffer *fb = crtc->primary->fb; |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 281 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
| 282 | struct drm_i915_gem_object *obj = intel_fb->obj; |
| 283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 284 | u32 dpfc_ctl; |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 285 | |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 286 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
| 287 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 288 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 289 | else |
| 290 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
| 291 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
| 292 | |
| 293 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 294 | |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 295 | if (IS_IVYBRIDGE(dev)) { |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 296 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
Ville Syrjälä | 2adb6db | 2014-03-05 13:05:46 +0200 | [diff] [blame] | 297 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 298 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 299 | ILK_FBCQ_DIS); |
Rodrigo Vivi | 2855416 | 2013-05-06 19:37:37 -0300 | [diff] [blame] | 300 | } else { |
Ville Syrjälä | 2adb6db | 2014-03-05 13:05:46 +0200 | [diff] [blame] | 301 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
Ville Syrjälä | 8f670bb | 2014-03-05 13:05:47 +0200 | [diff] [blame] | 302 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
| 303 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | |
| 304 | HSW_FBCQ_DIS); |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 305 | } |
Rodrigo Vivi | b74ea10 | 2013-05-09 14:08:38 -0300 | [diff] [blame] | 306 | |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 307 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 308 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 309 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 310 | |
| 311 | sandybridge_blit_fbc_update(dev); |
| 312 | |
Ville Syrjälä | b19870e | 2013-11-06 23:02:25 +0200 | [diff] [blame] | 313 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 314 | } |
| 315 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 316 | bool intel_fbc_enabled(struct drm_device *dev) |
| 317 | { |
| 318 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 319 | |
| 320 | if (!dev_priv->display.fbc_enabled) |
| 321 | return false; |
| 322 | |
| 323 | return dev_priv->display.fbc_enabled(dev); |
| 324 | } |
| 325 | |
| 326 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 327 | { |
| 328 | struct intel_fbc_work *work = |
| 329 | container_of(to_delayed_work(__work), |
| 330 | struct intel_fbc_work, work); |
| 331 | struct drm_device *dev = work->crtc->dev; |
| 332 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 333 | |
| 334 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 335 | if (work == dev_priv->fbc.fbc_work) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 336 | /* Double check that we haven't switched fb without cancelling |
| 337 | * the prior work. |
| 338 | */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 339 | if (work->crtc->primary->fb == work->fb) { |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 340 | dev_priv->display.enable_fbc(work->crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 341 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 342 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 343 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 344 | dev_priv->fbc.y = work->crtc->y; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 345 | } |
| 346 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 347 | dev_priv->fbc.fbc_work = NULL; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 348 | } |
| 349 | mutex_unlock(&dev->struct_mutex); |
| 350 | |
| 351 | kfree(work); |
| 352 | } |
| 353 | |
| 354 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
| 355 | { |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 356 | if (dev_priv->fbc.fbc_work == NULL) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 357 | return; |
| 358 | |
| 359 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
| 360 | |
| 361 | /* Synchronisation is provided by struct_mutex and checking of |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 362 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 363 | * entirely asynchronously. |
| 364 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 365 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 366 | /* tasklet was killed before being run, clean up */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 367 | kfree(dev_priv->fbc.fbc_work); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 368 | |
| 369 | /* Mark the work as no longer wanted so that if it does |
| 370 | * wake-up (because the work was already running and waiting |
| 371 | * for our mutex), it will discover that is no longer |
| 372 | * necessary to run. |
| 373 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 374 | dev_priv->fbc.fbc_work = NULL; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 375 | } |
| 376 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 377 | static void intel_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 378 | { |
| 379 | struct intel_fbc_work *work; |
| 380 | struct drm_device *dev = crtc->dev; |
| 381 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 382 | |
| 383 | if (!dev_priv->display.enable_fbc) |
| 384 | return; |
| 385 | |
| 386 | intel_cancel_fbc_work(dev_priv); |
| 387 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 388 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 389 | if (work == NULL) { |
Paulo Zanoni | 6cdcb5e | 2013-06-12 17:27:29 -0300 | [diff] [blame] | 390 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 391 | dev_priv->display.enable_fbc(crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 392 | return; |
| 393 | } |
| 394 | |
| 395 | work->crtc = crtc; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 396 | work->fb = crtc->primary->fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 397 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
| 398 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 399 | dev_priv->fbc.fbc_work = work; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 400 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 401 | /* Delay the actual enabling to let pageflipping cease and the |
| 402 | * display to settle before starting the compression. Note that |
| 403 | * this delay also serves a second purpose: it allows for a |
| 404 | * vblank to pass after disabling the FBC before we attempt |
| 405 | * to modify the control registers. |
| 406 | * |
| 407 | * A more complicated solution would involve tracking vblanks |
| 408 | * following the termination of the page-flipping sequence |
| 409 | * and indeed performing the enable as a co-routine and not |
| 410 | * waiting synchronously upon the vblank. |
Damien Lespiau | 7457d61 | 2013-06-07 17:41:07 +0100 | [diff] [blame] | 411 | * |
| 412 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 413 | */ |
| 414 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
| 415 | } |
| 416 | |
| 417 | void intel_disable_fbc(struct drm_device *dev) |
| 418 | { |
| 419 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 420 | |
| 421 | intel_cancel_fbc_work(dev_priv); |
| 422 | |
| 423 | if (!dev_priv->display.disable_fbc) |
| 424 | return; |
| 425 | |
| 426 | dev_priv->display.disable_fbc(dev); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 427 | dev_priv->fbc.plane = -1; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 428 | } |
| 429 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 430 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
| 431 | enum no_fbc_reason reason) |
| 432 | { |
| 433 | if (dev_priv->fbc.no_fbc_reason == reason) |
| 434 | return false; |
| 435 | |
| 436 | dev_priv->fbc.no_fbc_reason = reason; |
| 437 | return true; |
| 438 | } |
| 439 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 440 | /** |
| 441 | * intel_update_fbc - enable/disable FBC as needed |
| 442 | * @dev: the drm_device |
| 443 | * |
| 444 | * Set up the framebuffer compression hardware at mode set time. We |
| 445 | * enable it if possible: |
| 446 | * - plane A only (on pre-965) |
| 447 | * - no pixel mulitply/line duplication |
| 448 | * - no alpha buffer discard |
| 449 | * - no dual wide |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 450 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 451 | * |
| 452 | * We can't assume that any compression will take place (worst case), |
| 453 | * so the compressed buffer has to be the same size as the uncompressed |
| 454 | * one. It also must reside (along with the line length buffer) in |
| 455 | * stolen memory. |
| 456 | * |
| 457 | * We need to enable/disable FBC on a global basis. |
| 458 | */ |
| 459 | void intel_update_fbc(struct drm_device *dev) |
| 460 | { |
| 461 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 462 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
| 463 | struct intel_crtc *intel_crtc; |
| 464 | struct drm_framebuffer *fb; |
| 465 | struct intel_framebuffer *intel_fb; |
| 466 | struct drm_i915_gem_object *obj; |
Ville Syrjälä | ef644fd | 2013-09-04 18:25:21 +0300 | [diff] [blame] | 467 | const struct drm_display_mode *adjusted_mode; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 468 | unsigned int max_width, max_height; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 469 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 470 | if (!HAS_FBC(dev)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 471 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 472 | return; |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 473 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 474 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 475 | if (!i915.powersave) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 476 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
| 477 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 478 | return; |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 479 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 480 | |
| 481 | /* |
| 482 | * If FBC is already on, we just have to verify that we can |
| 483 | * keep it that way... |
| 484 | * Need to disable if: |
| 485 | * - more than one pipe is active |
| 486 | * - changing FBC params (stride, fence, mode) |
| 487 | * - new fb is too large to fit in compressed buffer |
| 488 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 489 | */ |
| 490 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 491 | if (intel_crtc_active(tmp_crtc) && |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 492 | to_intel_crtc(tmp_crtc)->primary_enabled) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 493 | if (crtc) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 494 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
| 495 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 496 | goto out_disable; |
| 497 | } |
| 498 | crtc = tmp_crtc; |
| 499 | } |
| 500 | } |
| 501 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 502 | if (!crtc || crtc->primary->fb == NULL) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 503 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
| 504 | DRM_DEBUG_KMS("no output, disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 505 | goto out_disable; |
| 506 | } |
| 507 | |
| 508 | intel_crtc = to_intel_crtc(crtc); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 509 | fb = crtc->primary->fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 510 | intel_fb = to_intel_framebuffer(fb); |
| 511 | obj = intel_fb->obj; |
Ville Syrjälä | ef644fd | 2013-09-04 18:25:21 +0300 | [diff] [blame] | 512 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 513 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 514 | if (i915.enable_fbc < 0 && |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 515 | INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 516 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
| 517 | DRM_DEBUG_KMS("disabled per chip default\n"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 518 | goto out_disable; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 519 | } |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 520 | if (!i915.enable_fbc) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 521 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
| 522 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 523 | goto out_disable; |
| 524 | } |
Ville Syrjälä | ef644fd | 2013-09-04 18:25:21 +0300 | [diff] [blame] | 525 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
| 526 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 527 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
| 528 | DRM_DEBUG_KMS("mode incompatible with compression, " |
| 529 | "disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 530 | goto out_disable; |
| 531 | } |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 532 | |
| 533 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 534 | max_width = 4096; |
| 535 | max_height = 2048; |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 536 | } else { |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 537 | max_width = 2048; |
| 538 | max_height = 1536; |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 539 | } |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 540 | if (intel_crtc->config.pipe_src_w > max_width || |
| 541 | intel_crtc->config.pipe_src_h > max_height) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 542 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
| 543 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 544 | goto out_disable; |
| 545 | } |
Ben Widawsky | 8f94d24 | 2014-02-20 16:01:20 -0800 | [diff] [blame] | 546 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
Ville Syrjälä | c5a44aa | 2013-11-28 17:29:58 +0200 | [diff] [blame] | 547 | intel_crtc->plane != PLANE_A) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 548 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
Ville Syrjälä | c5a44aa | 2013-11-28 17:29:58 +0200 | [diff] [blame] | 549 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 550 | goto out_disable; |
| 551 | } |
| 552 | |
| 553 | /* The use of a CPU fence is mandatory in order to detect writes |
| 554 | * by the CPU to the scanout and trigger updates to the FBC. |
| 555 | */ |
| 556 | if (obj->tiling_mode != I915_TILING_X || |
| 557 | obj->fence_reg == I915_FENCE_REG_NONE) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 558 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
| 559 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 560 | goto out_disable; |
| 561 | } |
| 562 | |
| 563 | /* If the kernel debugger is active, always disable compression */ |
| 564 | if (in_dbg_master()) |
| 565 | goto out_disable; |
| 566 | |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 567 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 568 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
| 569 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 570 | goto out_disable; |
| 571 | } |
| 572 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 573 | /* If the scanout has not changed, don't modify the FBC settings. |
| 574 | * Note that we make the fundamental assumption that the fb->obj |
| 575 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 576 | * without first being decoupled from the scanout and FBC disabled. |
| 577 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 578 | if (dev_priv->fbc.plane == intel_crtc->plane && |
| 579 | dev_priv->fbc.fb_id == fb->base.id && |
| 580 | dev_priv->fbc.y == crtc->y) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 581 | return; |
| 582 | |
| 583 | if (intel_fbc_enabled(dev)) { |
| 584 | /* We update FBC along two paths, after changing fb/crtc |
| 585 | * configuration (modeswitching) and after page-flipping |
| 586 | * finishes. For the latter, we know that not only did |
| 587 | * we disable the FBC at the start of the page-flip |
| 588 | * sequence, but also more than one vblank has passed. |
| 589 | * |
| 590 | * For the former case of modeswitching, it is possible |
| 591 | * to switch between two FBC valid configurations |
| 592 | * instantaneously so we do need to disable the FBC |
| 593 | * before we can modify its control registers. We also |
| 594 | * have to wait for the next vblank for that to take |
| 595 | * effect. However, since we delay enabling FBC we can |
| 596 | * assume that a vblank has passed since disabling and |
| 597 | * that we can safely alter the registers in the deferred |
| 598 | * callback. |
| 599 | * |
| 600 | * In the scenario that we go from a valid to invalid |
| 601 | * and then back to valid FBC configuration we have |
| 602 | * no strict enforcement that a vblank occurred since |
| 603 | * disabling the FBC. However, along all current pipe |
| 604 | * disabling paths we do need to wait for a vblank at |
| 605 | * some point. And we wait before enabling FBC anyway. |
| 606 | */ |
| 607 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
| 608 | intel_disable_fbc(dev); |
| 609 | } |
| 610 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 611 | intel_enable_fbc(crtc); |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 612 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 613 | return; |
| 614 | |
| 615 | out_disable: |
| 616 | /* Multiple disables should be harmless */ |
| 617 | if (intel_fbc_enabled(dev)) { |
| 618 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
| 619 | intel_disable_fbc(dev); |
| 620 | } |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 621 | i915_gem_stolen_cleanup_compression(dev); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 622 | } |
| 623 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 624 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
| 625 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 626 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 627 | u32 tmp; |
| 628 | |
| 629 | tmp = I915_READ(CLKCFG); |
| 630 | |
| 631 | switch (tmp & CLKCFG_FSB_MASK) { |
| 632 | case CLKCFG_FSB_533: |
| 633 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 634 | break; |
| 635 | case CLKCFG_FSB_800: |
| 636 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 637 | break; |
| 638 | case CLKCFG_FSB_667: |
| 639 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 640 | break; |
| 641 | case CLKCFG_FSB_400: |
| 642 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 643 | break; |
| 644 | } |
| 645 | |
| 646 | switch (tmp & CLKCFG_MEM_MASK) { |
| 647 | case CLKCFG_MEM_533: |
| 648 | dev_priv->mem_freq = 533; |
| 649 | break; |
| 650 | case CLKCFG_MEM_667: |
| 651 | dev_priv->mem_freq = 667; |
| 652 | break; |
| 653 | case CLKCFG_MEM_800: |
| 654 | dev_priv->mem_freq = 800; |
| 655 | break; |
| 656 | } |
| 657 | |
| 658 | /* detect pineview DDR3 setting */ |
| 659 | tmp = I915_READ(CSHRDDR3CTL); |
| 660 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
| 661 | } |
| 662 | |
| 663 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 664 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 665 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 666 | u16 ddrpll, csipll; |
| 667 | |
| 668 | ddrpll = I915_READ16(DDRMPLL1); |
| 669 | csipll = I915_READ16(CSIPLL0); |
| 670 | |
| 671 | switch (ddrpll & 0xff) { |
| 672 | case 0xc: |
| 673 | dev_priv->mem_freq = 800; |
| 674 | break; |
| 675 | case 0x10: |
| 676 | dev_priv->mem_freq = 1066; |
| 677 | break; |
| 678 | case 0x14: |
| 679 | dev_priv->mem_freq = 1333; |
| 680 | break; |
| 681 | case 0x18: |
| 682 | dev_priv->mem_freq = 1600; |
| 683 | break; |
| 684 | default: |
| 685 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 686 | ddrpll & 0xff); |
| 687 | dev_priv->mem_freq = 0; |
| 688 | break; |
| 689 | } |
| 690 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 691 | dev_priv->ips.r_t = dev_priv->mem_freq; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 692 | |
| 693 | switch (csipll & 0x3ff) { |
| 694 | case 0x00c: |
| 695 | dev_priv->fsb_freq = 3200; |
| 696 | break; |
| 697 | case 0x00e: |
| 698 | dev_priv->fsb_freq = 3733; |
| 699 | break; |
| 700 | case 0x010: |
| 701 | dev_priv->fsb_freq = 4266; |
| 702 | break; |
| 703 | case 0x012: |
| 704 | dev_priv->fsb_freq = 4800; |
| 705 | break; |
| 706 | case 0x014: |
| 707 | dev_priv->fsb_freq = 5333; |
| 708 | break; |
| 709 | case 0x016: |
| 710 | dev_priv->fsb_freq = 5866; |
| 711 | break; |
| 712 | case 0x018: |
| 713 | dev_priv->fsb_freq = 6400; |
| 714 | break; |
| 715 | default: |
| 716 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 717 | csipll & 0x3ff); |
| 718 | dev_priv->fsb_freq = 0; |
| 719 | break; |
| 720 | } |
| 721 | |
| 722 | if (dev_priv->fsb_freq == 3200) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 723 | dev_priv->ips.c_m = 0; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 724 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 725 | dev_priv->ips.c_m = 1; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 726 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 727 | dev_priv->ips.c_m = 2; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 728 | } |
| 729 | } |
| 730 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 731 | static const struct cxsr_latency cxsr_latency_table[] = { |
| 732 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 733 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 734 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 735 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 736 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
| 737 | |
| 738 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 739 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 740 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 741 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 742 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
| 743 | |
| 744 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 745 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 746 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 747 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 748 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
| 749 | |
| 750 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 751 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 752 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 753 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 754 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
| 755 | |
| 756 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 757 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 758 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 759 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 760 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
| 761 | |
| 762 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 763 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 764 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 765 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 766 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
| 767 | }; |
| 768 | |
Daniel Vetter | 63c6227 | 2012-04-21 23:17:55 +0200 | [diff] [blame] | 769 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 770 | int is_ddr3, |
| 771 | int fsb, |
| 772 | int mem) |
| 773 | { |
| 774 | const struct cxsr_latency *latency; |
| 775 | int i; |
| 776 | |
| 777 | if (fsb == 0 || mem == 0) |
| 778 | return NULL; |
| 779 | |
| 780 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 781 | latency = &cxsr_latency_table[i]; |
| 782 | if (is_desktop == latency->is_desktop && |
| 783 | is_ddr3 == latency->is_ddr3 && |
| 784 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 785 | return latency; |
| 786 | } |
| 787 | |
| 788 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 789 | |
| 790 | return NULL; |
| 791 | } |
| 792 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 793 | static void pineview_disable_cxsr(struct drm_device *dev) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 794 | { |
| 795 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 796 | |
| 797 | /* deactivate cxsr */ |
| 798 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
| 799 | } |
| 800 | |
| 801 | /* |
| 802 | * Latency for FIFO fetches is dependent on several factors: |
| 803 | * - memory configuration (speed, channels) |
| 804 | * - chipset |
| 805 | * - current MCH state |
| 806 | * It can be fairly high in some situations, so here we assume a fairly |
| 807 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 808 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 809 | * and power consumption (set it too low to save power and we might see |
| 810 | * FIFO underruns and display "flicker"). |
| 811 | * |
| 812 | * A value of 5us seems to be a good balance; safe for very low end |
| 813 | * platforms but not overly aggressive on lower latency configs. |
| 814 | */ |
| 815 | static const int latency_ns = 5000; |
| 816 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 817 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 818 | { |
| 819 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 820 | uint32_t dsparb = I915_READ(DSPARB); |
| 821 | int size; |
| 822 | |
| 823 | size = dsparb & 0x7f; |
| 824 | if (plane) |
| 825 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
| 826 | |
| 827 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 828 | plane ? "B" : "A", size); |
| 829 | |
| 830 | return size; |
| 831 | } |
| 832 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 833 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 834 | { |
| 835 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 836 | uint32_t dsparb = I915_READ(DSPARB); |
| 837 | int size; |
| 838 | |
| 839 | size = dsparb & 0x1ff; |
| 840 | if (plane) |
| 841 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
| 842 | size >>= 1; /* Convert to cachelines */ |
| 843 | |
| 844 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 845 | plane ? "B" : "A", size); |
| 846 | |
| 847 | return size; |
| 848 | } |
| 849 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 850 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 851 | { |
| 852 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 853 | uint32_t dsparb = I915_READ(DSPARB); |
| 854 | int size; |
| 855 | |
| 856 | size = dsparb & 0x7f; |
| 857 | size >>= 2; /* Convert to cachelines */ |
| 858 | |
| 859 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 860 | plane ? "B" : "A", |
| 861 | size); |
| 862 | |
| 863 | return size; |
| 864 | } |
| 865 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 866 | /* Pineview has different values for various configs */ |
| 867 | static const struct intel_watermark_params pineview_display_wm = { |
| 868 | PINEVIEW_DISPLAY_FIFO, |
| 869 | PINEVIEW_MAX_WM, |
| 870 | PINEVIEW_DFT_WM, |
| 871 | PINEVIEW_GUARD_WM, |
| 872 | PINEVIEW_FIFO_LINE_SIZE |
| 873 | }; |
| 874 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
| 875 | PINEVIEW_DISPLAY_FIFO, |
| 876 | PINEVIEW_MAX_WM, |
| 877 | PINEVIEW_DFT_HPLLOFF_WM, |
| 878 | PINEVIEW_GUARD_WM, |
| 879 | PINEVIEW_FIFO_LINE_SIZE |
| 880 | }; |
| 881 | static const struct intel_watermark_params pineview_cursor_wm = { |
| 882 | PINEVIEW_CURSOR_FIFO, |
| 883 | PINEVIEW_CURSOR_MAX_WM, |
| 884 | PINEVIEW_CURSOR_DFT_WM, |
| 885 | PINEVIEW_CURSOR_GUARD_WM, |
| 886 | PINEVIEW_FIFO_LINE_SIZE, |
| 887 | }; |
| 888 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
| 889 | PINEVIEW_CURSOR_FIFO, |
| 890 | PINEVIEW_CURSOR_MAX_WM, |
| 891 | PINEVIEW_CURSOR_DFT_WM, |
| 892 | PINEVIEW_CURSOR_GUARD_WM, |
| 893 | PINEVIEW_FIFO_LINE_SIZE |
| 894 | }; |
| 895 | static const struct intel_watermark_params g4x_wm_info = { |
| 896 | G4X_FIFO_SIZE, |
| 897 | G4X_MAX_WM, |
| 898 | G4X_MAX_WM, |
| 899 | 2, |
| 900 | G4X_FIFO_LINE_SIZE, |
| 901 | }; |
| 902 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
| 903 | I965_CURSOR_FIFO, |
| 904 | I965_CURSOR_MAX_WM, |
| 905 | I965_CURSOR_DFT_WM, |
| 906 | 2, |
| 907 | G4X_FIFO_LINE_SIZE, |
| 908 | }; |
| 909 | static const struct intel_watermark_params valleyview_wm_info = { |
| 910 | VALLEYVIEW_FIFO_SIZE, |
| 911 | VALLEYVIEW_MAX_WM, |
| 912 | VALLEYVIEW_MAX_WM, |
| 913 | 2, |
| 914 | G4X_FIFO_LINE_SIZE, |
| 915 | }; |
| 916 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
| 917 | I965_CURSOR_FIFO, |
| 918 | VALLEYVIEW_CURSOR_MAX_WM, |
| 919 | I965_CURSOR_DFT_WM, |
| 920 | 2, |
| 921 | G4X_FIFO_LINE_SIZE, |
| 922 | }; |
| 923 | static const struct intel_watermark_params i965_cursor_wm_info = { |
| 924 | I965_CURSOR_FIFO, |
| 925 | I965_CURSOR_MAX_WM, |
| 926 | I965_CURSOR_DFT_WM, |
| 927 | 2, |
| 928 | I915_FIFO_LINE_SIZE, |
| 929 | }; |
| 930 | static const struct intel_watermark_params i945_wm_info = { |
| 931 | I945_FIFO_SIZE, |
| 932 | I915_MAX_WM, |
| 933 | 1, |
| 934 | 2, |
| 935 | I915_FIFO_LINE_SIZE |
| 936 | }; |
| 937 | static const struct intel_watermark_params i915_wm_info = { |
| 938 | I915_FIFO_SIZE, |
| 939 | I915_MAX_WM, |
| 940 | 1, |
| 941 | 2, |
| 942 | I915_FIFO_LINE_SIZE |
| 943 | }; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 944 | static const struct intel_watermark_params i830_wm_info = { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 945 | I855GM_FIFO_SIZE, |
| 946 | I915_MAX_WM, |
| 947 | 1, |
| 948 | 2, |
| 949 | I830_FIFO_LINE_SIZE |
| 950 | }; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 951 | static const struct intel_watermark_params i845_wm_info = { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 952 | I830_FIFO_SIZE, |
| 953 | I915_MAX_WM, |
| 954 | 1, |
| 955 | 2, |
| 956 | I830_FIFO_LINE_SIZE |
| 957 | }; |
| 958 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 959 | /** |
| 960 | * intel_calculate_wm - calculate watermark level |
| 961 | * @clock_in_khz: pixel clock |
| 962 | * @wm: chip FIFO params |
| 963 | * @pixel_size: display pixel size |
| 964 | * @latency_ns: memory latency for the platform |
| 965 | * |
| 966 | * Calculate the watermark level (the level at which the display plane will |
| 967 | * start fetching from memory again). Each chip has a different display |
| 968 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 969 | * in the correct intel_watermark_params structure. |
| 970 | * |
| 971 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 972 | * on the pixel size. When it reaches the watermark level, it'll start |
| 973 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 974 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 975 | * will occur, and a display engine hang could result. |
| 976 | */ |
| 977 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 978 | const struct intel_watermark_params *wm, |
| 979 | int fifo_size, |
| 980 | int pixel_size, |
| 981 | unsigned long latency_ns) |
| 982 | { |
| 983 | long entries_required, wm_size; |
| 984 | |
| 985 | /* |
| 986 | * Note: we need to make sure we don't overflow for various clock & |
| 987 | * latency values. |
| 988 | * clocks go from a few thousand to several hundred thousand. |
| 989 | * latency is usually a few thousand |
| 990 | */ |
| 991 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 992 | 1000; |
| 993 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
| 994 | |
| 995 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
| 996 | |
| 997 | wm_size = fifo_size - (entries_required + wm->guard_size); |
| 998 | |
| 999 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
| 1000 | |
| 1001 | /* Don't promote wm_size to unsigned... */ |
| 1002 | if (wm_size > (long)wm->max_wm) |
| 1003 | wm_size = wm->max_wm; |
| 1004 | if (wm_size <= 0) |
| 1005 | wm_size = wm->default_wm; |
| 1006 | return wm_size; |
| 1007 | } |
| 1008 | |
| 1009 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 1010 | { |
| 1011 | struct drm_crtc *crtc, *enabled = NULL; |
| 1012 | |
| 1013 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1014 | if (intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1015 | if (enabled) |
| 1016 | return NULL; |
| 1017 | enabled = crtc; |
| 1018 | } |
| 1019 | } |
| 1020 | |
| 1021 | return enabled; |
| 1022 | } |
| 1023 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1024 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1025 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1026 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1027 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1028 | struct drm_crtc *crtc; |
| 1029 | const struct cxsr_latency *latency; |
| 1030 | u32 reg; |
| 1031 | unsigned long wm; |
| 1032 | |
| 1033 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 1034 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 1035 | if (!latency) { |
| 1036 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 1037 | pineview_disable_cxsr(dev); |
| 1038 | return; |
| 1039 | } |
| 1040 | |
| 1041 | crtc = single_enabled_crtc(dev); |
| 1042 | if (crtc) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1043 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1044 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1045 | int clock; |
| 1046 | |
| 1047 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1048 | clock = adjusted_mode->crtc_clock; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1049 | |
| 1050 | /* Display SR */ |
| 1051 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 1052 | pineview_display_wm.fifo_size, |
| 1053 | pixel_size, latency->display_sr); |
| 1054 | reg = I915_READ(DSPFW1); |
| 1055 | reg &= ~DSPFW_SR_MASK; |
| 1056 | reg |= wm << DSPFW_SR_SHIFT; |
| 1057 | I915_WRITE(DSPFW1, reg); |
| 1058 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 1059 | |
| 1060 | /* cursor SR */ |
| 1061 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 1062 | pineview_display_wm.fifo_size, |
| 1063 | pixel_size, latency->cursor_sr); |
| 1064 | reg = I915_READ(DSPFW3); |
| 1065 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 1066 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 1067 | I915_WRITE(DSPFW3, reg); |
| 1068 | |
| 1069 | /* Display HPLL off SR */ |
| 1070 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 1071 | pineview_display_hplloff_wm.fifo_size, |
| 1072 | pixel_size, latency->display_hpll_disable); |
| 1073 | reg = I915_READ(DSPFW3); |
| 1074 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 1075 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 1076 | I915_WRITE(DSPFW3, reg); |
| 1077 | |
| 1078 | /* cursor HPLL off SR */ |
| 1079 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 1080 | pineview_display_hplloff_wm.fifo_size, |
| 1081 | pixel_size, latency->cursor_hpll_disable); |
| 1082 | reg = I915_READ(DSPFW3); |
| 1083 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 1084 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 1085 | I915_WRITE(DSPFW3, reg); |
| 1086 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 1087 | |
| 1088 | /* activate cxsr */ |
| 1089 | I915_WRITE(DSPFW3, |
| 1090 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); |
| 1091 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
| 1092 | } else { |
| 1093 | pineview_disable_cxsr(dev); |
| 1094 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); |
| 1095 | } |
| 1096 | } |
| 1097 | |
| 1098 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 1099 | int plane, |
| 1100 | const struct intel_watermark_params *display, |
| 1101 | int display_latency_ns, |
| 1102 | const struct intel_watermark_params *cursor, |
| 1103 | int cursor_latency_ns, |
| 1104 | int *plane_wm, |
| 1105 | int *cursor_wm) |
| 1106 | { |
| 1107 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1108 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1109 | int htotal, hdisplay, clock, pixel_size; |
| 1110 | int line_time_us, line_count; |
| 1111 | int entries, tlb_miss; |
| 1112 | |
| 1113 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1114 | if (!intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1115 | *cursor_wm = cursor->guard_size; |
| 1116 | *plane_wm = display->guard_size; |
| 1117 | return false; |
| 1118 | } |
| 1119 | |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1120 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1121 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1122 | htotal = adjusted_mode->crtc_htotal; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1123 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1124 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1125 | |
| 1126 | /* Use the small buffer method to calculate plane watermark */ |
| 1127 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 1128 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 1129 | if (tlb_miss > 0) |
| 1130 | entries += tlb_miss; |
| 1131 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 1132 | *plane_wm = entries + display->guard_size; |
| 1133 | if (*plane_wm > (int)display->max_wm) |
| 1134 | *plane_wm = display->max_wm; |
| 1135 | |
| 1136 | /* Use the large buffer method to calculate cursor watermark */ |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1137 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1138 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1139 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1140 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 1141 | if (tlb_miss > 0) |
| 1142 | entries += tlb_miss; |
| 1143 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1144 | *cursor_wm = entries + cursor->guard_size; |
| 1145 | if (*cursor_wm > (int)cursor->max_wm) |
| 1146 | *cursor_wm = (int)cursor->max_wm; |
| 1147 | |
| 1148 | return true; |
| 1149 | } |
| 1150 | |
| 1151 | /* |
| 1152 | * Check the wm result. |
| 1153 | * |
| 1154 | * If any calculated watermark values is larger than the maximum value that |
| 1155 | * can be programmed into the associated watermark register, that watermark |
| 1156 | * must be disabled. |
| 1157 | */ |
| 1158 | static bool g4x_check_srwm(struct drm_device *dev, |
| 1159 | int display_wm, int cursor_wm, |
| 1160 | const struct intel_watermark_params *display, |
| 1161 | const struct intel_watermark_params *cursor) |
| 1162 | { |
| 1163 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 1164 | display_wm, cursor_wm); |
| 1165 | |
| 1166 | if (display_wm > display->max_wm) { |
| 1167 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
| 1168 | display_wm, display->max_wm); |
| 1169 | return false; |
| 1170 | } |
| 1171 | |
| 1172 | if (cursor_wm > cursor->max_wm) { |
| 1173 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
| 1174 | cursor_wm, cursor->max_wm); |
| 1175 | return false; |
| 1176 | } |
| 1177 | |
| 1178 | if (!(display_wm || cursor_wm)) { |
| 1179 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 1180 | return false; |
| 1181 | } |
| 1182 | |
| 1183 | return true; |
| 1184 | } |
| 1185 | |
| 1186 | static bool g4x_compute_srwm(struct drm_device *dev, |
| 1187 | int plane, |
| 1188 | int latency_ns, |
| 1189 | const struct intel_watermark_params *display, |
| 1190 | const struct intel_watermark_params *cursor, |
| 1191 | int *display_wm, int *cursor_wm) |
| 1192 | { |
| 1193 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1194 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1195 | int hdisplay, htotal, pixel_size, clock; |
| 1196 | unsigned long line_time_us; |
| 1197 | int line_count, line_size; |
| 1198 | int small, large; |
| 1199 | int entries; |
| 1200 | |
| 1201 | if (!latency_ns) { |
| 1202 | *display_wm = *cursor_wm = 0; |
| 1203 | return false; |
| 1204 | } |
| 1205 | |
| 1206 | crtc = intel_get_crtc_for_plane(dev, plane); |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1207 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1208 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1209 | htotal = adjusted_mode->crtc_htotal; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1210 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1211 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1212 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1213 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1214 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1215 | line_size = hdisplay * pixel_size; |
| 1216 | |
| 1217 | /* Use the minimum of the small and large buffer method for primary */ |
| 1218 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1219 | large = line_count * line_size; |
| 1220 | |
| 1221 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1222 | *display_wm = entries + display->guard_size; |
| 1223 | |
| 1224 | /* calculate the self-refresh watermark for display cursor */ |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1225 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1226 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1227 | *cursor_wm = entries + cursor->guard_size; |
| 1228 | |
| 1229 | return g4x_check_srwm(dev, |
| 1230 | *display_wm, *cursor_wm, |
| 1231 | display, cursor); |
| 1232 | } |
| 1233 | |
| 1234 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
| 1235 | int plane, |
| 1236 | int *plane_prec_mult, |
| 1237 | int *plane_dl, |
| 1238 | int *cursor_prec_mult, |
| 1239 | int *cursor_dl) |
| 1240 | { |
| 1241 | struct drm_crtc *crtc; |
| 1242 | int clock, pixel_size; |
| 1243 | int entries; |
| 1244 | |
| 1245 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1246 | if (!intel_crtc_active(crtc)) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1247 | return false; |
| 1248 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1249 | clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1250 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1251 | |
| 1252 | entries = (clock / 1000) * pixel_size; |
| 1253 | *plane_prec_mult = (entries > 256) ? |
| 1254 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
| 1255 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * |
| 1256 | pixel_size); |
| 1257 | |
| 1258 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ |
| 1259 | *cursor_prec_mult = (entries > 256) ? |
| 1260 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; |
| 1261 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); |
| 1262 | |
| 1263 | return true; |
| 1264 | } |
| 1265 | |
| 1266 | /* |
| 1267 | * Update drain latency registers of memory arbiter |
| 1268 | * |
| 1269 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
| 1270 | * to be programmed. Each plane has a drain latency multiplier and a drain |
| 1271 | * latency value. |
| 1272 | */ |
| 1273 | |
| 1274 | static void vlv_update_drain_latency(struct drm_device *dev) |
| 1275 | { |
| 1276 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1277 | int planea_prec, planea_dl, planeb_prec, planeb_dl; |
| 1278 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; |
| 1279 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is |
| 1280 | either 16 or 32 */ |
| 1281 | |
| 1282 | /* For plane A, Cursor A */ |
| 1283 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, |
| 1284 | &cursor_prec_mult, &cursora_dl)) { |
| 1285 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1286 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; |
| 1287 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1288 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; |
| 1289 | |
| 1290 | I915_WRITE(VLV_DDL1, cursora_prec | |
| 1291 | (cursora_dl << DDL_CURSORA_SHIFT) | |
| 1292 | planea_prec | planea_dl); |
| 1293 | } |
| 1294 | |
| 1295 | /* For plane B, Cursor B */ |
| 1296 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, |
| 1297 | &cursor_prec_mult, &cursorb_dl)) { |
| 1298 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1299 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; |
| 1300 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? |
| 1301 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; |
| 1302 | |
| 1303 | I915_WRITE(VLV_DDL2, cursorb_prec | |
| 1304 | (cursorb_dl << DDL_CURSORB_SHIFT) | |
| 1305 | planeb_prec | planeb_dl); |
| 1306 | } |
| 1307 | } |
| 1308 | |
| 1309 | #define single_plane_enabled(mask) is_power_of_2(mask) |
| 1310 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1311 | static void valleyview_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1312 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1313 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1314 | static const int sr_latency_ns = 12000; |
| 1315 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1316 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1317 | int plane_sr, cursor_sr; |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 1318 | int ignore_plane_sr, ignore_cursor_sr; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1319 | unsigned int enabled = 0; |
| 1320 | |
| 1321 | vlv_update_drain_latency(dev); |
| 1322 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1323 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1324 | &valleyview_wm_info, latency_ns, |
| 1325 | &valleyview_cursor_wm_info, latency_ns, |
| 1326 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1327 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1328 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1329 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1330 | &valleyview_wm_info, latency_ns, |
| 1331 | &valleyview_cursor_wm_info, latency_ns, |
| 1332 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1333 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1334 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1335 | if (single_plane_enabled(enabled) && |
| 1336 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1337 | sr_latency_ns, |
| 1338 | &valleyview_wm_info, |
| 1339 | &valleyview_cursor_wm_info, |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 1340 | &plane_sr, &ignore_cursor_sr) && |
| 1341 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1342 | 2*sr_latency_ns, |
| 1343 | &valleyview_wm_info, |
| 1344 | &valleyview_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1345 | &ignore_plane_sr, &cursor_sr)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1346 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1347 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1348 | I915_WRITE(FW_BLC_SELF_VLV, |
| 1349 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1350 | plane_sr = cursor_sr = 0; |
| 1351 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1352 | |
| 1353 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 1354 | planea_wm, cursora_wm, |
| 1355 | planeb_wm, cursorb_wm, |
| 1356 | plane_sr, cursor_sr); |
| 1357 | |
| 1358 | I915_WRITE(DSPFW1, |
| 1359 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1360 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1361 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1362 | planea_wm); |
| 1363 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1364 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1365 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1366 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1367 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
| 1368 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1369 | } |
| 1370 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1371 | static void g4x_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1372 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1373 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1374 | static const int sr_latency_ns = 12000; |
| 1375 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1376 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1377 | int plane_sr, cursor_sr; |
| 1378 | unsigned int enabled = 0; |
| 1379 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1380 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1381 | &g4x_wm_info, latency_ns, |
| 1382 | &g4x_cursor_wm_info, latency_ns, |
| 1383 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1384 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1385 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1386 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1387 | &g4x_wm_info, latency_ns, |
| 1388 | &g4x_cursor_wm_info, latency_ns, |
| 1389 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1390 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1391 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1392 | if (single_plane_enabled(enabled) && |
| 1393 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1394 | sr_latency_ns, |
| 1395 | &g4x_wm_info, |
| 1396 | &g4x_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1397 | &plane_sr, &cursor_sr)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1398 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1399 | } else { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1400 | I915_WRITE(FW_BLC_SELF, |
| 1401 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1402 | plane_sr = cursor_sr = 0; |
| 1403 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1404 | |
| 1405 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
| 1406 | planea_wm, cursora_wm, |
| 1407 | planeb_wm, cursorb_wm, |
| 1408 | plane_sr, cursor_sr); |
| 1409 | |
| 1410 | I915_WRITE(DSPFW1, |
| 1411 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1412 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1413 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1414 | planea_wm); |
| 1415 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1416 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1417 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1418 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 1419 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1420 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1421 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1422 | } |
| 1423 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1424 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1425 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1426 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1427 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1428 | struct drm_crtc *crtc; |
| 1429 | int srwm = 1; |
| 1430 | int cursor_sr = 16; |
| 1431 | |
| 1432 | /* Calc sr entries for one plane configs */ |
| 1433 | crtc = single_enabled_crtc(dev); |
| 1434 | if (crtc) { |
| 1435 | /* self-refresh has much higher latency */ |
| 1436 | static const int sr_latency_ns = 12000; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1437 | const struct drm_display_mode *adjusted_mode = |
| 1438 | &to_intel_crtc(crtc)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1439 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1440 | int htotal = adjusted_mode->crtc_htotal; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1441 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1442 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1443 | unsigned long line_time_us; |
| 1444 | int entries; |
| 1445 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1446 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1447 | |
| 1448 | /* Use ns/us then divide to preserve precision */ |
| 1449 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1450 | pixel_size * hdisplay; |
| 1451 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
| 1452 | srwm = I965_FIFO_SIZE - entries; |
| 1453 | if (srwm < 0) |
| 1454 | srwm = 1; |
| 1455 | srwm &= 0x1ff; |
| 1456 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 1457 | entries, srwm); |
| 1458 | |
| 1459 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1460 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1461 | entries = DIV_ROUND_UP(entries, |
| 1462 | i965_cursor_wm_info.cacheline_size); |
| 1463 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 1464 | (entries + i965_cursor_wm_info.guard_size); |
| 1465 | |
| 1466 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 1467 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 1468 | |
| 1469 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 1470 | "cursor %d\n", srwm, cursor_sr); |
| 1471 | |
| 1472 | if (IS_CRESTLINE(dev)) |
| 1473 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 1474 | } else { |
| 1475 | /* Turn off self refresh if both pipes are enabled */ |
| 1476 | if (IS_CRESTLINE(dev)) |
| 1477 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
| 1478 | & ~FW_BLC_SELF_EN); |
| 1479 | } |
| 1480 | |
| 1481 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 1482 | srwm); |
| 1483 | |
| 1484 | /* 965 has limitations... */ |
| 1485 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
| 1486 | (8 << 16) | (8 << 8) | (8 << 0)); |
| 1487 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
| 1488 | /* update cursor SR watermark */ |
| 1489 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1490 | } |
| 1491 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1492 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1493 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1494 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1496 | const struct intel_watermark_params *wm_info; |
| 1497 | uint32_t fwater_lo; |
| 1498 | uint32_t fwater_hi; |
| 1499 | int cwm, srwm = 1; |
| 1500 | int fifo_size; |
| 1501 | int planea_wm, planeb_wm; |
| 1502 | struct drm_crtc *crtc, *enabled = NULL; |
| 1503 | |
| 1504 | if (IS_I945GM(dev)) |
| 1505 | wm_info = &i945_wm_info; |
| 1506 | else if (!IS_GEN2(dev)) |
| 1507 | wm_info = &i915_wm_info; |
| 1508 | else |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1509 | wm_info = &i830_wm_info; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1510 | |
| 1511 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 1512 | crtc = intel_get_crtc_for_plane(dev, 0); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1513 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1514 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1515 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1516 | if (IS_GEN2(dev)) |
| 1517 | cpp = 4; |
| 1518 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1519 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1520 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1521 | wm_info, fifo_size, cpp, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1522 | latency_ns); |
| 1523 | enabled = crtc; |
| 1524 | } else |
| 1525 | planea_wm = fifo_size - wm_info->guard_size; |
| 1526 | |
| 1527 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 1528 | crtc = intel_get_crtc_for_plane(dev, 1); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1529 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1530 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1531 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1532 | if (IS_GEN2(dev)) |
| 1533 | cpp = 4; |
| 1534 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1535 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1536 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1537 | wm_info, fifo_size, cpp, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1538 | latency_ns); |
| 1539 | if (enabled == NULL) |
| 1540 | enabled = crtc; |
| 1541 | else |
| 1542 | enabled = NULL; |
| 1543 | } else |
| 1544 | planeb_wm = fifo_size - wm_info->guard_size; |
| 1545 | |
| 1546 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 1547 | |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1548 | if (IS_I915GM(dev) && enabled) { |
| 1549 | struct intel_framebuffer *fb; |
| 1550 | |
| 1551 | fb = to_intel_framebuffer(enabled->primary->fb); |
| 1552 | |
| 1553 | /* self-refresh seems busted with untiled */ |
| 1554 | if (fb->obj->tiling_mode == I915_TILING_NONE) |
| 1555 | enabled = NULL; |
| 1556 | } |
| 1557 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1558 | /* |
| 1559 | * Overlay gets an aggressive default since video jitter is bad. |
| 1560 | */ |
| 1561 | cwm = 2; |
| 1562 | |
| 1563 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
| 1564 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1565 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); |
| 1566 | else if (IS_I915GM(dev)) |
Ville Syrjälä | 3f2dc5a | 2014-01-10 14:06:47 +0200 | [diff] [blame] | 1567 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1568 | |
| 1569 | /* Calc sr entries for one plane configs */ |
| 1570 | if (HAS_FW_BLC(dev) && enabled) { |
| 1571 | /* self-refresh has much higher latency */ |
| 1572 | static const int sr_latency_ns = 6000; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1573 | const struct drm_display_mode *adjusted_mode = |
| 1574 | &to_intel_crtc(enabled)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1575 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1576 | int htotal = adjusted_mode->crtc_htotal; |
Daniel Vetter | f727b49 | 2013-11-20 15:02:10 +0100 | [diff] [blame] | 1577 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1578 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1579 | unsigned long line_time_us; |
| 1580 | int entries; |
| 1581 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1582 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1583 | |
| 1584 | /* Use ns/us then divide to preserve precision */ |
| 1585 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1586 | pixel_size * hdisplay; |
| 1587 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 1588 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 1589 | srwm = wm_info->fifo_size - entries; |
| 1590 | if (srwm < 0) |
| 1591 | srwm = 1; |
| 1592 | |
| 1593 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1594 | I915_WRITE(FW_BLC_SELF, |
| 1595 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 1596 | else if (IS_I915GM(dev)) |
| 1597 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 1598 | } |
| 1599 | |
| 1600 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
| 1601 | planea_wm, planeb_wm, cwm, srwm); |
| 1602 | |
| 1603 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 1604 | fwater_hi = (cwm & 0x1f); |
| 1605 | |
| 1606 | /* Set request length to 8 cachelines per fetch */ |
| 1607 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 1608 | fwater_hi = fwater_hi | (1 << 8); |
| 1609 | |
| 1610 | I915_WRITE(FW_BLC, fwater_lo); |
| 1611 | I915_WRITE(FW_BLC2, fwater_hi); |
| 1612 | |
| 1613 | if (HAS_FW_BLC(dev)) { |
| 1614 | if (enabled) { |
| 1615 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1616 | I915_WRITE(FW_BLC_SELF, |
| 1617 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); |
| 1618 | else if (IS_I915GM(dev)) |
Ville Syrjälä | 3f2dc5a | 2014-01-10 14:06:47 +0200 | [diff] [blame] | 1619 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1620 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
| 1621 | } else |
| 1622 | DRM_DEBUG_KMS("memory self refresh disabled\n"); |
| 1623 | } |
| 1624 | } |
| 1625 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1626 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1627 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1628 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1629 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1630 | struct drm_crtc *crtc; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1631 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1632 | uint32_t fwater_lo; |
| 1633 | int planea_wm; |
| 1634 | |
| 1635 | crtc = single_enabled_crtc(dev); |
| 1636 | if (crtc == NULL) |
| 1637 | return; |
| 1638 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1639 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1640 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1641 | &i845_wm_info, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1642 | dev_priv->display.get_fifo_size(dev, 0), |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1643 | 4, latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1644 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
| 1645 | fwater_lo |= (3<<8) | planea_wm; |
| 1646 | |
| 1647 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
| 1648 | |
| 1649 | I915_WRITE(FW_BLC, fwater_lo); |
| 1650 | } |
| 1651 | |
Ville Syrjälä | 3658729 | 2013-07-05 11:57:16 +0300 | [diff] [blame] | 1652 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
| 1653 | struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1654 | { |
| 1655 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1656 | uint32_t pixel_rate; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1657 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1658 | pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1659 | |
| 1660 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
| 1661 | * adjust the pixel_rate here. */ |
| 1662 | |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1663 | if (intel_crtc->config.pch_pfit.enabled) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1664 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1665 | uint32_t pfit_size = intel_crtc->config.pch_pfit.size; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1666 | |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1667 | pipe_w = intel_crtc->config.pipe_src_w; |
| 1668 | pipe_h = intel_crtc->config.pipe_src_h; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1669 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
| 1670 | pfit_h = pfit_size & 0xFFFF; |
| 1671 | if (pipe_w < pfit_w) |
| 1672 | pipe_w = pfit_w; |
| 1673 | if (pipe_h < pfit_h) |
| 1674 | pipe_h = pfit_h; |
| 1675 | |
| 1676 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
| 1677 | pfit_w * pfit_h); |
| 1678 | } |
| 1679 | |
| 1680 | return pixel_rate; |
| 1681 | } |
| 1682 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1683 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1684 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1685 | uint32_t latency) |
| 1686 | { |
| 1687 | uint64_t ret; |
| 1688 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1689 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1690 | return UINT_MAX; |
| 1691 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1692 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
| 1693 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
| 1694 | |
| 1695 | return ret; |
| 1696 | } |
| 1697 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1698 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1699 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1700 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
| 1701 | uint32_t latency) |
| 1702 | { |
| 1703 | uint32_t ret; |
| 1704 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1705 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1706 | return UINT_MAX; |
| 1707 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1708 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
| 1709 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
| 1710 | ret = DIV_ROUND_UP(ret, 64) + 2; |
| 1711 | return ret; |
| 1712 | } |
| 1713 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1714 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1715 | uint8_t bytes_per_pixel) |
| 1716 | { |
| 1717 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
| 1718 | } |
| 1719 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1720 | struct ilk_pipe_wm_parameters { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1721 | bool active; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1722 | uint32_t pipe_htotal; |
| 1723 | uint32_t pixel_rate; |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1724 | struct intel_plane_wm_parameters pri; |
| 1725 | struct intel_plane_wm_parameters spr; |
| 1726 | struct intel_plane_wm_parameters cur; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1727 | }; |
| 1728 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1729 | struct ilk_wm_maximums { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1730 | uint16_t pri; |
| 1731 | uint16_t spr; |
| 1732 | uint16_t cur; |
| 1733 | uint16_t fbc; |
| 1734 | }; |
| 1735 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1736 | /* used in computing the new watermarks state */ |
| 1737 | struct intel_wm_config { |
| 1738 | unsigned int num_pipes_active; |
| 1739 | bool sprites_enabled; |
| 1740 | bool sprites_scaled; |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1741 | }; |
| 1742 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1743 | /* |
| 1744 | * For both WM_PIPE and WM_LP. |
| 1745 | * mem_value must be in 0.1us units. |
| 1746 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1747 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1748 | uint32_t mem_value, |
| 1749 | bool is_lp) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1750 | { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1751 | uint32_t method1, method2; |
| 1752 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1753 | if (!params->active || !params->pri.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1754 | return 0; |
| 1755 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1756 | method1 = ilk_wm_method1(params->pixel_rate, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1757 | params->pri.bytes_per_pixel, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1758 | mem_value); |
| 1759 | |
| 1760 | if (!is_lp) |
| 1761 | return method1; |
| 1762 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1763 | method2 = ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1764 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1765 | params->pri.horiz_pixels, |
| 1766 | params->pri.bytes_per_pixel, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1767 | mem_value); |
| 1768 | |
| 1769 | return min(method1, method2); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1770 | } |
| 1771 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1772 | /* |
| 1773 | * For both WM_PIPE and WM_LP. |
| 1774 | * mem_value must be in 0.1us units. |
| 1775 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1776 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1777 | uint32_t mem_value) |
| 1778 | { |
| 1779 | uint32_t method1, method2; |
| 1780 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1781 | if (!params->active || !params->spr.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1782 | return 0; |
| 1783 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1784 | method1 = ilk_wm_method1(params->pixel_rate, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1785 | params->spr.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1786 | mem_value); |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1787 | method2 = ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1788 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1789 | params->spr.horiz_pixels, |
| 1790 | params->spr.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1791 | mem_value); |
| 1792 | return min(method1, method2); |
| 1793 | } |
| 1794 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1795 | /* |
| 1796 | * For both WM_PIPE and WM_LP. |
| 1797 | * mem_value must be in 0.1us units. |
| 1798 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1799 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1800 | uint32_t mem_value) |
| 1801 | { |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1802 | if (!params->active || !params->cur.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1803 | return 0; |
| 1804 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1805 | return ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1806 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1807 | params->cur.horiz_pixels, |
| 1808 | params->cur.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1809 | mem_value); |
| 1810 | } |
| 1811 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1812 | /* Only for WM_LP. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1813 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
Ville Syrjälä | 1fda988 | 2013-07-05 11:57:19 +0300 | [diff] [blame] | 1814 | uint32_t pri_val) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1815 | { |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1816 | if (!params->active || !params->pri.enabled) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1817 | return 0; |
| 1818 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1819 | return ilk_wm_fbc(pri_val, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1820 | params->pri.horiz_pixels, |
| 1821 | params->pri.bytes_per_pixel); |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1822 | } |
| 1823 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1824 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
| 1825 | { |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 1826 | if (INTEL_INFO(dev)->gen >= 8) |
| 1827 | return 3072; |
| 1828 | else if (INTEL_INFO(dev)->gen >= 7) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1829 | return 768; |
| 1830 | else |
| 1831 | return 512; |
| 1832 | } |
| 1833 | |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1834 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
| 1835 | int level, bool is_sprite) |
| 1836 | { |
| 1837 | if (INTEL_INFO(dev)->gen >= 8) |
| 1838 | /* BDW primary/sprite plane watermarks */ |
| 1839 | return level == 0 ? 255 : 2047; |
| 1840 | else if (INTEL_INFO(dev)->gen >= 7) |
| 1841 | /* IVB/HSW primary/sprite plane watermarks */ |
| 1842 | return level == 0 ? 127 : 1023; |
| 1843 | else if (!is_sprite) |
| 1844 | /* ILK/SNB primary plane watermarks */ |
| 1845 | return level == 0 ? 127 : 511; |
| 1846 | else |
| 1847 | /* ILK/SNB sprite plane watermarks */ |
| 1848 | return level == 0 ? 63 : 255; |
| 1849 | } |
| 1850 | |
| 1851 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, |
| 1852 | int level) |
| 1853 | { |
| 1854 | if (INTEL_INFO(dev)->gen >= 7) |
| 1855 | return level == 0 ? 63 : 255; |
| 1856 | else |
| 1857 | return level == 0 ? 31 : 63; |
| 1858 | } |
| 1859 | |
| 1860 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) |
| 1861 | { |
| 1862 | if (INTEL_INFO(dev)->gen >= 8) |
| 1863 | return 31; |
| 1864 | else |
| 1865 | return 15; |
| 1866 | } |
| 1867 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1868 | /* Calculate the maximum primary/sprite plane watermark */ |
| 1869 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, |
| 1870 | int level, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1871 | const struct intel_wm_config *config, |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1872 | enum intel_ddb_partitioning ddb_partitioning, |
| 1873 | bool is_sprite) |
| 1874 | { |
| 1875 | unsigned int fifo_size = ilk_display_fifo_size(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1876 | |
| 1877 | /* if sprites aren't enabled, sprites get nothing */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1878 | if (is_sprite && !config->sprites_enabled) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1879 | return 0; |
| 1880 | |
| 1881 | /* HSW allows LP1+ watermarks even with multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1882 | if (level == 0 || config->num_pipes_active > 1) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1883 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
| 1884 | |
| 1885 | /* |
| 1886 | * For some reason the non self refresh |
| 1887 | * FIFO size is only half of the self |
| 1888 | * refresh FIFO size on ILK/SNB. |
| 1889 | */ |
| 1890 | if (INTEL_INFO(dev)->gen <= 6) |
| 1891 | fifo_size /= 2; |
| 1892 | } |
| 1893 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1894 | if (config->sprites_enabled) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1895 | /* level 0 is always calculated with 1:1 split */ |
| 1896 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { |
| 1897 | if (is_sprite) |
| 1898 | fifo_size *= 5; |
| 1899 | fifo_size /= 6; |
| 1900 | } else { |
| 1901 | fifo_size /= 2; |
| 1902 | } |
| 1903 | } |
| 1904 | |
| 1905 | /* clamp to max that the registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1906 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1907 | } |
| 1908 | |
| 1909 | /* Calculate the maximum cursor plane watermark */ |
| 1910 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1911 | int level, |
| 1912 | const struct intel_wm_config *config) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1913 | { |
| 1914 | /* HSW LP1+ watermarks w/ multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1915 | if (level > 0 && config->num_pipes_active > 1) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1916 | return 64; |
| 1917 | |
| 1918 | /* otherwise just report max that registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1919 | return ilk_cursor_wm_reg_max(dev, level); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1920 | } |
| 1921 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 1922 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 1923 | int level, |
| 1924 | const struct intel_wm_config *config, |
| 1925 | enum intel_ddb_partitioning ddb_partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1926 | struct ilk_wm_maximums *max) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1927 | { |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1928 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
| 1929 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); |
| 1930 | max->cur = ilk_cursor_wm_max(dev, level, config); |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1931 | max->fbc = ilk_fbc_wm_reg_max(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1932 | } |
| 1933 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 1934 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
| 1935 | int level, |
| 1936 | struct ilk_wm_maximums *max) |
| 1937 | { |
| 1938 | max->pri = ilk_plane_wm_reg_max(dev, level, false); |
| 1939 | max->spr = ilk_plane_wm_reg_max(dev, level, true); |
| 1940 | max->cur = ilk_cursor_wm_reg_max(dev, level); |
| 1941 | max->fbc = ilk_fbc_wm_reg_max(dev); |
| 1942 | } |
| 1943 | |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 1944 | static bool ilk_validate_wm_level(int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1945 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 1946 | struct intel_wm_level *result) |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 1947 | { |
| 1948 | bool ret; |
| 1949 | |
| 1950 | /* already determined to be invalid? */ |
| 1951 | if (!result->enable) |
| 1952 | return false; |
| 1953 | |
| 1954 | result->enable = result->pri_val <= max->pri && |
| 1955 | result->spr_val <= max->spr && |
| 1956 | result->cur_val <= max->cur; |
| 1957 | |
| 1958 | ret = result->enable; |
| 1959 | |
| 1960 | /* |
| 1961 | * HACK until we can pre-compute everything, |
| 1962 | * and thus fail gracefully if LP0 watermarks |
| 1963 | * are exceeded... |
| 1964 | */ |
| 1965 | if (level == 0 && !result->enable) { |
| 1966 | if (result->pri_val > max->pri) |
| 1967 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", |
| 1968 | level, result->pri_val, max->pri); |
| 1969 | if (result->spr_val > max->spr) |
| 1970 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", |
| 1971 | level, result->spr_val, max->spr); |
| 1972 | if (result->cur_val > max->cur) |
| 1973 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", |
| 1974 | level, result->cur_val, max->cur); |
| 1975 | |
| 1976 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); |
| 1977 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); |
| 1978 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); |
| 1979 | result->enable = true; |
| 1980 | } |
| 1981 | |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 1982 | return ret; |
| 1983 | } |
| 1984 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 1985 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 1986 | int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1987 | const struct ilk_pipe_wm_parameters *p, |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 1988 | struct intel_wm_level *result) |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 1989 | { |
| 1990 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
| 1991 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; |
| 1992 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; |
| 1993 | |
| 1994 | /* WM1+ latency values stored in 0.5us units */ |
| 1995 | if (level > 0) { |
| 1996 | pri_latency *= 5; |
| 1997 | spr_latency *= 5; |
| 1998 | cur_latency *= 5; |
| 1999 | } |
| 2000 | |
| 2001 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); |
| 2002 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); |
| 2003 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); |
| 2004 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); |
| 2005 | result->enable = true; |
| 2006 | } |
| 2007 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2008 | static uint32_t |
| 2009 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2010 | { |
| 2011 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2012 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2013 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2014 | u32 linetime, ips_linetime; |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2015 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2016 | if (!intel_crtc_active(crtc)) |
| 2017 | return 0; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2018 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2019 | /* The WM are computed with base on how long it takes to fill a single |
| 2020 | * row at the given clock rate, multiplied by 8. |
| 2021 | * */ |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 2022 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
| 2023 | mode->crtc_clock); |
| 2024 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2025 | intel_ddi_get_cdclk_freq(dev_priv)); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2026 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2027 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
| 2028 | PIPE_WM_LINETIME_TIME(linetime); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2029 | } |
| 2030 | |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2031 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2032 | { |
| 2033 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2034 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2035 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2036 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
| 2037 | |
| 2038 | wm[0] = (sskpd >> 56) & 0xFF; |
| 2039 | if (wm[0] == 0) |
| 2040 | wm[0] = sskpd & 0xF; |
Ville Syrjälä | e5d5019 | 2013-07-05 11:57:22 +0300 | [diff] [blame] | 2041 | wm[1] = (sskpd >> 4) & 0xFF; |
| 2042 | wm[2] = (sskpd >> 12) & 0xFF; |
| 2043 | wm[3] = (sskpd >> 20) & 0x1FF; |
| 2044 | wm[4] = (sskpd >> 32) & 0x1FF; |
Ville Syrjälä | 63cf9a1 | 2013-07-05 11:57:23 +0300 | [diff] [blame] | 2045 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 2046 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
| 2047 | |
| 2048 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; |
| 2049 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; |
| 2050 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; |
| 2051 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; |
Ville Syrjälä | 3a88d0a | 2013-08-01 16:18:49 +0300 | [diff] [blame] | 2052 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 2053 | uint32_t mltr = I915_READ(MLTR_ILK); |
| 2054 | |
| 2055 | /* ILK primary LP0 latency is 700 ns */ |
| 2056 | wm[0] = 7; |
| 2057 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; |
| 2058 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2059 | } |
| 2060 | } |
| 2061 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2062 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2063 | { |
| 2064 | /* ILK sprite LP0 latency is 1300 ns */ |
| 2065 | if (INTEL_INFO(dev)->gen == 5) |
| 2066 | wm[0] = 13; |
| 2067 | } |
| 2068 | |
| 2069 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2070 | { |
| 2071 | /* ILK cursor LP0 latency is 1300 ns */ |
| 2072 | if (INTEL_INFO(dev)->gen == 5) |
| 2073 | wm[0] = 13; |
| 2074 | |
| 2075 | /* WaDoubleCursorLP3Latency:ivb */ |
| 2076 | if (IS_IVYBRIDGE(dev)) |
| 2077 | wm[3] *= 2; |
| 2078 | } |
| 2079 | |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2080 | static int ilk_wm_max_level(const struct drm_device *dev) |
| 2081 | { |
| 2082 | /* how many WM levels are we expecting */ |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2083 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2084 | return 4; |
| 2085 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2086 | return 3; |
| 2087 | else |
| 2088 | return 2; |
| 2089 | } |
| 2090 | |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2091 | static void intel_print_wm_latency(struct drm_device *dev, |
| 2092 | const char *name, |
| 2093 | const uint16_t wm[5]) |
| 2094 | { |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2095 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2096 | |
| 2097 | for (level = 0; level <= max_level; level++) { |
| 2098 | unsigned int latency = wm[level]; |
| 2099 | |
| 2100 | if (latency == 0) { |
| 2101 | DRM_ERROR("%s WM%d latency not provided\n", |
| 2102 | name, level); |
| 2103 | continue; |
| 2104 | } |
| 2105 | |
| 2106 | /* WM1+ latency values in 0.5us units */ |
| 2107 | if (level > 0) |
| 2108 | latency *= 5; |
| 2109 | |
| 2110 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", |
| 2111 | name, level, wm[level], |
| 2112 | latency / 10, latency % 10); |
| 2113 | } |
| 2114 | } |
| 2115 | |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 2116 | static void ilk_setup_wm_latency(struct drm_device *dev) |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2117 | { |
| 2118 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2119 | |
| 2120 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); |
| 2121 | |
| 2122 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, |
| 2123 | sizeof(dev_priv->wm.pri_latency)); |
| 2124 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, |
| 2125 | sizeof(dev_priv->wm.pri_latency)); |
| 2126 | |
| 2127 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); |
| 2128 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2129 | |
| 2130 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 2131 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 2132 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2133 | } |
| 2134 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2135 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2136 | struct ilk_pipe_wm_parameters *p) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2137 | { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2138 | struct drm_device *dev = crtc->dev; |
| 2139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2140 | enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2141 | struct drm_plane *plane; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2142 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2143 | if (!intel_crtc_active(crtc)) |
| 2144 | return; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2145 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2146 | p->active = true; |
| 2147 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; |
| 2148 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
| 2149 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; |
| 2150 | p->cur.bytes_per_pixel = 4; |
| 2151 | p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; |
| 2152 | p->cur.horiz_pixels = intel_crtc->cursor_width; |
| 2153 | /* TODO: for now, assume primary and cursor planes are always enabled. */ |
| 2154 | p->pri.enabled = true; |
| 2155 | p->cur.enabled = true; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2156 | |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 2157 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2158 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2159 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2160 | if (intel_plane->pipe == pipe) { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2161 | p->spr = intel_plane->wm; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2162 | break; |
| 2163 | } |
| 2164 | } |
| 2165 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2166 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2167 | static void ilk_compute_wm_config(struct drm_device *dev, |
| 2168 | struct intel_wm_config *config) |
| 2169 | { |
| 2170 | struct intel_crtc *intel_crtc; |
| 2171 | |
| 2172 | /* Compute the currently _active_ config */ |
| 2173 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { |
| 2174 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
| 2175 | |
| 2176 | if (!wm->pipe_enabled) |
| 2177 | continue; |
| 2178 | |
| 2179 | config->sprites_enabled |= wm->sprites_enabled; |
| 2180 | config->sprites_scaled |= wm->sprites_scaled; |
| 2181 | config->num_pipes_active++; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2182 | } |
| 2183 | } |
| 2184 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2185 | /* Compute new watermarks for the pipe */ |
| 2186 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2187 | const struct ilk_pipe_wm_parameters *params, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2188 | struct intel_pipe_wm *pipe_wm) |
| 2189 | { |
| 2190 | struct drm_device *dev = crtc->dev; |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 2191 | const struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2192 | int level, max_level = ilk_wm_max_level(dev); |
| 2193 | /* LP0 watermark maximums depend on this pipe alone */ |
| 2194 | struct intel_wm_config config = { |
| 2195 | .num_pipes_active = 1, |
| 2196 | .sprites_enabled = params->spr.enabled, |
| 2197 | .sprites_scaled = params->spr.scaled, |
| 2198 | }; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2199 | struct ilk_wm_maximums max; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2200 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2201 | pipe_wm->pipe_enabled = params->active; |
| 2202 | pipe_wm->sprites_enabled = params->spr.enabled; |
| 2203 | pipe_wm->sprites_scaled = params->spr.scaled; |
| 2204 | |
Ville Syrjälä | 7b39a0b | 2013-12-05 15:51:30 +0200 | [diff] [blame] | 2205 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
| 2206 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) |
| 2207 | max_level = 1; |
| 2208 | |
| 2209 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ |
| 2210 | if (params->spr.scaled) |
| 2211 | max_level = 0; |
| 2212 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2213 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2214 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2215 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 2216 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2217 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2218 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
| 2219 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
| 2220 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2221 | /* At least LP0 must be valid */ |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2222 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
| 2223 | return false; |
| 2224 | |
| 2225 | ilk_compute_wm_reg_maximums(dev, 1, &max); |
| 2226 | |
| 2227 | for (level = 1; level <= max_level; level++) { |
| 2228 | struct intel_wm_level wm = {}; |
| 2229 | |
| 2230 | ilk_compute_wm_level(dev_priv, level, params, &wm); |
| 2231 | |
| 2232 | /* |
| 2233 | * Disable any watermark level that exceeds the |
| 2234 | * register maximums since such watermarks are |
| 2235 | * always invalid. |
| 2236 | */ |
| 2237 | if (!ilk_validate_wm_level(level, &max, &wm)) |
| 2238 | break; |
| 2239 | |
| 2240 | pipe_wm->wm[level] = wm; |
| 2241 | } |
| 2242 | |
| 2243 | return true; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2244 | } |
| 2245 | |
| 2246 | /* |
| 2247 | * Merge the watermarks from all active pipes for a specific level. |
| 2248 | */ |
| 2249 | static void ilk_merge_wm_level(struct drm_device *dev, |
| 2250 | int level, |
| 2251 | struct intel_wm_level *ret_wm) |
| 2252 | { |
| 2253 | const struct intel_crtc *intel_crtc; |
| 2254 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2255 | ret_wm->enable = true; |
| 2256 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2257 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { |
Ville Syrjälä | fe392ef | 2014-03-07 18:32:10 +0200 | [diff] [blame] | 2258 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
| 2259 | const struct intel_wm_level *wm = &active->wm[level]; |
| 2260 | |
| 2261 | if (!active->pipe_enabled) |
| 2262 | continue; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2263 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2264 | /* |
| 2265 | * The watermark values may have been used in the past, |
| 2266 | * so we must maintain them in the registers for some |
| 2267 | * time even if the level is now disabled. |
| 2268 | */ |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2269 | if (!wm->enable) |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2270 | ret_wm->enable = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2271 | |
| 2272 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); |
| 2273 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); |
| 2274 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); |
| 2275 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); |
| 2276 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2277 | } |
| 2278 | |
| 2279 | /* |
| 2280 | * Merge all low power watermarks for all active pipes. |
| 2281 | */ |
| 2282 | static void ilk_wm_merge(struct drm_device *dev, |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2283 | const struct intel_wm_config *config, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2284 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2285 | struct intel_pipe_wm *merged) |
| 2286 | { |
| 2287 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2288 | int last_enabled_level = max_level; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2289 | |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2290 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
| 2291 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && |
| 2292 | config->num_pipes_active > 1) |
| 2293 | return; |
| 2294 | |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2295 | /* ILK: FBC WM must be disabled always */ |
| 2296 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2297 | |
| 2298 | /* merge each WM1+ level */ |
| 2299 | for (level = 1; level <= max_level; level++) { |
| 2300 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2301 | |
| 2302 | ilk_merge_wm_level(dev, level, wm); |
| 2303 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2304 | if (level > last_enabled_level) |
| 2305 | wm->enable = false; |
| 2306 | else if (!ilk_validate_wm_level(level, max, wm)) |
| 2307 | /* make sure all following levels get disabled */ |
| 2308 | last_enabled_level = level - 1; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2309 | |
| 2310 | /* |
| 2311 | * The spec says it is preferred to disable |
| 2312 | * FBC WMs instead of disabling a WM level. |
| 2313 | */ |
| 2314 | if (wm->fbc_val > max->fbc) { |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2315 | if (wm->enable) |
| 2316 | merged->fbc_wm_enabled = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2317 | wm->fbc_val = 0; |
| 2318 | } |
| 2319 | } |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2320 | |
| 2321 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ |
| 2322 | /* |
| 2323 | * FIXME this is racy. FBC might get enabled later. |
| 2324 | * What we should check here is whether FBC can be |
| 2325 | * enabled sometime later. |
| 2326 | */ |
| 2327 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { |
| 2328 | for (level = 2; level <= max_level; level++) { |
| 2329 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2330 | |
| 2331 | wm->enable = false; |
| 2332 | } |
| 2333 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2334 | } |
| 2335 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2336 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
| 2337 | { |
| 2338 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ |
| 2339 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); |
| 2340 | } |
| 2341 | |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2342 | /* The value we need to program into the WM_LPx latency field */ |
| 2343 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) |
| 2344 | { |
| 2345 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2346 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2347 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2348 | return 2 * level; |
| 2349 | else |
| 2350 | return dev_priv->wm.pri_latency[level]; |
| 2351 | } |
| 2352 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2353 | static void ilk_compute_wm_results(struct drm_device *dev, |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2354 | const struct intel_pipe_wm *merged, |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2355 | enum intel_ddb_partitioning partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2356 | struct ilk_wm_values *results) |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2357 | { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2358 | struct intel_crtc *intel_crtc; |
| 2359 | int level, wm_lp; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2360 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2361 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2362 | results->partitioning = partitioning; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2363 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2364 | /* LP1+ register values */ |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2365 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 2366 | const struct intel_wm_level *r; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2367 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2368 | level = ilk_wm_lp_to_level(wm_lp, merged); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2369 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2370 | r = &merged->wm[level]; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2371 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2372 | /* |
| 2373 | * Maintain the watermark values even if the level is |
| 2374 | * disabled. Doing otherwise could cause underruns. |
| 2375 | */ |
| 2376 | results->wm_lp[wm_lp - 1] = |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2377 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2378 | (r->pri_val << WM1_LP_SR_SHIFT) | |
| 2379 | r->cur_val; |
| 2380 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2381 | if (r->enable) |
| 2382 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; |
| 2383 | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2384 | if (INTEL_INFO(dev)->gen >= 8) |
| 2385 | results->wm_lp[wm_lp - 1] |= |
| 2386 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; |
| 2387 | else |
| 2388 | results->wm_lp[wm_lp - 1] |= |
| 2389 | r->fbc_val << WM1_LP_FBC_SHIFT; |
| 2390 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2391 | /* |
| 2392 | * Always set WM1S_LP_EN when spr_val != 0, even if the |
| 2393 | * level is disabled. Doing otherwise could cause underruns. |
| 2394 | */ |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2395 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
| 2396 | WARN_ON(wm_lp != 1); |
| 2397 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; |
| 2398 | } else |
| 2399 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2400 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2401 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2402 | /* LP0 register values */ |
| 2403 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { |
| 2404 | enum pipe pipe = intel_crtc->pipe; |
| 2405 | const struct intel_wm_level *r = |
| 2406 | &intel_crtc->wm.active.wm[0]; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2407 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2408 | if (WARN_ON(!r->enable)) |
| 2409 | continue; |
| 2410 | |
| 2411 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; |
| 2412 | |
| 2413 | results->wm_pipe[pipe] = |
| 2414 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | |
| 2415 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | |
| 2416 | r->cur_val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2417 | } |
| 2418 | } |
| 2419 | |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2420 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
| 2421 | * case both are at the same level. Prefer r1 in case they're the same. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2422 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2423 | struct intel_pipe_wm *r1, |
| 2424 | struct intel_pipe_wm *r2) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2425 | { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2426 | int level, max_level = ilk_wm_max_level(dev); |
| 2427 | int level1 = 0, level2 = 0; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2428 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2429 | for (level = 1; level <= max_level; level++) { |
| 2430 | if (r1->wm[level].enable) |
| 2431 | level1 = level; |
| 2432 | if (r2->wm[level].enable) |
| 2433 | level2 = level; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2434 | } |
| 2435 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2436 | if (level1 == level2) { |
| 2437 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2438 | return r2; |
| 2439 | else |
| 2440 | return r1; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2441 | } else if (level1 > level2) { |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2442 | return r1; |
| 2443 | } else { |
| 2444 | return r2; |
| 2445 | } |
| 2446 | } |
| 2447 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2448 | /* dirty bits used to track which watermarks need changes */ |
| 2449 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) |
| 2450 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) |
| 2451 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) |
| 2452 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) |
| 2453 | #define WM_DIRTY_FBC (1 << 24) |
| 2454 | #define WM_DIRTY_DDB (1 << 25) |
| 2455 | |
| 2456 | static unsigned int ilk_compute_wm_dirty(struct drm_device *dev, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2457 | const struct ilk_wm_values *old, |
| 2458 | const struct ilk_wm_values *new) |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2459 | { |
| 2460 | unsigned int dirty = 0; |
| 2461 | enum pipe pipe; |
| 2462 | int wm_lp; |
| 2463 | |
| 2464 | for_each_pipe(pipe) { |
| 2465 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
| 2466 | dirty |= WM_DIRTY_LINETIME(pipe); |
| 2467 | /* Must disable LP1+ watermarks too */ |
| 2468 | dirty |= WM_DIRTY_LP_ALL; |
| 2469 | } |
| 2470 | |
| 2471 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { |
| 2472 | dirty |= WM_DIRTY_PIPE(pipe); |
| 2473 | /* Must disable LP1+ watermarks too */ |
| 2474 | dirty |= WM_DIRTY_LP_ALL; |
| 2475 | } |
| 2476 | } |
| 2477 | |
| 2478 | if (old->enable_fbc_wm != new->enable_fbc_wm) { |
| 2479 | dirty |= WM_DIRTY_FBC; |
| 2480 | /* Must disable LP1+ watermarks too */ |
| 2481 | dirty |= WM_DIRTY_LP_ALL; |
| 2482 | } |
| 2483 | |
| 2484 | if (old->partitioning != new->partitioning) { |
| 2485 | dirty |= WM_DIRTY_DDB; |
| 2486 | /* Must disable LP1+ watermarks too */ |
| 2487 | dirty |= WM_DIRTY_LP_ALL; |
| 2488 | } |
| 2489 | |
| 2490 | /* LP1+ watermarks already deemed dirty, no need to continue */ |
| 2491 | if (dirty & WM_DIRTY_LP_ALL) |
| 2492 | return dirty; |
| 2493 | |
| 2494 | /* Find the lowest numbered LP1+ watermark in need of an update... */ |
| 2495 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
| 2496 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || |
| 2497 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) |
| 2498 | break; |
| 2499 | } |
| 2500 | |
| 2501 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ |
| 2502 | for (; wm_lp <= 3; wm_lp++) |
| 2503 | dirty |= WM_DIRTY_LP(wm_lp); |
| 2504 | |
| 2505 | return dirty; |
| 2506 | } |
| 2507 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2508 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
| 2509 | unsigned int dirty) |
| 2510 | { |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2511 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2512 | bool changed = false; |
| 2513 | |
| 2514 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
| 2515 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; |
| 2516 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); |
| 2517 | changed = true; |
| 2518 | } |
| 2519 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { |
| 2520 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; |
| 2521 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); |
| 2522 | changed = true; |
| 2523 | } |
| 2524 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { |
| 2525 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; |
| 2526 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); |
| 2527 | changed = true; |
| 2528 | } |
| 2529 | |
| 2530 | /* |
| 2531 | * Don't touch WM1S_LP_EN here. |
| 2532 | * Doing so could cause underruns. |
| 2533 | */ |
| 2534 | |
| 2535 | return changed; |
| 2536 | } |
| 2537 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2538 | /* |
| 2539 | * The spec says we shouldn't write when we don't need, because every write |
| 2540 | * causes WMs to be re-evaluated, expending some power. |
| 2541 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2542 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
| 2543 | struct ilk_wm_values *results) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2544 | { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2545 | struct drm_device *dev = dev_priv->dev; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2546 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2547 | unsigned int dirty; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2548 | uint32_t val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2549 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2550 | dirty = ilk_compute_wm_dirty(dev, previous, results); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2551 | if (!dirty) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2552 | return; |
| 2553 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2554 | _ilk_disable_lp_wm(dev_priv, dirty); |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2555 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2556 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2557 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2558 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2559 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2560 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2561 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
| 2562 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2563 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2564 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2565 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2566 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2567 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2568 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
| 2569 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2570 | if (dirty & WM_DIRTY_DDB) { |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2571 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2572 | val = I915_READ(WM_MISC); |
| 2573 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2574 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
| 2575 | else |
| 2576 | val |= WM_MISC_DATA_PARTITION_5_6; |
| 2577 | I915_WRITE(WM_MISC, val); |
| 2578 | } else { |
| 2579 | val = I915_READ(DISP_ARB_CTL2); |
| 2580 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2581 | val &= ~DISP_DATA_PARTITION_5_6; |
| 2582 | else |
| 2583 | val |= DISP_DATA_PARTITION_5_6; |
| 2584 | I915_WRITE(DISP_ARB_CTL2, val); |
| 2585 | } |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2586 | } |
| 2587 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2588 | if (dirty & WM_DIRTY_FBC) { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2589 | val = I915_READ(DISP_ARB_CTL); |
| 2590 | if (results->enable_fbc_wm) |
| 2591 | val &= ~DISP_FBC_WM_DIS; |
| 2592 | else |
| 2593 | val |= DISP_FBC_WM_DIS; |
| 2594 | I915_WRITE(DISP_ARB_CTL, val); |
| 2595 | } |
| 2596 | |
Imre Deak | 954911e | 2013-12-17 14:46:34 +0200 | [diff] [blame] | 2597 | if (dirty & WM_DIRTY_LP(1) && |
| 2598 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) |
| 2599 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
| 2600 | |
| 2601 | if (INTEL_INFO(dev)->gen >= 7) { |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2602 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
| 2603 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
| 2604 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) |
| 2605 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
| 2606 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2607 | |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2608 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2609 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2610 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2611 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2612 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2613 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2614 | |
| 2615 | dev_priv->wm.hw = *results; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2616 | } |
| 2617 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2618 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
| 2619 | { |
| 2620 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2621 | |
| 2622 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); |
| 2623 | } |
| 2624 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2625 | static void ilk_update_wm(struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2626 | { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 2628 | struct drm_device *dev = crtc->dev; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2629 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2630 | struct ilk_wm_maximums max; |
| 2631 | struct ilk_pipe_wm_parameters params = {}; |
| 2632 | struct ilk_wm_values results = {}; |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 2633 | enum intel_ddb_partitioning partitioning; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2634 | struct intel_pipe_wm pipe_wm = {}; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2635 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 2636 | struct intel_wm_config config = {}; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2637 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2638 | ilk_compute_wm_parameters(crtc, ¶ms); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2639 | |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2640 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); |
| 2641 | |
| 2642 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) |
| 2643 | return; |
| 2644 | |
| 2645 | intel_crtc->wm.active = pipe_wm; |
| 2646 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2647 | ilk_compute_wm_config(dev, &config); |
| 2648 | |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 2649 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2650 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2651 | |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 2652 | /* 5/6 split only in single pipe config on IVB+ */ |
Ville Syrjälä | ec98c8d | 2013-10-11 15:26:26 +0300 | [diff] [blame] | 2653 | if (INTEL_INFO(dev)->gen >= 7 && |
| 2654 | config.num_pipes_active == 1 && config.sprites_enabled) { |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 2655 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2656 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 2657 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2658 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2659 | } else { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2660 | best_lp_wm = &lp_wm_1_2; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2661 | } |
| 2662 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2663 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 2664 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2665 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2666 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2667 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2668 | ilk_write_wm_values(dev_priv, &results); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2669 | } |
| 2670 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2671 | static void ilk_update_sprite_wm(struct drm_plane *plane, |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2672 | struct drm_crtc *crtc, |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2673 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 2674 | bool enabled, bool scaled) |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2675 | { |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2676 | struct drm_device *dev = plane->dev; |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2677 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2678 | |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2679 | intel_plane->wm.enabled = enabled; |
| 2680 | intel_plane->wm.scaled = scaled; |
| 2681 | intel_plane->wm.horiz_pixels = sprite_width; |
| 2682 | intel_plane->wm.bytes_per_pixel = pixel_size; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2683 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2684 | /* |
| 2685 | * IVB workaround: must disable low power watermarks for at least |
| 2686 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 2687 | * when scaling is disabled. |
| 2688 | * |
| 2689 | * WaCxSRDisabledForSpriteScaling:ivb |
| 2690 | */ |
| 2691 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) |
| 2692 | intel_wait_for_vblank(dev, intel_plane->pipe); |
| 2693 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2694 | ilk_update_wm(crtc); |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2695 | } |
| 2696 | |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2697 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
| 2698 | { |
| 2699 | struct drm_device *dev = crtc->dev; |
| 2700 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2701 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2703 | struct intel_pipe_wm *active = &intel_crtc->wm.active; |
| 2704 | enum pipe pipe = intel_crtc->pipe; |
| 2705 | static const unsigned int wm0_pipe_reg[] = { |
| 2706 | [PIPE_A] = WM0_PIPEA_ILK, |
| 2707 | [PIPE_B] = WM0_PIPEB_ILK, |
| 2708 | [PIPE_C] = WM0_PIPEC_IVB, |
| 2709 | }; |
| 2710 | |
| 2711 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2712 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 2713 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2714 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2715 | active->pipe_enabled = intel_crtc_active(crtc); |
| 2716 | |
| 2717 | if (active->pipe_enabled) { |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2718 | u32 tmp = hw->wm_pipe[pipe]; |
| 2719 | |
| 2720 | /* |
| 2721 | * For active pipes LP0 watermark is marked as |
| 2722 | * enabled, and LP1+ watermaks as disabled since |
| 2723 | * we can't really reverse compute them in case |
| 2724 | * multiple pipes are active. |
| 2725 | */ |
| 2726 | active->wm[0].enable = true; |
| 2727 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; |
| 2728 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; |
| 2729 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; |
| 2730 | active->linetime = hw->wm_linetime[pipe]; |
| 2731 | } else { |
| 2732 | int level, max_level = ilk_wm_max_level(dev); |
| 2733 | |
| 2734 | /* |
| 2735 | * For inactive pipes, all watermark levels |
| 2736 | * should be marked as enabled but zeroed, |
| 2737 | * which is what we'd compute them to. |
| 2738 | */ |
| 2739 | for (level = 0; level <= max_level; level++) |
| 2740 | active->wm[level].enable = true; |
| 2741 | } |
| 2742 | } |
| 2743 | |
| 2744 | void ilk_wm_get_hw_state(struct drm_device *dev) |
| 2745 | { |
| 2746 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2747 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2748 | struct drm_crtc *crtc; |
| 2749 | |
| 2750 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
| 2751 | ilk_pipe_wm_get_hw_state(crtc); |
| 2752 | |
| 2753 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); |
| 2754 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); |
| 2755 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); |
| 2756 | |
| 2757 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
Ville Syrjälä | cfa7698 | 2014-03-07 18:32:08 +0200 | [diff] [blame] | 2758 | if (INTEL_INFO(dev)->gen >= 7) { |
| 2759 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
| 2760 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
| 2761 | } |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2762 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2763 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2764 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
| 2765 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
| 2766 | else if (IS_IVYBRIDGE(dev)) |
| 2767 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
| 2768 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2769 | |
| 2770 | hw->enable_fbc_wm = |
| 2771 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
| 2772 | } |
| 2773 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2774 | /** |
| 2775 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 2776 | * |
| 2777 | * Calculate watermark values for the various WM regs based on current mode |
| 2778 | * and plane configuration. |
| 2779 | * |
| 2780 | * There are several cases to deal with here: |
| 2781 | * - normal (i.e. non-self-refresh) |
| 2782 | * - self-refresh (SR) mode |
| 2783 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 2784 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 2785 | * lines), so need to account for TLB latency |
| 2786 | * |
| 2787 | * The normal calculation is: |
| 2788 | * watermark = dotclock * bytes per pixel * latency |
| 2789 | * where latency is platform & configuration dependent (we assume pessimal |
| 2790 | * values here). |
| 2791 | * |
| 2792 | * The SR calculation is: |
| 2793 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 2794 | * bytes per pixel |
| 2795 | * where |
| 2796 | * line time = htotal / dotclock |
| 2797 | * surface width = hdisplay for normal plane and 64 for cursor |
| 2798 | * and latency is assumed to be high, as above. |
| 2799 | * |
| 2800 | * The final value programmed to the register should always be rounded up, |
| 2801 | * and include an extra 2 entries to account for clock crossings. |
| 2802 | * |
| 2803 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 2804 | * to set the non-SR watermarks to 8. |
| 2805 | */ |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 2806 | void intel_update_watermarks(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2807 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 2808 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2809 | |
| 2810 | if (dev_priv->display.update_wm) |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 2811 | dev_priv->display.update_wm(crtc); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2812 | } |
| 2813 | |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2814 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 2815 | struct drm_crtc *crtc, |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 2816 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | 39db4a4 | 2013-08-06 22:24:00 +0300 | [diff] [blame] | 2817 | bool enabled, bool scaled) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2818 | { |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2819 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2820 | |
| 2821 | if (dev_priv->display.update_sprite_wm) |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2822 | dev_priv->display.update_sprite_wm(plane, crtc, sprite_width, |
Ville Syrjälä | 39db4a4 | 2013-08-06 22:24:00 +0300 | [diff] [blame] | 2823 | pixel_size, enabled, scaled); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2824 | } |
| 2825 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2826 | static struct drm_i915_gem_object * |
| 2827 | intel_alloc_context_page(struct drm_device *dev) |
| 2828 | { |
| 2829 | struct drm_i915_gem_object *ctx; |
| 2830 | int ret; |
| 2831 | |
| 2832 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 2833 | |
| 2834 | ctx = i915_gem_alloc_object(dev, 4096); |
| 2835 | if (!ctx) { |
| 2836 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 2837 | return NULL; |
| 2838 | } |
| 2839 | |
Daniel Vetter | c69766f | 2014-02-14 14:01:17 +0100 | [diff] [blame] | 2840 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2841 | if (ret) { |
| 2842 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 2843 | goto err_unref; |
| 2844 | } |
| 2845 | |
| 2846 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
| 2847 | if (ret) { |
| 2848 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 2849 | goto err_unpin; |
| 2850 | } |
| 2851 | |
| 2852 | return ctx; |
| 2853 | |
| 2854 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2855 | i915_gem_object_ggtt_unpin(ctx); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2856 | err_unref: |
| 2857 | drm_gem_object_unreference(&ctx->base); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2858 | return NULL; |
| 2859 | } |
| 2860 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2861 | /** |
| 2862 | * Lock protecting IPS related data structures |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2863 | */ |
| 2864 | DEFINE_SPINLOCK(mchdev_lock); |
| 2865 | |
| 2866 | /* Global for IPS driver to get at the current i915 device. Protected by |
| 2867 | * mchdev_lock. */ |
| 2868 | static struct drm_i915_private *i915_mch_dev; |
| 2869 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2870 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 2871 | { |
| 2872 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2873 | u16 rgvswctl; |
| 2874 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2875 | assert_spin_locked(&mchdev_lock); |
| 2876 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2877 | rgvswctl = I915_READ16(MEMSWCTL); |
| 2878 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 2879 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 2880 | return false; /* still busy with another command */ |
| 2881 | } |
| 2882 | |
| 2883 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 2884 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 2885 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 2886 | POSTING_READ16(MEMSWCTL); |
| 2887 | |
| 2888 | rgvswctl |= MEMCTL_CMD_STS; |
| 2889 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 2890 | |
| 2891 | return true; |
| 2892 | } |
| 2893 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2894 | static void ironlake_enable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2895 | { |
| 2896 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2897 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
| 2898 | u8 fmax, fmin, fstart, vstart; |
| 2899 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2900 | spin_lock_irq(&mchdev_lock); |
| 2901 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2902 | /* Enable temp reporting */ |
| 2903 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 2904 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 2905 | |
| 2906 | /* 100ms RC evaluation intervals */ |
| 2907 | I915_WRITE(RCUPEI, 100000); |
| 2908 | I915_WRITE(RCDNEI, 100000); |
| 2909 | |
| 2910 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 2911 | I915_WRITE(RCBMAXAVG, 90000); |
| 2912 | I915_WRITE(RCBMINAVG, 80000); |
| 2913 | |
| 2914 | I915_WRITE(MEMIHYST, 1); |
| 2915 | |
| 2916 | /* Set up min, max, and cur for interrupt handling */ |
| 2917 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 2918 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 2919 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 2920 | MEMMODE_FSTART_SHIFT; |
| 2921 | |
| 2922 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 2923 | PXVFREQ_PX_SHIFT; |
| 2924 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2925 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
| 2926 | dev_priv->ips.fstart = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2927 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2928 | dev_priv->ips.max_delay = fstart; |
| 2929 | dev_priv->ips.min_delay = fmin; |
| 2930 | dev_priv->ips.cur_delay = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2931 | |
| 2932 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 2933 | fmax, fmin, fstart); |
| 2934 | |
| 2935 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 2936 | |
| 2937 | /* |
| 2938 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 2939 | */ |
| 2940 | |
| 2941 | I915_WRITE(VIDSTART, vstart); |
| 2942 | POSTING_READ(VIDSTART); |
| 2943 | |
| 2944 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 2945 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 2946 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2947 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2948 | DRM_ERROR("stuck trying to change perf mode\n"); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2949 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2950 | |
| 2951 | ironlake_set_drps(dev, fstart); |
| 2952 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2953 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2954 | I915_READ(0x112e0); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2955 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
| 2956 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
| 2957 | getrawmonotonic(&dev_priv->ips.last_time2); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2958 | |
| 2959 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2960 | } |
| 2961 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 2962 | static void ironlake_disable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2963 | { |
| 2964 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2965 | u16 rgvswctl; |
| 2966 | |
| 2967 | spin_lock_irq(&mchdev_lock); |
| 2968 | |
| 2969 | rgvswctl = I915_READ16(MEMSWCTL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2970 | |
| 2971 | /* Ack interrupts, disable EFC interrupt */ |
| 2972 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 2973 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 2974 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 2975 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 2976 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 2977 | |
| 2978 | /* Go back to the starting frequency */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 2979 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2980 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2981 | rgvswctl |= MEMCTL_CMD_STS; |
| 2982 | I915_WRITE(MEMSWCTL, rgvswctl); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2983 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2984 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 2985 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2986 | } |
| 2987 | |
Daniel Vetter | acbe947 | 2012-07-26 11:50:05 +0200 | [diff] [blame] | 2988 | /* There's a funny hw issue where the hw returns all 0 when reading from |
| 2989 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
| 2990 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
| 2991 | * all limits and the gpu stuck at whatever frequency it is at atm). |
| 2992 | */ |
Chris Wilson | 6917c7b | 2013-11-06 13:56:26 -0200 | [diff] [blame] | 2993 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2994 | { |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 2995 | u32 limits; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 2996 | |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 2997 | /* Only set the down limit when we've reached the lowest level to avoid |
| 2998 | * getting more interrupts, otherwise leave this clear. This prevents a |
| 2999 | * race in the hw when coming out of rc6: There's a tiny window where |
| 3000 | * the hw runs at the minimal clock before selecting the desired |
| 3001 | * frequency, if the down threshold expires in that window we will not |
| 3002 | * receive a down interrupt. */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3003 | limits = dev_priv->rps.max_freq_softlimit << 24; |
| 3004 | if (val <= dev_priv->rps.min_freq_softlimit) |
| 3005 | limits |= dev_priv->rps.min_freq_softlimit << 16; |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3006 | |
| 3007 | return limits; |
| 3008 | } |
| 3009 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3010 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
| 3011 | { |
| 3012 | int new_power; |
| 3013 | |
| 3014 | new_power = dev_priv->rps.power; |
| 3015 | switch (dev_priv->rps.power) { |
| 3016 | case LOW_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3017 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3018 | new_power = BETWEEN; |
| 3019 | break; |
| 3020 | |
| 3021 | case BETWEEN: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3022 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3023 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3024 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3025 | new_power = HIGH_POWER; |
| 3026 | break; |
| 3027 | |
| 3028 | case HIGH_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3029 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3030 | new_power = BETWEEN; |
| 3031 | break; |
| 3032 | } |
| 3033 | /* Max/min bins are special */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3034 | if (val == dev_priv->rps.min_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3035 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3036 | if (val == dev_priv->rps.max_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3037 | new_power = HIGH_POWER; |
| 3038 | if (new_power == dev_priv->rps.power) |
| 3039 | return; |
| 3040 | |
| 3041 | /* Note the units here are not exactly 1us, but 1280ns. */ |
| 3042 | switch (new_power) { |
| 3043 | case LOW_POWER: |
| 3044 | /* Upclock if more than 95% busy over 16ms */ |
| 3045 | I915_WRITE(GEN6_RP_UP_EI, 12500); |
| 3046 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); |
| 3047 | |
| 3048 | /* Downclock if less than 85% busy over 32ms */ |
| 3049 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3050 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); |
| 3051 | |
| 3052 | I915_WRITE(GEN6_RP_CONTROL, |
| 3053 | GEN6_RP_MEDIA_TURBO | |
| 3054 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3055 | GEN6_RP_MEDIA_IS_GFX | |
| 3056 | GEN6_RP_ENABLE | |
| 3057 | GEN6_RP_UP_BUSY_AVG | |
| 3058 | GEN6_RP_DOWN_IDLE_AVG); |
| 3059 | break; |
| 3060 | |
| 3061 | case BETWEEN: |
| 3062 | /* Upclock if more than 90% busy over 13ms */ |
| 3063 | I915_WRITE(GEN6_RP_UP_EI, 10250); |
| 3064 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); |
| 3065 | |
| 3066 | /* Downclock if less than 75% busy over 32ms */ |
| 3067 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3068 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); |
| 3069 | |
| 3070 | I915_WRITE(GEN6_RP_CONTROL, |
| 3071 | GEN6_RP_MEDIA_TURBO | |
| 3072 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3073 | GEN6_RP_MEDIA_IS_GFX | |
| 3074 | GEN6_RP_ENABLE | |
| 3075 | GEN6_RP_UP_BUSY_AVG | |
| 3076 | GEN6_RP_DOWN_IDLE_AVG); |
| 3077 | break; |
| 3078 | |
| 3079 | case HIGH_POWER: |
| 3080 | /* Upclock if more than 85% busy over 10ms */ |
| 3081 | I915_WRITE(GEN6_RP_UP_EI, 8000); |
| 3082 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); |
| 3083 | |
| 3084 | /* Downclock if less than 60% busy over 32ms */ |
| 3085 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3086 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); |
| 3087 | |
| 3088 | I915_WRITE(GEN6_RP_CONTROL, |
| 3089 | GEN6_RP_MEDIA_TURBO | |
| 3090 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3091 | GEN6_RP_MEDIA_IS_GFX | |
| 3092 | GEN6_RP_ENABLE | |
| 3093 | GEN6_RP_UP_BUSY_AVG | |
| 3094 | GEN6_RP_DOWN_IDLE_AVG); |
| 3095 | break; |
| 3096 | } |
| 3097 | |
| 3098 | dev_priv->rps.power = new_power; |
| 3099 | dev_priv->rps.last_adj = 0; |
| 3100 | } |
| 3101 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3102 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
| 3103 | { |
| 3104 | u32 mask = 0; |
| 3105 | |
| 3106 | if (val > dev_priv->rps.min_freq_softlimit) |
| 3107 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
| 3108 | if (val < dev_priv->rps.max_freq_softlimit) |
| 3109 | mask |= GEN6_PM_RP_UP_THRESHOLD; |
| 3110 | |
| 3111 | /* IVB and SNB hard hangs on looping batchbuffer |
| 3112 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
| 3113 | */ |
| 3114 | if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) |
| 3115 | mask |= GEN6_PM_RP_UP_EI_EXPIRED; |
| 3116 | |
| 3117 | return ~mask; |
| 3118 | } |
| 3119 | |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3120 | /* gen6_set_rps is called to update the frequency request, but should also be |
| 3121 | * called when the range (min_delay and max_delay) is modified so that we can |
| 3122 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3123 | void gen6_set_rps(struct drm_device *dev, u8 val) |
| 3124 | { |
| 3125 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3126 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3127 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3128 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
| 3129 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3130 | |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3131 | /* min/max delay may still have been modified so be sure to |
| 3132 | * write the limits value. |
| 3133 | */ |
| 3134 | if (val != dev_priv->rps.cur_freq) { |
| 3135 | gen6_set_rps_thresholds(dev_priv, val); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3136 | |
Ben Widawsky | 50e6a2a | 2014-03-31 17:16:43 -0700 | [diff] [blame] | 3137 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3138 | I915_WRITE(GEN6_RPNSWREQ, |
| 3139 | HSW_FREQUENCY(val)); |
| 3140 | else |
| 3141 | I915_WRITE(GEN6_RPNSWREQ, |
| 3142 | GEN6_FREQUENCY(val) | |
| 3143 | GEN6_OFFSET(0) | |
| 3144 | GEN6_AGGRESSIVE_TURBO); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3145 | } |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3146 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3147 | /* Make sure we continue to get interrupts |
| 3148 | * until we hit the minimum or maximum frequencies. |
| 3149 | */ |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3150 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3151 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3152 | |
Ben Widawsky | d5570a7 | 2012-09-07 19:43:41 -0700 | [diff] [blame] | 3153 | POSTING_READ(GEN6_RPNSWREQ); |
| 3154 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3155 | dev_priv->rps.cur_freq = val; |
Daniel Vetter | be2cde9 | 2012-08-30 13:26:48 +0200 | [diff] [blame] | 3156 | trace_intel_gpu_freq_change(val * 50); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3157 | } |
| 3158 | |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3159 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
| 3160 | * |
| 3161 | * * If Gfx is Idle, then |
| 3162 | * 1. Mask Turbo interrupts |
| 3163 | * 2. Bring up Gfx clock |
| 3164 | * 3. Change the freq to Rpn and wait till P-Unit updates freq |
| 3165 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down |
| 3166 | * 5. Unmask Turbo interrupts |
| 3167 | */ |
| 3168 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) |
| 3169 | { |
| 3170 | /* |
| 3171 | * When we are idle. Drop to min voltage state. |
| 3172 | */ |
| 3173 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3174 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3175 | return; |
| 3176 | |
| 3177 | /* Mask turbo interrupt so that they will not come in between */ |
| 3178 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
| 3179 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 3180 | vlv_force_gfx_clock(dev_priv, true); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3181 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3182 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3183 | |
| 3184 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3185 | dev_priv->rps.min_freq_softlimit); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3186 | |
| 3187 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) |
| 3188 | & GENFREQSTATUS) == 0, 5)) |
| 3189 | DRM_ERROR("timed out waiting for Punit\n"); |
| 3190 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 3191 | vlv_force_gfx_clock(dev_priv, false); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3192 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3193 | I915_WRITE(GEN6_PMINTRMSK, |
| 3194 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3195 | } |
| 3196 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3197 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
| 3198 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3199 | struct drm_device *dev = dev_priv->dev; |
| 3200 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3201 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3202 | if (dev_priv->rps.enabled) { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3203 | if (IS_VALLEYVIEW(dev)) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3204 | vlv_set_rps_idle(dev_priv); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3205 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3206 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3207 | dev_priv->rps.last_adj = 0; |
| 3208 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3209 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3210 | } |
| 3211 | |
| 3212 | void gen6_rps_boost(struct drm_i915_private *dev_priv) |
| 3213 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3214 | struct drm_device *dev = dev_priv->dev; |
| 3215 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3216 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3217 | if (dev_priv->rps.enabled) { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3218 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3219 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3220 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3221 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3222 | dev_priv->rps.last_adj = 0; |
| 3223 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3224 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3225 | } |
| 3226 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3227 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
| 3228 | { |
| 3229 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 7a67092 | 2013-06-25 19:21:06 +0300 | [diff] [blame] | 3230 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3231 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3232 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
| 3233 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3234 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3235 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3236 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
| 3237 | dev_priv->rps.cur_freq, |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3238 | vlv_gpu_freq(dev_priv, val), val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3239 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3240 | if (val != dev_priv->rps.cur_freq) |
| 3241 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3242 | |
Imre Deak | 09c87db | 2014-04-03 20:02:42 +0300 | [diff] [blame] | 3243 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3244 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3245 | dev_priv->rps.cur_freq = val; |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3246 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3247 | } |
| 3248 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3249 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3250 | { |
| 3251 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3252 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3253 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3254 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & |
| 3255 | ~dev_priv->pm_rps_events); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3256 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 3257 | * item again unmasking PM interrupts because that is using a different |
| 3258 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
| 3259 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
| 3260 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 3261 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3262 | dev_priv->rps.pm_iir = 0; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 3263 | spin_unlock_irq(&dev_priv->irq_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3264 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3265 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3266 | } |
| 3267 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3268 | static void gen6_disable_rps(struct drm_device *dev) |
| 3269 | { |
| 3270 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3271 | |
| 3272 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3273 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
| 3274 | |
| 3275 | gen6_disable_rps_interrupts(dev); |
| 3276 | } |
| 3277 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3278 | static void valleyview_disable_rps(struct drm_device *dev) |
| 3279 | { |
| 3280 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3281 | |
| 3282 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3283 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3284 | gen6_disable_rps_interrupts(dev); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3285 | } |
| 3286 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3287 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
| 3288 | { |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 3289 | if (IS_VALLEYVIEW(dev)) { |
| 3290 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
| 3291 | mode = GEN6_RC_CTL_RC6_ENABLE; |
| 3292 | else |
| 3293 | mode = 0; |
| 3294 | } |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3295 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
Ben Widawsky | 1c79b42 | 2014-01-28 20:25:40 -0800 | [diff] [blame] | 3296 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
| 3297 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
| 3298 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3299 | } |
| 3300 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3301 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3302 | { |
Damien Lespiau | eb4926e | 2013-06-07 17:41:14 +0100 | [diff] [blame] | 3303 | /* No RC6 before Ironlake */ |
| 3304 | if (INTEL_INFO(dev)->gen < 5) |
| 3305 | return 0; |
| 3306 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3307 | /* RC6 is only on Ironlake mobile not on desktop */ |
| 3308 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) |
| 3309 | return 0; |
| 3310 | |
Imre Deak | f033579 | 2014-04-28 12:03:59 +0300 | [diff] [blame] | 3311 | /* Disable RC6 on Broadwell for now */ |
| 3312 | if (IS_BROADWELL(dev)) |
| 3313 | return 0; |
| 3314 | |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 3315 | /* Respect the kernel parameter if it is set */ |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3316 | if (enable_rc6 >= 0) { |
| 3317 | int mask; |
| 3318 | |
| 3319 | if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
| 3320 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
| 3321 | INTEL_RC6pp_ENABLE; |
| 3322 | else |
| 3323 | mask = INTEL_RC6_ENABLE; |
| 3324 | |
| 3325 | if ((enable_rc6 & mask) != enable_rc6) |
| 3326 | DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
| 3327 | enable_rc6, enable_rc6 & mask, mask); |
| 3328 | |
| 3329 | return enable_rc6 & mask; |
| 3330 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3331 | |
Chris Wilson | 6567d74 | 2012-11-10 10:00:06 +0000 | [diff] [blame] | 3332 | /* Disable RC6 on Ironlake */ |
| 3333 | if (INTEL_INFO(dev)->gen == 5) |
| 3334 | return 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3335 | |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 3336 | if (IS_IVYBRIDGE(dev)) |
Ben Widawsky | cca84a1 | 2014-01-28 20:25:38 -0800 | [diff] [blame] | 3337 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 3338 | |
| 3339 | return INTEL_RC6_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3340 | } |
| 3341 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3342 | int intel_enable_rc6(const struct drm_device *dev) |
| 3343 | { |
| 3344 | return i915.enable_rc6; |
| 3345 | } |
| 3346 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3347 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
| 3348 | { |
| 3349 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3350 | |
| 3351 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | a0b3335 | 2013-07-04 23:35:34 +0200 | [diff] [blame] | 3352 | WARN_ON(dev_priv->rps.pm_iir); |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3353 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
| 3354 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3355 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3356 | } |
| 3357 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3358 | static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) |
| 3359 | { |
| 3360 | /* All of these values are in units of 50MHz */ |
| 3361 | dev_priv->rps.cur_freq = 0; |
| 3362 | /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ |
| 3363 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
| 3364 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
| 3365 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
| 3366 | /* XXX: only BYT has a special efficient freq */ |
| 3367 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
| 3368 | /* hw_max = RP0 until we check for overclocking */ |
| 3369 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
| 3370 | |
| 3371 | /* Preserve min/max settings in case of re-init */ |
| 3372 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 3373 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 3374 | |
| 3375 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 3376 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 3377 | } |
| 3378 | |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3379 | static void gen8_enable_rps(struct drm_device *dev) |
| 3380 | { |
| 3381 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3382 | struct intel_ring_buffer *ring; |
| 3383 | uint32_t rc6_mask = 0, rp_state_cap; |
| 3384 | int unused; |
| 3385 | |
| 3386 | /* 1a: Software RC state - RC0 */ |
| 3387 | I915_WRITE(GEN6_RC_STATE, 0); |
| 3388 | |
| 3389 | /* 1c & 1d: Get forcewake during program sequence. Although the driver |
| 3390 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3391 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3392 | |
| 3393 | /* 2a: Disable RC states. */ |
| 3394 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3395 | |
| 3396 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3397 | parse_rp_state_cap(dev_priv, rp_state_cap); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3398 | |
| 3399 | /* 2b: Program RC6 thresholds.*/ |
| 3400 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 3401 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 3402 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 3403 | for_each_ring(ring, dev_priv, unused) |
| 3404 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 3405 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 3406 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
| 3407 | |
| 3408 | /* 3: Enable RC6 */ |
| 3409 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
| 3410 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
Ben Widawsky | abbf9d2 | 2014-01-28 20:25:41 -0800 | [diff] [blame] | 3411 | intel_print_rc6_info(dev, rc6_mask); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3412 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
Ben Widawsky | abbf9d2 | 2014-01-28 20:25:41 -0800 | [diff] [blame] | 3413 | GEN6_RC_CTL_EI_MODE(1) | |
| 3414 | rc6_mask); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3415 | |
| 3416 | /* 4 Program defaults and thresholds for RPS*/ |
Ben Widawsky | f9bdc58 | 2014-03-31 17:16:41 -0700 | [diff] [blame] | 3417 | I915_WRITE(GEN6_RPNSWREQ, |
| 3418 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
| 3419 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 3420 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3421 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
| 3422 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ |
| 3423 | |
| 3424 | /* Docs recommend 900MHz, and 300 MHz respectively */ |
| 3425 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3426 | dev_priv->rps.max_freq_softlimit << 24 | |
| 3427 | dev_priv->rps.min_freq_softlimit << 16); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3428 | |
| 3429 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ |
| 3430 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ |
| 3431 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ |
| 3432 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ |
| 3433 | |
| 3434 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 3435 | |
| 3436 | /* 5: Enable RPS */ |
| 3437 | I915_WRITE(GEN6_RP_CONTROL, |
| 3438 | GEN6_RP_MEDIA_TURBO | |
| 3439 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3440 | GEN6_RP_MEDIA_IS_GFX | |
| 3441 | GEN6_RP_ENABLE | |
| 3442 | GEN6_RP_UP_BUSY_AVG | |
| 3443 | GEN6_RP_DOWN_IDLE_AVG); |
| 3444 | |
| 3445 | /* 6: Ring frequency + overclocking (our driver does this later */ |
| 3446 | |
| 3447 | gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); |
| 3448 | |
| 3449 | gen6_enable_rps_interrupts(dev); |
| 3450 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3451 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3452 | } |
| 3453 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3454 | static void gen6_enable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3455 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3456 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3457 | struct intel_ring_buffer *ring; |
Ben Widawsky | 2a5913a | 2014-03-19 18:31:13 -0700 | [diff] [blame] | 3458 | u32 rp_state_cap; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3459 | u32 gt_perf_status; |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3460 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3461 | u32 gtfifodbg; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3462 | int rc6_mode; |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3463 | int i, ret; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3464 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3465 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3466 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3467 | /* Here begins a magic sequence of register writes to enable |
| 3468 | * auto-downclocking. |
| 3469 | * |
| 3470 | * Perhaps there might be some value in exposing these to |
| 3471 | * userspace... |
| 3472 | */ |
| 3473 | I915_WRITE(GEN6_RC_STATE, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3474 | |
| 3475 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 3476 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 3477 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 3478 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 3479 | } |
| 3480 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3481 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3482 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3483 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 3484 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 3485 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3486 | parse_rp_state_cap(dev_priv, rp_state_cap); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3487 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3488 | /* disable the counters and set deterministic thresholds */ |
| 3489 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3490 | |
| 3491 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 3492 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 3493 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 3494 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 3495 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 3496 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3497 | for_each_ring(ring, dev_priv, i) |
| 3498 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3499 | |
| 3500 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 3501 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
Daniel Vetter | 29c78f6 | 2013-11-16 16:04:26 +0100 | [diff] [blame] | 3502 | if (IS_IVYBRIDGE(dev)) |
Stéphane Marchesin | 351aa56 | 2013-08-13 11:55:17 -0700 | [diff] [blame] | 3503 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
| 3504 | else |
| 3505 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
Stéphane Marchesin | 0920a48 | 2013-01-29 19:41:59 -0800 | [diff] [blame] | 3506 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3507 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 3508 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3509 | /* Check if we are enabling RC6 */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3510 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 3511 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 3512 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 3513 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3514 | /* We don't use those on Haswell */ |
| 3515 | if (!IS_HASWELL(dev)) { |
| 3516 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 3517 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3518 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3519 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 3520 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 3521 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3522 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3523 | intel_print_rc6_info(dev, rc6_mask); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3524 | |
| 3525 | I915_WRITE(GEN6_RC_CONTROL, |
| 3526 | rc6_mask | |
| 3527 | GEN6_RC_CTL_EI_MODE(1) | |
| 3528 | GEN6_RC_CTL_HW_ENABLE); |
| 3529 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3530 | /* Power down if completely idle for over 50ms */ |
| 3531 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3532 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3533 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3534 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3535 | if (ret) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3536 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3537 | |
| 3538 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
| 3539 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
| 3540 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3541 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3542 | (pcu_mbox & 0xff) * 50); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3543 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3544 | } |
| 3545 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3546 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3547 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3548 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3549 | gen6_enable_rps_interrupts(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3550 | |
Ben Widawsky | 31643d5 | 2012-09-26 10:34:01 -0700 | [diff] [blame] | 3551 | rc6vids = 0; |
| 3552 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 3553 | if (IS_GEN6(dev) && ret) { |
| 3554 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
| 3555 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
| 3556 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
| 3557 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
| 3558 | rc6vids &= 0xffff00; |
| 3559 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
| 3560 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
| 3561 | if (ret) |
| 3562 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
| 3563 | } |
| 3564 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3565 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3566 | } |
| 3567 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 3568 | static void __gen6_update_ring_freq(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3569 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3570 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3571 | int min_freq = 15; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3572 | unsigned int gpu_freq; |
| 3573 | unsigned int max_ia_freq, min_ring_freq; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3574 | int scaling_factor = 180; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 3575 | struct cpufreq_policy *policy; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3576 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3577 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3578 | |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 3579 | policy = cpufreq_cpu_get(0); |
| 3580 | if (policy) { |
| 3581 | max_ia_freq = policy->cpuinfo.max_freq; |
| 3582 | cpufreq_cpu_put(policy); |
| 3583 | } else { |
| 3584 | /* |
| 3585 | * Default to measured freq if none found, PCU will ensure we |
| 3586 | * don't go over |
| 3587 | */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3588 | max_ia_freq = tsc_khz; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 3589 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3590 | |
| 3591 | /* Convert from kHz to MHz */ |
| 3592 | max_ia_freq /= 1000; |
| 3593 | |
Ben Widawsky | 153b4b95 | 2013-10-22 22:05:09 -0700 | [diff] [blame] | 3594 | min_ring_freq = I915_READ(DCLK) & 0xf; |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 3595 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
| 3596 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3597 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3598 | /* |
| 3599 | * For each potential GPU frequency, load a ring frequency we'd like |
| 3600 | * to use for memory access. We do this by specifying the IA frequency |
| 3601 | * the PCU should use as a reference to determine the ring frequency. |
| 3602 | */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3603 | for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3604 | gpu_freq--) { |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3605 | int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3606 | unsigned int ia_freq = 0, ring_freq = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3607 | |
Ben Widawsky | 46c764d | 2013-11-02 21:07:49 -0700 | [diff] [blame] | 3608 | if (INTEL_INFO(dev)->gen >= 8) { |
| 3609 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
| 3610 | ring_freq = max(min_ring_freq, gpu_freq); |
| 3611 | } else if (IS_HASWELL(dev)) { |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 3612 | ring_freq = mult_frac(gpu_freq, 5, 4); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3613 | ring_freq = max(min_ring_freq, ring_freq); |
| 3614 | /* leave ia_freq as the default, chosen by cpufreq */ |
| 3615 | } else { |
| 3616 | /* On older processors, there is no separate ring |
| 3617 | * clock domain, so in order to boost the bandwidth |
| 3618 | * of the ring, we need to upclock the CPU (ia_freq). |
| 3619 | * |
| 3620 | * For GPU frequencies less than 750MHz, |
| 3621 | * just use the lowest ring freq. |
| 3622 | */ |
| 3623 | if (gpu_freq < min_freq) |
| 3624 | ia_freq = 800; |
| 3625 | else |
| 3626 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 3627 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 3628 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3629 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3630 | sandybridge_pcode_write(dev_priv, |
| 3631 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3632 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
| 3633 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
| 3634 | gpu_freq); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3635 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3636 | } |
| 3637 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 3638 | void gen6_update_ring_freq(struct drm_device *dev) |
| 3639 | { |
| 3640 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3641 | |
| 3642 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) |
| 3643 | return; |
| 3644 | |
| 3645 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3646 | __gen6_update_ring_freq(dev); |
| 3647 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3648 | } |
| 3649 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3650 | int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
| 3651 | { |
| 3652 | u32 val, rp0; |
| 3653 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3654 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3655 | |
| 3656 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
| 3657 | /* Clamp to max */ |
| 3658 | rp0 = min_t(u32, rp0, 0xea); |
| 3659 | |
| 3660 | return rp0; |
| 3661 | } |
| 3662 | |
| 3663 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 3664 | { |
| 3665 | u32 val, rpe; |
| 3666 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3667 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3668 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3669 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3670 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
| 3671 | |
| 3672 | return rpe; |
| 3673 | } |
| 3674 | |
| 3675 | int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
| 3676 | { |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3677 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3678 | } |
| 3679 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 3680 | /* Check that the pctx buffer wasn't move under us. */ |
| 3681 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) |
| 3682 | { |
| 3683 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 3684 | |
| 3685 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + |
| 3686 | dev_priv->vlv_pctx->stolen->start); |
| 3687 | } |
| 3688 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3689 | static void valleyview_setup_pctx(struct drm_device *dev) |
| 3690 | { |
| 3691 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3692 | struct drm_i915_gem_object *pctx; |
| 3693 | unsigned long pctx_paddr; |
| 3694 | u32 pcbr; |
| 3695 | int pctx_size = 24*1024; |
| 3696 | |
Imre Deak | 17b0c1f | 2014-02-11 21:39:06 +0200 | [diff] [blame] | 3697 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 3698 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3699 | pcbr = I915_READ(VLV_PCBR); |
| 3700 | if (pcbr) { |
| 3701 | /* BIOS set it up already, grab the pre-alloc'd space */ |
| 3702 | int pcbr_offset; |
| 3703 | |
| 3704 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
| 3705 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
| 3706 | pcbr_offset, |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 3707 | I915_GTT_OFFSET_NONE, |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 3708 | pctx_size); |
| 3709 | goto out; |
| 3710 | } |
| 3711 | |
| 3712 | /* |
| 3713 | * From the Gunit register HAS: |
| 3714 | * The Gfx driver is expected to program this register and ensure |
| 3715 | * proper allocation within Gfx stolen memory. For example, this |
| 3716 | * register should be programmed such than the PCBR range does not |
| 3717 | * overlap with other ranges, such as the frame buffer, protected |
| 3718 | * memory, or any other relevant ranges. |
| 3719 | */ |
| 3720 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
| 3721 | if (!pctx) { |
| 3722 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
| 3723 | return; |
| 3724 | } |
| 3725 | |
| 3726 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
| 3727 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 3728 | |
| 3729 | out: |
| 3730 | dev_priv->vlv_pctx = pctx; |
| 3731 | } |
| 3732 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 3733 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
| 3734 | { |
| 3735 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3736 | |
| 3737 | if (WARN_ON(!dev_priv->vlv_pctx)) |
| 3738 | return; |
| 3739 | |
| 3740 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
| 3741 | dev_priv->vlv_pctx = NULL; |
| 3742 | } |
| 3743 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 3744 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
| 3745 | { |
| 3746 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3747 | |
| 3748 | valleyview_setup_pctx(dev); |
| 3749 | |
| 3750 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3751 | |
| 3752 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
| 3753 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 3754 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
| 3755 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
| 3756 | dev_priv->rps.max_freq); |
| 3757 | |
| 3758 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
| 3759 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
| 3760 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
| 3761 | dev_priv->rps.efficient_freq); |
| 3762 | |
| 3763 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
| 3764 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
| 3765 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
| 3766 | dev_priv->rps.min_freq); |
| 3767 | |
| 3768 | /* Preserve min/max settings in case of re-init */ |
| 3769 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 3770 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 3771 | |
| 3772 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 3773 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 3774 | |
| 3775 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3776 | } |
| 3777 | |
| 3778 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
| 3779 | { |
| 3780 | valleyview_cleanup_pctx(dev); |
| 3781 | } |
| 3782 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3783 | static void valleyview_enable_rps(struct drm_device *dev) |
| 3784 | { |
| 3785 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3786 | struct intel_ring_buffer *ring; |
Ben Widawsky | 2a5913a | 2014-03-19 18:31:13 -0700 | [diff] [blame] | 3787 | u32 gtfifodbg, val, rc6_mode = 0; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3788 | int i; |
| 3789 | |
| 3790 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 3791 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 3792 | valleyview_check_pctx(dev_priv); |
| 3793 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3794 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
Jesse Barnes | f7d85c1 | 2013-09-27 10:40:54 -0700 | [diff] [blame] | 3795 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 3796 | gtfifodbg); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3797 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 3798 | } |
| 3799 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3800 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
| 3801 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3802 | |
| 3803 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 3804 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 3805 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 3806 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 3807 | |
| 3808 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 3809 | |
| 3810 | I915_WRITE(GEN6_RP_CONTROL, |
| 3811 | GEN6_RP_MEDIA_TURBO | |
| 3812 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3813 | GEN6_RP_MEDIA_IS_GFX | |
| 3814 | GEN6_RP_ENABLE | |
| 3815 | GEN6_RP_UP_BUSY_AVG | |
| 3816 | GEN6_RP_DOWN_IDLE_CONT); |
| 3817 | |
| 3818 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
| 3819 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 3820 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 3821 | |
| 3822 | for_each_ring(ring, dev_priv, i) |
| 3823 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 3824 | |
Jesse Barnes | 2f0aa304 | 2013-11-15 09:32:11 -0800 | [diff] [blame] | 3825 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3826 | |
| 3827 | /* allows RC6 residency counter to work */ |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 3828 | I915_WRITE(VLV_COUNTER_CONTROL, |
| 3829 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
| 3830 | VLV_MEDIA_RC6_COUNT_EN | |
| 3831 | VLV_RENDER_RC6_COUNT_EN)); |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 3832 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
Jesse Barnes | 6b88f29 | 2013-11-15 09:32:12 -0800 | [diff] [blame] | 3833 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3834 | |
| 3835 | intel_print_rc6_info(dev, rc6_mode); |
| 3836 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 3837 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3838 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3839 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3840 | |
| 3841 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); |
| 3842 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 3843 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3844 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3845 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3846 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
| 3847 | dev_priv->rps.cur_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3848 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3849 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3850 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
| 3851 | dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3852 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3853 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3854 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3855 | gen6_enable_rps_interrupts(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3856 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3857 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3858 | } |
| 3859 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3860 | void ironlake_teardown_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3861 | { |
| 3862 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3863 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3864 | if (dev_priv->ips.renderctx) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3865 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3866 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
| 3867 | dev_priv->ips.renderctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3868 | } |
| 3869 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3870 | if (dev_priv->ips.pwrctx) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3871 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3872 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
| 3873 | dev_priv->ips.pwrctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3874 | } |
| 3875 | } |
| 3876 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3877 | static void ironlake_disable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3878 | { |
| 3879 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3880 | |
| 3881 | if (I915_READ(PWRCTXA)) { |
| 3882 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
| 3883 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
| 3884 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
| 3885 | 50); |
| 3886 | |
| 3887 | I915_WRITE(PWRCTXA, 0); |
| 3888 | POSTING_READ(PWRCTXA); |
| 3889 | |
| 3890 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
| 3891 | POSTING_READ(RSTDBYCTL); |
| 3892 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3893 | } |
| 3894 | |
| 3895 | static int ironlake_setup_rc6(struct drm_device *dev) |
| 3896 | { |
| 3897 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3898 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3899 | if (dev_priv->ips.renderctx == NULL) |
| 3900 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
| 3901 | if (!dev_priv->ips.renderctx) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3902 | return -ENOMEM; |
| 3903 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 3904 | if (dev_priv->ips.pwrctx == NULL) |
| 3905 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
| 3906 | if (!dev_priv->ips.pwrctx) { |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3907 | ironlake_teardown_rc6(dev); |
| 3908 | return -ENOMEM; |
| 3909 | } |
| 3910 | |
| 3911 | return 0; |
| 3912 | } |
| 3913 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 3914 | static void ironlake_enable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3915 | { |
| 3916 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3917 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3918 | bool was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3919 | int ret; |
| 3920 | |
| 3921 | /* rc6 disabled by default due to repeated reports of hanging during |
| 3922 | * boot and resume. |
| 3923 | */ |
| 3924 | if (!intel_enable_rc6(dev)) |
| 3925 | return; |
| 3926 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3927 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 3928 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3929 | ret = ironlake_setup_rc6(dev); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3930 | if (ret) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3931 | return; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3932 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3933 | was_interruptible = dev_priv->mm.interruptible; |
| 3934 | dev_priv->mm.interruptible = false; |
| 3935 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3936 | /* |
| 3937 | * GPU can automatically power down the render unit if given a page |
| 3938 | * to save state. |
| 3939 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3940 | ret = intel_ring_begin(ring, 6); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3941 | if (ret) { |
| 3942 | ironlake_teardown_rc6(dev); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3943 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3944 | return; |
| 3945 | } |
| 3946 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3947 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
| 3948 | intel_ring_emit(ring, MI_SET_CONTEXT); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3949 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 3950 | MI_MM_SPACE_GTT | |
| 3951 | MI_SAVE_EXT_STATE_EN | |
| 3952 | MI_RESTORE_EXT_STATE_EN | |
| 3953 | MI_RESTORE_INHIBIT); |
| 3954 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
| 3955 | intel_ring_emit(ring, MI_NOOP); |
| 3956 | intel_ring_emit(ring, MI_FLUSH); |
| 3957 | intel_ring_advance(ring); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3958 | |
| 3959 | /* |
| 3960 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
| 3961 | * does an implicit flush, combined with MI_FLUSH above, it should be |
| 3962 | * safe to assume that renderctx is valid |
| 3963 | */ |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 3964 | ret = intel_ring_idle(ring); |
| 3965 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3966 | if (ret) { |
Jani Nikula | def27a5 | 2013-03-12 10:49:19 +0200 | [diff] [blame] | 3967 | DRM_ERROR("failed to enable ironlake power savings\n"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3968 | ironlake_teardown_rc6(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3969 | return; |
| 3970 | } |
| 3971 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3972 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3973 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3974 | |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 3975 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3976 | } |
| 3977 | |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 3978 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 3979 | { |
| 3980 | unsigned long freq; |
| 3981 | int div = (vidfreq & 0x3f0000) >> 16; |
| 3982 | int post = (vidfreq & 0x3000) >> 12; |
| 3983 | int pre = (vidfreq & 0x7); |
| 3984 | |
| 3985 | if (!pre) |
| 3986 | return 0; |
| 3987 | |
| 3988 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 3989 | |
| 3990 | return freq; |
| 3991 | } |
| 3992 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 3993 | static const struct cparams { |
| 3994 | u16 i; |
| 3995 | u16 t; |
| 3996 | u16 m; |
| 3997 | u16 c; |
| 3998 | } cparams[] = { |
| 3999 | { 1, 1333, 301, 28664 }, |
| 4000 | { 1, 1066, 294, 24460 }, |
| 4001 | { 1, 800, 294, 25192 }, |
| 4002 | { 0, 1333, 276, 27605 }, |
| 4003 | { 0, 1066, 276, 27605 }, |
| 4004 | { 0, 800, 231, 23784 }, |
| 4005 | }; |
| 4006 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4007 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4008 | { |
| 4009 | u64 total_count, diff, ret; |
| 4010 | u32 count1, count2, count3, m = 0, c = 0; |
| 4011 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 4012 | int i; |
| 4013 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4014 | assert_spin_locked(&mchdev_lock); |
| 4015 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4016 | diff1 = now - dev_priv->ips.last_time1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4017 | |
| 4018 | /* Prevent division-by-zero if we are asking too fast. |
| 4019 | * Also, we don't get interesting results if we are polling |
| 4020 | * faster than once in 10ms, so just return the saved value |
| 4021 | * in such cases. |
| 4022 | */ |
| 4023 | if (diff1 <= 10) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4024 | return dev_priv->ips.chipset_power; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4025 | |
| 4026 | count1 = I915_READ(DMIEC); |
| 4027 | count2 = I915_READ(DDREC); |
| 4028 | count3 = I915_READ(CSIEC); |
| 4029 | |
| 4030 | total_count = count1 + count2 + count3; |
| 4031 | |
| 4032 | /* FIXME: handle per-counter overflow */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4033 | if (total_count < dev_priv->ips.last_count1) { |
| 4034 | diff = ~0UL - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4035 | diff += total_count; |
| 4036 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4037 | diff = total_count - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4038 | } |
| 4039 | |
| 4040 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4041 | if (cparams[i].i == dev_priv->ips.c_m && |
| 4042 | cparams[i].t == dev_priv->ips.r_t) { |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4043 | m = cparams[i].m; |
| 4044 | c = cparams[i].c; |
| 4045 | break; |
| 4046 | } |
| 4047 | } |
| 4048 | |
| 4049 | diff = div_u64(diff, diff1); |
| 4050 | ret = ((m * diff) + c); |
| 4051 | ret = div_u64(ret, 10); |
| 4052 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4053 | dev_priv->ips.last_count1 = total_count; |
| 4054 | dev_priv->ips.last_time1 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4055 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4056 | dev_priv->ips.chipset_power = ret; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4057 | |
| 4058 | return ret; |
| 4059 | } |
| 4060 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4061 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 4062 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4063 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4064 | unsigned long val; |
| 4065 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4066 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4067 | return 0; |
| 4068 | |
| 4069 | spin_lock_irq(&mchdev_lock); |
| 4070 | |
| 4071 | val = __i915_chipset_val(dev_priv); |
| 4072 | |
| 4073 | spin_unlock_irq(&mchdev_lock); |
| 4074 | |
| 4075 | return val; |
| 4076 | } |
| 4077 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4078 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 4079 | { |
| 4080 | unsigned long m, x, b; |
| 4081 | u32 tsfs; |
| 4082 | |
| 4083 | tsfs = I915_READ(TSFS); |
| 4084 | |
| 4085 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 4086 | x = I915_READ8(TR1); |
| 4087 | |
| 4088 | b = tsfs & TSFS_INTR_MASK; |
| 4089 | |
| 4090 | return ((m * x) / 127) - b; |
| 4091 | } |
| 4092 | |
| 4093 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
| 4094 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4095 | struct drm_device *dev = dev_priv->dev; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4096 | static const struct v_table { |
| 4097 | u16 vd; /* in .1 mil */ |
| 4098 | u16 vm; /* in .1 mil */ |
| 4099 | } v_table[] = { |
| 4100 | { 0, 0, }, |
| 4101 | { 375, 0, }, |
| 4102 | { 500, 0, }, |
| 4103 | { 625, 0, }, |
| 4104 | { 750, 0, }, |
| 4105 | { 875, 0, }, |
| 4106 | { 1000, 0, }, |
| 4107 | { 1125, 0, }, |
| 4108 | { 4125, 3000, }, |
| 4109 | { 4125, 3000, }, |
| 4110 | { 4125, 3000, }, |
| 4111 | { 4125, 3000, }, |
| 4112 | { 4125, 3000, }, |
| 4113 | { 4125, 3000, }, |
| 4114 | { 4125, 3000, }, |
| 4115 | { 4125, 3000, }, |
| 4116 | { 4125, 3000, }, |
| 4117 | { 4125, 3000, }, |
| 4118 | { 4125, 3000, }, |
| 4119 | { 4125, 3000, }, |
| 4120 | { 4125, 3000, }, |
| 4121 | { 4125, 3000, }, |
| 4122 | { 4125, 3000, }, |
| 4123 | { 4125, 3000, }, |
| 4124 | { 4125, 3000, }, |
| 4125 | { 4125, 3000, }, |
| 4126 | { 4125, 3000, }, |
| 4127 | { 4125, 3000, }, |
| 4128 | { 4125, 3000, }, |
| 4129 | { 4125, 3000, }, |
| 4130 | { 4125, 3000, }, |
| 4131 | { 4125, 3000, }, |
| 4132 | { 4250, 3125, }, |
| 4133 | { 4375, 3250, }, |
| 4134 | { 4500, 3375, }, |
| 4135 | { 4625, 3500, }, |
| 4136 | { 4750, 3625, }, |
| 4137 | { 4875, 3750, }, |
| 4138 | { 5000, 3875, }, |
| 4139 | { 5125, 4000, }, |
| 4140 | { 5250, 4125, }, |
| 4141 | { 5375, 4250, }, |
| 4142 | { 5500, 4375, }, |
| 4143 | { 5625, 4500, }, |
| 4144 | { 5750, 4625, }, |
| 4145 | { 5875, 4750, }, |
| 4146 | { 6000, 4875, }, |
| 4147 | { 6125, 5000, }, |
| 4148 | { 6250, 5125, }, |
| 4149 | { 6375, 5250, }, |
| 4150 | { 6500, 5375, }, |
| 4151 | { 6625, 5500, }, |
| 4152 | { 6750, 5625, }, |
| 4153 | { 6875, 5750, }, |
| 4154 | { 7000, 5875, }, |
| 4155 | { 7125, 6000, }, |
| 4156 | { 7250, 6125, }, |
| 4157 | { 7375, 6250, }, |
| 4158 | { 7500, 6375, }, |
| 4159 | { 7625, 6500, }, |
| 4160 | { 7750, 6625, }, |
| 4161 | { 7875, 6750, }, |
| 4162 | { 8000, 6875, }, |
| 4163 | { 8125, 7000, }, |
| 4164 | { 8250, 7125, }, |
| 4165 | { 8375, 7250, }, |
| 4166 | { 8500, 7375, }, |
| 4167 | { 8625, 7500, }, |
| 4168 | { 8750, 7625, }, |
| 4169 | { 8875, 7750, }, |
| 4170 | { 9000, 7875, }, |
| 4171 | { 9125, 8000, }, |
| 4172 | { 9250, 8125, }, |
| 4173 | { 9375, 8250, }, |
| 4174 | { 9500, 8375, }, |
| 4175 | { 9625, 8500, }, |
| 4176 | { 9750, 8625, }, |
| 4177 | { 9875, 8750, }, |
| 4178 | { 10000, 8875, }, |
| 4179 | { 10125, 9000, }, |
| 4180 | { 10250, 9125, }, |
| 4181 | { 10375, 9250, }, |
| 4182 | { 10500, 9375, }, |
| 4183 | { 10625, 9500, }, |
| 4184 | { 10750, 9625, }, |
| 4185 | { 10875, 9750, }, |
| 4186 | { 11000, 9875, }, |
| 4187 | { 11125, 10000, }, |
| 4188 | { 11250, 10125, }, |
| 4189 | { 11375, 10250, }, |
| 4190 | { 11500, 10375, }, |
| 4191 | { 11625, 10500, }, |
| 4192 | { 11750, 10625, }, |
| 4193 | { 11875, 10750, }, |
| 4194 | { 12000, 10875, }, |
| 4195 | { 12125, 11000, }, |
| 4196 | { 12250, 11125, }, |
| 4197 | { 12375, 11250, }, |
| 4198 | { 12500, 11375, }, |
| 4199 | { 12625, 11500, }, |
| 4200 | { 12750, 11625, }, |
| 4201 | { 12875, 11750, }, |
| 4202 | { 13000, 11875, }, |
| 4203 | { 13125, 12000, }, |
| 4204 | { 13250, 12125, }, |
| 4205 | { 13375, 12250, }, |
| 4206 | { 13500, 12375, }, |
| 4207 | { 13625, 12500, }, |
| 4208 | { 13750, 12625, }, |
| 4209 | { 13875, 12750, }, |
| 4210 | { 14000, 12875, }, |
| 4211 | { 14125, 13000, }, |
| 4212 | { 14250, 13125, }, |
| 4213 | { 14375, 13250, }, |
| 4214 | { 14500, 13375, }, |
| 4215 | { 14625, 13500, }, |
| 4216 | { 14750, 13625, }, |
| 4217 | { 14875, 13750, }, |
| 4218 | { 15000, 13875, }, |
| 4219 | { 15125, 14000, }, |
| 4220 | { 15250, 14125, }, |
| 4221 | { 15375, 14250, }, |
| 4222 | { 15500, 14375, }, |
| 4223 | { 15625, 14500, }, |
| 4224 | { 15750, 14625, }, |
| 4225 | { 15875, 14750, }, |
| 4226 | { 16000, 14875, }, |
| 4227 | { 16125, 15000, }, |
| 4228 | }; |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4229 | if (INTEL_INFO(dev)->is_mobile) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4230 | return v_table[pxvid].vm; |
| 4231 | else |
| 4232 | return v_table[pxvid].vd; |
| 4233 | } |
| 4234 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4235 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4236 | { |
| 4237 | struct timespec now, diff1; |
| 4238 | u64 diff; |
| 4239 | unsigned long diffms; |
| 4240 | u32 count; |
| 4241 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4242 | assert_spin_locked(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4243 | |
| 4244 | getrawmonotonic(&now); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4245 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4246 | |
| 4247 | /* Don't divide by 0 */ |
| 4248 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
| 4249 | if (!diffms) |
| 4250 | return; |
| 4251 | |
| 4252 | count = I915_READ(GFXEC); |
| 4253 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4254 | if (count < dev_priv->ips.last_count2) { |
| 4255 | diff = ~0UL - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4256 | diff += count; |
| 4257 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4258 | diff = count - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4259 | } |
| 4260 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4261 | dev_priv->ips.last_count2 = count; |
| 4262 | dev_priv->ips.last_time2 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4263 | |
| 4264 | /* More magic constants... */ |
| 4265 | diff = diff * 1181; |
| 4266 | diff = div_u64(diff, diffms * 10); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4267 | dev_priv->ips.gfx_power = diff; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4268 | } |
| 4269 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4270 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 4271 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4272 | struct drm_device *dev = dev_priv->dev; |
| 4273 | |
| 4274 | if (INTEL_INFO(dev)->gen != 5) |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4275 | return; |
| 4276 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4277 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4278 | |
| 4279 | __i915_update_gfx_val(dev_priv); |
| 4280 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4281 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4282 | } |
| 4283 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4284 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4285 | { |
| 4286 | unsigned long t, corr, state1, corr2, state2; |
| 4287 | u32 pxvid, ext_v; |
| 4288 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4289 | assert_spin_locked(&mchdev_lock); |
| 4290 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4291 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4292 | pxvid = (pxvid >> 24) & 0x7f; |
| 4293 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 4294 | |
| 4295 | state1 = ext_v; |
| 4296 | |
| 4297 | t = i915_mch_val(dev_priv); |
| 4298 | |
| 4299 | /* Revel in the empirically derived constants */ |
| 4300 | |
| 4301 | /* Correction factor in 1/100000 units */ |
| 4302 | if (t > 80) |
| 4303 | corr = ((t * 2349) + 135940); |
| 4304 | else if (t >= 50) |
| 4305 | corr = ((t * 964) + 29317); |
| 4306 | else /* < 50 */ |
| 4307 | corr = ((t * 301) + 1004); |
| 4308 | |
| 4309 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 4310 | corr /= 100000; |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4311 | corr2 = (corr * dev_priv->ips.corr); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4312 | |
| 4313 | state2 = (corr2 * state1) / 10000; |
| 4314 | state2 /= 100; /* convert to mW */ |
| 4315 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4316 | __i915_update_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4317 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4318 | return dev_priv->ips.gfx_power + state2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4319 | } |
| 4320 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4321 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 4322 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4323 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4324 | unsigned long val; |
| 4325 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4326 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4327 | return 0; |
| 4328 | |
| 4329 | spin_lock_irq(&mchdev_lock); |
| 4330 | |
| 4331 | val = __i915_gfx_val(dev_priv); |
| 4332 | |
| 4333 | spin_unlock_irq(&mchdev_lock); |
| 4334 | |
| 4335 | return val; |
| 4336 | } |
| 4337 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4338 | /** |
| 4339 | * i915_read_mch_val - return value for IPS use |
| 4340 | * |
| 4341 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 4342 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 4343 | */ |
| 4344 | unsigned long i915_read_mch_val(void) |
| 4345 | { |
| 4346 | struct drm_i915_private *dev_priv; |
| 4347 | unsigned long chipset_val, graphics_val, ret = 0; |
| 4348 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4349 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4350 | if (!i915_mch_dev) |
| 4351 | goto out_unlock; |
| 4352 | dev_priv = i915_mch_dev; |
| 4353 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4354 | chipset_val = __i915_chipset_val(dev_priv); |
| 4355 | graphics_val = __i915_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4356 | |
| 4357 | ret = chipset_val + graphics_val; |
| 4358 | |
| 4359 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4360 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4361 | |
| 4362 | return ret; |
| 4363 | } |
| 4364 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 4365 | |
| 4366 | /** |
| 4367 | * i915_gpu_raise - raise GPU frequency limit |
| 4368 | * |
| 4369 | * Raise the limit; IPS indicates we have thermal headroom. |
| 4370 | */ |
| 4371 | bool i915_gpu_raise(void) |
| 4372 | { |
| 4373 | struct drm_i915_private *dev_priv; |
| 4374 | bool ret = true; |
| 4375 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4376 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4377 | if (!i915_mch_dev) { |
| 4378 | ret = false; |
| 4379 | goto out_unlock; |
| 4380 | } |
| 4381 | dev_priv = i915_mch_dev; |
| 4382 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4383 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
| 4384 | dev_priv->ips.max_delay--; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4385 | |
| 4386 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4387 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4388 | |
| 4389 | return ret; |
| 4390 | } |
| 4391 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 4392 | |
| 4393 | /** |
| 4394 | * i915_gpu_lower - lower GPU frequency limit |
| 4395 | * |
| 4396 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 4397 | * frequency maximum. |
| 4398 | */ |
| 4399 | bool i915_gpu_lower(void) |
| 4400 | { |
| 4401 | struct drm_i915_private *dev_priv; |
| 4402 | bool ret = true; |
| 4403 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4404 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4405 | if (!i915_mch_dev) { |
| 4406 | ret = false; |
| 4407 | goto out_unlock; |
| 4408 | } |
| 4409 | dev_priv = i915_mch_dev; |
| 4410 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4411 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
| 4412 | dev_priv->ips.max_delay++; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4413 | |
| 4414 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4415 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4416 | |
| 4417 | return ret; |
| 4418 | } |
| 4419 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 4420 | |
| 4421 | /** |
| 4422 | * i915_gpu_busy - indicate GPU business to IPS |
| 4423 | * |
| 4424 | * Tell the IPS driver whether or not the GPU is busy. |
| 4425 | */ |
| 4426 | bool i915_gpu_busy(void) |
| 4427 | { |
| 4428 | struct drm_i915_private *dev_priv; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4429 | struct intel_ring_buffer *ring; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4430 | bool ret = false; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4431 | int i; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4432 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4433 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4434 | if (!i915_mch_dev) |
| 4435 | goto out_unlock; |
| 4436 | dev_priv = i915_mch_dev; |
| 4437 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4438 | for_each_ring(ring, dev_priv, i) |
| 4439 | ret |= !list_empty(&ring->request_list); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4440 | |
| 4441 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4442 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4443 | |
| 4444 | return ret; |
| 4445 | } |
| 4446 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 4447 | |
| 4448 | /** |
| 4449 | * i915_gpu_turbo_disable - disable graphics turbo |
| 4450 | * |
| 4451 | * Disable graphics turbo by resetting the max frequency and setting the |
| 4452 | * current frequency to the default. |
| 4453 | */ |
| 4454 | bool i915_gpu_turbo_disable(void) |
| 4455 | { |
| 4456 | struct drm_i915_private *dev_priv; |
| 4457 | bool ret = true; |
| 4458 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4459 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4460 | if (!i915_mch_dev) { |
| 4461 | ret = false; |
| 4462 | goto out_unlock; |
| 4463 | } |
| 4464 | dev_priv = i915_mch_dev; |
| 4465 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4466 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4467 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4468 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4469 | ret = false; |
| 4470 | |
| 4471 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4472 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4473 | |
| 4474 | return ret; |
| 4475 | } |
| 4476 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 4477 | |
| 4478 | /** |
| 4479 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 4480 | * IPS got loaded first. |
| 4481 | * |
| 4482 | * This awkward dance is so that neither module has to depend on the |
| 4483 | * other in order for IPS to do the appropriate communication of |
| 4484 | * GPU turbo limits to i915. |
| 4485 | */ |
| 4486 | static void |
| 4487 | ips_ping_for_i915_load(void) |
| 4488 | { |
| 4489 | void (*link)(void); |
| 4490 | |
| 4491 | link = symbol_get(ips_link_to_i915_driver); |
| 4492 | if (link) { |
| 4493 | link(); |
| 4494 | symbol_put(ips_link_to_i915_driver); |
| 4495 | } |
| 4496 | } |
| 4497 | |
| 4498 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
| 4499 | { |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4500 | /* We only register the i915 ips part with intel-ips once everything is |
| 4501 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4502 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4503 | i915_mch_dev = dev_priv; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4504 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4505 | |
| 4506 | ips_ping_for_i915_load(); |
| 4507 | } |
| 4508 | |
| 4509 | void intel_gpu_ips_teardown(void) |
| 4510 | { |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4511 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4512 | i915_mch_dev = NULL; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4513 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4514 | } |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4515 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4516 | static void intel_init_emon(struct drm_device *dev) |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 4517 | { |
| 4518 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4519 | u32 lcfuse; |
| 4520 | u8 pxw[16]; |
| 4521 | int i; |
| 4522 | |
| 4523 | /* Disable to program */ |
| 4524 | I915_WRITE(ECR, 0); |
| 4525 | POSTING_READ(ECR); |
| 4526 | |
| 4527 | /* Program energy weights for various events */ |
| 4528 | I915_WRITE(SDEW, 0x15040d00); |
| 4529 | I915_WRITE(CSIEW0, 0x007f0000); |
| 4530 | I915_WRITE(CSIEW1, 0x1e220004); |
| 4531 | I915_WRITE(CSIEW2, 0x04000004); |
| 4532 | |
| 4533 | for (i = 0; i < 5; i++) |
| 4534 | I915_WRITE(PEW + (i * 4), 0); |
| 4535 | for (i = 0; i < 3; i++) |
| 4536 | I915_WRITE(DEW + (i * 4), 0); |
| 4537 | |
| 4538 | /* Program P-state weights to account for frequency power adjustment */ |
| 4539 | for (i = 0; i < 16; i++) { |
| 4540 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 4541 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 4542 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 4543 | PXVFREQ_PX_SHIFT; |
| 4544 | unsigned long val; |
| 4545 | |
| 4546 | val = vid * vid; |
| 4547 | val *= (freq / 1000); |
| 4548 | val *= 255; |
| 4549 | val /= (127*127*900); |
| 4550 | if (val > 0xff) |
| 4551 | DRM_ERROR("bad pxval: %ld\n", val); |
| 4552 | pxw[i] = val; |
| 4553 | } |
| 4554 | /* Render standby states get 0 weight */ |
| 4555 | pxw[14] = 0; |
| 4556 | pxw[15] = 0; |
| 4557 | |
| 4558 | for (i = 0; i < 4; i++) { |
| 4559 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 4560 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 4561 | I915_WRITE(PXW + (i * 4), val); |
| 4562 | } |
| 4563 | |
| 4564 | /* Adjust magic regs to magic values (more experimental results) */ |
| 4565 | I915_WRITE(OGW0, 0); |
| 4566 | I915_WRITE(OGW1, 0); |
| 4567 | I915_WRITE(EG0, 0x00007f00); |
| 4568 | I915_WRITE(EG1, 0x0000000e); |
| 4569 | I915_WRITE(EG2, 0x000e0000); |
| 4570 | I915_WRITE(EG3, 0x68000300); |
| 4571 | I915_WRITE(EG4, 0x42000000); |
| 4572 | I915_WRITE(EG5, 0x00140031); |
| 4573 | I915_WRITE(EG6, 0); |
| 4574 | I915_WRITE(EG7, 0); |
| 4575 | |
| 4576 | for (i = 0; i < 8; i++) |
| 4577 | I915_WRITE(PXWL + (i * 4), 0); |
| 4578 | |
| 4579 | /* Enable PMON + select events */ |
| 4580 | I915_WRITE(ECR, 0x80000019); |
| 4581 | |
| 4582 | lcfuse = I915_READ(LCFUSE02); |
| 4583 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4584 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 4585 | } |
| 4586 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4587 | void intel_init_gt_powersave(struct drm_device *dev) |
| 4588 | { |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 4589 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
| 4590 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4591 | if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4592 | valleyview_init_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4593 | } |
| 4594 | |
| 4595 | void intel_cleanup_gt_powersave(struct drm_device *dev) |
| 4596 | { |
| 4597 | if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4598 | valleyview_cleanup_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4599 | } |
| 4600 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4601 | void intel_disable_gt_powersave(struct drm_device *dev) |
| 4602 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4603 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4604 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 4605 | /* Interrupts should be disabled already to avoid re-arming. */ |
| 4606 | WARN_ON(dev->irq_enabled); |
| 4607 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4608 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4609 | ironlake_disable_drps(dev); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4610 | ironlake_disable_rc6(dev); |
Imre Deak | 14dd0ea | 2014-04-14 20:24:34 +0300 | [diff] [blame] | 4611 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4612 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
Jesse Barnes | 250848c | 2013-04-23 10:09:27 -0700 | [diff] [blame] | 4613 | cancel_work_sync(&dev_priv->rps.work); |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4614 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 4615 | if (IS_VALLEYVIEW(dev)) |
| 4616 | valleyview_disable_rps(dev); |
| 4617 | else |
| 4618 | gen6_disable_rps(dev); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 4619 | dev_priv->rps.enabled = false; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4620 | mutex_unlock(&dev_priv->rps.hw_lock); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4621 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4622 | } |
| 4623 | |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4624 | static void intel_gen6_powersave_work(struct work_struct *work) |
| 4625 | { |
| 4626 | struct drm_i915_private *dev_priv = |
| 4627 | container_of(work, struct drm_i915_private, |
| 4628 | rps.delayed_resume_work.work); |
| 4629 | struct drm_device *dev = dev_priv->dev; |
| 4630 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4631 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4632 | |
| 4633 | if (IS_VALLEYVIEW(dev)) { |
| 4634 | valleyview_enable_rps(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 4635 | } else if (IS_BROADWELL(dev)) { |
| 4636 | gen8_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 4637 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4638 | } else { |
| 4639 | gen6_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 4640 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4641 | } |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 4642 | dev_priv->rps.enabled = true; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 4643 | mutex_unlock(&dev_priv->rps.hw_lock); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 4644 | |
| 4645 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4646 | } |
| 4647 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4648 | void intel_enable_gt_powersave(struct drm_device *dev) |
| 4649 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4650 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4651 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4652 | if (IS_IRONLAKE_M(dev)) { |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 4653 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4654 | ironlake_enable_drps(dev); |
| 4655 | ironlake_enable_rc6(dev); |
| 4656 | intel_init_emon(dev); |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 4657 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4658 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4659 | /* |
| 4660 | * PCU communication is slow and this doesn't need to be |
| 4661 | * done at any specific time, so do this out of our fast path |
| 4662 | * to make resume and init faster. |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 4663 | * |
| 4664 | * We depend on the HW RC6 power context save/restore |
| 4665 | * mechanism when entering D3 through runtime PM suspend. So |
| 4666 | * disable RPM until RPS/RC6 is properly setup. We can only |
| 4667 | * get here via the driver load/system resume/runtime resume |
| 4668 | * paths, so the _noresume version is enough (and in case of |
| 4669 | * runtime resume it's necessary). |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 4670 | */ |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 4671 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
| 4672 | round_jiffies_up_relative(HZ))) |
| 4673 | intel_runtime_pm_get_noresume(dev_priv); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4674 | } |
| 4675 | } |
| 4676 | |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 4677 | void intel_reset_gt_powersave(struct drm_device *dev) |
| 4678 | { |
| 4679 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4680 | |
| 4681 | dev_priv->rps.enabled = false; |
| 4682 | intel_enable_gt_powersave(dev); |
| 4683 | } |
| 4684 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4685 | static void ibx_init_clock_gating(struct drm_device *dev) |
| 4686 | { |
| 4687 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4688 | |
| 4689 | /* |
| 4690 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 4691 | * gating for the panel power sequencer or it will fail to |
| 4692 | * start up when no ports are active. |
| 4693 | */ |
| 4694 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 4695 | } |
| 4696 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4697 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
| 4698 | { |
| 4699 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4700 | int pipe; |
| 4701 | |
| 4702 | for_each_pipe(pipe) { |
| 4703 | I915_WRITE(DSPCNTR(pipe), |
| 4704 | I915_READ(DSPCNTR(pipe)) | |
| 4705 | DISPPLANE_TRICKLE_FEED_DISABLE); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 4706 | intel_flush_primary_plane(dev_priv, pipe); |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4707 | } |
| 4708 | } |
| 4709 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 4710 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
| 4711 | { |
| 4712 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4713 | |
| 4714 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
| 4715 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); |
| 4716 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
| 4717 | |
| 4718 | /* |
| 4719 | * Don't touch WM1S_LP_EN here. |
| 4720 | * Doing so could cause underruns. |
| 4721 | */ |
| 4722 | } |
| 4723 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4724 | static void ironlake_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4725 | { |
| 4726 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4727 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4728 | |
Damien Lespiau | f1e8fa5 | 2013-06-07 17:41:09 +0100 | [diff] [blame] | 4729 | /* |
| 4730 | * Required for FBC |
| 4731 | * WaFbcDisableDpfcClockGating:ilk |
| 4732 | */ |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 4733 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 4734 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
| 4735 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4736 | |
| 4737 | I915_WRITE(PCH_3DCGDIS0, |
| 4738 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 4739 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 4740 | I915_WRITE(PCH_3DCGDIS1, |
| 4741 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 4742 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4743 | /* |
| 4744 | * According to the spec the following bits should be set in |
| 4745 | * order to enable memory self-refresh |
| 4746 | * The bit 22/21 of 0x42004 |
| 4747 | * The bit 5 of 0x42020 |
| 4748 | * The bit 15 of 0x45000 |
| 4749 | */ |
| 4750 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4751 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4752 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 4753 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4754 | I915_WRITE(DISP_ARB_CTL, |
| 4755 | (I915_READ(DISP_ARB_CTL) | |
| 4756 | DISP_FBC_WM_DIS)); |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 4757 | |
| 4758 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4759 | |
| 4760 | /* |
| 4761 | * Based on the document from hardware guys the following bits |
| 4762 | * should be set unconditionally in order to enable FBC. |
| 4763 | * The bit 22 of 0x42000 |
| 4764 | * The bit 22 of 0x42004 |
| 4765 | * The bit 7,8,9 of 0x42020. |
| 4766 | */ |
| 4767 | if (IS_IRONLAKE_M(dev)) { |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 4768 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4769 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 4770 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 4771 | ILK_FBCQ_DIS); |
| 4772 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4773 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4774 | ILK_DPARB_GATE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4775 | } |
| 4776 | |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 4777 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
| 4778 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4779 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4780 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4781 | ILK_ELPIN_409_SELECT); |
| 4782 | I915_WRITE(_3D_CHICKEN2, |
| 4783 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 4784 | _3D_CHICKEN2_WM_READ_PIPELINED); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 4785 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4786 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 4787 | I915_WRITE(CACHE_MODE_0, |
| 4788 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4789 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 4790 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
| 4791 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 4792 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4793 | g4x_disable_trickle_feed(dev); |
Ville Syrjälä | bdad2b2 | 2013-06-07 10:47:03 +0300 | [diff] [blame] | 4794 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4795 | ibx_init_clock_gating(dev); |
| 4796 | } |
| 4797 | |
| 4798 | static void cpt_init_clock_gating(struct drm_device *dev) |
| 4799 | { |
| 4800 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4801 | int pipe; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4802 | uint32_t val; |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4803 | |
| 4804 | /* |
| 4805 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 4806 | * gating for the panel power sequencer or it will fail to |
| 4807 | * start up when no ports are active. |
| 4808 | */ |
Jesse Barnes | cd66407 | 2013-10-02 10:34:19 -0700 | [diff] [blame] | 4809 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
| 4810 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | |
| 4811 | PCH_CPUNIT_CLOCK_GATE_DISABLE); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4812 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 4813 | DPLS_EDP_PPS_FIX_DIS); |
Takashi Iwai | 335c07b | 2012-12-11 11:46:29 +0100 | [diff] [blame] | 4814 | /* The below fixes the weird display corruption, a few pixels shifted |
| 4815 | * downward, on (only) LVDS of some HP laptops with IVY. |
| 4816 | */ |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4817 | for_each_pipe(pipe) { |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 4818 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
| 4819 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 4820 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 4821 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4822 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 4823 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
| 4824 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
| 4825 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 4826 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
| 4827 | } |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4828 | /* WADP0ClockGatingDisable */ |
| 4829 | for_each_pipe(pipe) { |
| 4830 | I915_WRITE(TRANS_CHICKEN1(pipe), |
| 4831 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
| 4832 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4833 | } |
| 4834 | |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 4835 | static void gen6_check_mch_setup(struct drm_device *dev) |
| 4836 | { |
| 4837 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4838 | uint32_t tmp; |
| 4839 | |
| 4840 | tmp = I915_READ(MCH_SSKPD); |
| 4841 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { |
| 4842 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); |
| 4843 | DRM_INFO("This can cause pipe underruns and display issues.\n"); |
| 4844 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); |
| 4845 | } |
| 4846 | } |
| 4847 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 4848 | static void gen6_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4849 | { |
| 4850 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4851 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4852 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4853 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4854 | |
| 4855 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4856 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4857 | ILK_ELPIN_409_SELECT); |
| 4858 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4859 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
Daniel Vetter | 4283908 | 2012-12-14 23:38:28 +0100 | [diff] [blame] | 4860 | I915_WRITE(_3D_CHICKEN, |
| 4861 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
| 4862 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 4863 | /* WaSetupGtModeTdRowDispatch:snb */ |
Daniel Vetter | 6547fbd | 2012-12-14 23:38:29 +0100 | [diff] [blame] | 4864 | if (IS_SNB_GT1(dev)) |
| 4865 | I915_WRITE(GEN6_GT_MODE, |
| 4866 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); |
| 4867 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 4868 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
| 4869 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 4870 | |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 4871 | /* |
| 4872 | * BSpec recoomends 8x4 when MSAA is used, |
| 4873 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 4874 | * |
| 4875 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 4876 | * disable bit, which we don't touch here, but it's good |
| 4877 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 4878 | */ |
| 4879 | I915_WRITE(GEN6_GT_MODE, |
| 4880 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 4881 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 4882 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4883 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4884 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4885 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4886 | |
| 4887 | I915_WRITE(GEN6_UCGCTL1, |
| 4888 | I915_READ(GEN6_UCGCTL1) | |
| 4889 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
| 4890 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
| 4891 | |
| 4892 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 4893 | * gating disable must be set. Failure to set it results in |
| 4894 | * flickering pixels due to Z write ordering failures after |
| 4895 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 4896 | * Sanctuary and Tropics, and apparently anything else with |
| 4897 | * alpha test or pixel discard. |
| 4898 | * |
| 4899 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 4900 | * but we didn't debug actual testcases to find it out. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 4901 | * |
Ville Syrjälä | ef59318 | 2014-01-22 21:32:47 +0200 | [diff] [blame] | 4902 | * WaDisableRCCUnitClockGating:snb |
| 4903 | * WaDisableRCPBUnitClockGating:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4904 | */ |
| 4905 | I915_WRITE(GEN6_UCGCTL2, |
| 4906 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 4907 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 4908 | |
Ville Syrjälä | 5eb146d | 2014-02-04 21:59:16 +0200 | [diff] [blame] | 4909 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
Ville Syrjälä | 743b57d | 2014-02-04 21:59:17 +0200 | [diff] [blame] | 4910 | I915_WRITE(_3D_CHICKEN3, |
| 4911 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4912 | |
| 4913 | /* |
Ville Syrjälä | e927ecd | 2014-02-04 21:59:18 +0200 | [diff] [blame] | 4914 | * Bspec says: |
| 4915 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and |
| 4916 | * 3DSTATE_SF number of SF output attributes is more than 16." |
| 4917 | */ |
| 4918 | I915_WRITE(_3D_CHICKEN3, |
| 4919 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); |
| 4920 | |
| 4921 | /* |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4922 | * According to the spec the following bits should be |
| 4923 | * set in order to enable memory self-refresh and fbc: |
| 4924 | * The bit21 and bit22 of 0x42000 |
| 4925 | * The bit21 and bit22 of 0x42004 |
| 4926 | * The bit5 and bit7 of 0x42020 |
| 4927 | * The bit14 of 0x70180 |
| 4928 | * The bit14 of 0x71180 |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 4929 | * |
| 4930 | * WaFbcAsynchFlipDisableFbcQueue:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4931 | */ |
| 4932 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 4933 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 4934 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 4935 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 4936 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 4937 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 4938 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 4939 | I915_READ(ILK_DSPCLK_GATE_D) | |
| 4940 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
| 4941 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4942 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 4943 | g4x_disable_trickle_feed(dev); |
Ben Widawsky | f8f2ac9 | 2012-10-03 19:34:24 -0700 | [diff] [blame] | 4944 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 4945 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 4946 | |
| 4947 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4948 | } |
| 4949 | |
| 4950 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
| 4951 | { |
| 4952 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
| 4953 | |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 4954 | /* |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 4955 | * WaVSThreadDispatchOverride:ivb,vlv |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 4956 | * |
| 4957 | * This actually overrides the dispatch |
| 4958 | * mode for all thread types. |
| 4959 | */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 4960 | reg &= ~GEN7_FF_SCHED_MASK; |
| 4961 | reg |= GEN7_FF_TS_SCHED_HW; |
| 4962 | reg |= GEN7_FF_VS_SCHED_HW; |
| 4963 | reg |= GEN7_FF_DS_SCHED_HW; |
| 4964 | |
| 4965 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
| 4966 | } |
| 4967 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 4968 | static void lpt_init_clock_gating(struct drm_device *dev) |
| 4969 | { |
| 4970 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4971 | |
| 4972 | /* |
| 4973 | * TODO: this bit should only be enabled when really needed, then |
| 4974 | * disabled when not needed anymore in order to save power. |
| 4975 | */ |
| 4976 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
| 4977 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
| 4978 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
| 4979 | PCH_LP_PARTITION_LEVEL_DISABLE); |
Paulo Zanoni | 0a790cd | 2013-04-17 18:15:49 -0300 | [diff] [blame] | 4980 | |
| 4981 | /* WADPOClockGatingDisable:hsw */ |
| 4982 | I915_WRITE(_TRANSA_CHICKEN1, |
| 4983 | I915_READ(_TRANSA_CHICKEN1) | |
| 4984 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 4985 | } |
| 4986 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 4987 | static void lpt_suspend_hw(struct drm_device *dev) |
| 4988 | { |
| 4989 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4990 | |
| 4991 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 4992 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 4993 | |
| 4994 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 4995 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 4996 | } |
| 4997 | } |
| 4998 | |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 4999 | static void gen8_init_clock_gating(struct drm_device *dev) |
| 5000 | { |
| 5001 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5002 | enum pipe pipe; |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5003 | |
| 5004 | I915_WRITE(WM3_LP_ILK, 0); |
| 5005 | I915_WRITE(WM2_LP_ILK, 0); |
| 5006 | I915_WRITE(WM1_LP_ILK, 0); |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 5007 | |
| 5008 | /* FIXME(BDW): Check all the w/a, some might only apply to |
| 5009 | * pre-production hw. */ |
| 5010 | |
Kenneth Graunke | c8966e1 | 2014-02-26 23:59:30 -0800 | [diff] [blame] | 5011 | /* WaDisablePartialInstShootdown:bdw */ |
| 5012 | I915_WRITE(GEN8_ROW_CHICKEN, |
| 5013 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); |
| 5014 | |
Kenneth Graunke | 1411e6a | 2014-02-26 23:59:31 -0800 | [diff] [blame] | 5015 | /* WaDisableThreadStallDopClockGating:bdw */ |
| 5016 | /* FIXME: Unclear whether we really need this on production bdw. */ |
| 5017 | I915_WRITE(GEN8_ROW_CHICKEN, |
| 5018 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); |
| 5019 | |
Damien Lespiau | 4167e32 | 2014-01-16 16:51:35 +0000 | [diff] [blame] | 5020 | /* |
| 5021 | * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for |
| 5022 | * pre-production hardware |
| 5023 | */ |
Ben Widawsky | fd392b6 | 2013-11-04 22:52:39 -0800 | [diff] [blame] | 5024 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 5025 | _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS)); |
Ben Widawsky | bf66347 | 2013-11-02 21:07:57 -0700 | [diff] [blame] | 5026 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 5027 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); |
Ben Widawsky | 4afe8d3 | 2013-11-02 21:07:55 -0700 | [diff] [blame] | 5028 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); |
| 5029 | |
Ben Widawsky | 7f88da0 | 2013-11-02 21:07:58 -0700 | [diff] [blame] | 5030 | I915_WRITE(_3D_CHICKEN3, |
| 5031 | _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); |
| 5032 | |
Ben Widawsky | a75f362 | 2013-11-02 21:07:59 -0700 | [diff] [blame] | 5033 | I915_WRITE(COMMON_SLICE_CHICKEN2, |
| 5034 | _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); |
| 5035 | |
Ben Widawsky | 4c2e7a5 | 2013-11-02 21:08:00 -0700 | [diff] [blame] | 5036 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 5037 | _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); |
| 5038 | |
Ben Widawsky | 242a401 | 2014-04-18 18:04:29 -0300 | [diff] [blame] | 5039 | /* WaDisableDopClockGating:bdw May not be needed for production */ |
| 5040 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5041 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 5042 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5043 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 5044 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5045 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5046 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5047 | I915_WRITE(CHICKEN_PAR1_1, |
| 5048 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); |
| 5049 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5050 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5051 | for_each_pipe(pipe) { |
| 5052 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
Ville Syrjälä | c7c6562 | 2014-03-05 13:05:45 +0200 | [diff] [blame] | 5053 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
Ville Syrjälä | 8f670bb | 2014-03-05 13:05:47 +0200 | [diff] [blame] | 5054 | BDW_DPRS_MASK_VBLANK_SRD); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5055 | } |
Ben Widawsky | 63801f2 | 2013-12-12 17:26:03 -0800 | [diff] [blame] | 5056 | |
| 5057 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 5058 | * workaround for for a possible hang in the unlikely event a TLB |
| 5059 | * invalidation occurs during a PSD flush. |
| 5060 | */ |
| 5061 | I915_WRITE(HDC_CHICKEN0, |
| 5062 | I915_READ(HDC_CHICKEN0) | |
| 5063 | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5064 | |
| 5065 | /* WaVSRefCountFullforceMissDisable:bdw */ |
| 5066 | /* WaDSRefCountFullforceMissDisable:bdw */ |
| 5067 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 5068 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 5069 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | 36075a4 | 2014-02-04 21:59:21 +0200 | [diff] [blame] | 5070 | |
| 5071 | /* |
| 5072 | * BSpec recommends 8x4 when MSAA is used, |
| 5073 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5074 | * |
| 5075 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5076 | * disable bit, which we don't touch here, but it's good |
| 5077 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | 36075a4 | 2014-02-04 21:59:21 +0200 | [diff] [blame] | 5078 | */ |
| 5079 | I915_WRITE(GEN7_GT_MODE, |
| 5080 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
Ville Syrjälä | 295e8bb | 2014-02-27 21:59:01 +0200 | [diff] [blame] | 5081 | |
| 5082 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 5083 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 4f1ca9e | 2014-02-27 21:59:02 +0200 | [diff] [blame] | 5084 | |
| 5085 | /* WaDisableSDEUnitClockGating:bdw */ |
| 5086 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 5087 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Damien Lespiau | 5d70868 | 2014-03-26 18:41:51 +0000 | [diff] [blame] | 5088 | |
| 5089 | /* Wa4x4STCOptimizationDisable:bdw */ |
| 5090 | I915_WRITE(CACHE_MODE_1, |
| 5091 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5092 | } |
| 5093 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5094 | static void haswell_init_clock_gating(struct drm_device *dev) |
| 5095 | { |
| 5096 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5097 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5098 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5099 | |
Francisco Jerez | f3fc488 | 2013-10-02 15:53:16 -0700 | [diff] [blame] | 5100 | /* L3 caching of data atomics doesn't work -- disable it. */ |
| 5101 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); |
| 5102 | I915_WRITE(HSW_ROW_CHICKEN3, |
| 5103 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); |
| 5104 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5105 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5106 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 5107 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 5108 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 5109 | |
Ville Syrjälä | e36ea7f | 2014-01-22 21:33:00 +0200 | [diff] [blame] | 5110 | /* WaVSRefCountFullforceMissDisable:hsw */ |
| 5111 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 5112 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5113 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5114 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
| 5115 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5116 | |
Chia-I Wu | fe27c60 | 2014-01-28 13:29:33 +0800 | [diff] [blame] | 5117 | /* enable HiZ Raw Stall Optimization */ |
| 5118 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 5119 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 5120 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5121 | /* WaDisable4x2SubspanOptimization:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5122 | I915_WRITE(CACHE_MODE_1, |
| 5123 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 5124 | |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 5125 | /* |
| 5126 | * BSpec recommends 8x4 when MSAA is used, |
| 5127 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5128 | * |
| 5129 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5130 | * disable bit, which we don't touch here, but it's good |
| 5131 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 5132 | */ |
| 5133 | I915_WRITE(GEN7_GT_MODE, |
| 5134 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 5135 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5136 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
Ben Widawsky | e3dff58 | 2013-03-20 14:49:14 -0700 | [diff] [blame] | 5137 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
| 5138 | |
Paulo Zanoni | 90a8864 | 2013-05-03 17:23:45 -0300 | [diff] [blame] | 5139 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
| 5140 | I915_WRITE(CHICKEN_PAR1_1, |
| 5141 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 5142 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 5143 | lpt_init_clock_gating(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5144 | } |
| 5145 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5146 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5147 | { |
| 5148 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 5149 | uint32_t snpcr; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5150 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5151 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5152 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5153 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5154 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5155 | /* WaDisableEarlyCull:ivb */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 5156 | I915_WRITE(_3D_CHICKEN3, |
| 5157 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 5158 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5159 | /* WaDisableBackToBackFlipFix:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5160 | I915_WRITE(IVB_CHICKEN3, |
| 5161 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 5162 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 5163 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5164 | /* WaDisablePSDDualDispatchEnable:ivb */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5165 | if (IS_IVB_GT1(dev)) |
| 5166 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 5167 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5168 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5169 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
| 5170 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5171 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5172 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5173 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 5174 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 5175 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5176 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5177 | I915_WRITE(GEN7_L3CNTLREG1, |
| 5178 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 5179 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 5180 | GEN7_WA_L3_CHICKEN_MODE); |
| 5181 | if (IS_IVB_GT1(dev)) |
| 5182 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5183 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 5184 | else { |
| 5185 | /* must write both registers */ |
| 5186 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5187 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 5188 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
| 5189 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 5190 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5191 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5192 | /* WaForceL3Serialization:ivb */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 5193 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 5194 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 5195 | |
Ville Syrjälä | 1b80a19a | 2014-01-22 21:32:53 +0200 | [diff] [blame] | 5196 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5197 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5198 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5199 | */ |
| 5200 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 28acf3b | 2014-01-22 21:32:48 +0200 | [diff] [blame] | 5201 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5202 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5203 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5204 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 5205 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 5206 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 5207 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5208 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5209 | |
| 5210 | gen7_setup_fixed_func_scheduler(dev_priv); |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 5211 | |
Chris Wilson | 2272134 | 2014-03-04 09:41:43 +0000 | [diff] [blame] | 5212 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
| 5213 | /* enable HiZ Raw Stall Optimization */ |
| 5214 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 5215 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 5216 | } |
Chia-I Wu | 116f2b6 | 2014-01-28 13:29:34 +0800 | [diff] [blame] | 5217 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5218 | /* WaDisable4x2SubspanOptimization:ivb */ |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 5219 | I915_WRITE(CACHE_MODE_1, |
| 5220 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 5221 | |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 5222 | /* |
| 5223 | * BSpec recommends 8x4 when MSAA is used, |
| 5224 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5225 | * |
| 5226 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5227 | * disable bit, which we don't touch here, but it's good |
| 5228 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 5229 | */ |
| 5230 | I915_WRITE(GEN7_GT_MODE, |
| 5231 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 5232 | |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 5233 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 5234 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 5235 | snpcr |= GEN6_MBC_SNPCR_MED; |
| 5236 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5237 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 5238 | if (!HAS_PCH_NOP(dev)) |
| 5239 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5240 | |
| 5241 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5242 | } |
| 5243 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5244 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5245 | { |
| 5246 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5247 | u32 val; |
| 5248 | |
| 5249 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5250 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 5251 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5252 | switch ((val >> 6) & 3) { |
| 5253 | case 0: |
Deepak S | f6d5194 | 2014-04-03 21:01:28 +0530 | [diff] [blame] | 5254 | case 1: |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5255 | dev_priv->mem_freq = 800; |
| 5256 | break; |
Jesse Barnes | f64a28a | 2013-11-04 16:07:00 -0800 | [diff] [blame] | 5257 | case 2: |
Deepak S | f6d5194 | 2014-04-03 21:01:28 +0530 | [diff] [blame] | 5258 | dev_priv->mem_freq = 1066; |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5259 | break; |
Jesse Barnes | f64a28a | 2013-11-04 16:07:00 -0800 | [diff] [blame] | 5260 | case 3: |
Chon Ming Lee | 2325991 | 2013-11-07 15:23:26 +0800 | [diff] [blame] | 5261 | dev_priv->mem_freq = 1333; |
Jesse Barnes | f64a28a | 2013-11-04 16:07:00 -0800 | [diff] [blame] | 5262 | break; |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5263 | } |
| 5264 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5265 | |
Imre Deak | d60c447 | 2014-03-27 17:45:10 +0200 | [diff] [blame] | 5266 | dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv); |
| 5267 | DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz", |
| 5268 | dev_priv->vlv_cdclk_freq); |
| 5269 | |
Ville Syrjälä | d7fe0cc | 2013-05-21 18:01:50 +0300 | [diff] [blame] | 5270 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5271 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5272 | /* WaDisableEarlyCull:vlv */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 5273 | I915_WRITE(_3D_CHICKEN3, |
| 5274 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 5275 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5276 | /* WaDisableBackToBackFlipFix:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5277 | I915_WRITE(IVB_CHICKEN3, |
| 5278 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 5279 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 5280 | |
Ville Syrjälä | fad7d36 | 2014-01-22 21:32:39 +0200 | [diff] [blame] | 5281 | /* WaPsdDispatchEnable:vlv */ |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5282 | /* WaDisablePSDDualDispatchEnable:vlv */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5283 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
Jesse Barnes | d3bc030 | 2013-03-08 10:45:51 -0800 | [diff] [blame] | 5284 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
| 5285 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5286 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5287 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
| 5288 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5289 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5290 | /* WaForceL3Serialization:vlv */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 5291 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 5292 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 5293 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5294 | /* WaDisableDopClockGating:vlv */ |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 5295 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5296 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 5297 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5298 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5299 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 5300 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 5301 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 5302 | |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 5303 | gen7_setup_fixed_func_scheduler(dev_priv); |
| 5304 | |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 5305 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5306 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5307 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5308 | */ |
| 5309 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 5310 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5311 | |
Ville Syrjälä | c5c32cd | 2014-01-22 21:32:37 +0200 | [diff] [blame] | 5312 | /* WaDisableL3Bank2xClockGate:vlv */ |
Jesse Barnes | e3f33d4 | 2012-06-14 11:04:50 -0700 | [diff] [blame] | 5313 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
| 5314 | |
Ville Syrjälä | e0d8d59 | 2013-06-12 22:11:18 +0300 | [diff] [blame] | 5315 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5316 | |
Ville Syrjälä | afd58e7 | 2014-01-22 21:33:03 +0200 | [diff] [blame] | 5317 | /* |
| 5318 | * BSpec says this must be set, even though |
| 5319 | * WaDisable4x2SubspanOptimization isn't listed for VLV. |
| 5320 | */ |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 5321 | I915_WRITE(CACHE_MODE_1, |
| 5322 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Jesse Barnes | 7983117 | 2012-06-20 10:53:12 -0700 | [diff] [blame] | 5323 | |
| 5324 | /* |
Ville Syrjälä | 031994e | 2014-01-22 21:32:46 +0200 | [diff] [blame] | 5325 | * WaIncreaseL3CreditsForVLVB0:vlv |
| 5326 | * This is the hardware default actually. |
| 5327 | */ |
| 5328 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); |
| 5329 | |
| 5330 | /* |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5331 | * WaDisableVLVClockGating_VBIIssue:vlv |
Jesse Barnes | 2d80957 | 2012-10-25 12:15:44 -0700 | [diff] [blame] | 5332 | * Disable clock gating on th GCFG unit to prevent a delay |
| 5333 | * in the reporting of vblank events. |
| 5334 | */ |
Ville Syrjälä | 7a0d1ee | 2014-01-22 21:33:04 +0200 | [diff] [blame] | 5335 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5336 | } |
| 5337 | |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame^] | 5338 | static void cherryview_init_clock_gating(struct drm_device *dev) |
| 5339 | { |
| 5340 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5341 | |
| 5342 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
| 5343 | |
| 5344 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
| 5345 | } |
| 5346 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5347 | static void g4x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5348 | { |
| 5349 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5350 | uint32_t dspclk_gate; |
| 5351 | |
| 5352 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 5353 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 5354 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 5355 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 5356 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5357 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 5358 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 5359 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 5360 | if (IS_GM45(dev)) |
| 5361 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 5362 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 5363 | |
| 5364 | /* WaDisableRenderCachePipelinedFlush */ |
| 5365 | I915_WRITE(CACHE_MODE_0, |
| 5366 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 5367 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5368 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
| 5369 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5370 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5371 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5372 | } |
| 5373 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5374 | static void crestline_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5375 | { |
| 5376 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5377 | |
| 5378 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 5379 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 5380 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 5381 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5382 | I915_WRITE16(DEUC, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 5383 | I915_WRITE(MI_ARB_STATE, |
| 5384 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5385 | |
| 5386 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 5387 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5388 | } |
| 5389 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5390 | static void broadwater_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5391 | { |
| 5392 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5393 | |
| 5394 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 5395 | I965_RCC_CLOCK_GATE_DISABLE | |
| 5396 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 5397 | I965_ISC_CLOCK_GATE_DISABLE | |
| 5398 | I965_FBC_CLOCK_GATE_DISABLE); |
| 5399 | I915_WRITE(RENCLK_GATE_D2, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 5400 | I915_WRITE(MI_ARB_STATE, |
| 5401 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5402 | |
| 5403 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 5404 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5405 | } |
| 5406 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5407 | static void gen3_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5408 | { |
| 5409 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5410 | u32 dstate = I915_READ(D_STATE); |
| 5411 | |
| 5412 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 5413 | DSTATE_DOT_CLOCK_GATING; |
| 5414 | I915_WRITE(D_STATE, dstate); |
Chris Wilson | 13a86b8 | 2012-04-24 14:51:43 +0100 | [diff] [blame] | 5415 | |
| 5416 | if (IS_PINEVIEW(dev)) |
| 5417 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
Daniel Vetter | 974a3b0 | 2012-09-09 11:54:16 +0200 | [diff] [blame] | 5418 | |
| 5419 | /* IIR "flip pending" means done if this bit is set */ |
| 5420 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5421 | } |
| 5422 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5423 | static void i85x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5424 | { |
| 5425 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5426 | |
| 5427 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
| 5428 | } |
| 5429 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5430 | static void i830_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5431 | { |
| 5432 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5433 | |
| 5434 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 5435 | } |
| 5436 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5437 | void intel_init_clock_gating(struct drm_device *dev) |
| 5438 | { |
| 5439 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5440 | |
| 5441 | dev_priv->display.init_clock_gating(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5442 | } |
| 5443 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 5444 | void intel_suspend_hw(struct drm_device *dev) |
| 5445 | { |
| 5446 | if (HAS_PCH_LPT(dev)) |
| 5447 | lpt_suspend_hw(dev); |
| 5448 | } |
| 5449 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5450 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
| 5451 | for (i = 0; \ |
| 5452 | i < (power_domains)->power_well_count && \ |
| 5453 | ((power_well) = &(power_domains)->power_wells[i]); \ |
| 5454 | i++) \ |
| 5455 | if ((power_well)->domains & (domain_mask)) |
| 5456 | |
| 5457 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ |
| 5458 | for (i = (power_domains)->power_well_count - 1; \ |
| 5459 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
| 5460 | i--) \ |
| 5461 | if ((power_well)->domains & (domain_mask)) |
| 5462 | |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5463 | /** |
| 5464 | * We should only use the power well if we explicitly asked the hardware to |
| 5465 | * enable it, so check if it's enabled and also check if we've requested it to |
| 5466 | * be enabled. |
| 5467 | */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5468 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5469 | struct i915_power_well *power_well) |
| 5470 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5471 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
| 5472 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); |
| 5473 | } |
| 5474 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5475 | bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 5476 | enum intel_display_power_domain domain) |
| 5477 | { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 5478 | struct i915_power_domains *power_domains; |
| 5479 | |
| 5480 | power_domains = &dev_priv->power_domains; |
| 5481 | |
| 5482 | return power_domains->domain_use_count[domain]; |
| 5483 | } |
| 5484 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5485 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 5486 | enum intel_display_power_domain domain) |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5487 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5488 | struct i915_power_domains *power_domains; |
| 5489 | struct i915_power_well *power_well; |
| 5490 | bool is_enabled; |
| 5491 | int i; |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5492 | |
Paulo Zanoni | 882244a | 2014-04-01 14:55:12 -0300 | [diff] [blame] | 5493 | if (dev_priv->pm.suspended) |
| 5494 | return false; |
| 5495 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5496 | power_domains = &dev_priv->power_domains; |
| 5497 | |
| 5498 | is_enabled = true; |
| 5499 | |
| 5500 | mutex_lock(&power_domains->lock); |
| 5501 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 5502 | if (power_well->always_on) |
| 5503 | continue; |
| 5504 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5505 | if (!power_well->ops->is_enabled(dev_priv, power_well)) { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5506 | is_enabled = false; |
| 5507 | break; |
| 5508 | } |
| 5509 | } |
| 5510 | mutex_unlock(&power_domains->lock); |
| 5511 | |
| 5512 | return is_enabled; |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 5513 | } |
| 5514 | |
Imre Deak | 93c73e8 | 2014-02-18 00:02:19 +0200 | [diff] [blame] | 5515 | /* |
| 5516 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
| 5517 | * when not needed anymore. We have 4 registers that can request the power well |
| 5518 | * to be enabled, and it will only be disabled if none of the registers is |
| 5519 | * requesting it to be enabled. |
| 5520 | */ |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5521 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 5522 | { |
| 5523 | struct drm_device *dev = dev_priv->dev; |
| 5524 | unsigned long irqflags; |
| 5525 | |
Paulo Zanoni | f9dcb0d | 2013-12-11 18:50:10 -0200 | [diff] [blame] | 5526 | /* |
| 5527 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 5528 | * we'll get unclaimed register interrupts. This stops after we write |
| 5529 | * anything to the VGA MSR register. The vgacon module uses this |
| 5530 | * register all the time, so if we unbind our driver and, as a |
| 5531 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 5532 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 5533 | * sure vgacon can keep working normally without triggering interrupts |
| 5534 | * and error messages. |
| 5535 | */ |
| 5536 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 5537 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 5538 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 5539 | |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5540 | if (IS_BROADWELL(dev)) { |
| 5541 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 5542 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B), |
| 5543 | dev_priv->de_irq_mask[PIPE_B]); |
| 5544 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B), |
| 5545 | ~dev_priv->de_irq_mask[PIPE_B] | |
| 5546 | GEN8_PIPE_VBLANK); |
| 5547 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C), |
| 5548 | dev_priv->de_irq_mask[PIPE_C]); |
| 5549 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C), |
| 5550 | ~dev_priv->de_irq_mask[PIPE_C] | |
| 5551 | GEN8_PIPE_VBLANK); |
| 5552 | POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C)); |
| 5553 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 5554 | } |
| 5555 | } |
| 5556 | |
Imre Deak | dd7c0b6 | 2014-03-04 19:23:03 +0200 | [diff] [blame] | 5557 | static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe) |
| 5558 | { |
| 5559 | assert_spin_locked(&dev->vbl_lock); |
| 5560 | |
| 5561 | dev->vblank[pipe].last = 0; |
| 5562 | } |
| 5563 | |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5564 | static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv) |
| 5565 | { |
| 5566 | struct drm_device *dev = dev_priv->dev; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5567 | enum pipe pipe; |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5568 | unsigned long irqflags; |
| 5569 | |
| 5570 | /* |
| 5571 | * After this, the registers on the pipes that are part of the power |
| 5572 | * well will become zero, so we have to adjust our counters according to |
| 5573 | * that. |
| 5574 | * |
| 5575 | * FIXME: Should we do this in general in drm_vblank_post_modeset? |
| 5576 | */ |
| 5577 | spin_lock_irqsave(&dev->vbl_lock, irqflags); |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5578 | for_each_pipe(pipe) |
| 5579 | if (pipe != PIPE_A) |
Imre Deak | dd7c0b6 | 2014-03-04 19:23:03 +0200 | [diff] [blame] | 5580 | reset_vblank_counter(dev, pipe); |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5581 | spin_unlock_irqrestore(&dev->vbl_lock, irqflags); |
| 5582 | } |
| 5583 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5584 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5585 | struct i915_power_well *power_well, bool enable) |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5586 | { |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5587 | bool is_enabled, enable_requested; |
| 5588 | uint32_t tmp; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5589 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5590 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
Paulo Zanoni | 6aedd1f | 2013-08-02 16:22:25 -0300 | [diff] [blame] | 5591 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
| 5592 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5593 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5594 | if (enable) { |
| 5595 | if (!enable_requested) |
Paulo Zanoni | 6aedd1f | 2013-08-02 16:22:25 -0300 | [diff] [blame] | 5596 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
| 5597 | HSW_PWR_WELL_ENABLE_REQUEST); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5598 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5599 | if (!is_enabled) { |
| 5600 | DRM_DEBUG_KMS("Enabling power well\n"); |
| 5601 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
Paulo Zanoni | 6aedd1f | 2013-08-02 16:22:25 -0300 | [diff] [blame] | 5602 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5603 | DRM_ERROR("Timeout enabling power well\n"); |
| 5604 | } |
Ben Widawsky | 596cc11 | 2013-11-11 14:46:28 -0800 | [diff] [blame] | 5605 | |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5606 | hsw_power_well_post_enable(dev_priv); |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5607 | } else { |
| 5608 | if (enable_requested) { |
| 5609 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
Paulo Zanoni | 9dbd8fe | 2013-07-23 10:48:11 -0300 | [diff] [blame] | 5610 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5611 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
Paulo Zanoni | 9dbd8fe | 2013-07-23 10:48:11 -0300 | [diff] [blame] | 5612 | |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 5613 | hsw_power_well_post_disable(dev_priv); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5614 | } |
| 5615 | } |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 5616 | } |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 5617 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5618 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 5619 | struct i915_power_well *power_well) |
| 5620 | { |
| 5621 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 5622 | |
| 5623 | /* |
| 5624 | * We're taking over the BIOS, so clear any requests made by it since |
| 5625 | * the driver is in charge now. |
| 5626 | */ |
| 5627 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) |
| 5628 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 5629 | } |
| 5630 | |
| 5631 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, |
| 5632 | struct i915_power_well *power_well) |
| 5633 | { |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5634 | hsw_set_power_well(dev_priv, power_well, true); |
| 5635 | } |
| 5636 | |
| 5637 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, |
| 5638 | struct i915_power_well *power_well) |
| 5639 | { |
| 5640 | hsw_set_power_well(dev_priv, power_well, false); |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5641 | } |
| 5642 | |
Imre Deak | a45f4466 | 2014-03-04 19:22:56 +0200 | [diff] [blame] | 5643 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
| 5644 | struct i915_power_well *power_well) |
| 5645 | { |
| 5646 | } |
| 5647 | |
| 5648 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, |
| 5649 | struct i915_power_well *power_well) |
| 5650 | { |
| 5651 | return true; |
| 5652 | } |
| 5653 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 5654 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
| 5655 | struct i915_power_well *power_well, bool enable) |
| 5656 | { |
| 5657 | enum punit_power_well power_well_id = power_well->data; |
| 5658 | u32 mask; |
| 5659 | u32 state; |
| 5660 | u32 ctrl; |
| 5661 | |
| 5662 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 5663 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : |
| 5664 | PUNIT_PWRGT_PWR_GATE(power_well_id); |
| 5665 | |
| 5666 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5667 | |
| 5668 | #define COND \ |
| 5669 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) |
| 5670 | |
| 5671 | if (COND) |
| 5672 | goto out; |
| 5673 | |
| 5674 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); |
| 5675 | ctrl &= ~mask; |
| 5676 | ctrl |= state; |
| 5677 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
| 5678 | |
| 5679 | if (wait_for(COND, 100)) |
| 5680 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
| 5681 | state, |
| 5682 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
| 5683 | |
| 5684 | #undef COND |
| 5685 | |
| 5686 | out: |
| 5687 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5688 | } |
| 5689 | |
| 5690 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 5691 | struct i915_power_well *power_well) |
| 5692 | { |
| 5693 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 5694 | } |
| 5695 | |
| 5696 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, |
| 5697 | struct i915_power_well *power_well) |
| 5698 | { |
| 5699 | vlv_set_power_well(dev_priv, power_well, true); |
| 5700 | } |
| 5701 | |
| 5702 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, |
| 5703 | struct i915_power_well *power_well) |
| 5704 | { |
| 5705 | vlv_set_power_well(dev_priv, power_well, false); |
| 5706 | } |
| 5707 | |
| 5708 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, |
| 5709 | struct i915_power_well *power_well) |
| 5710 | { |
| 5711 | int power_well_id = power_well->data; |
| 5712 | bool enabled = false; |
| 5713 | u32 mask; |
| 5714 | u32 state; |
| 5715 | u32 ctrl; |
| 5716 | |
| 5717 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 5718 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); |
| 5719 | |
| 5720 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5721 | |
| 5722 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; |
| 5723 | /* |
| 5724 | * We only ever set the power-on and power-gate states, anything |
| 5725 | * else is unexpected. |
| 5726 | */ |
| 5727 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && |
| 5728 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); |
| 5729 | if (state == ctrl) |
| 5730 | enabled = true; |
| 5731 | |
| 5732 | /* |
| 5733 | * A transient state at this point would mean some unexpected party |
| 5734 | * is poking at the power controls too. |
| 5735 | */ |
| 5736 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; |
| 5737 | WARN_ON(ctrl != state); |
| 5738 | |
| 5739 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5740 | |
| 5741 | return enabled; |
| 5742 | } |
| 5743 | |
| 5744 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
| 5745 | struct i915_power_well *power_well) |
| 5746 | { |
| 5747 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 5748 | |
| 5749 | vlv_set_power_well(dev_priv, power_well, true); |
| 5750 | |
| 5751 | spin_lock_irq(&dev_priv->irq_lock); |
| 5752 | valleyview_enable_display_irqs(dev_priv); |
| 5753 | spin_unlock_irq(&dev_priv->irq_lock); |
| 5754 | |
| 5755 | /* |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 5756 | * During driver initialization/resume we can avoid restoring the |
| 5757 | * part of the HW/SW state that will be inited anyway explicitly. |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 5758 | */ |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 5759 | if (dev_priv->power_domains.initializing) |
| 5760 | return; |
| 5761 | |
| 5762 | intel_hpd_init(dev_priv->dev); |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 5763 | |
| 5764 | i915_redisable_vga_power_on(dev_priv->dev); |
| 5765 | } |
| 5766 | |
| 5767 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
| 5768 | struct i915_power_well *power_well) |
| 5769 | { |
| 5770 | struct drm_device *dev = dev_priv->dev; |
| 5771 | enum pipe pipe; |
| 5772 | |
| 5773 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 5774 | |
| 5775 | spin_lock_irq(&dev_priv->irq_lock); |
| 5776 | for_each_pipe(pipe) |
| 5777 | __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
| 5778 | |
| 5779 | valleyview_disable_display_irqs(dev_priv); |
| 5780 | spin_unlock_irq(&dev_priv->irq_lock); |
| 5781 | |
| 5782 | spin_lock_irq(&dev->vbl_lock); |
| 5783 | for_each_pipe(pipe) |
| 5784 | reset_vblank_counter(dev, pipe); |
| 5785 | spin_unlock_irq(&dev->vbl_lock); |
| 5786 | |
| 5787 | vlv_set_power_well(dev_priv, power_well, false); |
| 5788 | } |
| 5789 | |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 5790 | static void check_power_well_state(struct drm_i915_private *dev_priv, |
| 5791 | struct i915_power_well *power_well) |
| 5792 | { |
| 5793 | bool enabled = power_well->ops->is_enabled(dev_priv, power_well); |
| 5794 | |
| 5795 | if (power_well->always_on || !i915.disable_power_well) { |
| 5796 | if (!enabled) |
| 5797 | goto mismatch; |
| 5798 | |
| 5799 | return; |
| 5800 | } |
| 5801 | |
| 5802 | if (enabled != (power_well->count > 0)) |
| 5803 | goto mismatch; |
| 5804 | |
| 5805 | return; |
| 5806 | |
| 5807 | mismatch: |
| 5808 | WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", |
| 5809 | power_well->name, power_well->always_on, enabled, |
| 5810 | power_well->count, i915.disable_power_well); |
| 5811 | } |
| 5812 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5813 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 5814 | enum intel_display_power_domain domain) |
| 5815 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5816 | struct i915_power_domains *power_domains; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5817 | struct i915_power_well *power_well; |
| 5818 | int i; |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 5819 | |
Paulo Zanoni | 9e6ea71 | 2014-03-07 20:08:06 -0300 | [diff] [blame] | 5820 | intel_runtime_pm_get(dev_priv); |
| 5821 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5822 | power_domains = &dev_priv->power_domains; |
| 5823 | |
| 5824 | mutex_lock(&power_domains->lock); |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 5825 | |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 5826 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
| 5827 | if (!power_well->count++) { |
| 5828 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5829 | power_well->ops->enable(dev_priv, power_well); |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 5830 | } |
| 5831 | |
| 5832 | check_power_well_state(dev_priv, power_well); |
| 5833 | } |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 5834 | |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 5835 | power_domains->domain_use_count[domain]++; |
| 5836 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5837 | mutex_unlock(&power_domains->lock); |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 5838 | } |
| 5839 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5840 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 5841 | enum intel_display_power_domain domain) |
| 5842 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5843 | struct i915_power_domains *power_domains; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5844 | struct i915_power_well *power_well; |
| 5845 | int i; |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 5846 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5847 | power_domains = &dev_priv->power_domains; |
| 5848 | |
| 5849 | mutex_lock(&power_domains->lock); |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 5850 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 5851 | WARN_ON(!power_domains->domain_use_count[domain]); |
| 5852 | power_domains->domain_use_count[domain]--; |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 5853 | |
Imre Deak | 70bf407 | 2014-03-04 19:22:51 +0200 | [diff] [blame] | 5854 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 5855 | WARN_ON(!power_well->count); |
| 5856 | |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 5857 | if (!--power_well->count && i915.disable_power_well) { |
| 5858 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5859 | power_well->ops->disable(dev_priv, power_well); |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 5860 | } |
| 5861 | |
| 5862 | check_power_well_state(dev_priv, power_well); |
Imre Deak | 70bf407 | 2014-03-04 19:22:51 +0200 | [diff] [blame] | 5863 | } |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 5864 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5865 | mutex_unlock(&power_domains->lock); |
Paulo Zanoni | 9e6ea71 | 2014-03-07 20:08:06 -0300 | [diff] [blame] | 5866 | |
| 5867 | intel_runtime_pm_put(dev_priv); |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 5868 | } |
| 5869 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 5870 | static struct i915_power_domains *hsw_pwr; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5871 | |
| 5872 | /* Display audio driver power well request */ |
| 5873 | void i915_request_power_well(void) |
| 5874 | { |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 5875 | struct drm_i915_private *dev_priv; |
| 5876 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5877 | if (WARN_ON(!hsw_pwr)) |
| 5878 | return; |
| 5879 | |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 5880 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
| 5881 | power_domains); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5882 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5883 | } |
| 5884 | EXPORT_SYMBOL_GPL(i915_request_power_well); |
| 5885 | |
| 5886 | /* Display audio driver power well release */ |
| 5887 | void i915_release_power_well(void) |
| 5888 | { |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 5889 | struct drm_i915_private *dev_priv; |
| 5890 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5891 | if (WARN_ON(!hsw_pwr)) |
| 5892 | return; |
| 5893 | |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 5894 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
| 5895 | power_domains); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 5896 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 5897 | } |
| 5898 | EXPORT_SYMBOL_GPL(i915_release_power_well); |
| 5899 | |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 5900 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 5901 | |
| 5902 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 5903 | BIT(POWER_DOMAIN_PIPE_A) | \ |
Imre Deak | f5938f3 | 2014-03-04 19:22:54 +0200 | [diff] [blame] | 5904 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 5905 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 5906 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 5907 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 5908 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 5909 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 5910 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 5911 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 5912 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 5913 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
Imre Deak | f5938f3 | 2014-03-04 19:22:54 +0200 | [diff] [blame] | 5914 | BIT(POWER_DOMAIN_INIT)) |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 5915 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
| 5916 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 5917 | BIT(POWER_DOMAIN_INIT)) |
| 5918 | |
| 5919 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 5920 | HSW_ALWAYS_ON_POWER_DOMAINS | \ |
| 5921 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
| 5922 | #define BDW_DISPLAY_POWER_DOMAINS ( \ |
| 5923 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 5924 | BIT(POWER_DOMAIN_INIT)) |
| 5925 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 5926 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
| 5927 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK |
| 5928 | |
| 5929 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 5930 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 5931 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 5932 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 5933 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 5934 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
| 5935 | BIT(POWER_DOMAIN_INIT)) |
| 5936 | |
| 5937 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
| 5938 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 5939 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 5940 | BIT(POWER_DOMAIN_INIT)) |
| 5941 | |
| 5942 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
| 5943 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 5944 | BIT(POWER_DOMAIN_INIT)) |
| 5945 | |
| 5946 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
| 5947 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 5948 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 5949 | BIT(POWER_DOMAIN_INIT)) |
| 5950 | |
| 5951 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
| 5952 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 5953 | BIT(POWER_DOMAIN_INIT)) |
| 5954 | |
Imre Deak | a45f4466 | 2014-03-04 19:22:56 +0200 | [diff] [blame] | 5955 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
| 5956 | .sync_hw = i9xx_always_on_power_well_noop, |
| 5957 | .enable = i9xx_always_on_power_well_noop, |
| 5958 | .disable = i9xx_always_on_power_well_noop, |
| 5959 | .is_enabled = i9xx_always_on_power_well_enabled, |
| 5960 | }; |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5961 | |
Imre Deak | 1c2256d | 2013-11-25 17:15:34 +0200 | [diff] [blame] | 5962 | static struct i915_power_well i9xx_always_on_power_well[] = { |
| 5963 | { |
| 5964 | .name = "always-on", |
| 5965 | .always_on = 1, |
| 5966 | .domains = POWER_DOMAIN_MASK, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5967 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 1c2256d | 2013-11-25 17:15:34 +0200 | [diff] [blame] | 5968 | }, |
| 5969 | }; |
| 5970 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5971 | static const struct i915_power_well_ops hsw_power_well_ops = { |
| 5972 | .sync_hw = hsw_power_well_sync_hw, |
| 5973 | .enable = hsw_power_well_enable, |
| 5974 | .disable = hsw_power_well_disable, |
| 5975 | .is_enabled = hsw_power_well_enabled, |
| 5976 | }; |
| 5977 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5978 | static struct i915_power_well hsw_power_wells[] = { |
| 5979 | { |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 5980 | .name = "always-on", |
| 5981 | .always_on = 1, |
| 5982 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5983 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 5984 | }, |
| 5985 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5986 | .name = "display", |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 5987 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5988 | .ops = &hsw_power_well_ops, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 5989 | }, |
| 5990 | }; |
| 5991 | |
| 5992 | static struct i915_power_well bdw_power_wells[] = { |
| 5993 | { |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 5994 | .name = "always-on", |
| 5995 | .always_on = 1, |
| 5996 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 5997 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 5998 | }, |
| 5999 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6000 | .name = "display", |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 6001 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6002 | .ops = &hsw_power_well_ops, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6003 | }, |
| 6004 | }; |
| 6005 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6006 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
| 6007 | .sync_hw = vlv_power_well_sync_hw, |
| 6008 | .enable = vlv_display_power_well_enable, |
| 6009 | .disable = vlv_display_power_well_disable, |
| 6010 | .is_enabled = vlv_power_well_enabled, |
| 6011 | }; |
| 6012 | |
| 6013 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
| 6014 | .sync_hw = vlv_power_well_sync_hw, |
| 6015 | .enable = vlv_power_well_enable, |
| 6016 | .disable = vlv_power_well_disable, |
| 6017 | .is_enabled = vlv_power_well_enabled, |
| 6018 | }; |
| 6019 | |
| 6020 | static struct i915_power_well vlv_power_wells[] = { |
| 6021 | { |
| 6022 | .name = "always-on", |
| 6023 | .always_on = 1, |
| 6024 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 6025 | .ops = &i9xx_always_on_power_well_ops, |
| 6026 | }, |
| 6027 | { |
| 6028 | .name = "display", |
| 6029 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 6030 | .data = PUNIT_POWER_WELL_DISP2D, |
| 6031 | .ops = &vlv_display_power_well_ops, |
| 6032 | }, |
| 6033 | { |
| 6034 | .name = "dpio-common", |
| 6035 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, |
| 6036 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 6037 | .ops = &vlv_dpio_power_well_ops, |
| 6038 | }, |
| 6039 | { |
| 6040 | .name = "dpio-tx-b-01", |
| 6041 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6042 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6043 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6044 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6045 | .ops = &vlv_dpio_power_well_ops, |
| 6046 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 6047 | }, |
| 6048 | { |
| 6049 | .name = "dpio-tx-b-23", |
| 6050 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6051 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6052 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6053 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6054 | .ops = &vlv_dpio_power_well_ops, |
| 6055 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 6056 | }, |
| 6057 | { |
| 6058 | .name = "dpio-tx-c-01", |
| 6059 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6060 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6061 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6062 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6063 | .ops = &vlv_dpio_power_well_ops, |
| 6064 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 6065 | }, |
| 6066 | { |
| 6067 | .name = "dpio-tx-c-23", |
| 6068 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6069 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6070 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6071 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6072 | .ops = &vlv_dpio_power_well_ops, |
| 6073 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 6074 | }, |
| 6075 | }; |
| 6076 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6077 | #define set_power_wells(power_domains, __power_wells) ({ \ |
| 6078 | (power_domains)->power_wells = (__power_wells); \ |
| 6079 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ |
| 6080 | }) |
| 6081 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6082 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6083 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6084 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6085 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6086 | mutex_init(&power_domains->lock); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6087 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6088 | /* |
| 6089 | * The enabling order will be from lower to higher indexed wells, |
| 6090 | * the disabling order is reversed. |
| 6091 | */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6092 | if (IS_HASWELL(dev_priv->dev)) { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6093 | set_power_wells(power_domains, hsw_power_wells); |
| 6094 | hsw_pwr = power_domains; |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6095 | } else if (IS_BROADWELL(dev_priv->dev)) { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6096 | set_power_wells(power_domains, bdw_power_wells); |
| 6097 | hsw_pwr = power_domains; |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6098 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 6099 | set_power_wells(power_domains, vlv_power_wells); |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6100 | } else { |
Imre Deak | 1c2256d | 2013-11-25 17:15:34 +0200 | [diff] [blame] | 6101 | set_power_wells(power_domains, i9xx_always_on_power_well); |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6102 | } |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6103 | |
| 6104 | return 0; |
| 6105 | } |
| 6106 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6107 | void intel_power_domains_remove(struct drm_i915_private *dev_priv) |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6108 | { |
| 6109 | hsw_pwr = NULL; |
| 6110 | } |
| 6111 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6112 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 9cdb826 | 2013-09-16 17:38:27 +0300 | [diff] [blame] | 6113 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6114 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 6115 | struct i915_power_well *power_well; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6116 | int i; |
Ville Syrjälä | 9cdb826 | 2013-09-16 17:38:27 +0300 | [diff] [blame] | 6117 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6118 | mutex_lock(&power_domains->lock); |
Imre Deak | a45f4466 | 2014-03-04 19:22:56 +0200 | [diff] [blame] | 6119 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) |
| 6120 | power_well->ops->sync_hw(dev_priv, power_well); |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6121 | mutex_unlock(&power_domains->lock); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6122 | } |
| 6123 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6124 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6125 | { |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 6126 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 6127 | |
| 6128 | power_domains->initializing = true; |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6129 | /* For now, we need the power well to be always enabled. */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6130 | intel_display_set_init_power(dev_priv, true); |
| 6131 | intel_power_domains_resume(dev_priv); |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 6132 | power_domains->initializing = false; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6133 | } |
| 6134 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 6135 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
| 6136 | { |
Paulo Zanoni | d361ae2 | 2014-03-07 20:08:12 -0300 | [diff] [blame] | 6137 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 6138 | } |
| 6139 | |
| 6140 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
| 6141 | { |
Paulo Zanoni | d361ae2 | 2014-03-07 20:08:12 -0300 | [diff] [blame] | 6142 | intel_runtime_pm_put(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 6143 | } |
| 6144 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 6145 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
| 6146 | { |
| 6147 | struct drm_device *dev = dev_priv->dev; |
| 6148 | struct device *device = &dev->pdev->dev; |
| 6149 | |
| 6150 | if (!HAS_RUNTIME_PM(dev)) |
| 6151 | return; |
| 6152 | |
| 6153 | pm_runtime_get_sync(device); |
| 6154 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); |
| 6155 | } |
| 6156 | |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 6157 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
| 6158 | { |
| 6159 | struct drm_device *dev = dev_priv->dev; |
| 6160 | struct device *device = &dev->pdev->dev; |
| 6161 | |
| 6162 | if (!HAS_RUNTIME_PM(dev)) |
| 6163 | return; |
| 6164 | |
| 6165 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); |
| 6166 | pm_runtime_get_noresume(device); |
| 6167 | } |
| 6168 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 6169 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
| 6170 | { |
| 6171 | struct drm_device *dev = dev_priv->dev; |
| 6172 | struct device *device = &dev->pdev->dev; |
| 6173 | |
| 6174 | if (!HAS_RUNTIME_PM(dev)) |
| 6175 | return; |
| 6176 | |
| 6177 | pm_runtime_mark_last_busy(device); |
| 6178 | pm_runtime_put_autosuspend(device); |
| 6179 | } |
| 6180 | |
| 6181 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv) |
| 6182 | { |
| 6183 | struct drm_device *dev = dev_priv->dev; |
| 6184 | struct device *device = &dev->pdev->dev; |
| 6185 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 6186 | if (!HAS_RUNTIME_PM(dev)) |
| 6187 | return; |
| 6188 | |
| 6189 | pm_runtime_set_active(device); |
| 6190 | |
Imre Deak | aeab0b5 | 2014-04-14 20:24:36 +0300 | [diff] [blame] | 6191 | /* |
| 6192 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
| 6193 | * requirement. |
| 6194 | */ |
| 6195 | if (!intel_enable_rc6(dev)) { |
| 6196 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
| 6197 | return; |
| 6198 | } |
| 6199 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 6200 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
| 6201 | pm_runtime_mark_last_busy(device); |
| 6202 | pm_runtime_use_autosuspend(device); |
Paulo Zanoni | ba0239e | 2014-03-07 20:08:07 -0300 | [diff] [blame] | 6203 | |
| 6204 | pm_runtime_put_autosuspend(device); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 6205 | } |
| 6206 | |
| 6207 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) |
| 6208 | { |
| 6209 | struct drm_device *dev = dev_priv->dev; |
| 6210 | struct device *device = &dev->pdev->dev; |
| 6211 | |
| 6212 | if (!HAS_RUNTIME_PM(dev)) |
| 6213 | return; |
| 6214 | |
Imre Deak | aeab0b5 | 2014-04-14 20:24:36 +0300 | [diff] [blame] | 6215 | if (!intel_enable_rc6(dev)) |
| 6216 | return; |
| 6217 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 6218 | /* Make sure we're not suspended first. */ |
| 6219 | pm_runtime_get_sync(device); |
| 6220 | pm_runtime_disable(device); |
| 6221 | } |
| 6222 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6223 | /* Set up chip specific power management-related functions */ |
| 6224 | void intel_init_pm(struct drm_device *dev) |
| 6225 | { |
| 6226 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6227 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 6228 | if (HAS_FBC(dev)) { |
Ville Syrjälä | 4004546 | 2013-11-28 17:29:59 +0200 | [diff] [blame] | 6229 | if (INTEL_INFO(dev)->gen >= 7) { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6230 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
Ville Syrjälä | 4004546 | 2013-11-28 17:29:59 +0200 | [diff] [blame] | 6231 | dev_priv->display.enable_fbc = gen7_enable_fbc; |
| 6232 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 6233 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 6234 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
| 6235 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6236 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 6237 | } else if (IS_GM45(dev)) { |
| 6238 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 6239 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 6240 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
Ville Syrjälä | 4004546 | 2013-11-28 17:29:59 +0200 | [diff] [blame] | 6241 | } else { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6242 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 6243 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 6244 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 6245 | |
| 6246 | /* This value was pulled out of someone's hat */ |
| 6247 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6248 | } |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6249 | } |
| 6250 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 6251 | /* For cxsr */ |
| 6252 | if (IS_PINEVIEW(dev)) |
| 6253 | i915_pineview_get_mem_freq(dev); |
| 6254 | else if (IS_GEN5(dev)) |
| 6255 | i915_ironlake_get_mem_freq(dev); |
| 6256 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6257 | /* For FIFO watermark updates */ |
| 6258 | if (HAS_PCH_SPLIT(dev)) { |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 6259 | ilk_setup_wm_latency(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 6260 | |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6261 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
| 6262 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
| 6263 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
| 6264 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
| 6265 | dev_priv->display.update_wm = ilk_update_wm; |
| 6266 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; |
| 6267 | } else { |
| 6268 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 6269 | "Disable CxSR\n"); |
| 6270 | } |
| 6271 | |
| 6272 | if (IS_GEN5(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6273 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6274 | else if (IS_GEN6(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6275 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6276 | else if (IS_IVYBRIDGE(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6277 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6278 | else if (IS_HASWELL(dev)) |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 6279 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 6280 | else if (INTEL_INFO(dev)->gen == 8) |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 6281 | dev_priv->display.init_clock_gating = gen8_init_clock_gating; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame^] | 6282 | } else if (IS_CHERRYVIEW(dev)) { |
| 6283 | dev_priv->display.update_wm = valleyview_update_wm; |
| 6284 | dev_priv->display.init_clock_gating = |
| 6285 | cherryview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6286 | } else if (IS_VALLEYVIEW(dev)) { |
| 6287 | dev_priv->display.update_wm = valleyview_update_wm; |
| 6288 | dev_priv->display.init_clock_gating = |
| 6289 | valleyview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6290 | } else if (IS_PINEVIEW(dev)) { |
| 6291 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
| 6292 | dev_priv->is_ddr3, |
| 6293 | dev_priv->fsb_freq, |
| 6294 | dev_priv->mem_freq)) { |
| 6295 | DRM_INFO("failed to find known CxSR latency " |
| 6296 | "(found ddr%s fsb freq %d, mem freq %d), " |
| 6297 | "disabling CxSR\n", |
| 6298 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
| 6299 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 6300 | /* Disable CxSR and never update its watermark again */ |
| 6301 | pineview_disable_cxsr(dev); |
| 6302 | dev_priv->display.update_wm = NULL; |
| 6303 | } else |
| 6304 | dev_priv->display.update_wm = pineview_update_wm; |
| 6305 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 6306 | } else if (IS_G4X(dev)) { |
| 6307 | dev_priv->display.update_wm = g4x_update_wm; |
| 6308 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 6309 | } else if (IS_GEN4(dev)) { |
| 6310 | dev_priv->display.update_wm = i965_update_wm; |
| 6311 | if (IS_CRESTLINE(dev)) |
| 6312 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 6313 | else if (IS_BROADWATER(dev)) |
| 6314 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 6315 | } else if (IS_GEN3(dev)) { |
| 6316 | dev_priv->display.update_wm = i9xx_update_wm; |
| 6317 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 6318 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 6319 | } else if (IS_GEN2(dev)) { |
| 6320 | if (INTEL_INFO(dev)->num_pipes == 1) { |
| 6321 | dev_priv->display.update_wm = i845_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6322 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 6323 | } else { |
| 6324 | dev_priv->display.update_wm = i9xx_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6325 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 6326 | } |
| 6327 | |
| 6328 | if (IS_I85X(dev) || IS_I865G(dev)) |
| 6329 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 6330 | else |
| 6331 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
| 6332 | } else { |
| 6333 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6334 | } |
| 6335 | } |
| 6336 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6337 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
| 6338 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6339 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6340 | |
| 6341 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 6342 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
| 6343 | return -EAGAIN; |
| 6344 | } |
| 6345 | |
| 6346 | I915_WRITE(GEN6_PCODE_DATA, *val); |
| 6347 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 6348 | |
| 6349 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 6350 | 500)) { |
| 6351 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
| 6352 | return -ETIMEDOUT; |
| 6353 | } |
| 6354 | |
| 6355 | *val = I915_READ(GEN6_PCODE_DATA); |
| 6356 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 6357 | |
| 6358 | return 0; |
| 6359 | } |
| 6360 | |
| 6361 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) |
| 6362 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 6363 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 6364 | |
| 6365 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 6366 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
| 6367 | return -EAGAIN; |
| 6368 | } |
| 6369 | |
| 6370 | I915_WRITE(GEN6_PCODE_DATA, val); |
| 6371 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 6372 | |
| 6373 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 6374 | 500)) { |
| 6375 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
| 6376 | return -ETIMEDOUT; |
| 6377 | } |
| 6378 | |
| 6379 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 6380 | |
| 6381 | return 0; |
| 6382 | } |
Jesse Barnes | a0e4e19 | 2013-04-02 11:23:05 -0700 | [diff] [blame] | 6383 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 6384 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6385 | { |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6386 | int div; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6387 | |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6388 | /* 4 x czclk */ |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 6389 | switch (dev_priv->mem_freq) { |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6390 | case 800: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6391 | div = 10; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6392 | break; |
| 6393 | case 1066: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6394 | div = 12; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6395 | break; |
| 6396 | case 1333: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6397 | div = 16; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6398 | break; |
| 6399 | default: |
| 6400 | return -1; |
| 6401 | } |
| 6402 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 6403 | return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6404 | } |
| 6405 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 6406 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6407 | { |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6408 | int mul; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6409 | |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6410 | /* 4 x czclk */ |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 6411 | switch (dev_priv->mem_freq) { |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6412 | case 800: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6413 | mul = 10; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6414 | break; |
| 6415 | case 1066: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6416 | mul = 12; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6417 | break; |
| 6418 | case 1333: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 6419 | mul = 16; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6420 | break; |
| 6421 | default: |
| 6422 | return -1; |
| 6423 | } |
| 6424 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 6425 | return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 6426 | } |
| 6427 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 6428 | void intel_pm_setup(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 6429 | { |
| 6430 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6431 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 6432 | mutex_init(&dev_priv->rps.hw_lock); |
| 6433 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 6434 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
| 6435 | intel_gen6_powersave_work); |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 6436 | |
Paulo Zanoni | 33688d9 | 2014-03-07 20:08:19 -0300 | [diff] [blame] | 6437 | dev_priv->pm.suspended = false; |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 6438 | dev_priv->pm.irqs_disabled = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 6439 | } |