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gerrit-public.fairphone.software / kernel / msm-4.9 / a4643ba340a3bc5aadd0037085dd3621c53639ba / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 438839fb5f549ebc6b1cf42091492bcc803ad093 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]49
Alex Deucherf93bdef2013-01-29 14:10:56 -0500[diff] [blame]50u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
51 struct radeon_ring *ring);
52u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
53 struct radeon_ring *ring);
54void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
55 struct radeon_ring *ring);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]56
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]57/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]58 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]59 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]60struct r100_mc_save {
61 u32 GENMO_WT;
62 u32 CRTC_EXT_CNTL;
63 u32 CRTC_GEN_CNTL;
64 u32 CRTC2_GEN_CNTL;
65 u32 CUR_OFFSET;
66 u32 CUR2_OFFSET;
67};
68int r100_init(struct radeon_device *rdev);
69void r100_fini(struct radeon_device *rdev);
70int r100_suspend(struct radeon_device *rdev);
71int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]72void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]73bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]74int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]75u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]76void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
77int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]78void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]79int r100_irq_set(struct radeon_device *rdev);
80int r100_irq_process(struct radeon_device *rdev);
81void r100_fence_ring_emit(struct radeon_device *rdev,
82 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]83bool r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]84 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]85 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]86 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]87int r100_cs_parse(struct radeon_cs_parser *p);
88void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
89uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
90int r100_copy_blit(struct radeon_device *rdev,
91 uint64_t src_offset,
92 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]93 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]94 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]95int r100_set_surface_reg(struct radeon_device *rdev, int reg,
96 uint32_t tiling_flags, uint32_t pitch,
97 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]98void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]99void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]100void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]101int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]102void r100_hpd_init(struct radeon_device *rdev);
103void r100_hpd_fini(struct radeon_device *rdev);
104bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
105void r100_hpd_set_polarity(struct radeon_device *rdev,
106 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]107int r100_debugfs_rbbm_init(struct radeon_device *rdev);
108int r100_debugfs_cp_init(struct radeon_device *rdev);
109void r100_cp_disable(struct radeon_device *rdev);
110int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
111void r100_cp_fini(struct radeon_device *rdev);
112int r100_pci_gart_init(struct radeon_device *rdev);
113void r100_pci_gart_fini(struct radeon_device *rdev);
114int r100_pci_gart_enable(struct radeon_device *rdev);
115void r100_pci_gart_disable(struct radeon_device *rdev);
116int r100_debugfs_mc_info_init(struct radeon_device *rdev);
117int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]118int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]119void r100_irq_disable(struct radeon_device *rdev);
120void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
121void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
122void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]123int r100_cp_reset(struct radeon_device *rdev);
124void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]125void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]126int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
128 struct radeon_bo *robj);
129int r100_cs_parse_packet0(struct radeon_cs_parser *p,
130 struct radeon_cs_packet *pkt,
131 const unsigned *auth, unsigned n,
132 radeon_packet0_check_t check);
133int r100_cs_packet_parse(struct radeon_cs_parser *p,
134 struct radeon_cs_packet *pkt,
135 unsigned idx);
136void r100_enable_bm(struct radeon_device *rdev);
137void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]138void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]139extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]140extern void r100_pm_misc(struct radeon_device *rdev);
141extern void r100_pm_prepare(struct radeon_device *rdev);
142extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]143extern void r100_pm_init_profile(struct radeon_device *rdev);
144extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]145extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
146extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
147extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]148extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]149extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]150
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]151/*
152 * r200,rv250,rs300,rv280
153 */
154extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]155 uint64_t src_offset,
156 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]157 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]158 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]159void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]160
161/*
162 * r300,r350,rv350,rv380
163 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]164extern int r300_init(struct radeon_device *rdev);
165extern void r300_fini(struct radeon_device *rdev);
166extern int r300_suspend(struct radeon_device *rdev);
167extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]168extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]169extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]170extern void r300_fence_ring_emit(struct radeon_device *rdev,
171 struct radeon_fence *fence);
172extern int r300_cs_parse(struct radeon_cs_parser *p);
173extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
174extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]175extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]176extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]177extern void r300_set_reg_safe(struct radeon_device *rdev);
178extern void r300_mc_program(struct radeon_device *rdev);
179extern void r300_mc_init(struct radeon_device *rdev);
180extern void r300_clock_startup(struct radeon_device *rdev);
181extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
182extern int rv370_pcie_gart_init(struct radeon_device *rdev);
183extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
184extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
185extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]186extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]187
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]188/*
189 * r420,r423,rv410
190 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]191extern int r420_init(struct radeon_device *rdev);
192extern void r420_fini(struct radeon_device *rdev);
193extern int r420_suspend(struct radeon_device *rdev);
194extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]195extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]196extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
197extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
198extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
199extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]200
201/*
202 * rs400,rs480
203 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]204extern int rs400_init(struct radeon_device *rdev);
205extern void rs400_fini(struct radeon_device *rdev);
206extern int rs400_suspend(struct radeon_device *rdev);
207extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]208void rs400_gart_tlb_flush(struct radeon_device *rdev);
209int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
210uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
211void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]212int rs400_gart_init(struct radeon_device *rdev);
213int rs400_gart_enable(struct radeon_device *rdev);
214void rs400_gart_adjust_size(struct radeon_device *rdev);
215void rs400_gart_disable(struct radeon_device *rdev);
216void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]217extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]218
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]219/*
220 * rs600.
221 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]222extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]223extern int rs600_init(struct radeon_device *rdev);
224extern void rs600_fini(struct radeon_device *rdev);
225extern int rs600_suspend(struct radeon_device *rdev);
226extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]227int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]228int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]229void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]230u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]231void rs600_gart_tlb_flush(struct radeon_device *rdev);
232int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
233uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
234void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]235void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]236void rs600_hpd_init(struct radeon_device *rdev);
237void rs600_hpd_fini(struct radeon_device *rdev);
238bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
239void rs600_hpd_set_polarity(struct radeon_device *rdev,
240 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]241extern void rs600_pm_misc(struct radeon_device *rdev);
242extern void rs600_pm_prepare(struct radeon_device *rdev);
243extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]244extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
245extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
246extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]247void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]248extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]249extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]250
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]251/*
252 * rs690,rs740
253 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]254int rs690_init(struct radeon_device *rdev);
255void rs690_fini(struct radeon_device *rdev);
256int rs690_resume(struct radeon_device *rdev);
257int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]258uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
259void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]260void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]261void rs690_line_buffer_adjust(struct radeon_device *rdev,
262 struct drm_display_mode *mode1,
263 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]264extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]265
266/*
267 * rv515
268 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]269struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]270 u32 vga_render_control;
271 u32 vga_hdp_control;
Alex Deucher6253e4c2012-12-12 14:30:32 -0500[diff] [blame]272 bool crtc_enabled[2];
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]273};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]274
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]275int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]276void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]277uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
278void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]279void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]280void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]281int rv515_resume(struct radeon_device *rdev);
282int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]283void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
284void rv515_vga_render_disable(struct radeon_device *rdev);
285void rv515_set_safe_registers(struct radeon_device *rdev);
286void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
287void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
288void rv515_clock_startup(struct radeon_device *rdev);
289void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]290int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]291
292/*
293 * r520,rv530,rv560,rv570,r580
294 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]295int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]296int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]297int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]298
299/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]300 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]301 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]302int r600_init(struct radeon_device *rdev);
303void r600_fini(struct radeon_device *rdev);
304int r600_suspend(struct radeon_device *rdev);
305int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]306void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]307int r600_wb_init(struct radeon_device *rdev);
308void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]309void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]310uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
311void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]312int r600_cs_parse(struct radeon_cs_parser *p);
Alex Deuchercf4ccd02011-11-18 10:19:47 -0500[diff] [blame]313int r600_dma_cs_parse(struct radeon_cs_parser *p);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]314void r600_fence_ring_emit(struct radeon_device *rdev,
315 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]316bool r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]317 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]318 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]319 bool emit_wait);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]320void r600_dma_fence_ring_emit(struct radeon_device *rdev,
321 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]322bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]323 struct radeon_ring *ring,
324 struct radeon_semaphore *semaphore,
325 bool emit_wait);
326void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
327bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]328bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]329int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]330int r600_set_surface_reg(struct radeon_device *rdev, int reg,
331 uint32_t tiling_flags, uint32_t pitch,
332 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]333void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]334int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]335int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]336void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]337int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]338int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher072b5ac2013-07-11 14:48:05 -0400[diff] [blame]339int r600_copy_cpdma(struct radeon_device *rdev,
340 uint64_t src_offset, uint64_t dst_offset,
341 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]342int r600_copy_dma(struct radeon_device *rdev,
343 uint64_t src_offset, uint64_t dst_offset,
344 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]345void r600_hpd_init(struct radeon_device *rdev);
346void r600_hpd_fini(struct radeon_device *rdev);
347bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
348void r600_hpd_set_polarity(struct radeon_device *rdev,
349 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]350extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]351extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]352extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]353extern void r600_pm_init_profile(struct radeon_device *rdev);
354extern void rs780_pm_init_profile(struct radeon_device *rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]355extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
356extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]357extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]358extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
359extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]360bool r600_card_posted(struct radeon_device *rdev);
361void r600_cp_stop(struct radeon_device *rdev);
362int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]363void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]364int r600_cp_resume(struct radeon_device *rdev);
365void r600_cp_fini(struct radeon_device *rdev);
366int r600_count_pipe_bits(uint32_t val);
367int r600_mc_wait_for_idle(struct radeon_device *rdev);
368int r600_pcie_gart_init(struct radeon_device *rdev);
369void r600_scratch_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]370int r600_init_microcode(struct radeon_device *rdev);
371/* r600 irq */
372int r600_irq_process(struct radeon_device *rdev);
373int r600_irq_init(struct radeon_device *rdev);
374void r600_irq_fini(struct radeon_device *rdev);
375void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
376int r600_irq_set(struct radeon_device *rdev);
377void r600_irq_suspend(struct radeon_device *rdev);
378void r600_disable_interrupts(struct radeon_device *rdev);
379void r600_rlc_stop(struct radeon_device *rdev);
380/* r600 audio */
381int r600_audio_init(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]382struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]383void r600_audio_fini(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]384int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
385void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]386void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
387void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]388int r600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]389u32 r600_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]390uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]391int rv6xx_get_temp(struct radeon_device *rdev);
Alex Deucher1b9ba702013-09-05 09:52:37 -0400[diff] [blame]392int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher98243912013-01-16 13:13:42 -0500[diff] [blame]393int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
394void r600_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deuchera4643ba2013-12-19 12:18:13 -0500[diff] [blame^]395int r600_dpm_late_enable(struct radeon_device *rdev);
Christian König2e1e6da2013-08-13 11:56:52 +0200[diff] [blame]396/* r600 dma */
397uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
398 struct radeon_ring *ring);
399uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
400 struct radeon_ring *ring);
401void r600_dma_set_wptr(struct radeon_device *rdev,
402 struct radeon_ring *ring);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400[diff] [blame]403/* rv6xx dpm */
404int rv6xx_dpm_init(struct radeon_device *rdev);
405int rv6xx_dpm_enable(struct radeon_device *rdev);
406void rv6xx_dpm_disable(struct radeon_device *rdev);
407int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
408void rv6xx_setup_asic(struct radeon_device *rdev);
409void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
410void rv6xx_dpm_fini(struct radeon_device *rdev);
411u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
412u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
413void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
414 struct radeon_ps *ps);
Alex Deucher242916a2013-06-28 14:20:53 -0400[diff] [blame]415void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
416 struct seq_file *m);
Alex Deucherf4f85a82013-07-25 20:07:25 -0400[diff] [blame]417int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
418 enum radeon_dpm_forced_level level);
Alex Deucher9d670062013-04-12 13:59:22 -0400[diff] [blame]419/* rs780 dpm */
420int rs780_dpm_init(struct radeon_device *rdev);
421int rs780_dpm_enable(struct radeon_device *rdev);
422void rs780_dpm_disable(struct radeon_device *rdev);
423int rs780_dpm_set_power_state(struct radeon_device *rdev);
424void rs780_dpm_setup_asic(struct radeon_device *rdev);
425void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
426void rs780_dpm_fini(struct radeon_device *rdev);
427u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
428u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
429void rs780_dpm_print_power_state(struct radeon_device *rdev,
430 struct radeon_ps *ps);
Alex Deucher444bddc2013-07-02 13:05:23 -0400[diff] [blame]431void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
432 struct seq_file *m);
Anthoine Bourgeois63580c32013-09-03 13:52:19 -0400[diff] [blame]433int rs780_dpm_force_performance_level(struct radeon_device *rdev,
434 enum radeon_dpm_forced_level level);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]435
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]436/*
437 * rv770,rv730,rv710,rv740
438 */
439int rv770_init(struct radeon_device *rdev);
440void rv770_fini(struct radeon_device *rdev);
441int rv770_suspend(struct radeon_device *rdev);
442int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]443void rv770_pm_misc(struct radeon_device *rdev);
444u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
445void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
446void r700_cp_stop(struct radeon_device *rdev);
447void r700_cp_fini(struct radeon_device *rdev);
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]448int rv770_copy_dma(struct radeon_device *rdev,
449 uint64_t src_offset, uint64_t dst_offset,
450 unsigned num_gpu_pages,
451 struct radeon_fence **fence);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]452u32 rv770_get_xclk(struct radeon_device *rdev);
Christian Königef0e6e62013-04-08 12:41:35 +0200[diff] [blame]453int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]454int rv770_get_temp(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]455/* rv7xx pm */
456int rv770_dpm_init(struct radeon_device *rdev);
457int rv770_dpm_enable(struct radeon_device *rdev);
458void rv770_dpm_disable(struct radeon_device *rdev);
459int rv770_dpm_set_power_state(struct radeon_device *rdev);
460void rv770_dpm_setup_asic(struct radeon_device *rdev);
461void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
462void rv770_dpm_fini(struct radeon_device *rdev);
463u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
464u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
465void rv770_dpm_print_power_state(struct radeon_device *rdev,
466 struct radeon_ps *ps);
Alex Deucherbd210d12013-06-28 10:06:26 -0400[diff] [blame]467void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
468 struct seq_file *m);
Alex Deucher8b5e6b72013-07-02 18:40:35 -0400[diff] [blame]469int rv770_dpm_force_performance_level(struct radeon_device *rdev,
470 enum radeon_dpm_forced_level level);
Alex Deucherb06195d2013-07-08 11:49:48 -0400[diff] [blame]471bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]472
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]473/*
474 * evergreen
475 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]476struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]477 u32 vga_render_control;
478 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400[diff] [blame]479 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]480};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]481
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]482void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]483int evergreen_init(struct radeon_device *rdev);
484void evergreen_fini(struct radeon_device *rdev);
485int evergreen_suspend(struct radeon_device *rdev);
486int evergreen_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]487bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
488bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]489int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]490void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]491void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]492void evergreen_hpd_init(struct radeon_device *rdev);
493void evergreen_hpd_fini(struct radeon_device *rdev);
494bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
495void evergreen_hpd_set_polarity(struct radeon_device *rdev,
496 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]497u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
498int evergreen_irq_set(struct radeon_device *rdev);
499int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]500extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucherd2ead3e2012-12-13 09:55:45 -0500[diff] [blame]501extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]502extern void evergreen_pm_misc(struct radeon_device *rdev);
503extern void evergreen_pm_prepare(struct radeon_device *rdev);
504extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]505extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400[diff] [blame]506extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher23d33ba2013-04-08 12:41:32 +0200[diff] [blame]507int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deuchera8b49252013-04-08 12:41:33 +0200[diff] [blame]508int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]509extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
510extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
511extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]512extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]513void evergreen_disable_interrupt_state(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]514int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher233d1ad2012-12-04 15:25:59 -0500[diff] [blame]515void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
516 struct radeon_fence *fence);
517void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
518 struct radeon_ib *ib);
519int evergreen_copy_dma(struct radeon_device *rdev,
520 uint64_t src_offset, uint64_t dst_offset,
521 unsigned num_gpu_pages,
522 struct radeon_fence **fence);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]523void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
524void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]525int evergreen_get_temp(struct radeon_device *rdev);
526int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher29a15222012-12-14 11:57:36 -0500[diff] [blame]527int tn_get_temp(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -0400[diff] [blame]528int cypress_dpm_init(struct radeon_device *rdev);
529void cypress_dpm_setup_asic(struct radeon_device *rdev);
530int cypress_dpm_enable(struct radeon_device *rdev);
531void cypress_dpm_disable(struct radeon_device *rdev);
532int cypress_dpm_set_power_state(struct radeon_device *rdev);
533void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
534void cypress_dpm_fini(struct radeon_device *rdev);
Alex Deucherd0b54bd2013-07-08 11:56:09 -0400[diff] [blame]535bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]536int btc_dpm_init(struct radeon_device *rdev);
537void btc_dpm_setup_asic(struct radeon_device *rdev);
538int btc_dpm_enable(struct radeon_device *rdev);
539void btc_dpm_disable(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]540int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]541int btc_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]542void btc_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]543void btc_dpm_fini(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]544u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
545u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
Alex Deuchera84301c2013-07-08 12:03:55 -0400[diff] [blame]546bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]547int sumo_dpm_init(struct radeon_device *rdev);
548int sumo_dpm_enable(struct radeon_device *rdev);
549void sumo_dpm_disable(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]550int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]551int sumo_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]552void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]553void sumo_dpm_setup_asic(struct radeon_device *rdev);
554void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
555void sumo_dpm_fini(struct radeon_device *rdev);
556u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
557u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
558void sumo_dpm_print_power_state(struct radeon_device *rdev,
559 struct radeon_ps *ps);
Alex Deucherfb701602013-06-28 10:47:56 -0400[diff] [blame]560void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
561 struct seq_file *m);
Alex Deucher5d5e5592013-07-02 18:50:09 -0400[diff] [blame]562int sumo_dpm_force_performance_level(struct radeon_device *rdev,
563 enum radeon_dpm_forced_level level);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]564
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]565/*
566 * cayman
567 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]568void cayman_fence_ring_emit(struct radeon_device *rdev,
569 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]570void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
571int cayman_init(struct radeon_device *rdev);
572void cayman_fini(struct radeon_device *rdev);
573int cayman_suspend(struct radeon_device *rdev);
574int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]575int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]576void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
577int cayman_vm_init(struct radeon_device *rdev);
578void cayman_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]579void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König089a7862012-08-11 11:54:05 +0200[diff] [blame]580uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]581int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deuchercd459e52012-12-13 12:17:38 -0500[diff] [blame]582int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]583void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
584 struct radeon_ib *ib);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]585bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]586bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]587void cayman_dma_vm_set_page(struct radeon_device *rdev,
588 struct radeon_ib *ib,
589 uint64_t pe,
590 uint64_t addr, unsigned count,
591 uint32_t incr, uint32_t flags);
592
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]593void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]594
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]595int ni_dpm_init(struct radeon_device *rdev);
596void ni_dpm_setup_asic(struct radeon_device *rdev);
597int ni_dpm_enable(struct radeon_device *rdev);
598void ni_dpm_disable(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]599int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]600int ni_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]601void ni_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]602void ni_dpm_fini(struct radeon_device *rdev);
603u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
604u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
605void ni_dpm_print_power_state(struct radeon_device *rdev,
606 struct radeon_ps *ps);
Alex Deucherbdf0c4f2013-06-28 17:49:02 -0400[diff] [blame]607void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
608 struct seq_file *m);
Alex Deucher170a47f2013-07-02 18:43:53 -0400[diff] [blame]609int ni_dpm_force_performance_level(struct radeon_device *rdev,
610 enum radeon_dpm_forced_level level);
Alex Deucher76ad73e2013-07-08 12:09:41 -0400[diff] [blame]611bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]612int trinity_dpm_init(struct radeon_device *rdev);
613int trinity_dpm_enable(struct radeon_device *rdev);
614void trinity_dpm_disable(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]615int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]616int trinity_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]617void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]618void trinity_dpm_setup_asic(struct radeon_device *rdev);
619void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
620void trinity_dpm_fini(struct radeon_device *rdev);
621u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
622u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
623void trinity_dpm_print_power_state(struct radeon_device *rdev,
624 struct radeon_ps *ps);
Alex Deucher490ab932013-06-28 12:01:38 -0400[diff] [blame]625void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
626 struct seq_file *m);
Alex Deucher9b5de592013-07-02 18:52:10 -0400[diff] [blame]627int trinity_dpm_force_performance_level(struct radeon_device *rdev,
628 enum radeon_dpm_forced_level level);
Alex Deucher11877062013-09-09 19:19:52 -0400[diff] [blame]629void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]630
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]631/* DCE6 - SI */
632void dce6_bandwidth_update(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]633int dce6_audio_init(struct radeon_device *rdev);
634void dce6_audio_fini(struct radeon_device *rdev);
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]635
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]636/*
637 * si
638 */
639void si_fence_ring_emit(struct radeon_device *rdev,
640 struct radeon_fence *fence);
641void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
642int si_init(struct radeon_device *rdev);
643void si_fini(struct radeon_device *rdev);
644int si_suspend(struct radeon_device *rdev);
645int si_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]646bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
647bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]648int si_asic_reset(struct radeon_device *rdev);
649void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
650int si_irq_set(struct radeon_device *rdev);
651int si_irq_process(struct radeon_device *rdev);
652int si_vm_init(struct radeon_device *rdev);
653void si_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]654void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]655int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]656int si_copy_dma(struct radeon_device *rdev,
657 uint64_t src_offset, uint64_t dst_offset,
658 unsigned num_gpu_pages,
659 struct radeon_fence **fence);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]660void si_dma_vm_set_page(struct radeon_device *rdev,
661 struct radeon_ib *ib,
662 uint64_t pe,
663 uint64_t addr, unsigned count,
664 uint32_t incr, uint32_t flags);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]665void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]666u32 si_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]667uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
Christian König2539eb02013-04-08 12:41:34 +0200[diff] [blame]668int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]669int si_get_temp(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]670int si_dpm_init(struct radeon_device *rdev);
671void si_dpm_setup_asic(struct radeon_device *rdev);
672int si_dpm_enable(struct radeon_device *rdev);
673void si_dpm_disable(struct radeon_device *rdev);
674int si_dpm_pre_set_power_state(struct radeon_device *rdev);
675int si_dpm_set_power_state(struct radeon_device *rdev);
676void si_dpm_post_set_power_state(struct radeon_device *rdev);
677void si_dpm_fini(struct radeon_device *rdev);
678void si_dpm_display_configuration_changed(struct radeon_device *rdev);
Alex Deucher79821282013-06-28 18:02:19 -0400[diff] [blame]679void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
680 struct seq_file *m);
Alex Deuchera160a6a2013-07-02 18:46:28 -0400[diff] [blame]681int si_dpm_force_performance_level(struct radeon_device *rdev,
682 enum radeon_dpm_forced_level level);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]683
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]684/* DCE8 - CIK */
685void dce8_bandwidth_update(struct radeon_device *rdev);
686
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]687/*
688 * cik
689 */
690uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]691u32 cik_get_xclk(struct radeon_device *rdev);
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400[diff] [blame]692uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
693void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]694int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]695void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
696 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]697bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]698 struct radeon_ring *ring,
699 struct radeon_semaphore *semaphore,
700 bool emit_wait);
701void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
702int cik_copy_dma(struct radeon_device *rdev,
703 uint64_t src_offset, uint64_t dst_offset,
704 unsigned num_gpu_pages,
705 struct radeon_fence **fence);
Alex Deucherc9dbd702013-10-01 16:36:51 -0400[diff] [blame]706int cik_copy_cpdma(struct radeon_device *rdev,
707 uint64_t src_offset, uint64_t dst_offset,
708 unsigned num_gpu_pages,
709 struct radeon_fence **fence);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]710int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
711int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
712bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
713void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
714 struct radeon_fence *fence);
715void cik_fence_compute_ring_emit(struct radeon_device *rdev,
716 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]717bool cik_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]718 struct radeon_ring *cp,
719 struct radeon_semaphore *semaphore,
720 bool emit_wait);
721void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
722int cik_init(struct radeon_device *rdev);
723void cik_fini(struct radeon_device *rdev);
724int cik_suspend(struct radeon_device *rdev);
725int cik_resume(struct radeon_device *rdev);
726bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
727int cik_asic_reset(struct radeon_device *rdev);
728void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
729int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
730int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
731int cik_irq_set(struct radeon_device *rdev);
732int cik_irq_process(struct radeon_device *rdev);
733int cik_vm_init(struct radeon_device *rdev);
734void cik_vm_fini(struct radeon_device *rdev);
735void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]736void cik_sdma_vm_set_page(struct radeon_device *rdev,
737 struct radeon_ib *ib,
738 uint64_t pe,
739 uint64_t addr, unsigned count,
740 uint32_t incr, uint32_t flags);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]741void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
742int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
743u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
744 struct radeon_ring *ring);
745u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
746 struct radeon_ring *ring);
747void cik_compute_ring_set_wptr(struct radeon_device *rdev,
748 struct radeon_ring *ring);
Alex Deucher286d9cc2013-06-21 15:50:47 -0400[diff] [blame]749int ci_get_temp(struct radeon_device *rdev);
750int kv_get_temp(struct radeon_device *rdev);
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]751
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]752int ci_dpm_init(struct radeon_device *rdev);
753int ci_dpm_enable(struct radeon_device *rdev);
754void ci_dpm_disable(struct radeon_device *rdev);
755int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
756int ci_dpm_set_power_state(struct radeon_device *rdev);
757void ci_dpm_post_set_power_state(struct radeon_device *rdev);
758void ci_dpm_setup_asic(struct radeon_device *rdev);
759void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
760void ci_dpm_fini(struct radeon_device *rdev);
761u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
762u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
763void ci_dpm_print_power_state(struct radeon_device *rdev,
764 struct radeon_ps *ps);
Alex Deucher94b4adc2013-07-15 17:34:33 -0400[diff] [blame]765void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
766 struct seq_file *m);
Alex Deucher89536fd2013-07-15 18:14:24 -0400[diff] [blame]767int ci_dpm_force_performance_level(struct radeon_device *rdev,
768 enum radeon_dpm_forced_level level);
Alex Deucher54961312013-07-15 18:24:31 -0400[diff] [blame]769bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher942bdf72013-08-09 10:05:24 -0400[diff] [blame]770void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]771
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]772int kv_dpm_init(struct radeon_device *rdev);
773int kv_dpm_enable(struct radeon_device *rdev);
774void kv_dpm_disable(struct radeon_device *rdev);
775int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
776int kv_dpm_set_power_state(struct radeon_device *rdev);
777void kv_dpm_post_set_power_state(struct radeon_device *rdev);
778void kv_dpm_setup_asic(struct radeon_device *rdev);
779void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
780void kv_dpm_fini(struct radeon_device *rdev);
781u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
782u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
783void kv_dpm_print_power_state(struct radeon_device *rdev,
784 struct radeon_ps *ps);
Alex Deucherae3e40e2013-07-18 16:39:53 -0400[diff] [blame]785void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
786 struct seq_file *m);
Alex Deucher2b4c8022013-07-18 16:48:46 -0400[diff] [blame]787int kv_dpm_force_performance_level(struct radeon_device *rdev,
788 enum radeon_dpm_forced_level level);
Alex Deucher77df5082013-08-09 10:02:40 -0400[diff] [blame]789void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deucherb7a5ae92013-09-09 19:33:08 -0400[diff] [blame]790void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]791
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]792/* uvd v1.0 */
793uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
794 struct radeon_ring *ring);
795uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
796 struct radeon_ring *ring);
797void uvd_v1_0_set_wptr(struct radeon_device *rdev,
798 struct radeon_ring *ring);
799
800int uvd_v1_0_init(struct radeon_device *rdev);
801void uvd_v1_0_fini(struct radeon_device *rdev);
802int uvd_v1_0_start(struct radeon_device *rdev);
803void uvd_v1_0_stop(struct radeon_device *rdev);
804
805int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
806int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]807bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]808 struct radeon_ring *ring,
809 struct radeon_semaphore *semaphore,
810 bool emit_wait);
811void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
812
813/* uvd v2.2 */
814int uvd_v2_2_resume(struct radeon_device *rdev);
815void uvd_v2_2_fence_emit(struct radeon_device *rdev,
816 struct radeon_fence *fence);
817
818/* uvd v3.1 */
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]819bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]820 struct radeon_ring *ring,
821 struct radeon_semaphore *semaphore,
822 bool emit_wait);
823
824/* uvd v4.2 */
825int uvd_v4_2_resume(struct radeon_device *rdev);
826
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]827#endif