Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "intel_drv.h" |
| 25 | |
| 26 | struct intel_shared_dpll * |
| 27 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
| 28 | { |
| 29 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 30 | |
| 31 | if (crtc->config->shared_dpll < 0) |
| 32 | return NULL; |
| 33 | |
| 34 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
| 35 | } |
| 36 | |
| 37 | /* For ILK+ */ |
| 38 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 39 | struct intel_shared_dpll *pll, |
| 40 | bool state) |
| 41 | { |
| 42 | bool cur_state; |
| 43 | struct intel_dpll_hw_state hw_state; |
| 44 | |
| 45 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
| 46 | return; |
| 47 | |
| 48 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
| 49 | I915_STATE_WARN(cur_state != state, |
| 50 | "%s assertion failure (expected %s, current %s)\n", |
| 51 | pll->name, onoff(state), onoff(cur_state)); |
| 52 | } |
| 53 | |
| 54 | void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
| 55 | { |
| 56 | struct drm_device *dev = crtc->base.dev; |
| 57 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 58 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 59 | |
| 60 | if (WARN_ON(pll == NULL)) |
| 61 | return; |
| 62 | |
| 63 | WARN_ON(!pll->config.crtc_mask); |
| 64 | if (pll->active == 0) { |
| 65 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
| 66 | WARN_ON(pll->on); |
| 67 | assert_shared_dpll_disabled(dev_priv, pll); |
| 68 | |
| 69 | pll->mode_set(dev_priv, pll); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | /** |
| 74 | * intel_enable_shared_dpll - enable PCH PLL |
| 75 | * @dev_priv: i915 private structure |
| 76 | * @pipe: pipe PLL to enable |
| 77 | * |
| 78 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 79 | * drives the transcoder clock. |
| 80 | */ |
| 81 | void intel_enable_shared_dpll(struct intel_crtc *crtc) |
| 82 | { |
| 83 | struct drm_device *dev = crtc->base.dev; |
| 84 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 85 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 86 | |
| 87 | if (WARN_ON(pll == NULL)) |
| 88 | return; |
| 89 | |
| 90 | if (WARN_ON(pll->config.crtc_mask == 0)) |
| 91 | return; |
| 92 | |
| 93 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
| 94 | pll->name, pll->active, pll->on, |
| 95 | crtc->base.base.id); |
| 96 | |
| 97 | if (pll->active++) { |
| 98 | WARN_ON(!pll->on); |
| 99 | assert_shared_dpll_enabled(dev_priv, pll); |
| 100 | return; |
| 101 | } |
| 102 | WARN_ON(pll->on); |
| 103 | |
| 104 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
| 105 | |
| 106 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
| 107 | pll->enable(dev_priv, pll); |
| 108 | pll->on = true; |
| 109 | } |
| 110 | |
| 111 | void intel_disable_shared_dpll(struct intel_crtc *crtc) |
| 112 | { |
| 113 | struct drm_device *dev = crtc->base.dev; |
| 114 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 115 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 116 | |
| 117 | /* PCH only available on ILK+ */ |
| 118 | if (INTEL_INFO(dev)->gen < 5) |
| 119 | return; |
| 120 | |
| 121 | if (pll == NULL) |
| 122 | return; |
| 123 | |
| 124 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
| 125 | return; |
| 126 | |
| 127 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
| 128 | pll->name, pll->active, pll->on, |
| 129 | crtc->base.base.id); |
| 130 | |
| 131 | if (WARN_ON(pll->active == 0)) { |
| 132 | assert_shared_dpll_disabled(dev_priv, pll); |
| 133 | return; |
| 134 | } |
| 135 | |
| 136 | assert_shared_dpll_enabled(dev_priv, pll); |
| 137 | WARN_ON(!pll->on); |
| 138 | if (--pll->active) |
| 139 | return; |
| 140 | |
| 141 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
| 142 | pll->disable(dev_priv, pll); |
| 143 | pll->on = false; |
| 144 | |
| 145 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 146 | } |
| 147 | |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 148 | static enum intel_dpll_id |
| 149 | ibx_get_fixed_dpll(struct intel_crtc *crtc, |
| 150 | struct intel_crtc_state *crtc_state) |
| 151 | { |
| 152 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 153 | struct intel_shared_dpll *pll; |
| 154 | enum intel_dpll_id i; |
| 155 | |
| 156 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
| 157 | i = (enum intel_dpll_id) crtc->pipe; |
| 158 | pll = &dev_priv->shared_dplls[i]; |
| 159 | |
| 160 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 161 | crtc->base.base.id, pll->name); |
| 162 | |
| 163 | return i; |
| 164 | } |
| 165 | |
| 166 | static enum intel_dpll_id |
| 167 | bxt_get_fixed_dpll(struct intel_crtc *crtc, |
| 168 | struct intel_crtc_state *crtc_state) |
| 169 | { |
| 170 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 171 | struct intel_encoder *encoder; |
| 172 | struct intel_digital_port *intel_dig_port; |
| 173 | struct intel_shared_dpll *pll; |
| 174 | enum intel_dpll_id i; |
| 175 | |
| 176 | /* PLL is attached to port in bxt */ |
| 177 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); |
| 178 | if (WARN_ON(!encoder)) |
| 179 | return DPLL_ID_PRIVATE; |
| 180 | |
| 181 | intel_dig_port = enc_to_dig_port(&encoder->base); |
| 182 | /* 1:1 mapping between ports and PLLs */ |
| 183 | i = (enum intel_dpll_id)intel_dig_port->port; |
| 184 | pll = &dev_priv->shared_dplls[i]; |
| 185 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 186 | crtc->base.base.id, pll->name); |
| 187 | |
| 188 | return i; |
| 189 | } |
| 190 | |
| 191 | static enum intel_dpll_id |
| 192 | intel_find_shared_dpll(struct intel_crtc *crtc, |
| 193 | struct intel_crtc_state *crtc_state) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 194 | { |
| 195 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 196 | struct intel_shared_dpll *pll; |
| 197 | struct intel_shared_dpll_config *shared_dpll; |
| 198 | enum intel_dpll_id i; |
| 199 | int max = dev_priv->num_shared_dpll; |
| 200 | |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 201 | if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 202 | /* Do not consider SPLL */ |
| 203 | max = 2; |
| 204 | |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 205 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
| 206 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 207 | for (i = 0; i < max; i++) { |
| 208 | pll = &dev_priv->shared_dplls[i]; |
| 209 | |
| 210 | /* Only want to check enabled timings first */ |
| 211 | if (shared_dpll[i].crtc_mask == 0) |
| 212 | continue; |
| 213 | |
| 214 | if (memcmp(&crtc_state->dpll_hw_state, |
| 215 | &shared_dpll[i].hw_state, |
| 216 | sizeof(crtc_state->dpll_hw_state)) == 0) { |
| 217 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
| 218 | crtc->base.base.id, pll->name, |
| 219 | shared_dpll[i].crtc_mask, |
| 220 | pll->active); |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 221 | return i; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 222 | } |
| 223 | } |
| 224 | |
| 225 | /* Ok no matching timings, maybe there's a free one? */ |
| 226 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 227 | pll = &dev_priv->shared_dplls[i]; |
| 228 | if (shared_dpll[i].crtc_mask == 0) { |
| 229 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
| 230 | crtc->base.base.id, pll->name); |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 231 | return i; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 232 | } |
| 233 | } |
| 234 | |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 235 | return DPLL_ID_PRIVATE; |
| 236 | } |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 237 | |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame^] | 238 | struct intel_shared_dpll * |
| 239 | intel_get_shared_dpll(struct intel_crtc *crtc, |
| 240 | struct intel_crtc_state *crtc_state) |
| 241 | { |
| 242 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 243 | struct intel_shared_dpll *pll; |
| 244 | struct intel_shared_dpll_config *shared_dpll; |
| 245 | enum intel_dpll_id i; |
| 246 | |
| 247 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
| 248 | |
| 249 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 250 | i = ibx_get_fixed_dpll(crtc, crtc_state); |
| 251 | WARN_ON(shared_dpll[i].crtc_mask); |
| 252 | } else if (IS_BROXTON(dev_priv->dev)) { |
| 253 | i = bxt_get_fixed_dpll(crtc, crtc_state); |
| 254 | WARN_ON(shared_dpll[i].crtc_mask); |
| 255 | } else { |
| 256 | i = intel_find_shared_dpll(crtc, crtc_state); |
| 257 | } |
| 258 | |
| 259 | if (i < 0) |
| 260 | return NULL; |
| 261 | |
| 262 | pll = &dev_priv->shared_dplls[i]; |
| 263 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 264 | if (shared_dpll[i].crtc_mask == 0) |
| 265 | shared_dpll[i].hw_state = |
| 266 | crtc_state->dpll_hw_state; |
| 267 | |
| 268 | crtc_state->shared_dpll = i; |
| 269 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
| 270 | pipe_name(crtc->pipe)); |
| 271 | |
| 272 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
| 273 | |
| 274 | return pll; |
| 275 | } |
| 276 | |
| 277 | void intel_shared_dpll_commit(struct drm_atomic_state *state) |
| 278 | { |
| 279 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
| 280 | struct intel_shared_dpll_config *shared_dpll; |
| 281 | struct intel_shared_dpll *pll; |
| 282 | enum intel_dpll_id i; |
| 283 | |
| 284 | if (!to_intel_atomic_state(state)->dpll_set) |
| 285 | return; |
| 286 | |
| 287 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
| 288 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 289 | pll = &dev_priv->shared_dplls[i]; |
| 290 | pll->config = shared_dpll[i]; |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 295 | struct intel_shared_dpll *pll, |
| 296 | struct intel_dpll_hw_state *hw_state) |
| 297 | { |
| 298 | uint32_t val; |
| 299 | |
| 300 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 301 | return false; |
| 302 | |
| 303 | val = I915_READ(PCH_DPLL(pll->id)); |
| 304 | hw_state->dpll = val; |
| 305 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
| 306 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
| 307 | |
| 308 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 309 | |
| 310 | return val & DPLL_VCO_ENABLE; |
| 311 | } |
| 312 | |
| 313 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
| 314 | struct intel_shared_dpll *pll) |
| 315 | { |
| 316 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
| 317 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); |
| 318 | } |
| 319 | |
| 320 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
| 321 | { |
| 322 | u32 val; |
| 323 | bool enabled; |
| 324 | |
| 325 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
| 326 | |
| 327 | val = I915_READ(PCH_DREF_CONTROL); |
| 328 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 329 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 330 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 331 | } |
| 332 | |
| 333 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
| 334 | struct intel_shared_dpll *pll) |
| 335 | { |
| 336 | /* PCH refclock must be enabled first */ |
| 337 | ibx_assert_pch_refclk_enabled(dev_priv); |
| 338 | |
| 339 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
| 340 | |
| 341 | /* Wait for the clocks to stabilize. */ |
| 342 | POSTING_READ(PCH_DPLL(pll->id)); |
| 343 | udelay(150); |
| 344 | |
| 345 | /* The pixel multiplier can only be updated once the |
| 346 | * DPLL is enabled and the clocks are stable. |
| 347 | * |
| 348 | * So write it again. |
| 349 | */ |
| 350 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
| 351 | POSTING_READ(PCH_DPLL(pll->id)); |
| 352 | udelay(200); |
| 353 | } |
| 354 | |
| 355 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
| 356 | struct intel_shared_dpll *pll) |
| 357 | { |
| 358 | struct drm_device *dev = dev_priv->dev; |
| 359 | struct intel_crtc *crtc; |
| 360 | |
| 361 | /* Make sure no transcoder isn't still depending on us. */ |
| 362 | for_each_intel_crtc(dev, crtc) { |
| 363 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
| 364 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
| 365 | } |
| 366 | |
| 367 | I915_WRITE(PCH_DPLL(pll->id), 0); |
| 368 | POSTING_READ(PCH_DPLL(pll->id)); |
| 369 | udelay(200); |
| 370 | } |
| 371 | |
| 372 | static char *ibx_pch_dpll_names[] = { |
| 373 | "PCH DPLL A", |
| 374 | "PCH DPLL B", |
| 375 | }; |
| 376 | |
| 377 | static void ibx_pch_dpll_init(struct drm_device *dev) |
| 378 | { |
| 379 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 380 | int i; |
| 381 | |
| 382 | dev_priv->num_shared_dpll = 2; |
| 383 | |
| 384 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 385 | dev_priv->shared_dplls[i].id = i; |
| 386 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
| 387 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
| 388 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
| 389 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
| 390 | dev_priv->shared_dplls[i].get_hw_state = |
| 391 | ibx_pch_dpll_get_hw_state; |
| 392 | } |
| 393 | } |
| 394 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 395 | static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, |
| 396 | struct intel_shared_dpll *pll) |
| 397 | { |
| 398 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
| 399 | POSTING_READ(WRPLL_CTL(pll->id)); |
| 400 | udelay(20); |
| 401 | } |
| 402 | |
| 403 | static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, |
| 404 | struct intel_shared_dpll *pll) |
| 405 | { |
| 406 | I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); |
| 407 | POSTING_READ(SPLL_CTL); |
| 408 | udelay(20); |
| 409 | } |
| 410 | |
| 411 | static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, |
| 412 | struct intel_shared_dpll *pll) |
| 413 | { |
| 414 | uint32_t val; |
| 415 | |
| 416 | val = I915_READ(WRPLL_CTL(pll->id)); |
| 417 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
| 418 | POSTING_READ(WRPLL_CTL(pll->id)); |
| 419 | } |
| 420 | |
| 421 | static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, |
| 422 | struct intel_shared_dpll *pll) |
| 423 | { |
| 424 | uint32_t val; |
| 425 | |
| 426 | val = I915_READ(SPLL_CTL); |
| 427 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
| 428 | POSTING_READ(SPLL_CTL); |
| 429 | } |
| 430 | |
| 431 | static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 432 | struct intel_shared_dpll *pll, |
| 433 | struct intel_dpll_hw_state *hw_state) |
| 434 | { |
| 435 | uint32_t val; |
| 436 | |
| 437 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 438 | return false; |
| 439 | |
| 440 | val = I915_READ(WRPLL_CTL(pll->id)); |
| 441 | hw_state->wrpll = val; |
| 442 | |
| 443 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 444 | |
| 445 | return val & WRPLL_PLL_ENABLE; |
| 446 | } |
| 447 | |
| 448 | static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, |
| 449 | struct intel_shared_dpll *pll, |
| 450 | struct intel_dpll_hw_state *hw_state) |
| 451 | { |
| 452 | uint32_t val; |
| 453 | |
| 454 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 455 | return false; |
| 456 | |
| 457 | val = I915_READ(SPLL_CTL); |
| 458 | hw_state->spll = val; |
| 459 | |
| 460 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 461 | |
| 462 | return val & SPLL_PLL_ENABLE; |
| 463 | } |
| 464 | |
| 465 | |
| 466 | static const char * const hsw_ddi_pll_names[] = { |
| 467 | "WRPLL 1", |
| 468 | "WRPLL 2", |
| 469 | "SPLL" |
| 470 | }; |
| 471 | |
| 472 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
| 473 | { |
| 474 | int i; |
| 475 | |
| 476 | dev_priv->num_shared_dpll = 3; |
| 477 | |
| 478 | for (i = 0; i < 2; i++) { |
| 479 | dev_priv->shared_dplls[i].id = i; |
| 480 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
| 481 | dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; |
| 482 | dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; |
| 483 | dev_priv->shared_dplls[i].get_hw_state = |
| 484 | hsw_ddi_wrpll_get_hw_state; |
| 485 | } |
| 486 | |
| 487 | /* SPLL is special, but needs to be initialized anyway.. */ |
| 488 | dev_priv->shared_dplls[i].id = i; |
| 489 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
| 490 | dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; |
| 491 | dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; |
| 492 | dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; |
| 493 | |
| 494 | } |
| 495 | |
| 496 | static const char * const skl_ddi_pll_names[] = { |
| 497 | "DPLL 1", |
| 498 | "DPLL 2", |
| 499 | "DPLL 3", |
| 500 | }; |
| 501 | |
| 502 | struct skl_dpll_regs { |
| 503 | i915_reg_t ctl, cfgcr1, cfgcr2; |
| 504 | }; |
| 505 | |
| 506 | /* this array is indexed by the *shared* pll id */ |
| 507 | static const struct skl_dpll_regs skl_dpll_regs[3] = { |
| 508 | { |
| 509 | /* DPLL 1 */ |
| 510 | .ctl = LCPLL2_CTL, |
| 511 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), |
| 512 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), |
| 513 | }, |
| 514 | { |
| 515 | /* DPLL 2 */ |
| 516 | .ctl = WRPLL_CTL(0), |
| 517 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), |
| 518 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), |
| 519 | }, |
| 520 | { |
| 521 | /* DPLL 3 */ |
| 522 | .ctl = WRPLL_CTL(1), |
| 523 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), |
| 524 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), |
| 525 | }, |
| 526 | }; |
| 527 | |
| 528 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, |
| 529 | struct intel_shared_dpll *pll) |
| 530 | { |
| 531 | uint32_t val; |
| 532 | unsigned int dpll; |
| 533 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 534 | |
| 535 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
| 536 | dpll = pll->id + 1; |
| 537 | |
| 538 | val = I915_READ(DPLL_CTRL1); |
| 539 | |
| 540 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | |
| 541 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
| 542 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); |
| 543 | |
| 544 | I915_WRITE(DPLL_CTRL1, val); |
| 545 | POSTING_READ(DPLL_CTRL1); |
| 546 | |
| 547 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); |
| 548 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); |
| 549 | POSTING_READ(regs[pll->id].cfgcr1); |
| 550 | POSTING_READ(regs[pll->id].cfgcr2); |
| 551 | |
| 552 | /* the enable bit is always bit 31 */ |
| 553 | I915_WRITE(regs[pll->id].ctl, |
| 554 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); |
| 555 | |
| 556 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) |
| 557 | DRM_ERROR("DPLL %d not locked\n", dpll); |
| 558 | } |
| 559 | |
| 560 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, |
| 561 | struct intel_shared_dpll *pll) |
| 562 | { |
| 563 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 564 | |
| 565 | /* the enable bit is always bit 31 */ |
| 566 | I915_WRITE(regs[pll->id].ctl, |
| 567 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); |
| 568 | POSTING_READ(regs[pll->id].ctl); |
| 569 | } |
| 570 | |
| 571 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
| 572 | struct intel_shared_dpll *pll, |
| 573 | struct intel_dpll_hw_state *hw_state) |
| 574 | { |
| 575 | uint32_t val; |
| 576 | unsigned int dpll; |
| 577 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 578 | bool ret; |
| 579 | |
| 580 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 581 | return false; |
| 582 | |
| 583 | ret = false; |
| 584 | |
| 585 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
| 586 | dpll = pll->id + 1; |
| 587 | |
| 588 | val = I915_READ(regs[pll->id].ctl); |
| 589 | if (!(val & LCPLL_PLL_ENABLE)) |
| 590 | goto out; |
| 591 | |
| 592 | val = I915_READ(DPLL_CTRL1); |
| 593 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; |
| 594 | |
| 595 | /* avoid reading back stale values if HDMI mode is not enabled */ |
| 596 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { |
| 597 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); |
| 598 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); |
| 599 | } |
| 600 | ret = true; |
| 601 | |
| 602 | out: |
| 603 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 604 | |
| 605 | return ret; |
| 606 | } |
| 607 | |
| 608 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) |
| 609 | { |
| 610 | int i; |
| 611 | |
| 612 | dev_priv->num_shared_dpll = 3; |
| 613 | |
| 614 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 615 | dev_priv->shared_dplls[i].id = i; |
| 616 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; |
| 617 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; |
| 618 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; |
| 619 | dev_priv->shared_dplls[i].get_hw_state = |
| 620 | skl_ddi_pll_get_hw_state; |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | static const char * const bxt_ddi_pll_names[] = { |
| 625 | "PORT PLL A", |
| 626 | "PORT PLL B", |
| 627 | "PORT PLL C", |
| 628 | }; |
| 629 | |
| 630 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, |
| 631 | struct intel_shared_dpll *pll) |
| 632 | { |
| 633 | uint32_t temp; |
| 634 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
| 635 | |
| 636 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 637 | temp &= ~PORT_PLL_REF_SEL; |
| 638 | /* Non-SSC reference */ |
| 639 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 640 | |
| 641 | /* Disable 10 bit clock */ |
| 642 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
| 643 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
| 644 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
| 645 | |
| 646 | /* Write P1 & P2 */ |
| 647 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
| 648 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); |
| 649 | temp |= pll->config.hw_state.ebb0; |
| 650 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); |
| 651 | |
| 652 | /* Write M2 integer */ |
| 653 | temp = I915_READ(BXT_PORT_PLL(port, 0)); |
| 654 | temp &= ~PORT_PLL_M2_MASK; |
| 655 | temp |= pll->config.hw_state.pll0; |
| 656 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); |
| 657 | |
| 658 | /* Write N */ |
| 659 | temp = I915_READ(BXT_PORT_PLL(port, 1)); |
| 660 | temp &= ~PORT_PLL_N_MASK; |
| 661 | temp |= pll->config.hw_state.pll1; |
| 662 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); |
| 663 | |
| 664 | /* Write M2 fraction */ |
| 665 | temp = I915_READ(BXT_PORT_PLL(port, 2)); |
| 666 | temp &= ~PORT_PLL_M2_FRAC_MASK; |
| 667 | temp |= pll->config.hw_state.pll2; |
| 668 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); |
| 669 | |
| 670 | /* Write M2 fraction enable */ |
| 671 | temp = I915_READ(BXT_PORT_PLL(port, 3)); |
| 672 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; |
| 673 | temp |= pll->config.hw_state.pll3; |
| 674 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); |
| 675 | |
| 676 | /* Write coeff */ |
| 677 | temp = I915_READ(BXT_PORT_PLL(port, 6)); |
| 678 | temp &= ~PORT_PLL_PROP_COEFF_MASK; |
| 679 | temp &= ~PORT_PLL_INT_COEFF_MASK; |
| 680 | temp &= ~PORT_PLL_GAIN_CTL_MASK; |
| 681 | temp |= pll->config.hw_state.pll6; |
| 682 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); |
| 683 | |
| 684 | /* Write calibration val */ |
| 685 | temp = I915_READ(BXT_PORT_PLL(port, 8)); |
| 686 | temp &= ~PORT_PLL_TARGET_CNT_MASK; |
| 687 | temp |= pll->config.hw_state.pll8; |
| 688 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); |
| 689 | |
| 690 | temp = I915_READ(BXT_PORT_PLL(port, 9)); |
| 691 | temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; |
| 692 | temp |= pll->config.hw_state.pll9; |
| 693 | I915_WRITE(BXT_PORT_PLL(port, 9), temp); |
| 694 | |
| 695 | temp = I915_READ(BXT_PORT_PLL(port, 10)); |
| 696 | temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; |
| 697 | temp &= ~PORT_PLL_DCO_AMP_MASK; |
| 698 | temp |= pll->config.hw_state.pll10; |
| 699 | I915_WRITE(BXT_PORT_PLL(port, 10), temp); |
| 700 | |
| 701 | /* Recalibrate with new settings */ |
| 702 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
| 703 | temp |= PORT_PLL_RECALIBRATE; |
| 704 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
| 705 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
| 706 | temp |= pll->config.hw_state.ebb4; |
| 707 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); |
| 708 | |
| 709 | /* Enable PLL */ |
| 710 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 711 | temp |= PORT_PLL_ENABLE; |
| 712 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 713 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
| 714 | |
| 715 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & |
| 716 | PORT_PLL_LOCK), 200)) |
| 717 | DRM_ERROR("PLL %d not locked\n", port); |
| 718 | |
| 719 | /* |
| 720 | * While we write to the group register to program all lanes at once we |
| 721 | * can read only lane registers and we pick lanes 0/1 for that. |
| 722 | */ |
| 723 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); |
| 724 | temp &= ~LANE_STAGGER_MASK; |
| 725 | temp &= ~LANESTAGGER_STRAP_OVRD; |
| 726 | temp |= pll->config.hw_state.pcsdw12; |
| 727 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); |
| 728 | } |
| 729 | |
| 730 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, |
| 731 | struct intel_shared_dpll *pll) |
| 732 | { |
| 733 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
| 734 | uint32_t temp; |
| 735 | |
| 736 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 737 | temp &= ~PORT_PLL_ENABLE; |
| 738 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 739 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
| 740 | } |
| 741 | |
| 742 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
| 743 | struct intel_shared_dpll *pll, |
| 744 | struct intel_dpll_hw_state *hw_state) |
| 745 | { |
| 746 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
| 747 | uint32_t val; |
| 748 | bool ret; |
| 749 | |
| 750 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 751 | return false; |
| 752 | |
| 753 | ret = false; |
| 754 | |
| 755 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 756 | if (!(val & PORT_PLL_ENABLE)) |
| 757 | goto out; |
| 758 | |
| 759 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); |
| 760 | hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; |
| 761 | |
| 762 | hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); |
| 763 | hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; |
| 764 | |
| 765 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); |
| 766 | hw_state->pll0 &= PORT_PLL_M2_MASK; |
| 767 | |
| 768 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); |
| 769 | hw_state->pll1 &= PORT_PLL_N_MASK; |
| 770 | |
| 771 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); |
| 772 | hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; |
| 773 | |
| 774 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); |
| 775 | hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; |
| 776 | |
| 777 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); |
| 778 | hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | |
| 779 | PORT_PLL_INT_COEFF_MASK | |
| 780 | PORT_PLL_GAIN_CTL_MASK; |
| 781 | |
| 782 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); |
| 783 | hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; |
| 784 | |
| 785 | hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); |
| 786 | hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; |
| 787 | |
| 788 | hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); |
| 789 | hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | |
| 790 | PORT_PLL_DCO_AMP_MASK; |
| 791 | |
| 792 | /* |
| 793 | * While we write to the group register to program all lanes at once we |
| 794 | * can read only lane registers. We configure all lanes the same way, so |
| 795 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. |
| 796 | */ |
| 797 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); |
| 798 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) |
| 799 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", |
| 800 | hw_state->pcsdw12, |
| 801 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); |
| 802 | hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; |
| 803 | |
| 804 | ret = true; |
| 805 | |
| 806 | out: |
| 807 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 808 | |
| 809 | return ret; |
| 810 | } |
| 811 | |
| 812 | static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) |
| 813 | { |
| 814 | int i; |
| 815 | |
| 816 | dev_priv->num_shared_dpll = 3; |
| 817 | |
| 818 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 819 | dev_priv->shared_dplls[i].id = i; |
| 820 | dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; |
| 821 | dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; |
| 822 | dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; |
| 823 | dev_priv->shared_dplls[i].get_hw_state = |
| 824 | bxt_ddi_pll_get_hw_state; |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | static void intel_ddi_pll_init(struct drm_device *dev) |
| 829 | { |
| 830 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 831 | uint32_t val = I915_READ(LCPLL_CTL); |
| 832 | |
| 833 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
| 834 | skl_shared_dplls_init(dev_priv); |
| 835 | else if (IS_BROXTON(dev)) |
| 836 | bxt_shared_dplls_init(dev_priv); |
| 837 | else |
| 838 | hsw_shared_dplls_init(dev_priv); |
| 839 | |
| 840 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
| 841 | int cdclk_freq; |
| 842 | |
| 843 | cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
| 844 | dev_priv->skl_boot_cdclk = cdclk_freq; |
| 845 | if (skl_sanitize_cdclk(dev_priv)) |
| 846 | DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); |
| 847 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) |
| 848 | DRM_ERROR("LCPLL1 is disabled\n"); |
| 849 | } else if (IS_BROXTON(dev)) { |
| 850 | broxton_init_cdclk(dev); |
| 851 | broxton_ddi_phy_init(dev); |
| 852 | } else { |
| 853 | /* |
| 854 | * The LCPLL register should be turned on by the BIOS. For now |
| 855 | * let's just check its state and print errors in case |
| 856 | * something is wrong. Don't even try to turn it on. |
| 857 | */ |
| 858 | |
| 859 | if (val & LCPLL_CD_SOURCE_FCLK) |
| 860 | DRM_ERROR("CDCLK source is not LCPLL\n"); |
| 861 | |
| 862 | if (val & LCPLL_PLL_DISABLE) |
| 863 | DRM_ERROR("LCPLL is disabled\n"); |
| 864 | } |
| 865 | } |
| 866 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 867 | void intel_shared_dpll_init(struct drm_device *dev) |
| 868 | { |
| 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 870 | |
| 871 | if (HAS_DDI(dev)) |
| 872 | intel_ddi_pll_init(dev); |
| 873 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 874 | ibx_pch_dpll_init(dev); |
| 875 | else |
| 876 | dev_priv->num_shared_dpll = 0; |
| 877 | |
| 878 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
| 879 | } |