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Marc Zyngier0369f6a2012-12-10 10:46:47 +00001/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM64_KVM_ARM_H__
19#define __ARM64_KVM_ARM_H__
20
Mark Rutland6e530312014-11-24 14:05:44 +000021#include <asm/esr.h>
Geoff Levand286fb1c2014-10-31 23:06:47 +000022#include <asm/memory.h>
Marc Zyngier0369f6a2012-12-10 10:46:47 +000023#include <asm/types.h>
24
25/* Hyp Configuration Register (HCR) bits */
Marc Zyngier68908bf2015-01-29 15:47:55 +000026#define HCR_E2H (UL(1) << 34)
Marc Zyngier0369f6a2012-12-10 10:46:47 +000027#define HCR_ID (UL(1) << 33)
28#define HCR_CD (UL(1) << 32)
29#define HCR_RW_SHIFT 31
30#define HCR_RW (UL(1) << HCR_RW_SHIFT)
31#define HCR_TRVM (UL(1) << 30)
32#define HCR_HCD (UL(1) << 29)
33#define HCR_TDZ (UL(1) << 28)
34#define HCR_TGE (UL(1) << 27)
35#define HCR_TVM (UL(1) << 26)
36#define HCR_TTLB (UL(1) << 25)
37#define HCR_TPU (UL(1) << 24)
38#define HCR_TPC (UL(1) << 23)
39#define HCR_TSW (UL(1) << 22)
40#define HCR_TAC (UL(1) << 21)
41#define HCR_TIDCP (UL(1) << 20)
42#define HCR_TSC (UL(1) << 19)
43#define HCR_TID3 (UL(1) << 18)
44#define HCR_TID2 (UL(1) << 17)
45#define HCR_TID1 (UL(1) << 16)
46#define HCR_TID0 (UL(1) << 15)
47#define HCR_TWE (UL(1) << 14)
48#define HCR_TWI (UL(1) << 13)
49#define HCR_DC (UL(1) << 12)
50#define HCR_BSU (3 << 10)
51#define HCR_BSU_IS (UL(1) << 10)
52#define HCR_FB (UL(1) << 9)
53#define HCR_VA (UL(1) << 8)
54#define HCR_VI (UL(1) << 7)
55#define HCR_VF (UL(1) << 6)
56#define HCR_AMO (UL(1) << 5)
57#define HCR_IMO (UL(1) << 4)
58#define HCR_FMO (UL(1) << 3)
59#define HCR_PTW (UL(1) << 2)
60#define HCR_SWIO (UL(1) << 1)
61#define HCR_VM (UL(1) << 0)
62
63/*
64 * The bits we set in HCR:
Adam Buchbinderef769e32016-02-24 09:52:41 -080065 * RW: 64bit by default, can be overridden for 32bit VMs
Marc Zyngier0369f6a2012-12-10 10:46:47 +000066 * TAC: Trap ACTLR
67 * TSC: Trap SMC
Marc Zyngier4d449232014-01-14 18:00:55 +000068 * TVM: Trap VM ops (until M+C set in SCTLR_EL1)
Marc Zyngier0369f6a2012-12-10 10:46:47 +000069 * TSW: Trap cache operations by set/way
Marc Zyngierd241aac2013-08-02 11:41:13 +010070 * TWE: Trap WFE
Marc Zyngier0369f6a2012-12-10 10:46:47 +000071 * TWI: Trap WFI
72 * TIDCP: Trap L2CTLR/L2ECTLR
73 * BSU_IS: Upgrade barriers to the inner shareable domain
74 * FB: Force broadcast of all maintainance operations
75 * AMO: Override CPSR.A and enable signaling with VA
76 * IMO: Override CPSR.I and enable signaling with VI
77 * FMO: Override CPSR.F and enable signaling with VF
78 * SWIO: Turn set/way invalidates into set/way clean+invalidate
79 */
Marc Zyngierd241aac2013-08-02 11:41:13 +010080#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
Marc Zyngier4d449232014-01-14 18:00:55 +000081 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
Marc Zyngierac3c3742013-08-09 18:19:11 +010082 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
Marc Zyngier0369f6a2012-12-10 10:46:47 +000083#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
Marc Zyngierac3c3742013-08-09 18:19:11 +010084#define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO)
Marc Zyngier68908bf2015-01-29 15:47:55 +000085#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
Marc Zyngier0369f6a2012-12-10 10:46:47 +000086
87/* Hyp System Control Register (SCTLR_EL2) bits */
88#define SCTLR_EL2_EE (1 << 25)
89#define SCTLR_EL2_WXN (1 << 19)
90#define SCTLR_EL2_I (1 << 12)
91#define SCTLR_EL2_SA (1 << 3)
92#define SCTLR_EL2_C (1 << 2)
93#define SCTLR_EL2_A (1 << 1)
94#define SCTLR_EL2_M 1
95#define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | \
96 SCTLR_EL2_SA | SCTLR_EL2_I)
97
98/* TCR_EL2 Registers bits */
Suzuki K Poulosea563f752016-04-04 11:43:15 +010099#define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
100#define TCR_EL2_TBI (1 << 20)
101#define TCR_EL2_PS_SHIFT 16
102#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
103#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
104#define TCR_EL2_TG0_MASK TCR_TG0_MASK
105#define TCR_EL2_SH0_MASK TCR_SH0_MASK
106#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
107#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
108#define TCR_EL2_T0SZ_MASK 0x3f
109#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
110 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000111
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000112/* VTCR_EL2 Registers bits */
Mark Rutland857d1a92015-08-24 14:42:05 +0100113#define VTCR_EL2_RES1 (1 << 31)
Suzuki K Poulosea563f752016-04-04 11:43:15 +0100114#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
115#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
116#define VTCR_EL2_TG0_4K TCR_TG0_4K
Suzuki K Poulose02e0b762016-03-17 14:29:24 +0000117#define VTCR_EL2_TG0_16K TCR_TG0_16K
Suzuki K Poulosea563f752016-04-04 11:43:15 +0100118#define VTCR_EL2_TG0_64K TCR_TG0_64K
119#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
120#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
121#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
122#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
123#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
124#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
125#define VTCR_EL2_SL0_SHIFT 6
126#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
127#define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT)
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000128#define VTCR_EL2_T0SZ_MASK 0x3f
129#define VTCR_EL2_T0SZ_40B 24
Suzuki K Poulosecb678d62016-03-30 14:33:59 +0100130#define VTCR_EL2_VS_SHIFT 19
131#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
132#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000133
Joel Schoppdbff1242014-07-09 11:17:04 -0500134/*
135 * We configure the Stage-2 page tables to always restrict the IPA space to be
136 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
137 * not known to exist and will break with this configuration.
138 *
Marc Zyngier84ed7412015-03-10 19:07:01 +0000139 * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
140 * (see hyp-init.S).
141 *
Joel Schoppdbff1242014-07-09 11:17:04 -0500142 * Note that when using 4K pages, we concatenate two first level page tables
Suzuki K Poulose02e0b762016-03-17 14:29:24 +0000143 * together. With 16K pages, we concatenate 16 first level page tables.
Joel Schoppdbff1242014-07-09 11:17:04 -0500144 *
145 * The magic numbers used for VTTBR_X in this patch can be found in Tables
146 * D4-23 and D4-25 in ARM DDI 0487A.b.
147 */
Suzuki K Pouloseacd05012016-04-04 11:53:52 +0100148
149#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B
150#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
151 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
152
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000153#ifdef CONFIG_ARM64_64K_PAGES
154/*
155 * Stage2 translation configuration:
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000156 * 64kB pages (TG0 = 1)
157 * 2 level page tables (SL = 1)
158 */
Suzuki K Pouloseacd05012016-04-04 11:53:52 +0100159#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
160#define VTTBR_X_TGRAN_MAGIC 38
Suzuki K Poulose02e0b762016-03-17 14:29:24 +0000161#elif defined(CONFIG_ARM64_16K_PAGES)
162/*
163 * Stage2 translation configuration:
164 * 16kB pages (TG0 = 2)
165 * 2 level page tables (SL = 1)
166 */
167#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
168#define VTTBR_X_TGRAN_MAGIC 42
169#else /* 4K */
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000170/*
171 * Stage2 translation configuration:
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000172 * 4kB pages (TG0 = 0)
173 * 3 level page tables (SL = 1)
174 */
Suzuki K Pouloseacd05012016-04-04 11:53:52 +0100175#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
176#define VTTBR_X_TGRAN_MAGIC 37
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000177#endif
178
Suzuki K Pouloseacd05012016-04-04 11:53:52 +0100179#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
180#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
181
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000182#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
Geoff Levand286fb1c2014-10-31 23:06:47 +0000183#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
184#define VTTBR_VMID_SHIFT (UL(48))
Vladimir Murzin20475f72015-11-16 11:28:18 +0000185#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000186
187/* Hyp System Trap Register */
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000188#define HSTR_EL2_T(x) (1 << x)
189
Mario Smarduch33c76a02015-07-16 22:29:37 +0100190/* Hyp Coproccessor Trap Register Shifts */
191#define CPTR_EL2_TFP_SHIFT 10
192
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000193/* Hyp Coprocessor Trap Register */
194#define CPTR_EL2_TCPAC (1 << 31)
195#define CPTR_EL2_TTA (1 << 20)
Mario Smarduch33c76a02015-07-16 22:29:37 +0100196#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
Dave Martina7e0ac22016-01-19 16:20:18 +0000197#define CPTR_EL2_DEFAULT 0x000033ff
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000198
199/* Hyp Debug Configuration Register bits */
200#define MDCR_EL2_TDRA (1 << 11)
201#define MDCR_EL2_TDOSA (1 << 10)
202#define MDCR_EL2_TDA (1 << 9)
203#define MDCR_EL2_TDE (1 << 8)
204#define MDCR_EL2_HPME (1 << 7)
205#define MDCR_EL2_TPM (1 << 6)
206#define MDCR_EL2_TPMCR (1 << 5)
207#define MDCR_EL2_HPMN_MASK (0x1F)
208
Mark Rutland6e530312014-11-24 14:05:44 +0000209/* For compatibility with fault code shared with 32-bit */
210#define FSC_FAULT ESR_ELx_FSC_FAULT
Marc Zyngier35307b92015-03-12 18:16:51 +0000211#define FSC_ACCESS ESR_ELx_FSC_ACCESS
Mark Rutland6e530312014-11-24 14:05:44 +0000212#define FSC_PERM ESR_ELx_FSC_PERM
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000213
214/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
Geoff Levand286fb1c2014-10-31 23:06:47 +0000215#define HPFAR_MASK (~UL(0xf))
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000216
Christoffer Dallb5905dc2015-08-30 15:55:22 +0200217#define kvm_arm_exception_type \
218 {0, "IRQ" }, \
219 {1, "TRAP" }
220
221#define ECN(x) { ESR_ELx_EC_##x, #x }
222
223#define kvm_arm_exception_class \
224 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
225 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
226 ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
227 ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
228 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
229 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
230 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
231 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
232
Marc Zyngier32876222015-10-28 14:15:45 +0000233#define CPACR_EL1_FPEN (3 << 20)
234#define CPACR_EL1_TTA (1 << 28)
235
Marc Zyngier0369f6a2012-12-10 10:46:47 +0000236#endif /* __ARM64_KVM_ARM_H__ */