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Doug Thompsoncfe40fd2009-05-04 19:25:34 +02001/*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 *
10 * Originally Written by Thayne Harbaugh
11 *
12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
13 * - K8 CPU Revision D and greater support
14 *
15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
16 * - Module largely rewritten, with new (and hopefully correct)
17 * code for dealing with node and chip select interleaving,
18 * various code cleanup, and bug fixes
19 * - Added support for memory hoisting using DRAM hole address
20 * register
21 *
22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
23 * -K8 Rev (1207) revision support added, required Revision
24 * specific mini-driver code to support Rev F as well as
25 * prior revisions
26 *
27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
28 * -Family 10h revision support added. New PCI Device IDs,
29 * indicating new changes. Actual registers modified
30 * were slight, less than the Rev E to Rev F transition
31 * but changing the PCI Device ID was the proper thing to
32 * do, as it provides for almost automactic family
33 * detection. The mods to Rev F required more family
34 * information detection.
35 *
Borislav Petkov43aff262012-10-29 18:40:09 +010036 * Changes/Fixes by Borislav Petkov <bp@alien8.de>:
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020037 * - misc fixes and code cleanups
38 *
39 * This module is based on the following documents
40 * (available from http://www.amd.com/):
41 *
42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
43 * Opteron Processors
44 * AMD publication #: 26094
45 *` Revision: 3.26
46 *
47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
48 * Processors
49 * AMD publication #: 32559
50 * Revision: 3.00
51 * Issue Date: May 2006
52 *
53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
54 * Processors
55 * AMD publication #: 31116
56 * Revision: 3.00
57 * Issue Date: September 07, 2007
58 *
59 * Sections in the first 2 documents are no longer in sync with each other.
60 * The Family 10h BKDG was totally re-written from scratch with a new
61 * presentation model.
62 * Therefore, comments that refer to a Document section might be off.
63 */
64
65#include <linux/module.h>
66#include <linux/ctype.h>
67#include <linux/init.h>
68#include <linux/pci.h>
69#include <linux/pci_ids.h>
70#include <linux/slab.h>
71#include <linux/mmzone.h>
72#include <linux/edac.h>
Doug Thompsonf9431992009-04-27 19:46:08 +020073#include <asm/msr.h>
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020074#include "edac_core.h"
Borislav Petkov47ca08a2010-09-27 15:30:39 +020075#include "mce_amd.h"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020076
Borislav Petkov24f9a7f2010-10-07 18:29:15 +020077#define amd64_debug(fmt, arg...) \
78 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020079
Borislav Petkov24f9a7f2010-10-07 18:29:15 +020080#define amd64_info(fmt, arg...) \
81 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
82
83#define amd64_notice(fmt, arg...) \
84 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
85
86#define amd64_warn(fmt, arg...) \
87 edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
88
89#define amd64_err(fmt, arg...) \
90 edac_printk(KERN_ERR, "amd64", fmt, ##arg)
91
92#define amd64_mc_warn(mci, fmt, arg...) \
93 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
94
95#define amd64_mc_err(mci, fmt, arg...) \
96 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +020097
98/*
99 * Throughout the comments in this code, the following terms are used:
100 *
101 * SysAddr, DramAddr, and InputAddr
102 *
103 * These terms come directly from the amd64 documentation
104 * (AMD publication #26094). They are defined as follows:
105 *
106 * SysAddr:
107 * This is a physical address generated by a CPU core or a device
108 * doing DMA. If generated by a CPU core, a SysAddr is the result of
109 * a virtual to physical address translation by the CPU core's address
110 * translation mechanism (MMU).
111 *
112 * DramAddr:
113 * A DramAddr is derived from a SysAddr by subtracting an offset that
114 * depends on which node the SysAddr maps to and whether the SysAddr
115 * is within a range affected by memory hoisting. The DRAM Base
116 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
117 * determine which node a SysAddr maps to.
118 *
119 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
120 * is within the range of addresses specified by this register, then
121 * a value x from the DHAR is subtracted from the SysAddr to produce a
122 * DramAddr. Here, x represents the base address for the node that
123 * the SysAddr maps to plus an offset due to memory hoisting. See
124 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
125 * sys_addr_to_dram_addr() below for more information.
126 *
127 * If the SysAddr is not affected by the DHAR then a value y is
128 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
129 * base address for the node that the SysAddr maps to. See section
130 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
131 * information.
132 *
133 * InputAddr:
134 * A DramAddr is translated to an InputAddr before being passed to the
135 * memory controller for the node that the DramAddr is associated
136 * with. The memory controller then maps the InputAddr to a csrow.
137 * If node interleaving is not in use, then the InputAddr has the same
138 * value as the DramAddr. Otherwise, the InputAddr is produced by
139 * discarding the bits used for node interleaving from the DramAddr.
140 * See section 3.4.4 for more information.
141 *
142 * The memory controller for a given node uses its DRAM CS Base and
143 * DRAM CS Mask registers to map an InputAddr to a csrow. See
144 * sections 3.5.4 and 3.5.5 for more information.
145 */
146
Borislav Petkovdf71a052011-01-19 18:15:10 +0100147#define EDAC_AMD64_VERSION "3.4.0"
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200148#define EDAC_MOD_STR "amd64_edac"
149
150/* Extended Model from CPUID, for CPU Revision numbers */
Borislav Petkov1433eb92009-10-21 13:44:36 +0200151#define K8_REV_D 1
152#define K8_REV_E 2
153#define K8_REV_F 4
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200154
155/* Hardware limit on ChipSelect rows per MC and processors per system */
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200156#define NUM_CHIPSELECTS 8
157#define DRAM_RANGES 8
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200158
Borislav Petkovf6d6ae92009-11-03 15:29:26 +0100159#define ON true
160#define OFF false
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200161
162/*
163 * PCI-defined configuration space registers
164 */
Borislav Petkovdf71a052011-01-19 18:15:10 +0100165#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
166#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
Aravind Gopalakrishnana597d2a2014-10-30 12:16:09 +0100167#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
168#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
169#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
170#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
Aravind Gopalakrishnan94c1acf2013-04-17 14:57:13 -0500171#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
172#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
Aravind Gopalakrishnan85a88852014-02-20 10:28:46 -0600173#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
174#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200175
176/*
177 * Function 1 - Address Map
178 */
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200179#define DRAM_BASE_LO 0x40
180#define DRAM_LIMIT_LO 0x44
181
Aravind Gopalakrishnan18b94f62013-08-09 11:54:49 -0500182/*
183 * F15 M30h D18F1x2[1C:00]
184 */
185#define DRAM_CONT_BASE 0x200
186#define DRAM_CONT_LIMIT 0x204
187
188/*
189 * F15 M30h D18F1x2[4C:40]
190 */
191#define DRAM_CONT_HIGH_OFF 0x240
192
Borislav Petkov151fa712011-02-21 19:33:10 +0100193#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
194#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
195#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200196
Borislav Petkovbc21fa52010-11-11 17:29:13 +0100197#define DHAR 0xf0
Borislav Petkovc8e518d2010-12-10 19:49:19 +0100198#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
199#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
200#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200201
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200202 /* NOTE: Extra mask bit vs K8 */
Borislav Petkovc8e518d2010-12-10 19:49:19 +0100203#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200204
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200205#define DCT_CFG_SEL 0x10C
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200206
Borislav Petkovc1ae6832011-03-30 15:42:10 +0200207#define DRAM_LOCAL_NODE_BASE 0x120
Borislav Petkovf08e4572011-03-21 20:45:06 +0100208#define DRAM_LOCAL_NODE_LIM 0x124
209
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200210#define DRAM_BASE_HI 0x140
211#define DRAM_LIMIT_HI 0x144
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200212
213
214/*
215 * Function 2 - DRAM controller
216 */
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100217#define DCSB0 0x40
218#define DCSB1 0x140
219#define DCSB_CS_ENABLE BIT(0)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200220
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100221#define DCSM0 0x60
222#define DCSM1 0x160
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200223
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100224#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200225
Aravind Gopalakrishnana597d2a2014-10-30 12:16:09 +0100226#define DRAM_CONTROL 0x78
227
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200228#define DBAM0 0x80
229#define DBAM1 0x180
230
231/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
Borislav Petkov0a5dfc32012-09-12 18:16:01 +0200232#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200233
234#define DBAM_MAX_VALUE 11
235
Borislav Petkovcb328502010-12-22 14:28:24 +0100236#define DCLR0 0x90
237#define DCLR1 0x190
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200238#define REVE_WIDTH_128 BIT(16)
Borislav Petkov41d8bfa2011-01-18 19:16:08 +0100239#define WIDTH_128 BIT(11)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200240
Borislav Petkovcb328502010-12-22 14:28:24 +0100241#define DCHR0 0x94
242#define DCHR1 0x194
Borislav Petkov1433eb92009-10-21 13:44:36 +0200243#define DDR3_MODE BIT(8)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200244
Borislav Petkov78da1212010-12-22 19:31:45 +0100245#define DCT_SEL_LO 0x110
Borislav Petkov78da1212010-12-22 19:31:45 +0100246#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
247#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
Borislav Petkovcb328502010-12-22 14:28:24 +0100248
Borislav Petkov78da1212010-12-22 19:31:45 +0100249#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
Borislav Petkovcb328502010-12-22 14:28:24 +0100250
Borislav Petkov78da1212010-12-22 19:31:45 +0100251#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
Borislav Petkov78da1212010-12-22 19:31:45 +0100252#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200253
Borislav Petkov95b0ef52011-01-11 22:08:07 +0100254#define SWAP_INTLV_REG 0x10c
255
Borislav Petkov78da1212010-12-22 19:31:45 +0100256#define DCT_SEL_HI 0x114
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200257
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200258/*
259 * Function 3 - Misc Control
260 */
Borislav Petkovc9f4f262010-12-22 19:48:20 +0100261#define NBCTL 0x40
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200262
Borislav Petkova97fa682010-12-23 14:07:18 +0100263#define NBCFG 0x44
264#define NBCFG_CHIPKILL BIT(23)
265#define NBCFG_ECC_ENABLE BIT(22)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200266
Borislav Petkov5980bb92011-01-07 16:26:49 +0100267/* F3x48: NBSL */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200268#define F10_NBSL_EXT_ERR_ECC 0x8
Borislav Petkov5980bb92011-01-07 16:26:49 +0100269#define NBSL_PP_OBS 0x2
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200270
Borislav Petkov5980bb92011-01-07 16:26:49 +0100271#define SCRCTRL 0x58
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200272
273#define F10_ONLINE_SPARE 0xB0
Borislav Petkov614ec9d2011-01-13 18:02:22 +0100274#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
275#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200276
277#define F10_NB_ARRAY_ADDR 0xB8
Borislav Petkov6e71a872012-08-09 18:23:53 +0200278#define F10_NB_ARRAY_DRAM BIT(31)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200279
280/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
Borislav Petkov6e71a872012-08-09 18:23:53 +0200281#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200282
283#define F10_NB_ARRAY_DATA 0xBC
Borislav Petkov66fed2d2012-08-09 18:41:07 +0200284#define F10_NB_ARR_ECC_WR_REQ BIT(17)
Borislav Petkov6e71a872012-08-09 18:23:53 +0200285#define SET_NB_DRAM_INJECTION_WRITE(inj) \
286 (BIT(((inj.word) & 0xF) + 20) | \
Borislav Petkov66fed2d2012-08-09 18:41:07 +0200287 F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
Borislav Petkov6e71a872012-08-09 18:23:53 +0200288#define SET_NB_DRAM_INJECTION_READ(inj) \
289 (BIT(((inj.word) & 0xF) + 20) | \
290 BIT(16) | inj.bit_map)
291
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200292
Borislav Petkov5980bb92011-01-07 16:26:49 +0100293#define NBCAP 0xE8
294#define NBCAP_CHIPKILL BIT(4)
295#define NBCAP_SECDED BIT(3)
296#define NBCAP_DCT_DUAL BIT(0)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200297
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100298#define EXT_NB_MCA_CFG 0x180
299
Borislav Petkovf6d6ae92009-11-03 15:29:26 +0100300/* MSRs */
Borislav Petkov5980bb92011-01-07 16:26:49 +0100301#define MSR_MCGCTL_NBE BIT(4)
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200302
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200303enum amd_families {
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200304 K8_CPUS = 0,
305 F10_CPUS,
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200306 F15_CPUS,
Aravind Gopalakrishnan18b94f62013-08-09 11:54:49 -0500307 F15_M30H_CPUS,
Aravind Gopalakrishnana597d2a2014-10-30 12:16:09 +0100308 F15_M60H_CPUS,
Aravind Gopalakrishnan94c1acf2013-04-17 14:57:13 -0500309 F16_CPUS,
Aravind Gopalakrishnan85a88852014-02-20 10:28:46 -0600310 F16_M30H_CPUS,
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200311 NUM_FAMILIES,
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200312};
313
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200314/* Error injection control structure */
315struct error_injection {
Borislav Petkov66fed2d2012-08-09 18:41:07 +0200316 u32 section;
317 u32 word;
318 u32 bit_map;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200319};
320
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200321/* low and high part of PCI config space regs */
322struct reg_pair {
323 u32 lo, hi;
324};
325
326/*
327 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
328 */
329struct dram_range {
330 struct reg_pair base;
331 struct reg_pair lim;
332};
333
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100334/* A DCT chip selects collection */
335struct chip_select {
336 u32 csbases[NUM_CHIPSELECTS];
337 u8 b_cnt;
338
339 u32 csmasks[NUM_CHIPSELECTS];
340 u8 m_cnt;
341};
342
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200343struct amd64_pvt {
Borislav Petkovb8cfa022010-10-01 19:35:38 +0200344 struct low_ops *ops;
345
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200346 /* pci_device handles which we utilize */
Borislav Petkov8d5b5d92010-10-01 20:11:07 +0200347 struct pci_dev *F1, *F2, *F3;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200348
Daniel J Bluemanc7e53012012-11-30 16:44:20 +0800349 u16 mc_node_id; /* MC index of this MC node */
Aravind Gopalakrishnan18b94f62013-08-09 11:54:49 -0500350 u8 fam; /* CPU family */
Borislav Petkova4b4bed2013-08-10 13:54:48 +0200351 u8 model; /* ... model */
352 u8 stepping; /* ... stepping */
353
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200354 int ext_model; /* extended model value of this node */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200355 int channel_count;
356
357 /* Raw registers */
358 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
359 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
360 u32 dchr0; /* DRAM Configuration High DCT0 reg */
361 u32 dchr1; /* DRAM Configuration High DCT1 reg */
362 u32 nbcap; /* North Bridge Capabilities */
363 u32 nbcfg; /* F10 North Bridge Configuration */
364 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
365 u32 dhar; /* DRAM Hoist reg */
366 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
367 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
368
Borislav Petkov11c75ea2010-11-29 19:49:02 +0100369 /* one for each DCT */
370 struct chip_select csels[2];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200371
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200372 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
373 struct dram_range ranges[DRAM_RANGES];
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200374
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200375 u64 top_mem; /* top of memory below 4GB */
376 u64 top_mem2; /* top of memory above 4GB */
377
Borislav Petkov78da1212010-12-22 19:31:45 +0100378 u32 dct_sel_lo; /* DRAM Controller Select Low */
379 u32 dct_sel_hi; /* DRAM Controller Select High */
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200380 u32 online_spare; /* On-Line spare Reg */
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200381
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100382 /* x4 or x8 syndromes in use */
Borislav Petkova3b7db02011-01-19 20:35:12 +0100383 u8 ecc_sym_sz;
Borislav Petkovad6a32e2010-03-09 12:46:00 +0100384
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200385 /* place to store error injection parameters prior to issue */
386 struct error_injection injection;
Aravind Gopalakrishnana597d2a2014-10-30 12:16:09 +0100387
388 /* cache the dram_type */
389 enum mem_type dram_type;
Borislav Petkovae7bb7c2010-10-14 16:01:30 +0200390};
391
Borislav Petkov33ca0642012-08-30 18:01:36 +0200392enum err_codes {
393 DECODE_OK = 0,
394 ERR_NODE = -1,
395 ERR_CSROW = -2,
396 ERR_CHANNEL = -3,
397};
398
399struct err_info {
400 int err_code;
401 struct mem_ctl_info *src_mci;
402 int csrow;
403 int channel;
404 u16 syndrome;
405 u32 page;
406 u32 offset;
407};
408
Daniel J Bluemanc7e53012012-11-30 16:44:20 +0800409static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200410{
411 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
412
413 if (boot_cpu_data.x86 == 0xf)
414 return addr;
415
416 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
417}
418
Daniel J Bluemanc7e53012012-11-30 16:44:20 +0800419static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
Borislav Petkov7f19bf72010-10-21 18:52:53 +0200420{
421 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
422
423 if (boot_cpu_data.x86 == 0xf)
424 return lim;
425
426 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
427}
428
Borislav Petkovf192c7b2011-01-10 14:24:32 +0100429static inline u16 extract_syndrome(u64 status)
430{
431 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
432}
433
Aravind Gopalakrishnan18b94f62013-08-09 11:54:49 -0500434static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
435{
436 if (pvt->fam == 0x15 && pvt->model >= 0x30)
437 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
438 ((pvt->dct_sel_lo >> 6) & 0x3);
439
440 return ((pvt)->dct_sel_lo >> 6) & 0x3;
441}
Borislav Petkovae7bb7c2010-10-14 16:01:30 +0200442/*
443 * per-node ECC settings descriptor
444 */
445struct ecc_settings {
446 u32 old_nbctl;
447 bool nbctl_valid;
448
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200449 struct flags {
Borislav Petkovd95cf4d2010-02-24 14:49:47 +0100450 unsigned long nb_mce_enable:1;
451 unsigned long nb_ecc_prev:1;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200452 } flags;
453};
454
Doug Thompson7d6034d2009-04-27 20:01:01 +0200455#ifdef CONFIG_EDAC_DEBUG
Mauro Carvalho Chehabc5608752012-03-21 14:00:44 -0300456int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci);
457void amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci);
458
Doug Thompson7d6034d2009-04-27 20:01:01 +0200459#else
Mauro Carvalho Chehabc5608752012-03-21 14:00:44 -0300460static inline int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci)
461{
462 return 0;
463}
464static void inline amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci)
465{
466}
Doug Thompson7d6034d2009-04-27 20:01:01 +0200467#endif
468
469#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
Mauro Carvalho Chehabc5608752012-03-21 14:00:44 -0300470int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci);
471void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci);
Doug Thompson7d6034d2009-04-27 20:01:01 +0200472
Mauro Carvalho Chehabc5608752012-03-21 14:00:44 -0300473#else
474static inline int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci)
475{
476 return 0;
477}
478static inline void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci)
479{
480}
481#endif
Doug Thompson7d6034d2009-04-27 20:01:01 +0200482
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200483/*
484 * Each of the PCI Device IDs types have their own set of hardware accessor
485 * functions and per device encoding/decoding logic.
486 */
487struct low_ops {
Borislav Petkov1433eb92009-10-21 13:44:36 +0200488 int (*early_channel_count) (struct amd64_pvt *pvt);
Borislav Petkovf192c7b2011-01-10 14:24:32 +0100489 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
Borislav Petkov33ca0642012-08-30 18:01:36 +0200490 struct err_info *);
Aravind Gopalakrishnana597d2a2014-10-30 12:16:09 +0100491 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
492 unsigned cs_mode, int cs_mask_nr);
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200493};
494
495struct amd64_family_type {
496 const char *ctl_name;
Borislav Petkov8d5b5d92010-10-01 20:11:07 +0200497 u16 f1_id, f3_id;
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200498 struct low_ops ops;
499};
500
Borislav Petkov66fed2d2012-08-09 18:41:07 +0200501int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
502 u32 *val, const char *func);
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200503int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
504 u32 val, const char *func);
Borislav Petkov6ba5dcd2009-10-13 19:26:55 +0200505
506#define amd64_read_pci_cfg(pdev, offset, val) \
Borislav Petkovb2b0c602010-10-08 18:32:29 +0200507 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
508
509#define amd64_write_pci_cfg(pdev, offset, val) \
510 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
511
Doug Thompsoncfe40fd2009-05-04 19:25:34 +0200512int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
513 u64 *hole_offset, u64 *hole_size);
Mauro Carvalho Chehabc5608752012-03-21 14:00:44 -0300514
515#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
Borislav Petkov66fed2d2012-08-09 18:41:07 +0200516
517/* Injection helpers */
518static inline void disable_caches(void *dummy)
519{
520 write_cr0(read_cr0() | X86_CR0_CD);
521 wbinvd();
522}
523
524static inline void enable_caches(void *dummy)
525{
526 write_cr0(read_cr0() & ~X86_CR0_CD);
527}
Aravind Gopalakrishnan18b94f62013-08-09 11:54:49 -0500528
529static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
530{
531 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
532 u32 tmp;
533 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
534 return (u8) tmp & 0xF;
535 }
536 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
537}
538
539static inline u8 dhar_valid(struct amd64_pvt *pvt)
540{
541 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
542 u32 tmp;
543 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
544 return (tmp >> 1) & BIT(0);
545 }
546 return (pvt)->dhar & BIT(0);
547}
548
549static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
550{
551 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
552 u32 tmp;
553 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
554 return (tmp >> 11) & 0x1FFF;
555 }
556 return (pvt)->dct_sel_lo & 0xFFFFF800;
557}