Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1 | /* |
Tingwei Zhang | 5ac9677 | 2018-01-04 09:54:03 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include "skeleton64.dtsi" |
| 15 | #include <dt-bindings/gpio/gpio.h> |
Kiran Gunda | 0954f39 | 2017-10-16 16:24:55 +0530 | [diff] [blame] | 16 | #include <dt-bindings/spmi/spmi.h> |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Kiran Gunda | 0954f39 | 2017-10-16 16:24:55 +0530 | [diff] [blame] | 18 | #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 19 | #include <dt-bindings/clock/msm-clocks-8953.h> |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 20 | |
| 21 | / { |
Maria Yu | f307a0f | 2017-11-24 16:34:30 +0800 | [diff] [blame] | 22 | model = "Qualcomm Technologies, Inc. MSM8953"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 23 | compatible = "qcom,msm8953"; |
| 24 | qcom,msm-id = <293 0x0>; |
Maria Yu | f307a0f | 2017-11-24 16:34:30 +0800 | [diff] [blame] | 25 | qcom,msm-name = "MSM8953"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 26 | interrupt-parent = <&intc>; |
| 27 | |
| 28 | chosen { |
| 29 | bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1"; |
| 30 | }; |
| 31 | |
Tingwei Zhang | 5ac9677 | 2018-01-04 09:54:03 +0800 | [diff] [blame] | 32 | firmware: firmware { |
| 33 | android { |
| 34 | compatible = "android,firmware"; |
| 35 | fstab { |
| 36 | compatible = "android,fstab"; |
| 37 | vendor { |
| 38 | compatible = "android,vendor"; |
| 39 | dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; |
| 40 | type = "ext4"; |
| 41 | mnt_flags = "ro,barrier=1,discard"; |
| 42 | fsmgr_flags = "wait"; |
| 43 | status = "ok"; |
| 44 | }; |
| 45 | system { |
| 46 | compatible = "android,system"; |
| 47 | dev = "/dev/block/platform/soc/7824900.sdhci/by-name/system"; |
| 48 | type = "ext4"; |
| 49 | mnt_flags = "ro,barrier=1,discard"; |
| 50 | fsmgr_flags = "wait"; |
| 51 | status = "ok"; |
| 52 | }; |
| 53 | |
| 54 | }; |
| 55 | }; |
| 56 | }; |
| 57 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 58 | reserved-memory { |
| 59 | #address-cells = <2>; |
| 60 | #size-cells = <2>; |
| 61 | ranges; |
| 62 | |
| 63 | other_ext_mem: other_ext_region@0 { |
| 64 | compatible = "removed-dma-pool"; |
| 65 | no-map; |
| 66 | reg = <0x0 0x85b00000 0x0 0xd00000>; |
| 67 | }; |
| 68 | |
| 69 | modem_mem: modem_region@0 { |
| 70 | compatible = "removed-dma-pool"; |
| 71 | no-map-fixup; |
| 72 | reg = <0x0 0x86c00000 0x0 0x6a00000>; |
| 73 | }; |
| 74 | |
| 75 | adsp_fw_mem: adsp_fw_region@0 { |
| 76 | compatible = "removed-dma-pool"; |
| 77 | no-map; |
| 78 | reg = <0x0 0x8d600000 0x0 0x1100000>; |
| 79 | }; |
| 80 | |
| 81 | wcnss_fw_mem: wcnss_fw_region@0 { |
| 82 | compatible = "removed-dma-pool"; |
| 83 | no-map; |
| 84 | reg = <0x0 0x8e700000 0x0 0x700000>; |
| 85 | }; |
| 86 | |
| 87 | venus_mem: venus_region@0 { |
| 88 | compatible = "shared-dma-pool"; |
| 89 | reusable; |
| 90 | alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; |
| 91 | alignment = <0 0x400000>; |
| 92 | size = <0 0x0800000>; |
| 93 | }; |
| 94 | |
| 95 | secure_mem: secure_region@0 { |
| 96 | compatible = "shared-dma-pool"; |
| 97 | reusable; |
| 98 | alignment = <0 0x400000>; |
| 99 | size = <0 0x09800000>; |
| 100 | }; |
| 101 | |
| 102 | qseecom_mem: qseecom_region@0 { |
| 103 | compatible = "shared-dma-pool"; |
| 104 | reusable; |
| 105 | alignment = <0 0x400000>; |
| 106 | size = <0 0x1000000>; |
| 107 | }; |
| 108 | |
| 109 | adsp_mem: adsp_region@0 { |
| 110 | compatible = "shared-dma-pool"; |
| 111 | reusable; |
| 112 | size = <0 0x400000>; |
| 113 | }; |
| 114 | |
| 115 | dfps_data_mem: dfps_data_mem@90000000 { |
Sachin Bhayare | e25c1f0 | 2018-01-16 14:04:54 +0530 | [diff] [blame] | 116 | reg = <0 0x90000000 0 0x1000>; |
| 117 | label = "dfps_data_mem"; |
| 118 | status = "disabled"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 119 | }; |
| 120 | |
| 121 | cont_splash_mem: splash_region@0x90001000 { |
| 122 | reg = <0x0 0x90001000 0x0 0x13ff000>; |
| 123 | label = "cont_splash_mem"; |
| 124 | }; |
| 125 | |
| 126 | gpu_mem: gpu_region@0 { |
| 127 | compatible = "shared-dma-pool"; |
| 128 | reusable; |
| 129 | alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; |
| 130 | alignment = <0 0x400000>; |
| 131 | size = <0 0x800000>; |
| 132 | }; |
| 133 | }; |
| 134 | |
| 135 | aliases { |
| 136 | /* smdtty devices */ |
Arun Kumar Neelakantam | 36151aa | 2017-11-02 21:34:33 +0530 | [diff] [blame] | 137 | smd1 = &smdtty_apps_fm; |
| 138 | smd2 = &smdtty_apps_riva_bt_acl; |
| 139 | smd3 = &smdtty_apps_riva_bt_cmd; |
| 140 | smd4 = &smdtty_mbalbridge; |
| 141 | smd5 = &smdtty_apps_riva_ant_cmd; |
| 142 | smd6 = &smdtty_apps_riva_ant_data; |
| 143 | smd7 = &smdtty_data1; |
| 144 | smd8 = &smdtty_data4; |
| 145 | smd11 = &smdtty_data11; |
| 146 | smd21 = &smdtty_data21; |
| 147 | smd36 = &smdtty_loopback; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 148 | sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ |
| 149 | sdhc2 = &sdhc_2; /* SDC2 for SD card */ |
Shrey Vijay | 88eddb5 | 2017-11-30 14:47:52 +0530 | [diff] [blame] | 150 | i2c2 = &i2c_2; |
| 151 | i2c3 = &i2c_3; |
| 152 | i2c5 = &i2c_5; |
| 153 | spi3 = &spi_3; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | soc: soc { }; |
| 157 | |
| 158 | }; |
| 159 | |
| 160 | #include "msm8953-pinctrl.dtsi" |
| 161 | #include "msm8953-cpu.dtsi" |
Raju P.L.S.S.S.N | e0b22c9 | 2017-11-02 13:42:27 +0530 | [diff] [blame] | 162 | #include "msm8953-pm.dtsi" |
Odelu Kukatla | 1a81104 | 2017-10-29 17:26:44 +0530 | [diff] [blame] | 163 | #include "msm8953-bus.dtsi" |
Mukesh Ojha | e07d80e | 2017-11-28 20:22:44 +0530 | [diff] [blame] | 164 | #include "msm8953-coresight.dtsi" |
Charan Teja Reddy | 6f1f829 | 2017-12-26 20:54:26 +0530 | [diff] [blame] | 165 | #include "msm8953-ion.dtsi" |
Charan Teja Reddy | f20a02f | 2017-10-20 11:12:39 +0530 | [diff] [blame] | 166 | #include "msm-arm-smmu-8953.dtsi" |
Sunil Khatri | fc03ac6 | 2018-01-03 12:31:08 +0530 | [diff] [blame] | 167 | #include "msm8953-gpu.dtsi" |
Sachin Bhayare | e25c1f0 | 2018-01-16 14:04:54 +0530 | [diff] [blame] | 168 | #include "msm8953-mdss.dtsi" |
| 169 | #include "msm8953-mdss-pll.dtsi" |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 170 | |
| 171 | &soc { |
| 172 | #address-cells = <1>; |
| 173 | #size-cells = <1>; |
| 174 | ranges = <0 0 0 0xffffffff>; |
| 175 | compatible = "simple-bus"; |
| 176 | |
Mukesh Ojha | e07d80e | 2017-11-28 20:22:44 +0530 | [diff] [blame] | 177 | dcc: dcc@b3000 { |
| 178 | compatible = "qcom,dcc"; |
| 179 | reg = <0xb3000 0x1000>, |
| 180 | <0xb4000 0x800>; |
| 181 | reg-names = "dcc-base", "dcc-ram-base"; |
| 182 | |
| 183 | clocks = <&clock_gcc clk_gcc_dcc_clk>; |
| 184 | clock-names = "apb_pclk"; |
| 185 | qcom,save-reg; |
| 186 | }; |
| 187 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 188 | apc_apm: apm@b111000 { |
| 189 | compatible = "qcom,msm8953-apm"; |
| 190 | reg = <0xb111000 0x1000>; |
| 191 | reg-names = "pm-apcc-glb"; |
| 192 | qcom,apm-post-halt-delay = <0x2>; |
| 193 | qcom,apm-halt-clk-delay = <0x11>; |
| 194 | qcom,apm-resume-clk-delay = <0x10>; |
| 195 | qcom,apm-sel-switch-delay = <0x01>; |
| 196 | }; |
| 197 | |
| 198 | intc: interrupt-controller@b000000 { |
| 199 | compatible = "qcom,msm-qgic2"; |
| 200 | interrupt-controller; |
| 201 | #interrupt-cells = <3>; |
| 202 | reg = <0x0b000000 0x1000>, |
| 203 | <0x0b002000 0x1000>; |
| 204 | }; |
| 205 | |
| 206 | qcom,msm-gladiator@b1c0000 { |
| 207 | compatible = "qcom,msm-gladiator"; |
| 208 | reg = <0x0b1c0000 0x4000>; |
| 209 | reg-names = "gladiator_base"; |
| 210 | interrupts = <0 22 0>; |
| 211 | }; |
| 212 | |
| 213 | timer { |
| 214 | compatible = "arm,armv8-timer"; |
| 215 | interrupts = <1 2 0xff08>, |
| 216 | <1 3 0xff08>, |
| 217 | <1 4 0xff08>, |
| 218 | <1 1 0xff08>; |
| 219 | clock-frequency = <19200000>; |
| 220 | }; |
| 221 | |
| 222 | timer@b120000 { |
| 223 | #address-cells = <1>; |
| 224 | #size-cells = <1>; |
| 225 | ranges; |
| 226 | compatible = "arm,armv7-timer-mem"; |
| 227 | reg = <0xb120000 0x1000>; |
| 228 | clock-frequency = <19200000>; |
| 229 | |
| 230 | frame@b121000 { |
| 231 | frame-number = <0>; |
| 232 | interrupts = <0 8 0x4>, |
| 233 | <0 7 0x4>; |
| 234 | reg = <0xb121000 0x1000>, |
| 235 | <0xb122000 0x1000>; |
| 236 | }; |
| 237 | |
| 238 | frame@b123000 { |
| 239 | frame-number = <1>; |
| 240 | interrupts = <0 9 0x4>; |
| 241 | reg = <0xb123000 0x1000>; |
| 242 | status = "disabled"; |
| 243 | }; |
| 244 | |
| 245 | frame@b124000 { |
| 246 | frame-number = <2>; |
| 247 | interrupts = <0 10 0x4>; |
| 248 | reg = <0xb124000 0x1000>; |
| 249 | status = "disabled"; |
| 250 | }; |
| 251 | |
| 252 | frame@b125000 { |
| 253 | frame-number = <3>; |
| 254 | interrupts = <0 11 0x4>; |
| 255 | reg = <0xb125000 0x1000>; |
| 256 | status = "disabled"; |
| 257 | }; |
| 258 | |
| 259 | frame@b126000 { |
| 260 | frame-number = <4>; |
| 261 | interrupts = <0 12 0x4>; |
| 262 | reg = <0xb126000 0x1000>; |
| 263 | status = "disabled"; |
| 264 | }; |
| 265 | |
| 266 | frame@b127000 { |
| 267 | frame-number = <5>; |
| 268 | interrupts = <0 13 0x4>; |
| 269 | reg = <0xb127000 0x1000>; |
| 270 | status = "disabled"; |
| 271 | }; |
| 272 | |
| 273 | frame@b128000 { |
| 274 | frame-number = <6>; |
| 275 | interrupts = <0 14 0x4>; |
| 276 | reg = <0xb128000 0x1000>; |
| 277 | status = "disabled"; |
| 278 | }; |
| 279 | }; |
| 280 | qcom,rmtfs_sharedmem@00000000 { |
| 281 | compatible = "qcom,sharedmem-uio"; |
| 282 | reg = <0x00000000 0x00180000>; |
| 283 | reg-names = "rmtfs"; |
| 284 | qcom,client-id = <0x00000001>; |
| 285 | }; |
| 286 | |
| 287 | restart@4ab000 { |
| 288 | compatible = "qcom,pshold"; |
| 289 | reg = <0x4ab000 0x4>, |
| 290 | <0x193d100 0x4>; |
| 291 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 292 | }; |
| 293 | |
| 294 | qcom,mpm2-sleep-counter@4a3000 { |
| 295 | compatible = "qcom,mpm2-sleep-counter"; |
| 296 | reg = <0x4a3000 0x1000>; |
| 297 | clock-frequency = <32768>; |
| 298 | }; |
| 299 | |
| 300 | cpu-pmu { |
| 301 | compatible = "arm,armv8-pmuv3"; |
| 302 | interrupts = <1 7 0xff00>; |
| 303 | }; |
| 304 | |
| 305 | qcom,sps { |
| 306 | compatible = "qcom,msm_sps_4k"; |
| 307 | qcom,pipe-attr-ee; |
| 308 | }; |
| 309 | |
Manaf Meethalavalappu Pallikunhi | 4eb2b27 | 2018-01-02 17:29:37 +0530 | [diff] [blame] | 310 | thermal_zones: thermal-zones {}; |
Ashok Jammigumpula | db43f57 | 2017-12-06 18:05:57 +0530 | [diff] [blame] | 311 | |
| 312 | tsens0: tsens@4a8000 { |
| 313 | compatible = "qcom,msm8953-tsens"; |
| 314 | reg = <0x4a8000 0x1000>, |
| 315 | <0x4a9000 0x1000>; |
| 316 | reg-names = "tsens_srot_physical", |
| 317 | "tsens_tm_physical"; |
| 318 | interrupts = <0 184 0>, <0 314 0>; |
| 319 | interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| 320 | #thermal-sensor-cells = <1>; |
| 321 | }; |
| 322 | |
mohamed sunfeer | 2bfd8c8 | 2017-11-30 13:08:36 +0530 | [diff] [blame] | 323 | qcom_seecom: qseecom@85b00000 { |
| 324 | compatible = "qcom,qseecom"; |
| 325 | reg = <0x85b00000 0x800000>; |
| 326 | reg-names = "secapp-region"; |
| 327 | qcom,hlos-num-ce-hw-instances = <1>; |
| 328 | qcom,hlos-ce-hw-instance = <0>; |
| 329 | qcom,qsee-ce-hw-instance = <0>; |
| 330 | qcom,disk-encrypt-pipe-pair = <2>; |
| 331 | qcom,support-fde; |
| 332 | qcom,msm-bus,name = "qseecom-noc"; |
| 333 | qcom,msm-bus,num-cases = <4>; |
| 334 | qcom,msm-bus,num-paths = <1>; |
| 335 | qcom,support-bus-scaling; |
| 336 | qcom,msm-bus,vectors-KBps = |
| 337 | <55 512 0 0>, |
| 338 | <55 512 0 0>, |
| 339 | <55 512 120000 1200000>, |
| 340 | <55 512 393600 3936000>; |
| 341 | clocks = <&clock_gcc clk_crypto_clk_src>, |
| 342 | <&clock_gcc clk_gcc_crypto_clk>, |
| 343 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 344 | <&clock_gcc clk_gcc_crypto_axi_clk>; |
| 345 | clock-names = "core_clk_src", "core_clk", |
| 346 | "iface_clk", "bus_clk"; |
| 347 | qcom,ce-opp-freq = <100000000>; |
Brahmaji K | 2219183 | 2017-12-27 13:42:35 +0530 | [diff] [blame] | 348 | status = "okay"; |
mohamed sunfeer | 2bfd8c8 | 2017-11-30 13:08:36 +0530 | [diff] [blame] | 349 | }; |
| 350 | |
mohamed sunfeer | d9761e6 | 2017-11-30 13:33:02 +0530 | [diff] [blame] | 351 | qcom_tzlog: tz-log@08600720 { |
| 352 | compatible = "qcom,tz-log"; |
| 353 | reg = <0x08600720 0x2000>; |
Brahmaji K | 2219183 | 2017-12-27 13:42:35 +0530 | [diff] [blame] | 354 | status = "okay"; |
mohamed sunfeer | d9761e6 | 2017-11-30 13:33:02 +0530 | [diff] [blame] | 355 | }; |
| 356 | |
mohamed sunfeer | 0d62322 | 2017-11-30 13:51:20 +0530 | [diff] [blame] | 357 | qcom_rng: qrng@e3000 { |
| 358 | compatible = "qcom,msm-rng"; |
| 359 | reg = <0xe3000 0x1000>; |
| 360 | qcom,msm-rng-iface-clk; |
| 361 | qcom,no-qrng-config; |
| 362 | qcom,msm-bus,name = "msm-rng-noc"; |
| 363 | qcom,msm-bus,num-cases = <2>; |
| 364 | qcom,msm-bus,num-paths = <1>; |
| 365 | qcom,msm-bus,vectors-KBps = |
| 366 | <1 618 0 0>, /* No vote */ |
| 367 | <1 618 0 800>; /* 100 MB/s */ |
| 368 | clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; |
| 369 | clock-names = "iface_clk"; |
Brahmaji K | 2219183 | 2017-12-27 13:42:35 +0530 | [diff] [blame] | 370 | status = "okay"; |
mohamed sunfeer | 0d62322 | 2017-11-30 13:51:20 +0530 | [diff] [blame] | 371 | }; |
| 372 | |
mohamed sunfeer | 1f6a4e0 | 2017-11-30 14:07:28 +0530 | [diff] [blame] | 373 | qcom_crypto: qcrypto@720000 { |
| 374 | compatible = "qcom,qcrypto"; |
| 375 | reg = <0x720000 0x20000>, |
| 376 | <0x704000 0x20000>; |
| 377 | reg-names = "crypto-base","crypto-bam-base"; |
| 378 | interrupts = <0 207 0>; |
| 379 | qcom,bam-pipe-pair = <2>; |
| 380 | qcom,ce-hw-instance = <0>; |
| 381 | qcom,ce-device = <0>; |
| 382 | qcom,ce-hw-shared; |
| 383 | qcom,clk-mgmt-sus-res; |
| 384 | qcom,msm-bus,name = "qcrypto-noc"; |
| 385 | qcom,msm-bus,num-cases = <2>; |
| 386 | qcom,msm-bus,num-paths = <1>; |
| 387 | qcom,msm-bus,vectors-KBps = |
| 388 | <55 512 0 0>, |
| 389 | <55 512 393600 393600>; |
| 390 | clocks = <&clock_gcc clk_crypto_clk_src>, |
| 391 | <&clock_gcc clk_gcc_crypto_clk>, |
| 392 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 393 | <&clock_gcc clk_gcc_crypto_axi_clk>; |
| 394 | clock-names = "core_clk_src", "core_clk", |
| 395 | "iface_clk", "bus_clk"; |
| 396 | qcom,use-sw-aes-cbc-ecb-ctr-algo; |
| 397 | qcom,use-sw-aes-xts-algo; |
| 398 | qcom,use-sw-aes-ccm-algo; |
| 399 | qcom,use-sw-ahash-algo; |
| 400 | qcom,use-sw-hmac-algo; |
| 401 | qcom,use-sw-aead-algo; |
| 402 | qcom,ce-opp-freq = <100000000>; |
Brahmaji K | 2219183 | 2017-12-27 13:42:35 +0530 | [diff] [blame] | 403 | status = "okay"; |
mohamed sunfeer | 1f6a4e0 | 2017-11-30 14:07:28 +0530 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | qcom_cedev: qcedev@720000 { |
| 407 | compatible = "qcom,qcedev"; |
| 408 | reg = <0x720000 0x20000>, |
| 409 | <0x704000 0x20000>; |
| 410 | reg-names = "crypto-base","crypto-bam-base"; |
| 411 | interrupts = <0 207 0>; |
| 412 | qcom,bam-pipe-pair = <1>; |
| 413 | qcom,ce-hw-instance = <0>; |
| 414 | qcom,ce-device = <0>; |
| 415 | qcom,ce-hw-shared; |
| 416 | qcom,msm-bus,name = "qcedev-noc"; |
| 417 | qcom,msm-bus,num-cases = <2>; |
| 418 | qcom,msm-bus,num-paths = <1>; |
| 419 | qcom,msm-bus,vectors-KBps = |
| 420 | <55 512 0 0>, |
| 421 | <55 512 393600 393600>; |
| 422 | clocks = <&clock_gcc clk_crypto_clk_src>, |
| 423 | <&clock_gcc clk_gcc_crypto_clk>, |
| 424 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 425 | <&clock_gcc clk_gcc_crypto_axi_clk>; |
| 426 | clock-names = "core_clk_src", "core_clk", |
| 427 | "iface_clk", "bus_clk"; |
| 428 | qcom,ce-opp-freq = <100000000>; |
Brahmaji K | 2219183 | 2017-12-27 13:42:35 +0530 | [diff] [blame] | 429 | status = "okay"; |
mohamed sunfeer | 1f6a4e0 | 2017-11-30 14:07:28 +0530 | [diff] [blame] | 430 | }; |
| 431 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 432 | blsp1_uart0: serial@78af000 { |
| 433 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 434 | reg = <0x78af000 0x200>; |
| 435 | interrupts = <0 107 0>; |
Maria Yu | af0e925 | 2017-11-30 19:58:44 +0800 | [diff] [blame] | 436 | clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, |
| 437 | <&clock_gcc clk_gcc_blsp1_ahb_clk>; |
| 438 | clock-names = "core", "iface"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 439 | status = "disabled"; |
| 440 | }; |
| 441 | |
Shrey Vijay | 88eddb5 | 2017-11-30 14:47:52 +0530 | [diff] [blame] | 442 | blsp1_uart1: uart@78b0000 { |
| 443 | compatible = "qcom,msm-hsuart-v14"; |
| 444 | reg = <0x78b0000 0x200>, |
| 445 | <0x7884000 0x1f000>; |
| 446 | reg-names = "core_mem", "bam_mem"; |
| 447 | |
| 448 | interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; |
| 449 | #address-cells = <0>; |
| 450 | interrupt-parent = <&blsp1_uart1>; |
| 451 | interrupts = <0 1 2>; |
| 452 | #interrupt-cells = <1>; |
| 453 | interrupt-map-mask = <0xffffffff>; |
| 454 | interrupt-map = <0 &intc 0 108 0 |
| 455 | 1 &intc 0 238 0 |
| 456 | 2 &tlmm 13 0>; |
| 457 | |
| 458 | qcom,inject-rx-on-wakeup; |
| 459 | qcom,rx-char-to-inject = <0xFD>; |
| 460 | qcom,master-id = <86>; |
| 461 | clock-names = "core_clk", "iface_clk"; |
| 462 | clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, |
| 463 | <&clock_gcc clk_gcc_blsp1_ahb_clk>; |
| 464 | pinctrl-names = "sleep", "default"; |
| 465 | pinctrl-0 = <&hsuart_sleep>; |
| 466 | pinctrl-1 = <&hsuart_active>; |
| 467 | qcom,bam-tx-ep-pipe-index = <2>; |
| 468 | qcom,bam-rx-ep-pipe-index = <3>; |
| 469 | qcom,msm-bus,name = "blsp1_uart1"; |
| 470 | qcom,msm-bus,num-cases = <2>; |
| 471 | qcom,msm-bus,num-paths = <1>; |
| 472 | qcom,msm-bus,vectors-KBps = |
| 473 | <86 512 0 0>, |
| 474 | <86 512 500 800>; |
| 475 | status = "disabled"; |
| 476 | }; |
| 477 | |
| 478 | blsp2_uart0: uart@7aef000 { |
| 479 | compatible = "qcom,msm-hsuart-v14"; |
| 480 | reg = <0x7aef000 0x200>, |
| 481 | <0x7ac4000 0x1f000>; |
| 482 | reg-names = "core_mem", "bam_mem"; |
| 483 | |
| 484 | interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; |
| 485 | #address-cells = <0>; |
| 486 | interrupt-parent = <&blsp2_uart0>; |
| 487 | interrupts = <0 1 2>; |
| 488 | #interrupt-cells = <1>; |
| 489 | interrupt-map-mask = <0xffffffff>; |
| 490 | interrupt-map = <0 &intc 0 306 0 |
| 491 | 1 &intc 0 239 0 |
| 492 | 2 &tlmm 17 0>; |
| 493 | |
| 494 | qcom,inject-rx-on-wakeup; |
| 495 | qcom,rx-char-to-inject = <0xFD>; |
| 496 | qcom,master-id = <84>; |
| 497 | clock-names = "core_clk", "iface_clk"; |
| 498 | clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>, |
| 499 | <&clock_gcc clk_gcc_blsp2_ahb_clk>; |
| 500 | pinctrl-names = "sleep", "default"; |
| 501 | pinctrl-0 = <&blsp2_uart0_sleep>; |
| 502 | pinctrl-1 = <&blsp2_uart0_active>; |
| 503 | qcom,bam-tx-ep-pipe-index = <0>; |
| 504 | qcom,bam-rx-ep-pipe-index = <1>; |
| 505 | qcom,msm-bus,name = "blsp2_uart0"; |
| 506 | qcom,msm-bus,num-cases = <2>; |
| 507 | qcom,msm-bus,num-paths = <1>; |
| 508 | qcom,msm-bus,vectors-KBps = |
| 509 | <84 512 0 0>, |
| 510 | <84 512 500 800>; |
| 511 | status = "disabled"; |
| 512 | }; |
| 513 | |
Maria Yu | f16c160 | 2017-12-22 13:05:17 +0800 | [diff] [blame] | 514 | blsp1_serial1: serial@78b0000 { |
| 515 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| 516 | reg = <0x78b0000 0x200>; |
| 517 | interrupts = <0 108 0>; |
| 518 | clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, |
| 519 | <&clock_gcc clk_gcc_blsp1_ahb_clk>; |
| 520 | clock-names = "core", "iface"; |
| 521 | status = "disabled"; |
| 522 | }; |
| 523 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 524 | dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ |
| 525 | #dma-cells = <4>; |
| 526 | compatible = "qcom,sps-dma"; |
| 527 | reg = <0x7884000 0x1f000>; |
| 528 | interrupts = <0 238 0>; |
| 529 | qcom,summing-threshold = <10>; |
| 530 | }; |
| 531 | |
| 532 | dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */ |
| 533 | #dma-cells = <4>; |
| 534 | compatible = "qcom,sps-dma"; |
| 535 | reg = <0x7ac4000 0x1f000>; |
| 536 | interrupts = <0 239 0>; |
| 537 | qcom,summing-threshold = <10>; |
| 538 | }; |
| 539 | |
Shrey Vijay | 88eddb5 | 2017-11-30 14:47:52 +0530 | [diff] [blame] | 540 | spi_3: spi@78b7000 { /* BLSP1 QUP3 */ |
| 541 | compatible = "qcom,spi-qup-v2"; |
| 542 | #address-cells = <1>; |
| 543 | #size-cells = <0>; |
| 544 | reg-names = "spi_physical", "spi_bam_physical"; |
| 545 | reg = <0x78b7000 0x600>, |
| 546 | <0x7884000 0x1f000>; |
| 547 | interrupt-names = "spi_irq", "spi_bam_irq"; |
| 548 | interrupts = <0 97 0>, <0 238 0>; |
| 549 | spi-max-frequency = <19200000>; |
| 550 | pinctrl-names = "spi_default", "spi_sleep"; |
| 551 | pinctrl-0 = <&spi3_default &spi3_cs0_active>; |
| 552 | pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>; |
| 553 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 554 | <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>; |
| 555 | clock-names = "iface_clk", "core_clk"; |
| 556 | qcom,infinite-mode = <0>; |
| 557 | qcom,use-bam; |
| 558 | qcom,use-pinctrl; |
| 559 | qcom,ver-reg-exists; |
| 560 | qcom,bam-consumer-pipe-index = <8>; |
| 561 | qcom,bam-producer-pipe-index = <9>; |
| 562 | qcom,master-id = <86>; |
| 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
| 566 | i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ |
| 567 | compatible = "qcom,i2c-msm-v2"; |
| 568 | #address-cells = <1>; |
| 569 | #size-cells = <0>; |
| 570 | reg-names = "qup_phys_addr"; |
| 571 | reg = <0x78b6000 0x600>; |
| 572 | interrupt-names = "qup_irq"; |
| 573 | interrupts = <0 96 0>; |
| 574 | qcom,clk-freq-out = <400000>; |
| 575 | qcom,clk-freq-in = <19200000>; |
| 576 | clock-names = "iface_clk", "core_clk"; |
| 577 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 578 | <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>; |
| 579 | |
| 580 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 581 | pinctrl-0 = <&i2c_2_active>; |
| 582 | pinctrl-1 = <&i2c_2_sleep>; |
| 583 | qcom,noise-rjct-scl = <0>; |
| 584 | qcom,noise-rjct-sda = <0>; |
| 585 | qcom,master-id = <86>; |
| 586 | dmas = <&dma_blsp1 6 64 0x20000020 0x20>, |
| 587 | <&dma_blsp1 7 32 0x20000020 0x20>; |
| 588 | dma-names = "tx", "rx"; |
| 589 | status = "disabled"; |
| 590 | }; |
| 591 | |
| 592 | i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ |
| 593 | compatible = "qcom,i2c-msm-v2"; |
| 594 | #address-cells = <1>; |
| 595 | #size-cells = <0>; |
| 596 | reg-names = "qup_phys_addr"; |
| 597 | reg = <0x78b7000 0x600>; |
| 598 | interrupt-names = "qup_irq"; |
| 599 | interrupts = <0 97 0>; |
| 600 | qcom,clk-freq-out = <400000>; |
| 601 | qcom,clk-freq-in = <19200000>; |
| 602 | clock-names = "iface_clk", "core_clk"; |
| 603 | clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, |
| 604 | <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>; |
| 605 | |
| 606 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 607 | pinctrl-0 = <&i2c_3_active>; |
| 608 | pinctrl-1 = <&i2c_3_sleep>; |
| 609 | qcom,noise-rjct-scl = <0>; |
| 610 | qcom,noise-rjct-sda = <0>; |
| 611 | qcom,master-id = <86>; |
| 612 | dmas = <&dma_blsp1 8 64 0x20000020 0x20>, |
| 613 | <&dma_blsp1 9 32 0x20000020 0x20>; |
| 614 | dma-names = "tx", "rx"; |
| 615 | status = "disabled"; |
| 616 | }; |
| 617 | |
| 618 | i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */ |
| 619 | compatible = "qcom,i2c-msm-v2"; |
| 620 | #address-cells = <1>; |
| 621 | #size-cells = <0>; |
| 622 | reg-names = "qup_phys_addr"; |
| 623 | reg = <0x7af5000 0x600>; |
| 624 | interrupt-names = "qup_irq"; |
| 625 | interrupts = <0 299 0>; |
| 626 | qcom,clk-freq-out = <400000>; |
| 627 | qcom,clk-freq-in = <19200000>; |
| 628 | clock-names = "iface_clk", "core_clk"; |
| 629 | clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, |
| 630 | <&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>; |
| 631 | |
| 632 | pinctrl-names = "i2c_active", "i2c_sleep"; |
| 633 | pinctrl-0 = <&i2c_5_active>; |
| 634 | pinctrl-1 = <&i2c_5_sleep>; |
| 635 | qcom,noise-rjct-scl = <0>; |
| 636 | qcom,noise-rjct-sda = <0>; |
| 637 | qcom,master-id = <84>; |
| 638 | dmas = <&dma_blsp2 4 64 0x20000020 0x20>, |
| 639 | <&dma_blsp2 5 32 0x20000020 0x20>; |
| 640 | dma-names = "tx", "rx"; |
| 641 | status = "disabled"; |
| 642 | }; |
| 643 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 644 | slim_msm: slim@c140000{ |
| 645 | cell-index = <1>; |
| 646 | compatible = "qcom,slim-ngd"; |
| 647 | reg = <0xc140000 0x2c000>, |
| 648 | <0xc104000 0x2a000>; |
| 649 | reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| 650 | interrupts = <0 163 0>, <0 180 0>; |
| 651 | interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| 652 | qcom,apps-ch-pipes = <0x600000>; |
| 653 | qcom,ea-pc = <0x200>; |
| 654 | status = "disabled"; |
| 655 | }; |
| 656 | |
Sachin Bhayare | e25c1f0 | 2018-01-16 14:04:54 +0530 | [diff] [blame] | 657 | clock_gcc_mdss: qcom,gcc-mdss@1800000 { |
| 658 | compatible = "qcom,gcc-mdss-8953"; |
| 659 | reg = <0x1800000 0x80000>; |
| 660 | reg-names = "cc_base"; |
| 661 | clock-names = "pclk0_src", "pclk1_src", |
| 662 | "byte0_src", "byte1_src"; |
| 663 | clocks = <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>, |
| 664 | <&mdss_dsi1_pll clk_dsi1pll_pixel_clk_mux>, |
| 665 | <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>, |
| 666 | <&mdss_dsi1_pll clk_dsi1pll_byte_clk_mux>; |
| 667 | #clock-cells = <1>; |
| 668 | }; |
| 669 | |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 670 | clock_gcc: qcom,gcc@1800000 { |
| 671 | compatible = "qcom,gcc-8953"; |
| 672 | reg = <0x1800000 0x80000>, |
| 673 | <0x00a4124 0x08>; |
| 674 | reg-names = "cc_base", "efuse"; |
| 675 | vdd_dig-supply = <&pm8953_s2_level>; |
| 676 | #clock-cells = <1>; |
| 677 | #reset-cells = <1>; |
| 678 | }; |
| 679 | |
| 680 | clock_debug: qcom,cc-debug@1874000 { |
| 681 | compatible = "qcom,cc-debug-8953"; |
| 682 | reg = <0x1874000 0x4>; |
| 683 | reg-names = "cc_base"; |
| 684 | clocks = <&clock_cpu clk_cpu_debug_pri_mux>; |
| 685 | clock-names = "debug_cpu_clk"; |
| 686 | #clock-cells = <1>; |
| 687 | }; |
| 688 | |
| 689 | clock_gcc_gfx: qcom,gcc-gfx@1800000 { |
| 690 | compatible = "qcom,gcc-gfx-8953"; |
| 691 | reg = <0x1800000 0x80000>; |
| 692 | reg-names = "cc_base"; |
| 693 | vdd_gfx-supply = <&gfx_vreg_corner>; |
Amit Nischal | 6b27af6 | 2018-01-17 18:01:18 +0530 | [diff] [blame] | 694 | clocks = <&clock_gcc clk_xo_clk_src>; |
| 695 | clock-names = "xo"; |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 696 | qcom,gfxfreq-corner = |
| 697 | < 0 0 >, |
| 698 | < 133330000 1 >, /* Min SVS */ |
| 699 | < 216000000 2 >, /* Low SVS */ |
| 700 | < 320000000 3 >, /* SVS */ |
| 701 | < 400000000 4 >, /* SVS Plus */ |
| 702 | < 510000000 5 >, /* NOM */ |
| 703 | < 560000000 6 >, /* Nom Plus */ |
| 704 | < 650000000 7 >; /* Turbo */ |
| 705 | #clock-cells = <1>; |
| 706 | }; |
| 707 | |
| 708 | clock_cpu: qcom,cpu-clock-8953@b116000 { |
| 709 | compatible = "qcom,cpu-clock-8953"; |
| 710 | reg = <0xb114000 0x68>, |
| 711 | <0xb014000 0x68>, |
| 712 | <0xb116000 0x400>, |
| 713 | <0xb111050 0x08>, |
| 714 | <0xb011050 0x08>, |
| 715 | <0xb1d1050 0x08>, |
| 716 | <0x00a4124 0x08>; |
| 717 | reg-names = "rcgwr-c0-base", "rcgwr-c1-base", |
| 718 | "c0-pll", "c0-mux", "c1-mux", |
| 719 | "cci-mux", "efuse"; |
| 720 | vdd-mx-supply = <&pm8953_s7_level_ao>; |
| 721 | vdd-cl-supply = <&apc_vreg>; |
| 722 | clocks = <&clock_gcc clk_xo_a_clk_src>; |
| 723 | clock-names = "xo_a"; |
| 724 | qcom,num-clusters = <2>; |
| 725 | qcom,speed0-bin-v0-cl = |
| 726 | < 0 0>, |
| 727 | < 652800000 1>, |
| 728 | < 1036800000 2>, |
| 729 | < 1401600000 3>, |
| 730 | < 1689600000 4>, |
| 731 | < 1804800000 5>, |
| 732 | < 1958400000 6>, |
| 733 | < 2016000000 7>; |
| 734 | qcom,speed0-bin-v0-cci = |
| 735 | < 0 0>, |
| 736 | < 261120000 1>, |
| 737 | < 414720000 2>, |
| 738 | < 560640000 3>, |
| 739 | < 675840000 4>, |
| 740 | < 721920000 5>, |
| 741 | < 783360000 6>, |
| 742 | < 806400000 7>; |
| 743 | qcom,speed2-bin-v0-cl = |
| 744 | < 0 0>, |
| 745 | < 652800000 1>, |
| 746 | < 1036800000 2>, |
| 747 | < 1401600000 3>, |
| 748 | < 1689600000 4>, |
| 749 | < 1804800000 5>, |
| 750 | < 1958400000 6>, |
| 751 | < 2016000000 7>; |
| 752 | qcom,speed2-bin-v0-cci = |
| 753 | < 0 0>, |
| 754 | < 261120000 1>, |
| 755 | < 414720000 2>, |
| 756 | < 560640000 3>, |
| 757 | < 675840000 4>, |
| 758 | < 721920000 5>, |
| 759 | < 783360000 6>, |
| 760 | < 806400000 7>; |
| 761 | qcom,speed7-bin-v0-cl = |
| 762 | < 0 0>, |
| 763 | < 652800000 1>, |
| 764 | < 1036800000 2>, |
| 765 | < 1401600000 3>, |
| 766 | < 1689600000 4>, |
| 767 | < 1804800000 5>, |
| 768 | < 1958400000 6>, |
| 769 | < 2016000000 7>, |
| 770 | < 2150400000 8>, |
| 771 | < 2208000000 9>; |
| 772 | qcom,speed7-bin-v0-cci = |
| 773 | < 0 0>, |
| 774 | < 261120000 1>, |
| 775 | < 414720000 2>, |
| 776 | < 560640000 3>, |
| 777 | < 675840000 4>, |
| 778 | < 721920000 5>, |
| 779 | < 783360000 6>, |
| 780 | < 806400000 7>, |
| 781 | < 860160000 8>, |
| 782 | < 883200000 9>; |
| 783 | qcom,speed6-bin-v0-cl = |
| 784 | < 0 0>, |
| 785 | < 652800000 1>, |
| 786 | < 1036800000 2>, |
| 787 | < 1401600000 3>, |
| 788 | < 1689600000 4>, |
| 789 | < 1804800000 5>; |
| 790 | qcom,speed6-bin-v0-cci = |
| 791 | < 0 0>, |
| 792 | < 261120000 1>, |
| 793 | < 414720000 2>, |
| 794 | < 560640000 3>, |
| 795 | < 675840000 4>, |
| 796 | < 721920000 5>; |
| 797 | #clock-cells = <1>; |
Maria Yu | b90c548 | 2017-12-01 13:28:56 +0800 | [diff] [blame] | 798 | }; |
| 799 | |
| 800 | msm_cpufreq: qcom,msm-cpufreq { |
| 801 | compatible = "qcom,msm-cpufreq"; |
| 802 | clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk", |
| 803 | "cpu3_clk", "cpu4_clk", "cpu5_clk", |
| 804 | "cpu6_clk", "cpu7_clk"; |
| 805 | clocks = <&clock_cpu clk_cci_clk>, |
| 806 | <&clock_cpu clk_a53_pwr_clk>, |
| 807 | <&clock_cpu clk_a53_pwr_clk>, |
| 808 | <&clock_cpu clk_a53_pwr_clk>, |
| 809 | <&clock_cpu clk_a53_pwr_clk>, |
| 810 | <&clock_cpu clk_a53_pwr_clk>, |
| 811 | <&clock_cpu clk_a53_pwr_clk>, |
| 812 | <&clock_cpu clk_a53_pwr_clk>, |
| 813 | <&clock_cpu clk_a53_pwr_clk>; |
| 814 | |
| 815 | qcom,cpufreq-table = |
| 816 | < 652800 >, |
| 817 | < 1036800 >, |
| 818 | < 1401600 >, |
| 819 | < 1689600 >, |
| 820 | < 1804800 >, |
| 821 | < 1958400 >, |
| 822 | < 2016000 >, |
| 823 | < 2150400 >, |
| 824 | < 2208000 >; |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 825 | }; |
| 826 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 827 | cpubw: qcom,cpubw { |
| 828 | compatible = "qcom,devbw"; |
| 829 | governor = "cpufreq"; |
| 830 | qcom,src-dst-ports = <1 512>; |
| 831 | qcom,active-only; |
| 832 | qcom,bw-tbl = |
| 833 | < 769 /* 100.8 MHz */ >, |
| 834 | < 1611 /* 211.2 MHz */ >, /*Low SVS*/ |
| 835 | < 2124 /* 278.4 MHz */ >, |
| 836 | < 2929 /* 384 MHz */ >, |
| 837 | < 3221 /* 422.4 MHz */ >, /* SVS */ |
| 838 | < 4248 /* 556.8 MHz */ >, |
| 839 | < 5126 /* 672 MHz */ >, |
| 840 | < 5859 /* 768 MHz */ >, /* SVS+ */ |
| 841 | < 6152 /* 806.4 MHz */ >, |
| 842 | < 6445 /* 844.8 MHz */ >, /* NOM */ |
| 843 | < 7104 /* 931.2 MHz */ >; /* TURBO */ |
| 844 | }; |
| 845 | |
| 846 | mincpubw: qcom,mincpubw { |
| 847 | compatible = "qcom,devbw"; |
| 848 | governor = "cpufreq"; |
| 849 | qcom,src-dst-ports = <1 512>; |
| 850 | qcom,active-only; |
| 851 | qcom,bw-tbl = |
| 852 | < 769 /* 100.8 MHz */ >, |
| 853 | < 1611 /* 211.2 MHz */ >, /*Low SVS*/ |
| 854 | < 2124 /* 278.4 MHz */ >, |
| 855 | < 2929 /* 384 MHz */ >, |
| 856 | < 3221 /* 422.4 MHz */ >, /* SVS */ |
| 857 | < 4248 /* 556.8 MHz */ >, |
| 858 | < 5126 /* 672 MHz */ >, |
| 859 | < 5859 /* 768 MHz */ >, /* SVS+ */ |
| 860 | < 6152 /* 806.4 MHz */ >, |
| 861 | < 6445 /* 844.8 MHz */ >, /* NOM */ |
| 862 | < 7104 /* 931.2 MHz */ >; /* TURBO */ |
| 863 | }; |
| 864 | |
| 865 | qcom,cpu-bwmon { |
| 866 | compatible = "qcom,bimc-bwmon2"; |
| 867 | reg = <0x408000 0x300>, <0x401000 0x200>; |
| 868 | reg-names = "base", "global_base"; |
| 869 | interrupts = <0 183 4>; |
| 870 | qcom,mport = <0>; |
| 871 | qcom,target-dev = <&cpubw>; |
| 872 | }; |
| 873 | |
| 874 | devfreq-cpufreq { |
| 875 | cpubw-cpufreq { |
| 876 | target-dev = <&cpubw>; |
| 877 | cpu-to-dev-map = |
| 878 | < 652800 1611>, |
| 879 | < 1036800 3221>, |
| 880 | < 1401600 5859>, |
| 881 | < 1689600 6445>, |
| 882 | < 1804800 7104>, |
| 883 | < 1958400 7104>, |
| 884 | < 2208000 7104>; |
| 885 | }; |
| 886 | |
| 887 | mincpubw-cpufreq { |
| 888 | target-dev = <&mincpubw>; |
| 889 | cpu-to-dev-map = |
| 890 | < 652800 1611 >, |
| 891 | < 1401600 3221 >, |
| 892 | < 2208000 5859 >; |
| 893 | }; |
| 894 | }; |
| 895 | |
Jonathan Avila | c7a6fd5 | 2017-10-12 15:24:05 -0700 | [diff] [blame] | 896 | cpubw_compute: qcom,cpubw-compute { |
| 897 | compatible = "qcom,arm-cpu-mon"; |
| 898 | qcom,cpulist = < &CPU0 &CPU1 &CPU2 &CPU3 |
| 899 | &CPU4 &CPU5 &CPU6 &CPU7 >; |
| 900 | qcom,target-dev = <&cpubw>; |
| 901 | qcom,core-dev-table = |
| 902 | < 652800 1611>, |
| 903 | < 1036800 3221>, |
| 904 | < 1401600 5859>, |
| 905 | < 1689600 6445>, |
| 906 | < 1804800 7104>, |
| 907 | < 1958400 7104>, |
| 908 | < 2208000 7104>; |
| 909 | }; |
| 910 | |
| 911 | mincpubw_compute: qcom,mincpubw-compute { |
| 912 | compatible = "qcom,arm-cpu-mon"; |
| 913 | qcom,cpulist = < &CPU0 &CPU1 &CPU2 &CPU3 |
| 914 | &CPU4 &CPU5 &CPU6 &CPU7 >; |
| 915 | qcom,target-dev = <&mincpubw>; |
| 916 | qcom,core-dev-table = |
| 917 | < 652800 1611 >, |
| 918 | < 1401600 3221 >, |
| 919 | < 2208000 5859 >; |
| 920 | }; |
| 921 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 922 | qcom,ipc-spinlock@1905000 { |
| 923 | compatible = "qcom,ipc-spinlock-sfpb"; |
| 924 | reg = <0x1905000 0x8000>; |
| 925 | qcom,num-locks = <8>; |
| 926 | }; |
| 927 | |
| 928 | qcom,smem@86300000 { |
| 929 | compatible = "qcom,smem"; |
| 930 | reg = <0x86300000 0x100000>, |
| 931 | <0x0b011008 0x4>, |
| 932 | <0x60000 0x8000>, |
| 933 | <0x193d000 0x8>; |
| 934 | reg-names = "smem", "irq-reg-base", |
| 935 | "aux-mem1", "smem_targ_info_reg"; |
| 936 | qcom,mpu-enabled; |
| 937 | |
| 938 | qcom,smd-modem { |
| 939 | compatible = "qcom,smd"; |
| 940 | qcom,smd-edge = <0>; |
| 941 | qcom,smd-irq-offset = <0x0>; |
| 942 | qcom,smd-irq-bitmask = <0x1000>; |
| 943 | interrupts = <0 25 1>; |
| 944 | label = "modem"; |
| 945 | qcom,not-loadable; |
| 946 | }; |
| 947 | |
| 948 | qcom,smsm-modem { |
| 949 | compatible = "qcom,smsm"; |
| 950 | qcom,smsm-edge = <0>; |
| 951 | qcom,smsm-irq-offset = <0x0>; |
| 952 | qcom,smsm-irq-bitmask = <0x2000>; |
| 953 | interrupts = <0 26 1>; |
| 954 | }; |
| 955 | |
| 956 | qcom,smd-wcnss { |
| 957 | compatible = "qcom,smd"; |
| 958 | qcom,smd-edge = <6>; |
| 959 | qcom,smd-irq-offset = <0x0>; |
| 960 | qcom,smd-irq-bitmask = <0x20000>; |
| 961 | interrupts = <0 142 1>; |
| 962 | label = "wcnss"; |
| 963 | }; |
| 964 | |
| 965 | qcom,smsm-wcnss { |
| 966 | compatible = "qcom,smsm"; |
| 967 | qcom,smsm-edge = <6>; |
| 968 | qcom,smsm-irq-offset = <0x0>; |
| 969 | qcom,smsm-irq-bitmask = <0x80000>; |
| 970 | interrupts = <0 144 1>; |
| 971 | }; |
| 972 | |
| 973 | qcom,smd-adsp { |
| 974 | compatible = "qcom,smd"; |
| 975 | qcom,smd-edge = <1>; |
| 976 | qcom,smd-irq-offset = <0x0>; |
| 977 | qcom,smd-irq-bitmask = <0x100>; |
| 978 | interrupts = <0 289 1>; |
| 979 | label = "adsp"; |
| 980 | }; |
| 981 | |
| 982 | qcom,smsm-adsp { |
| 983 | compatible = "qcom,smsm"; |
| 984 | qcom,smsm-edge = <1>; |
| 985 | qcom,smsm-irq-offset = <0x0>; |
| 986 | qcom,smsm-irq-bitmask = <0x200>; |
| 987 | interrupts = <0 290 1>; |
| 988 | }; |
| 989 | |
| 990 | qcom,smd-rpm { |
| 991 | compatible = "qcom,smd"; |
| 992 | qcom,smd-edge = <15>; |
| 993 | qcom,smd-irq-offset = <0x0>; |
| 994 | qcom,smd-irq-bitmask = <0x1>; |
| 995 | interrupts = <0 168 1>; |
| 996 | label = "rpm"; |
| 997 | qcom,irq-no-suspend; |
| 998 | qcom,not-loadable; |
| 999 | }; |
| 1000 | }; |
| 1001 | |
Arun Kumar Neelakantam | 36151aa | 2017-11-02 21:34:33 +0530 | [diff] [blame] | 1002 | qcom,smdtty { |
| 1003 | compatible = "qcom,smdtty"; |
| 1004 | |
| 1005 | smdtty_apps_fm: qcom,smdtty-apps-fm { |
| 1006 | qcom,smdtty-remote = "wcnss"; |
| 1007 | qcom,smdtty-port-name = "APPS_FM"; |
| 1008 | }; |
| 1009 | |
| 1010 | smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { |
| 1011 | qcom,smdtty-remote = "wcnss"; |
| 1012 | qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; |
| 1013 | }; |
| 1014 | |
| 1015 | smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { |
| 1016 | qcom,smdtty-remote = "wcnss"; |
| 1017 | qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; |
| 1018 | }; |
| 1019 | |
| 1020 | smdtty_mbalbridge: qcom,smdtty-mbalbridge { |
| 1021 | qcom,smdtty-remote = "modem"; |
| 1022 | qcom,smdtty-port-name = "MBALBRIDGE"; |
| 1023 | }; |
| 1024 | |
| 1025 | smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { |
| 1026 | qcom,smdtty-remote = "wcnss"; |
| 1027 | qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; |
| 1028 | }; |
| 1029 | |
| 1030 | smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { |
| 1031 | qcom,smdtty-remote = "wcnss"; |
| 1032 | qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; |
| 1033 | }; |
| 1034 | |
| 1035 | smdtty_data1: qcom,smdtty-data1 { |
| 1036 | qcom,smdtty-remote = "modem"; |
| 1037 | qcom,smdtty-port-name = "DATA1"; |
| 1038 | }; |
| 1039 | |
| 1040 | smdtty_data4: qcom,smdtty-data4 { |
| 1041 | qcom,smdtty-remote = "modem"; |
| 1042 | qcom,smdtty-port-name = "DATA4"; |
| 1043 | }; |
| 1044 | |
| 1045 | smdtty_data11: qcom,smdtty-data11 { |
| 1046 | qcom,smdtty-remote = "modem"; |
| 1047 | qcom,smdtty-port-name = "DATA11"; |
| 1048 | }; |
| 1049 | |
| 1050 | smdtty_data21: qcom,smdtty-data21 { |
| 1051 | qcom,smdtty-remote = "modem"; |
| 1052 | qcom,smdtty-port-name = "DATA21"; |
| 1053 | }; |
| 1054 | |
| 1055 | smdtty_loopback: smdtty-loopback { |
| 1056 | qcom,smdtty-remote = "modem"; |
| 1057 | qcom,smdtty-port-name = "LOOPBACK"; |
| 1058 | qcom,smdtty-dev-name = "LOOPBACK_TTY"; |
| 1059 | }; |
| 1060 | }; |
| 1061 | |
Arun Kumar Neelakantam | ea07e3d | 2017-11-02 21:27:50 +0530 | [diff] [blame] | 1062 | qcom,smdpkt { |
| 1063 | compatible = "qcom,smdpkt"; |
| 1064 | |
| 1065 | qcom,smdpkt-data5-cntl { |
| 1066 | qcom,smdpkt-remote = "modem"; |
| 1067 | qcom,smdpkt-port-name = "DATA5_CNTL"; |
| 1068 | qcom,smdpkt-dev-name = "smdcntl0"; |
| 1069 | }; |
| 1070 | |
| 1071 | qcom,smdpkt-data22 { |
| 1072 | qcom,smdpkt-remote = "modem"; |
| 1073 | qcom,smdpkt-port-name = "DATA22"; |
| 1074 | qcom,smdpkt-dev-name = "smd22"; |
| 1075 | }; |
| 1076 | |
| 1077 | qcom,smdpkt-data40-cntl { |
| 1078 | qcom,smdpkt-remote = "modem"; |
| 1079 | qcom,smdpkt-port-name = "DATA40_CNTL"; |
| 1080 | qcom,smdpkt-dev-name = "smdcntl8"; |
| 1081 | }; |
| 1082 | |
| 1083 | qcom,smdpkt-apr-apps2 { |
| 1084 | qcom,smdpkt-remote = "adsp"; |
| 1085 | qcom,smdpkt-port-name = "apr_apps2"; |
| 1086 | qcom,smdpkt-dev-name = "apr_apps2"; |
| 1087 | }; |
| 1088 | |
| 1089 | qcom,smdpkt-loopback { |
| 1090 | qcom,smdpkt-remote = "modem"; |
| 1091 | qcom,smdpkt-port-name = "LOOPBACK"; |
| 1092 | qcom,smdpkt-dev-name = "smd_pkt_loopback"; |
| 1093 | }; |
| 1094 | }; |
| 1095 | |
Raju P.L.S.S.S.N | 786994d | 2017-11-08 17:03:56 +0530 | [diff] [blame] | 1096 | rpm_bus: qcom,rpm-smd { |
| 1097 | compatible = "qcom,rpm-smd"; |
| 1098 | rpm-channel-name = "rpm_requests"; |
| 1099 | rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| 1100 | }; |
| 1101 | |
Maria Yu | f16c160 | 2017-12-22 13:05:17 +0800 | [diff] [blame] | 1102 | wdog: qcom,wdt@b017000 { |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1103 | compatible = "qcom,msm-watchdog"; |
| 1104 | reg = <0xb017000 0x1000>; |
| 1105 | reg-names = "wdt-base"; |
| 1106 | interrupts = <0 3 0>, <0 4 0>; |
| 1107 | qcom,bark-time = <11000>; |
| 1108 | qcom,pet-time = <10000>; |
| 1109 | qcom,ipi-ping; |
| 1110 | qcom,wakeup-enable; |
| 1111 | }; |
| 1112 | |
| 1113 | qcom,chd { |
| 1114 | compatible = "qcom,core-hang-detect"; |
| 1115 | qcom,threshold-arr = <0xb1880b0 0xb1980b0 0xb1a80b0 |
| 1116 | 0xb1b80b0 0xb0880b0 0xb0980b0 0xb0a80b0 0xb0b80b0>; |
| 1117 | qcom,config-arr = <0xb1880b8 0xb1980b8 0xb1a80b8 |
| 1118 | 0xb1b80b8 0xb0880b8 0xb0980b8 0xb0a80b8 0xb0b80b8>; |
| 1119 | }; |
| 1120 | |
| 1121 | qcom,msm-rtb { |
| 1122 | compatible = "qcom,msm-rtb"; |
| 1123 | qcom,rtb-size = <0x100000>; |
| 1124 | }; |
| 1125 | |
| 1126 | qcom,msm-imem@8600000 { |
| 1127 | compatible = "qcom,msm-imem"; |
| 1128 | reg = <0x08600000 0x1000>; |
| 1129 | ranges = <0x0 0x08600000 0x1000>; |
| 1130 | #address-cells = <1>; |
| 1131 | #size-cells = <1>; |
| 1132 | |
| 1133 | mem_dump_table@10 { |
| 1134 | compatible = "qcom,msm-imem-mem_dump_table"; |
| 1135 | reg = <0x10 8>; |
| 1136 | }; |
| 1137 | |
Maria Yu | 06cf96e | 2017-09-21 17:35:13 +0800 | [diff] [blame] | 1138 | dload_type@18 { |
| 1139 | compatible = "qcom,msm-imem-dload-type"; |
| 1140 | reg = <0x18 4>; |
| 1141 | }; |
| 1142 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1143 | restart_reason@65c { |
| 1144 | compatible = "qcom,msm-imem-restart_reason"; |
| 1145 | reg = <0x65c 4>; |
| 1146 | }; |
| 1147 | |
| 1148 | boot_stats@6b0 { |
| 1149 | compatible = "qcom,msm-imem-boot_stats"; |
| 1150 | reg = <0x6b0 32>; |
| 1151 | }; |
| 1152 | |
Maria Yu | 575d67f | 2017-12-05 16:31:19 +0800 | [diff] [blame] | 1153 | kaslr_offset@6d0 { |
| 1154 | compatible = "qcom,msm-imem-kaslr_offset"; |
| 1155 | reg = <0x6d0 12>; |
| 1156 | }; |
| 1157 | |
| 1158 | pil@94c { |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1159 | compatible = "qcom,msm-imem-pil"; |
| 1160 | reg = <0x94c 200>; |
| 1161 | |
| 1162 | }; |
Sriharsha Allenki | a5bcba7 | 2018-02-13 15:22:34 +0530 | [diff] [blame^] | 1163 | |
| 1164 | diag_dload@c8 { |
| 1165 | compatible = "qcom,msm-imem-diag-dload"; |
| 1166 | reg = <0xc8 200>; |
| 1167 | }; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1168 | }; |
| 1169 | |
| 1170 | qcom,memshare { |
| 1171 | compatible = "qcom,memshare"; |
| 1172 | |
| 1173 | qcom,client_1 { |
| 1174 | compatible = "qcom,memshare-peripheral"; |
| 1175 | qcom,peripheral-size = <0x200000>; |
| 1176 | qcom,client-id = <0>; |
| 1177 | qcom,allocate-boot-time; |
| 1178 | label = "modem"; |
| 1179 | }; |
| 1180 | |
| 1181 | qcom,client_2 { |
| 1182 | compatible = "qcom,memshare-peripheral"; |
| 1183 | qcom,peripheral-size = <0x300000>; |
| 1184 | qcom,client-id = <2>; |
| 1185 | label = "modem"; |
| 1186 | }; |
| 1187 | |
Manoj Prabhu B | 4dd89f8 | 2018-02-06 12:42:52 +0530 | [diff] [blame] | 1188 | qcom,client_3 { |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1189 | compatible = "qcom,memshare-peripheral"; |
Manoj Prabhu B | 4dd89f8 | 2018-02-06 12:42:52 +0530 | [diff] [blame] | 1190 | qcom,peripheral-size = <0x500000>; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1191 | qcom,client-id = <1>; |
Manoj Prabhu B | 4dd89f8 | 2018-02-06 12:42:52 +0530 | [diff] [blame] | 1192 | qcom,allocate-boot-time; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1193 | label = "modem"; |
| 1194 | }; |
| 1195 | }; |
| 1196 | sdcc1_ice: sdcc1ice@7803000 { |
| 1197 | compatible = "qcom,ice"; |
| 1198 | reg = <0x7803000 0x8000>; |
| 1199 | interrupt-names = "sdcc_ice_nonsec_level_irq", |
| 1200 | "sdcc_ice_sec_level_irq"; |
| 1201 | interrupts = <0 312 0>, <0 313 0>; |
| 1202 | qcom,enable-ice-clk; |
Sayali Lokhande | 3129993 | 2017-12-06 09:41:17 +0530 | [diff] [blame] | 1203 | clock-names = "ice_core_clk_src", "ice_core_clk", |
| 1204 | "bus_clk", "iface_clk"; |
| 1205 | clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>, |
| 1206 | <&clock_gcc clk_gcc_sdcc1_ice_core_clk>, |
| 1207 | <&clock_gcc clk_gcc_sdcc1_apps_clk>, |
| 1208 | <&clock_gcc clk_gcc_sdcc1_ahb_clk>; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1209 | qcom,op-freq-hz = <270000000>, <0>, <0>, <0>; |
| 1210 | qcom,msm-bus,name = "sdcc_ice_noc"; |
| 1211 | qcom,msm-bus,num-cases = <2>; |
| 1212 | qcom,msm-bus,num-paths = <1>; |
| 1213 | qcom,msm-bus,vectors-KBps = |
| 1214 | <78 512 0 0>, /* No vote */ |
| 1215 | <78 512 1000 0>; /* Max. bandwidth */ |
| 1216 | qcom,bus-vector-names = "MIN", "MAX"; |
| 1217 | qcom,instance-type = "sdcc"; |
| 1218 | }; |
| 1219 | |
| 1220 | sdhc_1: sdhci@7824900 { |
| 1221 | compatible = "qcom,sdhci-msm"; |
| 1222 | reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>; |
| 1223 | reg-names = "hc_mem", "core_mem", "cmdq_mem"; |
| 1224 | |
| 1225 | interrupts = <0 123 0>, <0 138 0>; |
| 1226 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1227 | |
| 1228 | sdhc-msm-crypto = <&sdcc1_ice>; |
| 1229 | qcom,bus-width = <8>; |
| 1230 | |
| 1231 | qcom,devfreq,freq-table = <50000000 200000000>; |
| 1232 | |
| 1233 | qcom,pm-qos-irq-type = "affine_irq"; |
| 1234 | qcom,pm-qos-irq-latency = <2 213>; |
| 1235 | |
| 1236 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1237 | qcom,pm-qos-cmdq-latency-us = <2 213>, <2 213>; |
| 1238 | |
| 1239 | qcom,pm-qos-legacy-latency-us = <2 213>, <2 213>; |
| 1240 | |
| 1241 | qcom,msm-bus,name = "sdhc1"; |
| 1242 | qcom,msm-bus,num-cases = <9>; |
| 1243 | qcom,msm-bus,num-paths = <1>; |
| 1244 | qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ |
| 1245 | <78 512 1046 3200>, /* 400 KB/s*/ |
| 1246 | <78 512 52286 160000>, /* 20 MB/s */ |
| 1247 | <78 512 65360 200000>, /* 25 MB/s */ |
| 1248 | <78 512 130718 400000>, /* 50 MB/s */ |
| 1249 | <78 512 130718 400000>, /* 100 MB/s */ |
| 1250 | <78 512 261438 800000>, /* 200 MB/s */ |
| 1251 | <78 512 261438 800000>, /* 400 MB/s */ |
| 1252 | <78 512 1338562 4096000>; /* Max. bandwidth */ |
| 1253 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 1254 | 100000000 200000000 400000000 4294967295>; |
| 1255 | |
Sayali Lokhande | 3129993 | 2017-12-06 09:41:17 +0530 | [diff] [blame] | 1256 | clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, |
| 1257 | <&clock_gcc clk_gcc_sdcc1_apps_clk>, |
| 1258 | <&clock_gcc clk_gcc_sdcc1_ice_core_clk>; |
| 1259 | clock-names = "iface_clk", "core_clk", "ice_core_clk"; |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1260 | qcom,ice-clk-rates = <270000000 160000000>; |
| 1261 | qcom,large-address-bus; |
| 1262 | |
| 1263 | status = "disabled"; |
| 1264 | }; |
| 1265 | |
| 1266 | sdhc_2: sdhci@7864900 { |
| 1267 | compatible = "qcom,sdhci-msm"; |
| 1268 | reg = <0x7864900 0x500>, <0x7864000 0x800>; |
| 1269 | reg-names = "hc_mem", "core_mem"; |
| 1270 | |
| 1271 | interrupts = <0 125 0>, <0 221 0>; |
| 1272 | interrupt-names = "hc_irq", "pwr_irq"; |
| 1273 | |
| 1274 | qcom,bus-width = <4>; |
| 1275 | |
| 1276 | qcom,pm-qos-irq-type = "affine_irq"; |
| 1277 | qcom,pm-qos-irq-latency = <2 213>; |
| 1278 | |
| 1279 | qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| 1280 | qcom,pm-qos-legacy-latency-us = <2 213>, <2 213>; |
| 1281 | |
| 1282 | qcom,devfreq,freq-table = <50000000 200000000>; |
| 1283 | |
| 1284 | qcom,msm-bus,name = "sdhc2"; |
| 1285 | qcom,msm-bus,num-cases = <8>; |
| 1286 | qcom,msm-bus,num-paths = <1>; |
| 1287 | qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ |
| 1288 | <81 512 1046 3200>, /* 400 KB/s*/ |
| 1289 | <81 512 52286 160000>, /* 20 MB/s */ |
| 1290 | <81 512 65360 200000>, /* 25 MB/s */ |
| 1291 | <81 512 130718 400000>, /* 50 MB/s */ |
| 1292 | <81 512 261438 800000>, /* 100 MB/s */ |
| 1293 | <81 512 261438 800000>, /* 200 MB/s */ |
| 1294 | <81 512 1338562 4096000>; /* Max. bandwidth */ |
| 1295 | qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 1296 | 100000000 200000000 4294967295>; |
| 1297 | |
Sayali Lokhande | 3129993 | 2017-12-06 09:41:17 +0530 | [diff] [blame] | 1298 | clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, |
| 1299 | <&clock_gcc clk_gcc_sdcc2_apps_clk>; |
| 1300 | clock-names = "iface_clk", "core_clk"; |
| 1301 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1302 | qcom,large-address-bus; |
| 1303 | status = "disabled"; |
| 1304 | }; |
| 1305 | |
Tharun Kumar Merugu | c1413e7 | 2018-01-22 19:23:58 +0530 | [diff] [blame] | 1306 | qcom,msm-adsprpc-mem { |
| 1307 | compatible = "qcom,msm-adsprpc-mem-region"; |
| 1308 | memory-region = <&adsp_mem>; |
| 1309 | }; |
| 1310 | |
| 1311 | qcom,msm_fastrpc { |
| 1312 | compatible = "qcom,msm-fastrpc-legacy-compute"; |
| 1313 | qcom,msm_fastrpc_compute_cb { |
| 1314 | compatible = "qcom,msm-fastrpc-legacy-compute-cb"; |
| 1315 | label = "adsprpc-smd"; |
| 1316 | iommus = <&apps_iommu 0x2408 0x7>; |
| 1317 | sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; |
| 1318 | }; |
| 1319 | }; |
| 1320 | |
| 1321 | |
Mohammed Javid | f62ec62 | 2017-11-29 20:07:32 +0530 | [diff] [blame] | 1322 | ipa_hw: qcom,ipa@07900000 { |
| 1323 | compatible = "qcom,ipa"; |
| 1324 | reg = <0x07900000 0x4effc>, <0x07904000 0x26934>; |
| 1325 | reg-names = "ipa-base", "bam-base"; |
| 1326 | interrupts = <0 228 0>, |
| 1327 | <0 230 0>; |
| 1328 | interrupt-names = "ipa-irq", "bam-irq"; |
| 1329 | qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */ |
| 1330 | qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ |
| 1331 | qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/ |
| 1332 | qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/ |
| 1333 | clock-names = "core_clk"; |
| 1334 | clocks = <&clock_gcc clk_ipa_clk>; |
| 1335 | qcom,ee = <0>; |
| 1336 | qcom,use-ipa-tethering-bridge; |
| 1337 | qcom,modem-cfg-emb-pipe-flt; |
| 1338 | qcom,msm-bus,name = "ipa"; |
| 1339 | qcom,msm-bus,num-cases = <3>; |
| 1340 | qcom,msm-bus,num-paths = <1>; |
| 1341 | qcom,msm-bus,vectors-KBps = |
| 1342 | <90 512 0 0>, /* No BIMC vote (ab=0 Mbps, ib=0 Mbps ~ 0MHZ) */ |
| 1343 | <90 512 100000 800000>, /* SVS (ab=100, ib=800 ~ 50MHz) */ |
| 1344 | <90 512 100000 1200000>; /* PERF (ab=100, ib=1200 ~ 75MHz) */ |
| 1345 | qcom,bus-vector-names = "MIN", "SVS", "PERF"; |
| 1346 | }; |
| 1347 | |
| 1348 | qcom,rmnet-ipa { |
| 1349 | compatible = "qcom,rmnet-ipa"; |
| 1350 | qcom,rmnet-ipa-ssr; |
| 1351 | qcom,ipa-loaduC; |
| 1352 | qcom,ipa-advertise-sg-support; |
| 1353 | }; |
| 1354 | |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 1355 | spmi_bus: qcom,spmi@200f000 { |
| 1356 | compatible = "qcom,spmi-pmic-arb"; |
| 1357 | reg = <0x200f000 0x1000>, |
| 1358 | <0x2400000 0x800000>, |
| 1359 | <0x2c00000 0x800000>, |
| 1360 | <0x3800000 0x200000>, |
| 1361 | <0x200a000 0x2100>; |
| 1362 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 1363 | interrupt-names = "periph_irq"; |
| 1364 | interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; |
| 1365 | qcom,ee = <0>; |
| 1366 | qcom,channel = <0>; |
Kiran Gunda | 90e356a | 2017-11-22 17:04:46 +0530 | [diff] [blame] | 1367 | #address-cells = <2>; |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 1368 | #size-cells = <0>; |
| 1369 | interrupt-controller; |
Kiran Gunda | 90e356a | 2017-11-22 17:04:46 +0530 | [diff] [blame] | 1370 | #interrupt-cells = <4>; |
Kiran Gunda | af6a0b6 | 2017-10-23 16:03:10 +0530 | [diff] [blame] | 1371 | cell-index = <0>; |
| 1372 | }; |
Chandana Kishori Chiluveru | 34872ee | 2017-11-30 17:35:26 +0530 | [diff] [blame] | 1373 | |
| 1374 | usb3: ssusb@7000000{ |
| 1375 | compatible = "qcom,dwc-usb3-msm"; |
| 1376 | reg = <0x07000000 0xfc000>, |
| 1377 | <0x0007e000 0x400>; |
| 1378 | reg-names = "core_base", |
| 1379 | "ahb2phy_base"; |
| 1380 | #address-cells = <1>; |
| 1381 | #size-cells = <1>; |
| 1382 | ranges; |
| 1383 | |
| 1384 | interrupts = <0 136 0>, <0 220 0>, <0 134 0>; |
| 1385 | interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; |
| 1386 | |
| 1387 | USB3_GDSC-supply = <&gdsc_usb30>; |
| 1388 | qcom,usb-dbm = <&dbm_1p5>; |
| 1389 | qcom,msm-bus,name = "usb3"; |
| 1390 | qcom,msm-bus,num-cases = <3>; |
| 1391 | qcom,msm-bus,num-paths = <1>; |
| 1392 | qcom,msm-bus,vectors-KBps = |
| 1393 | <61 512 0 0>, |
| 1394 | <61 512 240000 800000>, |
| 1395 | <61 512 240000 800000>; |
| 1396 | |
| 1397 | /* CPU-CLUSTER-WFI-LVL latency +1 */ |
| 1398 | qcom,pm-qos-latency = <2>; |
| 1399 | |
| 1400 | qcom,dwc-usb3-msm-tx-fifo-size = <21288>; |
| 1401 | |
| 1402 | clocks = <&clock_gcc clk_gcc_usb30_master_clk>, |
| 1403 | <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>, |
| 1404 | <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, |
| 1405 | <&clock_gcc clk_gcc_usb30_sleep_clk>, |
| 1406 | <&clock_gcc clk_xo_dwc3_clk>, |
| 1407 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>; |
| 1408 | |
| 1409 | clock-names = "core_clk", "iface_clk", "utmi_clk", |
| 1410 | "sleep_clk", "xo", "cfg_ahb_clk"; |
| 1411 | |
| 1412 | qcom,core-clk-rate = <133333333>; /* NOM */ |
| 1413 | qcom,core-clk-rate-hs = <60000000>; /* LOW SVS */ |
| 1414 | |
| 1415 | resets = <&clock_gcc GCC_USB_30_BCR>; |
| 1416 | reset-names = "core_reset"; |
| 1417 | |
| 1418 | dwc3@7000000 { |
| 1419 | compatible = "snps,dwc3"; |
| 1420 | reg = <0x07000000 0xc8d0>; |
| 1421 | interrupt-parent = <&intc>; |
| 1422 | interrupts = <0 140 0>; |
| 1423 | usb-phy = <&qusb_phy>, <&ssphy>; |
| 1424 | tx-fifo-resize; |
| 1425 | snps,usb3-u1u2-disable; |
| 1426 | snps,nominal-elastic-buffer; |
| 1427 | snps,is-utmi-l1-suspend; |
| 1428 | snps,hird-threshold = /bits/ 8 <0x0>; |
| 1429 | }; |
| 1430 | |
| 1431 | qcom,usbbam@7104000 { |
| 1432 | compatible = "qcom,usb-bam-msm"; |
| 1433 | reg = <0x07104000 0x1a934>; |
| 1434 | interrupt-parent = <&intc>; |
| 1435 | interrupts = <0 135 0>; |
| 1436 | |
| 1437 | qcom,bam-type = <0>; |
| 1438 | qcom,usb-bam-fifo-baseaddr = <0x08605000>; |
| 1439 | qcom,usb-bam-num-pipes = <8>; |
| 1440 | qcom,ignore-core-reset-ack; |
| 1441 | qcom,disable-clk-gating; |
| 1442 | qcom,usb-bam-override-threshold = <0x4001>; |
| 1443 | qcom,usb-bam-max-mbps-highspeed = <400>; |
| 1444 | qcom,usb-bam-max-mbps-superspeed = <3600>; |
| 1445 | qcom,reset-bam-on-connect; |
| 1446 | |
| 1447 | qcom,pipe0 { |
| 1448 | label = "ssusb-ipa-out-0"; |
| 1449 | qcom,usb-bam-mem-type = <1>; |
| 1450 | qcom,dir = <0>; |
| 1451 | qcom,pipe-num = <0>; |
| 1452 | qcom,peer-bam = <1>; |
| 1453 | qcom,src-bam-pipe-index = <1>; |
| 1454 | qcom,data-fifo-size = <0x8000>; |
| 1455 | qcom,descriptor-fifo-size = <0x2000>; |
| 1456 | }; |
| 1457 | |
| 1458 | qcom,pipe1 { |
| 1459 | label = "ssusb-ipa-in-0"; |
| 1460 | qcom,usb-bam-mem-type = <1>; |
| 1461 | qcom,dir = <1>; |
| 1462 | qcom,pipe-num = <0>; |
| 1463 | qcom,peer-bam = <1>; |
| 1464 | qcom,dst-bam-pipe-index = <0>; |
| 1465 | qcom,data-fifo-size = <0x8000>; |
| 1466 | qcom,descriptor-fifo-size = <0x2000>; |
| 1467 | }; |
| 1468 | |
| 1469 | qcom,pipe2 { |
| 1470 | label = "ssusb-qdss-in-0"; |
| 1471 | qcom,usb-bam-mem-type = <2>; |
| 1472 | qcom,dir = <1>; |
| 1473 | qcom,pipe-num = <0>; |
| 1474 | qcom,peer-bam = <0>; |
| 1475 | qcom,peer-bam-physical-address = <0x06044000>; |
| 1476 | qcom,src-bam-pipe-index = <0>; |
| 1477 | qcom,dst-bam-pipe-index = <2>; |
| 1478 | qcom,data-fifo-offset = <0x0>; |
| 1479 | qcom,data-fifo-size = <0xe00>; |
| 1480 | qcom,descriptor-fifo-offset = <0xe00>; |
| 1481 | qcom,descriptor-fifo-size = <0x200>; |
| 1482 | }; |
| 1483 | |
| 1484 | qcom,pipe3 { |
| 1485 | label = "ssusb-dpl-ipa-in-1"; |
| 1486 | qcom,usb-bam-mem-type = <1>; |
| 1487 | qcom,dir = <1>; |
| 1488 | qcom,pipe-num = <1>; |
| 1489 | qcom,peer-bam = <1>; |
| 1490 | qcom,dst-bam-pipe-index = <2>; |
| 1491 | qcom,data-fifo-size = <0x8000>; |
| 1492 | qcom,descriptor-fifo-size = <0x2000>; |
| 1493 | }; |
| 1494 | }; |
| 1495 | }; |
| 1496 | |
| 1497 | qusb_phy: qusb@79000 { |
| 1498 | compatible = "qcom,qusb2phy"; |
| 1499 | reg = <0x079000 0x180>, |
| 1500 | <0x01841030 0x4>, |
| 1501 | <0x0193f020 0x4>; |
| 1502 | reg-names = "qusb_phy_base", |
| 1503 | "ref_clk_addr", |
| 1504 | "tcsr_clamp_dig_n_1p8"; |
| 1505 | |
| 1506 | USB3_GDSC-supply = <&gdsc_usb30>; |
| 1507 | vdd-supply = <&pm8953_l3>; |
| 1508 | vdda18-supply = <&pm8953_l7>; |
| 1509 | vdda33-supply = <&pm8953_l13>; |
| 1510 | qcom,vdd-voltage-level = <0 925000 925000>; |
| 1511 | |
| 1512 | qcom,qusb-phy-init-seq = <0xf8 0x80 |
| 1513 | 0xb3 0x84 |
| 1514 | 0x83 0x88 |
| 1515 | 0xc0 0x8c |
| 1516 | 0x14 0x9c |
| 1517 | 0x30 0x08 |
| 1518 | 0x79 0x0c |
| 1519 | 0x21 0x10 |
| 1520 | 0x00 0x90 |
| 1521 | 0x9f 0x1c |
| 1522 | 0x00 0x18>; |
| 1523 | phy_type= "utmi"; |
| 1524 | qcom,phy-clk-scheme = "cml"; |
| 1525 | qcom,major-rev = <1>; |
| 1526 | |
| 1527 | clocks = <&clock_gcc clk_bb_clk1>, |
| 1528 | <&clock_gcc clk_gcc_qusb_ref_clk>, |
| 1529 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, |
| 1530 | <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>, |
| 1531 | <&clock_gcc clk_gcc_usb30_master_clk>; |
| 1532 | |
| 1533 | clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", |
| 1534 | "iface_clk", "core_clk"; |
| 1535 | |
| 1536 | resets = <&clock_gcc GCC_QUSB2_PHY_BCR>; |
| 1537 | reset-names = "phy_reset"; |
| 1538 | }; |
| 1539 | |
| 1540 | ssphy: ssphy@78000 { |
| 1541 | compatible = "qcom,usb-ssphy-qmp"; |
| 1542 | reg = <0x78000 0x9f8>, |
| 1543 | <0x0193f244 0x4>; |
| 1544 | reg-names = "qmp_phy_base", |
| 1545 | "vls_clamp_reg"; |
| 1546 | |
| 1547 | qcom,qmp-phy-init-seq = /*<reg_offset, value, delay>*/ |
| 1548 | <0xac 0x14 0x00 |
| 1549 | 0x34 0x08 0x00 |
| 1550 | 0x174 0x30 0x00 |
| 1551 | 0x3c 0x06 0x00 |
| 1552 | 0xb4 0x00 0x00 |
| 1553 | 0xb8 0x08 0x00 |
| 1554 | 0x194 0x06 0x3e8 |
| 1555 | 0x19c 0x01 0x00 |
| 1556 | 0x178 0x00 0x00 |
| 1557 | 0xd0 0x82 0x00 |
| 1558 | 0xdc 0x55 0x00 |
| 1559 | 0xe0 0x55 0x00 |
| 1560 | 0xe4 0x03 0x00 |
| 1561 | 0x78 0x0b 0x00 |
| 1562 | 0x84 0x16 0x00 |
| 1563 | 0x90 0x28 0x00 |
| 1564 | 0x108 0x80 0x00 |
| 1565 | 0x10c 0x00 0x00 |
| 1566 | 0x184 0x0a 0x00 |
| 1567 | 0x4c 0x15 0x00 |
| 1568 | 0x50 0x34 0x00 |
| 1569 | 0x54 0x00 0x00 |
| 1570 | 0xc8 0x00 0x00 |
| 1571 | 0x18c 0x00 0x00 |
| 1572 | 0xcc 0x00 0x00 |
| 1573 | 0x128 0x00 0x00 |
| 1574 | 0x0c 0x0a 0x00 |
| 1575 | 0x10 0x01 0x00 |
| 1576 | 0x1c 0x31 0x00 |
| 1577 | 0x20 0x01 0x00 |
| 1578 | 0x14 0x00 0x00 |
| 1579 | 0x18 0x00 0x00 |
| 1580 | 0x24 0xde 0x00 |
| 1581 | 0x28 0x07 0x00 |
| 1582 | 0x48 0x0f 0x00 |
| 1583 | 0x70 0x0f 0x00 |
| 1584 | 0x100 0x80 0x00 |
| 1585 | 0x440 0x0b 0x00 |
| 1586 | 0x4d8 0x02 0x00 |
| 1587 | 0x4dc 0x6c 0x00 |
| 1588 | 0x4e0 0xbb 0x00 |
| 1589 | 0x508 0x77 0x00 |
| 1590 | 0x50c 0x80 0x00 |
| 1591 | 0x514 0x03 0x00 |
| 1592 | 0x51c 0x16 0x00 |
| 1593 | 0x448 0x75 0x00 |
| 1594 | 0x454 0x00 0x00 |
| 1595 | 0x40c 0x0a 0x00 |
| 1596 | 0x41c 0x06 0x00 |
| 1597 | 0x510 0x00 0x00 |
| 1598 | 0x268 0x45 0x00 |
| 1599 | 0x2ac 0x12 0x00 |
| 1600 | 0x294 0x06 0x00 |
| 1601 | 0x254 0x00 0x00 |
| 1602 | 0x8c8 0x83 0x00 |
| 1603 | 0x8c4 0x02 0x00 |
| 1604 | 0x8cc 0x09 0x00 |
| 1605 | 0x8d0 0xa2 0x00 |
| 1606 | 0x8d4 0x85 0x00 |
| 1607 | 0x880 0xd1 0x00 |
| 1608 | 0x884 0x1f 0x00 |
| 1609 | 0x888 0x47 0x00 |
| 1610 | 0x80c 0x9f 0x00 |
| 1611 | 0x824 0x17 0x00 |
| 1612 | 0x828 0x0f 0x00 |
| 1613 | 0x8b8 0x75 0x00 |
| 1614 | 0x8bc 0x13 0x00 |
| 1615 | 0x8b0 0x86 0x00 |
| 1616 | 0x8a0 0x04 0x00 |
| 1617 | 0x88c 0x44 0x00 |
| 1618 | 0x870 0xe7 0x00 |
| 1619 | 0x874 0x03 0x00 |
| 1620 | 0x878 0x40 0x00 |
| 1621 | 0x87c 0x00 0x00 |
| 1622 | 0x9d8 0x88 0x00 |
| 1623 | 0xffffffff 0x00 0x00>; |
| 1624 | qcom,qmp-phy-reg-offset = |
| 1625 | <0x974 /* USB3_PHY_PCS_STATUS */ |
| 1626 | 0x8d8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ |
| 1627 | 0x8dc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ |
| 1628 | 0x804 /* USB3_PHY_POWER_DOWN_CONTROL */ |
| 1629 | 0x800 /* USB3_PHY_SW_RESET */ |
| 1630 | 0x808>; /* USB3_PHY_START */ |
| 1631 | |
| 1632 | vdd-supply = <&pm8953_l3>; |
| 1633 | core-supply = <&pm8953_l7>; |
| 1634 | qcom,vdd-voltage-level = <0 925000 925000>; |
| 1635 | qcom,core-voltage-level = <0 1800000 1800000>; |
| 1636 | qcom,vbus-valid-override; |
| 1637 | |
| 1638 | clocks = <&clock_gcc clk_gcc_usb3_aux_clk>, |
| 1639 | <&clock_gcc clk_gcc_usb3_pipe_clk>, |
| 1640 | <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, |
| 1641 | <&clock_gcc clk_bb_clk1>, |
| 1642 | <&clock_gcc clk_gcc_usb_ss_ref_clk>; |
| 1643 | |
| 1644 | clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", |
| 1645 | "ref_clk_src", "ref_clk"; |
| 1646 | |
| 1647 | resets = <&clock_gcc GCC_USB3_PHY_BCR>, |
| 1648 | <&clock_gcc GCC_USB3PHY_PHY_BCR>; |
| 1649 | |
| 1650 | reset-names = "phy_reset", "phy_phy_reset"; |
| 1651 | }; |
| 1652 | |
| 1653 | dbm_1p5: dbm@70f8000 { |
| 1654 | compatible = "qcom,usb-dbm-1p5"; |
| 1655 | reg = <0x070f8000 0x300>; |
| 1656 | qcom,reset-ep-after-lpm-resume; |
| 1657 | }; |
Jitendra Sharma | c5c3197 | 2017-11-10 14:26:13 +0530 | [diff] [blame] | 1658 | |
Jingbiao Lu | e44c5e5 | 2018-01-03 15:26:26 +0800 | [diff] [blame] | 1659 | qcom,mss@4080000 { |
| 1660 | compatible = "qcom,pil-q6v55-mss"; |
| 1661 | reg = <0x04080000 0x100>, |
| 1662 | <0x0194f000 0x010>, |
| 1663 | <0x01950000 0x008>, |
| 1664 | <0x01951000 0x008>, |
| 1665 | <0x04020000 0x040>, |
| 1666 | <0x01871000 0x004>; |
| 1667 | reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", |
| 1668 | "rmb_base", "restart_reg"; |
| 1669 | |
| 1670 | interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; |
| 1671 | vdd_mss-supply = <&pm8953_s1>; |
| 1672 | vdd_cx-supply = <&pm8953_s2_level>; |
| 1673 | vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| 1674 | vdd_mx-supply = <&pm8953_s7_level_ao>; |
| 1675 | vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| 1676 | vdd_pll-supply = <&pm8953_l7>; |
| 1677 | qcom,vdd_pll = <1800000>; |
| 1678 | vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| 1679 | |
| 1680 | clocks = <&clock_gcc clk_xo_pil_mss_clk>, |
| 1681 | <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, |
| 1682 | <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, |
| 1683 | <&clock_gcc clk_gcc_boot_rom_ahb_clk>; |
| 1684 | clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; |
| 1685 | qcom,proxy-clock-names = "xo"; |
| 1686 | qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; |
| 1687 | |
| 1688 | qcom,pas-id = <5>; |
| 1689 | qcom,pil-mss-memsetup; |
| 1690 | qcom,firmware-name = "modem"; |
| 1691 | qcom,pil-self-auth; |
| 1692 | qcom,sysmon-id = <0>; |
| 1693 | qcom,ssctl-instance-id = <0x12>; |
| 1694 | qcom,qdsp6v56-1-10; |
| 1695 | qcom,reset-clk; |
| 1696 | |
| 1697 | memory-region = <&modem_mem>; |
| 1698 | }; |
| 1699 | |
Jitendra Sharma | c5c3197 | 2017-11-10 14:26:13 +0530 | [diff] [blame] | 1700 | qcom,lpass@c200000 { |
| 1701 | compatible = "qcom,pil-tz-generic"; |
| 1702 | reg = <0xc200000 0x00100>; |
| 1703 | interrupts = <0 293 1>; |
| 1704 | |
| 1705 | vdd_cx-supply = <&pm8953_s2_level>; |
| 1706 | qcom,proxy-reg-names = "vdd_cx"; |
| 1707 | qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; |
Jingbiao Lu | 60bda87 | 2017-12-27 10:54:21 +0800 | [diff] [blame] | 1708 | qcom,mas-crypto = <&mas_crypto>; |
Jitendra Sharma | c5c3197 | 2017-11-10 14:26:13 +0530 | [diff] [blame] | 1709 | |
| 1710 | clocks = <&clock_gcc clk_xo_pil_lpass_clk>, |
| 1711 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1712 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1713 | <&clock_gcc clk_gcc_crypto_axi_clk>, |
| 1714 | <&clock_gcc clk_crypto_clk_src>; |
| 1715 | clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1716 | "scm_bus_clk", "scm_core_clk_src"; |
| 1717 | qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1718 | "scm_bus_clk", "scm_core_clk_src"; |
| 1719 | qcom,scm_core_clk_src-freq = <80000000>; |
| 1720 | |
| 1721 | qcom,pas-id = <1>; |
| 1722 | qcom,complete-ramdump; |
| 1723 | qcom,proxy-timeout-ms = <10000>; |
| 1724 | qcom,smem-id = <423>; |
| 1725 | qcom,sysmon-id = <1>; |
| 1726 | qcom,ssctl-instance-id = <0x14>; |
| 1727 | qcom,firmware-name = "adsp"; |
| 1728 | |
| 1729 | memory-region = <&adsp_fw_mem>; |
| 1730 | }; |
Jitendra Sharma | a50d808 | 2017-11-10 14:33:32 +0530 | [diff] [blame] | 1731 | |
| 1732 | qcom,pronto@a21b000 { |
| 1733 | compatible = "qcom,pil-tz-generic"; |
| 1734 | reg = <0x0a21b000 0x3000>; |
| 1735 | interrupts = <0 149 1>; |
| 1736 | |
| 1737 | vdd_pronto_pll-supply = <&pm8953_l7>; |
| 1738 | proxy-reg-names = "vdd_pronto_pll"; |
| 1739 | vdd_pronto_pll-uV-uA = <1800000 18000>; |
Jingbiao Lu | 60bda87 | 2017-12-27 10:54:21 +0800 | [diff] [blame] | 1740 | qcom,mas-crypto = <&mas_crypto>; |
| 1741 | |
Jitendra Sharma | a50d808 | 2017-11-10 14:33:32 +0530 | [diff] [blame] | 1742 | clocks = <&clock_gcc clk_xo_pil_pronto_clk>, |
| 1743 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1744 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1745 | <&clock_gcc clk_gcc_crypto_axi_clk>, |
| 1746 | <&clock_gcc clk_crypto_clk_src>; |
| 1747 | |
| 1748 | clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1749 | "scm_bus_clk", "scm_core_clk_src"; |
| 1750 | qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", |
| 1751 | "scm_bus_clk", "scm_core_clk_src"; |
| 1752 | qcom,scm_core_clk_src = <80000000>; |
| 1753 | |
| 1754 | qcom,pas-id = <6>; |
| 1755 | qcom,proxy-timeout-ms = <10000>; |
| 1756 | qcom,smem-id = <422>; |
| 1757 | qcom,sysmon-id = <6>; |
| 1758 | qcom,ssctl-instance-id = <0x13>; |
| 1759 | qcom,firmware-name = "wcnss"; |
| 1760 | |
| 1761 | memory-region = <&wcnss_fw_mem>; |
| 1762 | }; |
| 1763 | |
Tingwei Zhang | 63c1b7d | 2017-12-22 16:38:16 +0800 | [diff] [blame] | 1764 | qcom,venus@1de0000 { |
| 1765 | compatible = "qcom,pil-tz-generic"; |
| 1766 | reg = <0x1de0000 0x4000>; |
| 1767 | |
| 1768 | vdd-supply = <&gdsc_venus>; |
| 1769 | qcom,proxy-reg-names = "vdd"; |
Tingwei Zhang | 7f3d05b | 2018-01-18 21:08:07 +0800 | [diff] [blame] | 1770 | qcom,mas-crypto = <&mas_crypto>; |
Tingwei Zhang | 63c1b7d | 2017-12-22 16:38:16 +0800 | [diff] [blame] | 1771 | |
| 1772 | clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>, |
| 1773 | <&clock_gcc clk_gcc_venus0_ahb_clk>, |
| 1774 | <&clock_gcc clk_gcc_venus0_axi_clk>, |
| 1775 | <&clock_gcc clk_gcc_crypto_clk>, |
| 1776 | <&clock_gcc clk_gcc_crypto_ahb_clk>, |
| 1777 | <&clock_gcc clk_gcc_crypto_axi_clk>, |
| 1778 | <&clock_gcc clk_crypto_clk_src>; |
| 1779 | |
| 1780 | clock-names = "core_clk", "iface_clk", "bus_clk", |
| 1781 | "scm_core_clk", "scm_iface_clk", |
| 1782 | "scm_bus_clk", "scm_core_clk_src"; |
| 1783 | |
| 1784 | qcom,proxy-clock-names = "core_clk", "iface_clk", |
| 1785 | "bus_clk", "scm_core_clk", |
| 1786 | "scm_iface_clk", "scm_bus_clk", |
| 1787 | "scm_core_clk_src"; |
| 1788 | qcom,scm_core_clk_src-freq = <80000000>; |
| 1789 | |
| 1790 | qcom,msm-bus,name = "pil-venus"; |
| 1791 | qcom,msm-bus,num-cases = <2>; |
| 1792 | qcom,msm-bus,num-paths = <1>; |
| 1793 | qcom,msm-bus,vectors-KBps = |
| 1794 | <63 512 0 0>, |
| 1795 | <63 512 0 304000>; |
| 1796 | qcom,pas-id = <9>; |
| 1797 | qcom,proxy-timeout-ms = <100>; |
| 1798 | qcom,firmware-name = "venus"; |
| 1799 | memory-region = <&venus_mem>; |
| 1800 | }; |
Anurag Chouhan | 0c6dba8 | 2018-01-08 15:20:30 +0530 | [diff] [blame] | 1801 | |
| 1802 | qcom,wcnss-wlan@0a000000 { |
| 1803 | compatible = "qcom,wcnss_wlan"; |
| 1804 | reg = <0x0a000000 0x280000>, |
| 1805 | <0x0b011008 0x04>, |
| 1806 | <0x0a21b000 0x3000>, |
| 1807 | <0x03204000 0x00000100>, |
| 1808 | <0x03200800 0x00000200>, |
| 1809 | <0x0a100400 0x00000200>, |
| 1810 | <0x0a205050 0x00000200>, |
| 1811 | <0x0a219000 0x00000020>, |
| 1812 | <0x0a080488 0x00000008>, |
| 1813 | <0x0a080fb0 0x00000008>, |
| 1814 | <0x0a08040c 0x00000008>, |
| 1815 | <0x0a0120a8 0x00000008>, |
| 1816 | <0x0a012448 0x00000008>, |
| 1817 | <0x0a080c00 0x00000001>; |
| 1818 | |
| 1819 | reg-names = "wcnss_mmio", "wcnss_fiq", |
| 1820 | "pronto_phy_base", "riva_phy_base", |
| 1821 | "riva_ccu_base", "pronto_a2xb_base", |
| 1822 | "pronto_ccpu_base", "pronto_saw2_base", |
| 1823 | "wlan_tx_phy_aborts","wlan_brdg_err_source", |
| 1824 | "wlan_tx_status", "alarms_txctl", |
| 1825 | "alarms_tactl", "pronto_mcu_base"; |
| 1826 | |
| 1827 | interrupts = <0 145 0 0 146 0>; |
| 1828 | interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; |
| 1829 | |
| 1830 | qcom,pronto-vddmx-supply = <&pm8953_s7_level_ao>; |
| 1831 | qcom,pronto-vddcx-supply = <&pm8953_s2_level>; |
| 1832 | qcom,pronto-vddpx-supply = <&pm8953_l5>; |
| 1833 | qcom,iris-vddxo-supply = <&pm8953_l7>; |
| 1834 | qcom,iris-vddrfa-supply = <&pm8953_l19>; |
| 1835 | qcom,iris-vddpa-supply = <&pm8953_l9>; |
| 1836 | qcom,iris-vdddig-supply = <&pm8953_l5>; |
| 1837 | |
| 1838 | qcom,iris-vddxo-voltage-level = <1800000 0 1800000>; |
| 1839 | qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>; |
| 1840 | qcom,iris-vddpa-voltage-level = <3300000 0 3300000>; |
| 1841 | qcom,iris-vdddig-voltage-level = <1800000 0 1800000>; |
| 1842 | |
| 1843 | qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO |
| 1844 | RPM_SMD_REGULATOR_LEVEL_NONE |
| 1845 | RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| 1846 | qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM |
| 1847 | RPM_SMD_REGULATOR_LEVEL_NONE |
| 1848 | RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| 1849 | qcom,vddpx-voltage-level = <1800000 0 1800000>; |
| 1850 | |
| 1851 | qcom,iris-vddxo-current = <10000>; |
| 1852 | qcom,iris-vddrfa-current = <100000>; |
| 1853 | qcom,iris-vddpa-current = <515000>; |
| 1854 | qcom,iris-vdddig-current = <10000>; |
| 1855 | |
| 1856 | qcom,pronto-vddmx-current = <0>; |
| 1857 | qcom,pronto-vddcx-current = <0>; |
| 1858 | qcom,pronto-vddpx-current = <0>; |
| 1859 | |
| 1860 | pinctrl-names = "wcnss_default", "wcnss_sleep", |
| 1861 | "wcnss_gpio_default"; |
| 1862 | pinctrl-0 = <&wcnss_default>; |
| 1863 | pinctrl-1 = <&wcnss_sleep>; |
| 1864 | pinctrl-2 = <&wcnss_gpio_default>; |
| 1865 | |
| 1866 | gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>, |
| 1867 | <&tlmm 79 0>, <&tlmm 80 0>; |
| 1868 | |
| 1869 | clocks = <&clock_gcc clk_xo_wlan_clk>, |
| 1870 | <&clock_gcc clk_rf_clk2>, |
| 1871 | <&clock_debug clk_gcc_debug_mux>, |
| 1872 | <&clock_gcc clk_wcnss_m_clk>; |
| 1873 | |
| 1874 | clock-names = "xo", "rf_clk", "measure", "wcnss_debug"; |
| 1875 | |
| 1876 | qcom,has-autodetect-xo; |
| 1877 | qcom,is-pronto-v3; |
| 1878 | qcom,has-pronto-hw; |
| 1879 | qcom,has-vsys-adc-channel; |
| 1880 | qcom,has-a2xb-split-reg; |
| 1881 | qcom,wcnss-adc_tm = <&pm8953_adc_tm>; |
| 1882 | }; |
| 1883 | |
Srinivas Ramana | 3cac278 | 2017-09-13 16:31:17 +0530 | [diff] [blame] | 1884 | }; |
Kiran Gunda | 0954f39 | 2017-10-16 16:24:55 +0530 | [diff] [blame] | 1885 | |
| 1886 | #include "pm8953-rpm-regulator.dtsi" |
| 1887 | #include "pm8953.dtsi" |
| 1888 | #include "msm8953-regulator.dtsi" |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 1889 | #include "msm-gdsc-8916.dtsi" |
Manaf Meethalavalappu Pallikunhi | 4eb2b27 | 2018-01-02 17:29:37 +0530 | [diff] [blame] | 1890 | #include "msm8953-thermal.dtsi" |
Shefali Jain | 44e24ad | 2017-11-23 12:27:33 +0530 | [diff] [blame] | 1891 | |
| 1892 | &gdsc_venus { |
| 1893 | clock-names = "bus_clk", "core_clk"; |
| 1894 | clocks = <&clock_gcc clk_gcc_venus0_axi_clk>, |
| 1895 | <&clock_gcc clk_gcc_venus0_vcodec0_clk>; |
| 1896 | status = "okay"; |
| 1897 | }; |
| 1898 | |
| 1899 | &gdsc_venus_core0 { |
| 1900 | qcom,support-hw-trigger; |
| 1901 | clock-names ="core0_clk"; |
| 1902 | clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>; |
| 1903 | status = "okay"; |
| 1904 | }; |
| 1905 | |
| 1906 | &gdsc_mdss { |
| 1907 | clock-names = "core_clk", "bus_clk"; |
| 1908 | clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, |
| 1909 | <&clock_gcc clk_gcc_mdss_axi_clk>; |
| 1910 | proxy-supply = <&gdsc_mdss>; |
| 1911 | qcom,proxy-consumer-enable; |
| 1912 | status = "okay"; |
| 1913 | }; |
| 1914 | |
| 1915 | &gdsc_oxili_gx { |
| 1916 | clock-names = "core_root_clk"; |
| 1917 | clocks =<&clock_gcc_gfx clk_gfx3d_clk_src>; |
| 1918 | qcom,force-enable-root-clk; |
| 1919 | parent-supply = <&gfx_vreg_corner>; |
| 1920 | status = "okay"; |
| 1921 | }; |
| 1922 | |
| 1923 | &gdsc_jpeg { |
| 1924 | clock-names = "core_clk", "bus_clk"; |
| 1925 | clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>, |
| 1926 | <&clock_gcc clk_gcc_camss_jpeg_axi_clk>; |
| 1927 | status = "okay"; |
| 1928 | }; |
| 1929 | |
| 1930 | &gdsc_vfe { |
| 1931 | clock-names = "core_clk", "bus_clk", "micro_clk", |
| 1932 | "csi_clk"; |
| 1933 | clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>, |
| 1934 | <&clock_gcc clk_gcc_camss_vfe_axi_clk>, |
| 1935 | <&clock_gcc clk_gcc_camss_micro_ahb_clk>, |
| 1936 | <&clock_gcc clk_gcc_camss_csi_vfe0_clk>; |
| 1937 | status = "okay"; |
| 1938 | }; |
| 1939 | |
| 1940 | &gdsc_vfe1 { |
| 1941 | clock-names = "core_clk", "bus_clk", "micro_clk", |
| 1942 | "csi_clk"; |
| 1943 | clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>, |
| 1944 | <&clock_gcc clk_gcc_camss_vfe1_axi_clk>, |
| 1945 | <&clock_gcc clk_gcc_camss_micro_ahb_clk>, |
| 1946 | <&clock_gcc clk_gcc_camss_csi_vfe1_clk>; |
| 1947 | status = "okay"; |
| 1948 | }; |
| 1949 | |
| 1950 | &gdsc_cpp { |
| 1951 | clock-names = "core_clk", "bus_clk"; |
| 1952 | clocks = <&clock_gcc clk_gcc_camss_cpp_clk>, |
| 1953 | <&clock_gcc clk_gcc_camss_cpp_axi_clk>; |
| 1954 | status = "okay"; |
| 1955 | }; |
| 1956 | |
| 1957 | &gdsc_oxili_cx { |
| 1958 | clock-names = "core_clk"; |
| 1959 | clocks = <&clock_gcc_gfx clk_gcc_oxili_gfx3d_clk>; |
| 1960 | status = "okay"; |
| 1961 | }; |
| 1962 | |
| 1963 | &gdsc_usb30 { |
| 1964 | status = "okay"; |
| 1965 | }; |