Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/drm_crtc.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 35 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 37 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 40 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 41 | /** |
| 42 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 43 | * @intel_dp: DP struct |
| 44 | * |
| 45 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 46 | * will return true, and false otherwise. |
| 47 | */ |
| 48 | static bool is_edp(struct intel_dp *intel_dp) |
| 49 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 51 | |
| 52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 53 | } |
| 54 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 55 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
| 56 | { |
| 57 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 58 | |
| 59 | return intel_dig_port->base.base.dev; |
| 60 | } |
| 61 | |
Adam Jackson | 1c95822 | 2011-10-14 17:22:25 -0400 | [diff] [blame] | 62 | /** |
| 63 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? |
| 64 | * @intel_dp: DP struct |
| 65 | * |
| 66 | * Returns true if the given DP struct corresponds to a CPU eDP port. |
| 67 | */ |
| 68 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
| 69 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 70 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 71 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 72 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 73 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 74 | return is_edp(intel_dp) && |
| 75 | (port == PORT_A || (port == PORT_C && IS_VALLEYVIEW(dev))); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 76 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 77 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 78 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 79 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 80 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 81 | } |
| 82 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 83 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 84 | |
| 85 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 86 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 87 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 88 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 89 | |
| 90 | switch (max_link_bw) { |
| 91 | case DP_LINK_BW_1_62: |
| 92 | case DP_LINK_BW_2_7: |
| 93 | break; |
| 94 | default: |
| 95 | max_link_bw = DP_LINK_BW_1_62; |
| 96 | break; |
| 97 | } |
| 98 | return max_link_bw; |
| 99 | } |
| 100 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 101 | /* |
| 102 | * The units on the numbers in the next two are... bizarre. Examples will |
| 103 | * make it clearer; this one parallels an example in the eDP spec. |
| 104 | * |
| 105 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 106 | * |
| 107 | * 270000 * 1 * 8 / 10 == 216000 |
| 108 | * |
| 109 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 110 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 111 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 112 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 113 | * |
| 114 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 115 | * get the result in decakilobits instead of kilobits. |
| 116 | */ |
| 117 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 118 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 119 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 120 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 121 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 125 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 126 | { |
| 127 | return (max_link_clock * max_lanes * 8) / 10; |
| 128 | } |
| 129 | |
| 130 | static int |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 131 | intel_dp_mode_valid(struct drm_connector *connector, |
| 132 | struct drm_display_mode *mode) |
| 133 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 134 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 135 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 136 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 137 | int target_clock = mode->clock; |
| 138 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 139 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 140 | if (is_edp(intel_dp) && fixed_mode) { |
| 141 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 142 | return MODE_PANEL; |
| 143 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 144 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 145 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 146 | |
| 147 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 148 | } |
| 149 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 150 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
| 151 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
| 152 | |
| 153 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 154 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 155 | |
| 156 | if (mode_rate > max_rate) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 157 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 158 | |
| 159 | if (mode->clock < 10000) |
| 160 | return MODE_CLOCK_LOW; |
| 161 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 162 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 163 | return MODE_H_ILLEGAL; |
| 164 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 165 | return MODE_OK; |
| 166 | } |
| 167 | |
| 168 | static uint32_t |
| 169 | pack_aux(uint8_t *src, int src_bytes) |
| 170 | { |
| 171 | int i; |
| 172 | uint32_t v = 0; |
| 173 | |
| 174 | if (src_bytes > 4) |
| 175 | src_bytes = 4; |
| 176 | for (i = 0; i < src_bytes; i++) |
| 177 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 178 | return v; |
| 179 | } |
| 180 | |
| 181 | static void |
| 182 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 183 | { |
| 184 | int i; |
| 185 | if (dst_bytes > 4) |
| 186 | dst_bytes = 4; |
| 187 | for (i = 0; i < dst_bytes; i++) |
| 188 | dst[i] = src >> ((3-i) * 8); |
| 189 | } |
| 190 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 191 | /* hrawclock is 1/4 the FSB frequency */ |
| 192 | static int |
| 193 | intel_hrawclk(struct drm_device *dev) |
| 194 | { |
| 195 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 196 | uint32_t clkcfg; |
| 197 | |
Vijay Purushothaman | 9473c8f | 2012-09-27 19:13:01 +0530 | [diff] [blame] | 198 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
| 199 | if (IS_VALLEYVIEW(dev)) |
| 200 | return 200; |
| 201 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 202 | clkcfg = I915_READ(CLKCFG); |
| 203 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 204 | case CLKCFG_FSB_400: |
| 205 | return 100; |
| 206 | case CLKCFG_FSB_533: |
| 207 | return 133; |
| 208 | case CLKCFG_FSB_667: |
| 209 | return 166; |
| 210 | case CLKCFG_FSB_800: |
| 211 | return 200; |
| 212 | case CLKCFG_FSB_1067: |
| 213 | return 266; |
| 214 | case CLKCFG_FSB_1333: |
| 215 | return 333; |
| 216 | /* these two are just a guess; one of them might be right */ |
| 217 | case CLKCFG_FSB_1600: |
| 218 | case CLKCFG_FSB_1600_ALT: |
| 219 | return 400; |
| 220 | default: |
| 221 | return 133; |
| 222 | } |
| 223 | } |
| 224 | |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 225 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
| 226 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 227 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 228 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 229 | u32 pp_stat_reg; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 230 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 231 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
| 232 | return (I915_READ(pp_stat_reg) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 233 | } |
| 234 | |
| 235 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
| 236 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 237 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 238 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 239 | u32 pp_ctrl_reg; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 240 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 241 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 242 | return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 243 | } |
| 244 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 245 | static void |
| 246 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 247 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 248 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 249 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 250 | u32 pp_stat_reg, pp_ctrl_reg; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 251 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 252 | if (!is_edp(intel_dp)) |
| 253 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 254 | |
| 255 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
| 256 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 257 | |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 258 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 259 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 260 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 261 | I915_READ(pp_stat_reg), |
| 262 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 263 | } |
| 264 | } |
| 265 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 266 | static uint32_t |
| 267 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 268 | { |
| 269 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 270 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 271 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 272 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 273 | uint32_t status; |
| 274 | bool done; |
| 275 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 276 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 277 | if (has_aux_irq) |
Paulo Zanoni | b90f517 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 278 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
| 279 | msecs_to_jiffies(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 280 | else |
| 281 | done = wait_for_atomic(C, 10) == 0; |
| 282 | if (!done) |
| 283 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 284 | has_aux_irq); |
| 285 | #undef C |
| 286 | |
| 287 | return status; |
| 288 | } |
| 289 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 290 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 291 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 292 | uint8_t *send, int send_bytes, |
| 293 | uint8_t *recv, int recv_size) |
| 294 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 296 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 297 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 298 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 299 | uint32_t ch_data = ch_ctl + 4; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 300 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 301 | uint32_t status; |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 302 | uint32_t aux_clock_divider; |
Daniel Vetter | 6b4e0a9 | 2012-06-14 22:15:00 +0200 | [diff] [blame] | 303 | int try, precharge; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 304 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
| 305 | |
| 306 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 307 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 308 | * deep sleep states. |
| 309 | */ |
| 310 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 311 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 312 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 313 | /* The clock divider is based off the hrawclk, |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 314 | * and would like to run at 2MHz. So, take the |
| 315 | * hrawclk value and divide by 2 and use that |
Jesse Barnes | 6176b8f | 2010-09-08 12:42:00 -0700 | [diff] [blame] | 316 | * |
| 317 | * Note that PCH attached eDP panels should use a 125MHz input |
| 318 | * clock divider. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 319 | */ |
Imre Deak | a62d083 | 2013-05-16 14:40:35 +0300 | [diff] [blame^] | 320 | if (IS_VALLEYVIEW(dev)) { |
| 321 | aux_clock_divider = 100; |
| 322 | } else if (intel_dig_port->port == PORT_A) { |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 323 | if (HAS_DDI(dev)) |
Paulo Zanoni | b2b877f | 2013-05-03 17:23:42 -0300 | [diff] [blame] | 324 | aux_clock_divider = DIV_ROUND_CLOSEST( |
| 325 | intel_ddi_get_cdclk_freq(dev_priv), 2000); |
Vijay Purushothaman | 9473c8f | 2012-09-27 19:13:01 +0530 | [diff] [blame] | 326 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 327 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 328 | else |
| 329 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
Jani Nikula | 2c55c33 | 2013-04-09 08:11:00 +0300 | [diff] [blame] | 330 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 331 | /* Workaround for non-ULT HSW */ |
| 332 | aux_clock_divider = 74; |
| 333 | } else if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | 6b3ec1c | 2012-10-20 20:57:44 +0200 | [diff] [blame] | 334 | aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
Jani Nikula | 2c55c33 | 2013-04-09 08:11:00 +0300 | [diff] [blame] | 335 | } else { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 336 | aux_clock_divider = intel_hrawclk(dev) / 2; |
Jani Nikula | 2c55c33 | 2013-04-09 08:11:00 +0300 | [diff] [blame] | 337 | } |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 338 | |
Daniel Vetter | 6b4e0a9 | 2012-06-14 22:15:00 +0200 | [diff] [blame] | 339 | if (IS_GEN6(dev)) |
| 340 | precharge = 3; |
| 341 | else |
| 342 | precharge = 5; |
| 343 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 344 | /* Try to wait for any previous AUX channel activity */ |
| 345 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 346 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 347 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 348 | break; |
| 349 | msleep(1); |
| 350 | } |
| 351 | |
| 352 | if (try == 3) { |
| 353 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 354 | I915_READ(ch_ctl)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 355 | ret = -EBUSY; |
| 356 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 357 | } |
| 358 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 359 | /* Must try at least 3 times according to DP spec */ |
| 360 | for (try = 0; try < 5; try++) { |
| 361 | /* Load the send data into the aux channel data registers */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 362 | for (i = 0; i < send_bytes; i += 4) |
| 363 | I915_WRITE(ch_data + i, |
| 364 | pack_aux(send + i, send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 365 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 366 | /* Send the command and wait for it to complete */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 367 | I915_WRITE(ch_ctl, |
| 368 | DP_AUX_CH_CTL_SEND_BUSY | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 369 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 370 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 371 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 372 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 373 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
| 374 | DP_AUX_CH_CTL_DONE | |
| 375 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 376 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 377 | |
| 378 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 379 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 380 | /* Clear done status and any errors */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 381 | I915_WRITE(ch_ctl, |
| 382 | status | |
| 383 | DP_AUX_CH_CTL_DONE | |
| 384 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 385 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 386 | |
| 387 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 388 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
| 389 | continue; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 390 | if (status & DP_AUX_CH_CTL_DONE) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 391 | break; |
| 392 | } |
| 393 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 394 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 395 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 396 | ret = -EBUSY; |
| 397 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | /* Check for timeout or receive error. |
| 401 | * Timeouts occur when the sink is not connected |
| 402 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 403 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 404 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 405 | ret = -EIO; |
| 406 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 407 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 408 | |
| 409 | /* Timeouts occur when the device isn't connected, so they're |
| 410 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 411 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 412 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 413 | ret = -ETIMEDOUT; |
| 414 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 415 | } |
| 416 | |
| 417 | /* Unload any bytes sent back from the other side */ |
| 418 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 419 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 420 | if (recv_bytes > recv_size) |
| 421 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 422 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 423 | for (i = 0; i < recv_bytes; i += 4) |
| 424 | unpack_aux(I915_READ(ch_data + i), |
| 425 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 426 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 427 | ret = recv_bytes; |
| 428 | out: |
| 429 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 430 | |
| 431 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | /* Write data to the aux channel in native mode */ |
| 435 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 436 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 437 | uint16_t address, uint8_t *send, int send_bytes) |
| 438 | { |
| 439 | int ret; |
| 440 | uint8_t msg[20]; |
| 441 | int msg_bytes; |
| 442 | uint8_t ack; |
| 443 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 444 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 445 | if (send_bytes > 16) |
| 446 | return -1; |
| 447 | msg[0] = AUX_NATIVE_WRITE << 4; |
| 448 | msg[1] = address >> 8; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 449 | msg[2] = address & 0xff; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 450 | msg[3] = send_bytes - 1; |
| 451 | memcpy(&msg[4], send, send_bytes); |
| 452 | msg_bytes = send_bytes + 4; |
| 453 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 454 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 455 | if (ret < 0) |
| 456 | return ret; |
| 457 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
| 458 | break; |
| 459 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 460 | udelay(100); |
| 461 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 462 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 463 | } |
| 464 | return send_bytes; |
| 465 | } |
| 466 | |
| 467 | /* Write a single byte to the aux channel in native mode */ |
| 468 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 469 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 470 | uint16_t address, uint8_t byte) |
| 471 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 472 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | /* read bytes from a native aux channel */ |
| 476 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 477 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 478 | uint16_t address, uint8_t *recv, int recv_bytes) |
| 479 | { |
| 480 | uint8_t msg[4]; |
| 481 | int msg_bytes; |
| 482 | uint8_t reply[20]; |
| 483 | int reply_bytes; |
| 484 | uint8_t ack; |
| 485 | int ret; |
| 486 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 487 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 488 | msg[0] = AUX_NATIVE_READ << 4; |
| 489 | msg[1] = address >> 8; |
| 490 | msg[2] = address & 0xff; |
| 491 | msg[3] = recv_bytes - 1; |
| 492 | |
| 493 | msg_bytes = 4; |
| 494 | reply_bytes = recv_bytes + 1; |
| 495 | |
| 496 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 497 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 498 | reply, reply_bytes); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 499 | if (ret == 0) |
| 500 | return -EPROTO; |
| 501 | if (ret < 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 502 | return ret; |
| 503 | ack = reply[0]; |
| 504 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
| 505 | memcpy(recv, reply + 1, ret - 1); |
| 506 | return ret - 1; |
| 507 | } |
| 508 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 509 | udelay(100); |
| 510 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 511 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 512 | } |
| 513 | } |
| 514 | |
| 515 | static int |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 516 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 517 | uint8_t write_byte, uint8_t *read_byte) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 518 | { |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 519 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 520 | struct intel_dp *intel_dp = container_of(adapter, |
| 521 | struct intel_dp, |
| 522 | adapter); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 523 | uint16_t address = algo_data->address; |
| 524 | uint8_t msg[5]; |
| 525 | uint8_t reply[2]; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 526 | unsigned retry; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 527 | int msg_bytes; |
| 528 | int reply_bytes; |
| 529 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 530 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 531 | intel_dp_check_edp(intel_dp); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 532 | /* Set up the command byte */ |
| 533 | if (mode & MODE_I2C_READ) |
| 534 | msg[0] = AUX_I2C_READ << 4; |
| 535 | else |
| 536 | msg[0] = AUX_I2C_WRITE << 4; |
| 537 | |
| 538 | if (!(mode & MODE_I2C_STOP)) |
| 539 | msg[0] |= AUX_I2C_MOT << 4; |
| 540 | |
| 541 | msg[1] = address >> 8; |
| 542 | msg[2] = address; |
| 543 | |
| 544 | switch (mode) { |
| 545 | case MODE_I2C_WRITE: |
| 546 | msg[3] = 0; |
| 547 | msg[4] = write_byte; |
| 548 | msg_bytes = 5; |
| 549 | reply_bytes = 1; |
| 550 | break; |
| 551 | case MODE_I2C_READ: |
| 552 | msg[3] = 0; |
| 553 | msg_bytes = 4; |
| 554 | reply_bytes = 2; |
| 555 | break; |
| 556 | default: |
| 557 | msg_bytes = 3; |
| 558 | reply_bytes = 1; |
| 559 | break; |
| 560 | } |
| 561 | |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 562 | for (retry = 0; retry < 5; retry++) { |
| 563 | ret = intel_dp_aux_ch(intel_dp, |
| 564 | msg, msg_bytes, |
| 565 | reply, reply_bytes); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 566 | if (ret < 0) { |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 567 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 568 | return ret; |
| 569 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 570 | |
| 571 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { |
| 572 | case AUX_NATIVE_REPLY_ACK: |
| 573 | /* I2C-over-AUX Reply field is only valid |
| 574 | * when paired with AUX ACK. |
| 575 | */ |
| 576 | break; |
| 577 | case AUX_NATIVE_REPLY_NACK: |
| 578 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
| 579 | return -EREMOTEIO; |
| 580 | case AUX_NATIVE_REPLY_DEFER: |
| 581 | udelay(100); |
| 582 | continue; |
| 583 | default: |
| 584 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
| 585 | reply[0]); |
| 586 | return -EREMOTEIO; |
| 587 | } |
| 588 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 589 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
| 590 | case AUX_I2C_REPLY_ACK: |
| 591 | if (mode == MODE_I2C_READ) { |
| 592 | *read_byte = reply[1]; |
| 593 | } |
| 594 | return reply_bytes - 1; |
| 595 | case AUX_I2C_REPLY_NACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 596 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 597 | return -EREMOTEIO; |
| 598 | case AUX_I2C_REPLY_DEFER: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 599 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 600 | udelay(100); |
| 601 | break; |
| 602 | default: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 603 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 604 | return -EREMOTEIO; |
| 605 | } |
| 606 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 607 | |
| 608 | DRM_ERROR("too many retries, giving up\n"); |
| 609 | return -EREMOTEIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 610 | } |
| 611 | |
| 612 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 613 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 614 | struct intel_connector *intel_connector, const char *name) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 615 | { |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 616 | int ret; |
| 617 | |
Zhenyu Wang | d54e9d2 | 2009-10-19 15:43:51 +0800 | [diff] [blame] | 618 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 619 | intel_dp->algo.running = false; |
| 620 | intel_dp->algo.address = 0; |
| 621 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 622 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 623 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 624 | intel_dp->adapter.owner = THIS_MODULE; |
| 625 | intel_dp->adapter.class = I2C_CLASS_DDC; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 626 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 627 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
| 628 | intel_dp->adapter.algo_data = &intel_dp->algo; |
| 629 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; |
| 630 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 631 | ironlake_edp_panel_vdd_on(intel_dp); |
| 632 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 633 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 634 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 635 | } |
| 636 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 637 | static void |
| 638 | intel_dp_set_clock(struct intel_encoder *encoder, |
| 639 | struct intel_crtc_config *pipe_config, int link_bw) |
| 640 | { |
| 641 | struct drm_device *dev = encoder->base.dev; |
| 642 | |
| 643 | if (IS_G4X(dev)) { |
| 644 | if (link_bw == DP_LINK_BW_1_62) { |
| 645 | pipe_config->dpll.p1 = 2; |
| 646 | pipe_config->dpll.p2 = 10; |
| 647 | pipe_config->dpll.n = 2; |
| 648 | pipe_config->dpll.m1 = 23; |
| 649 | pipe_config->dpll.m2 = 8; |
| 650 | } else { |
| 651 | pipe_config->dpll.p1 = 1; |
| 652 | pipe_config->dpll.p2 = 10; |
| 653 | pipe_config->dpll.n = 1; |
| 654 | pipe_config->dpll.m1 = 14; |
| 655 | pipe_config->dpll.m2 = 2; |
| 656 | } |
| 657 | pipe_config->clock_set = true; |
| 658 | } else if (IS_HASWELL(dev)) { |
| 659 | /* Haswell has special-purpose DP DDI clocks. */ |
| 660 | } else if (HAS_PCH_SPLIT(dev)) { |
| 661 | if (link_bw == DP_LINK_BW_1_62) { |
| 662 | pipe_config->dpll.n = 1; |
| 663 | pipe_config->dpll.p1 = 2; |
| 664 | pipe_config->dpll.p2 = 10; |
| 665 | pipe_config->dpll.m1 = 12; |
| 666 | pipe_config->dpll.m2 = 9; |
| 667 | } else { |
| 668 | pipe_config->dpll.n = 2; |
| 669 | pipe_config->dpll.p1 = 1; |
| 670 | pipe_config->dpll.p2 = 10; |
| 671 | pipe_config->dpll.m1 = 14; |
| 672 | pipe_config->dpll.m2 = 8; |
| 673 | } |
| 674 | pipe_config->clock_set = true; |
| 675 | } else if (IS_VALLEYVIEW(dev)) { |
| 676 | /* FIXME: Need to figure out optimized DP clocks for vlv. */ |
| 677 | } |
| 678 | } |
| 679 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 680 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 681 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 682 | struct intel_crtc_config *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 683 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 684 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 685 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 686 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 687 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 688 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 689 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 690 | int lane_count, clock; |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 691 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 692 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 693 | int bpp, mode_rate; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 694 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 695 | int target_clock, link_avail, link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 696 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 697 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp)) |
| 698 | pipe_config->has_pch_encoder = true; |
| 699 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 700 | pipe_config->has_dp_encoder = true; |
| 701 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 702 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 703 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 704 | adjusted_mode); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 705 | if (!HAS_PCH_SPLIT(dev)) |
| 706 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 707 | intel_connector->panel.fitting_mode); |
| 708 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 709 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 710 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 711 | } |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 712 | /* We need to take the panel's fixed mode into account. */ |
| 713 | target_clock = adjusted_mode->clock; |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 714 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 715 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 716 | return false; |
| 717 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 718 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| 719 | "max bw %02x pixel clock %iKHz\n", |
Daniel Vetter | 7124465 | 2012-06-04 18:39:20 +0200 | [diff] [blame] | 720 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 721 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 722 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 723 | * bpc in between. */ |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 724 | bpp = min_t(int, 8*3, pipe_config->pipe_bpp); |
Daniel Vetter | e1b73cb | 2013-05-21 09:52:16 +0200 | [diff] [blame] | 725 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) |
| 726 | bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp); |
Daniel Vetter | af13188 | 2013-02-19 17:45:00 +0100 | [diff] [blame] | 727 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 728 | for (; bpp >= 6*3; bpp -= 2*3) { |
| 729 | mode_rate = intel_dp_link_required(target_clock, bpp); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 730 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 731 | for (clock = 0; clock <= max_clock; clock++) { |
| 732 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
| 733 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
| 734 | link_avail = intel_dp_max_data_rate(link_clock, |
| 735 | lane_count); |
| 736 | |
| 737 | if (mode_rate <= link_avail) { |
| 738 | goto found; |
| 739 | } |
| 740 | } |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | return false; |
| 745 | |
| 746 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 747 | if (intel_dp->color_range_auto) { |
| 748 | /* |
| 749 | * See: |
| 750 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 751 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 752 | */ |
Thierry Reding | 18316c8 | 2012-12-20 15:41:44 +0100 | [diff] [blame] | 753 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 754 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 755 | else |
| 756 | intel_dp->color_range = 0; |
| 757 | } |
| 758 | |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 759 | if (intel_dp->color_range) |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 760 | pipe_config->limited_color_range = true; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 761 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 762 | intel_dp->link_bw = bws[clock]; |
| 763 | intel_dp->lane_count = lane_count; |
| 764 | adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 765 | pipe_config->pipe_bpp = bpp; |
Daniel Vetter | df92b1e | 2013-03-28 10:41:58 +0100 | [diff] [blame] | 766 | pipe_config->pixel_target_clock = target_clock; |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 767 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 768 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
| 769 | intel_dp->link_bw, intel_dp->lane_count, |
| 770 | adjusted_mode->clock, bpp); |
| 771 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 772 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 773 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 774 | intel_link_compute_m_n(bpp, lane_count, |
| 775 | target_clock, adjusted_mode->clock, |
| 776 | &pipe_config->dp_m_n); |
| 777 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 778 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
| 779 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 780 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 781 | } |
| 782 | |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 783 | void intel_dp_init_link_config(struct intel_dp *intel_dp) |
| 784 | { |
| 785 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
| 786 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
| 787 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
| 788 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
| 789 | /* |
| 790 | * Check for DPCD version > 1.1 and enhanced framing support |
| 791 | */ |
| 792 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 793 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
| 794 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 795 | } |
| 796 | } |
| 797 | |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 798 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
| 799 | { |
| 800 | struct drm_device *dev = crtc->dev; |
| 801 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 802 | u32 dpa_ctl; |
| 803 | |
| 804 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
| 805 | dpa_ctl = I915_READ(DP_A); |
| 806 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 807 | |
| 808 | if (clock < 200000) { |
Daniel Vetter | 1ce1703 | 2012-11-29 15:59:32 +0100 | [diff] [blame] | 809 | /* For a long time we've carried around a ILK-DevA w/a for the |
| 810 | * 160MHz clock. If we're really unlucky, it's still required. |
| 811 | */ |
| 812 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 813 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 814 | } else { |
| 815 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 816 | } |
Daniel Vetter | 1ce1703 | 2012-11-29 15:59:32 +0100 | [diff] [blame] | 817 | |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 818 | I915_WRITE(DP_A, dpa_ctl); |
| 819 | |
| 820 | POSTING_READ(DP_A); |
| 821 | udelay(500); |
| 822 | } |
| 823 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 824 | static void |
| 825 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 826 | struct drm_display_mode *adjusted_mode) |
| 827 | { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 828 | struct drm_device *dev = encoder->dev; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 829 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 830 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 831 | struct drm_crtc *crtc = encoder->crtc; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 833 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 834 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 835 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 836 | * |
| 837 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 838 | * SNB CPU |
| 839 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 840 | * CPT PCH |
| 841 | * |
| 842 | * IBX PCH and CPU are the same for almost everything, |
| 843 | * except that the CPU DP PLL is configured in this |
| 844 | * register |
| 845 | * |
| 846 | * CPT PCH is quite different, having many bits moved |
| 847 | * to the TRANS_DP_CTL register instead. That |
| 848 | * configuration happens (oddly) in ironlake_pch_enable |
| 849 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 850 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 851 | /* Preserve the BIOS-computed detected bit. This is |
| 852 | * supposed to be read-only. |
| 853 | */ |
| 854 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 855 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 856 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 857 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Daniel Vetter | 17aa6be | 2013-04-30 14:01:40 +0200 | [diff] [blame] | 858 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 859 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 860 | if (intel_dp->has_audio) { |
| 861 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
| 862 | pipe_name(intel_crtc->pipe)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 863 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 864 | intel_write_eld(encoder, adjusted_mode); |
| 865 | } |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 866 | |
| 867 | intel_dp_init_link_config(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 868 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 869 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 870 | |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 871 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 872 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 873 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 874 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 875 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 876 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 877 | |
| 878 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
| 879 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 880 | |
| 881 | intel_dp->DP |= intel_crtc->pipe << 29; |
| 882 | |
| 883 | /* don't miss out required setting for eDP */ |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 884 | if (adjusted_mode->clock < 200000) |
| 885 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
| 886 | else |
| 887 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 888 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 889 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 890 | intel_dp->DP |= intel_dp->color_range; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 891 | |
| 892 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 893 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 894 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 895 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 896 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 897 | |
| 898 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
| 899 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 900 | |
| 901 | if (intel_crtc->pipe == 1) |
| 902 | intel_dp->DP |= DP_PIPEB_SELECT; |
| 903 | |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 904 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 905 | /* don't miss out required setting for eDP */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 906 | if (adjusted_mode->clock < 200000) |
| 907 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
| 908 | else |
| 909 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 910 | } |
| 911 | } else { |
| 912 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 913 | } |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 914 | |
Jesse Barnes | 5d66d5b | 2013-03-01 13:14:30 -0800 | [diff] [blame] | 915 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 916 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 917 | } |
| 918 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 919 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 920 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
| 921 | |
| 922 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 923 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| 924 | |
| 925 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 926 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| 927 | |
| 928 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
| 929 | u32 mask, |
| 930 | u32 value) |
| 931 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 932 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 933 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 934 | u32 pp_stat_reg, pp_ctrl_reg; |
| 935 | |
| 936 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
| 937 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 938 | |
| 939 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 940 | mask, value, |
| 941 | I915_READ(pp_stat_reg), |
| 942 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 943 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 944 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 945 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 946 | I915_READ(pp_stat_reg), |
| 947 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 948 | } |
| 949 | } |
| 950 | |
| 951 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
| 952 | { |
| 953 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
| 954 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
| 955 | } |
| 956 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 957 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
| 958 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 959 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 960 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 961 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 962 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 963 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) |
| 964 | { |
| 965 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
| 966 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
| 967 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 968 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 969 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 970 | /* Read the current pp_control value, unlocking the register if it |
| 971 | * is locked |
| 972 | */ |
| 973 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 974 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 975 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 976 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 977 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 978 | u32 control; |
| 979 | u32 pp_ctrl_reg; |
| 980 | |
| 981 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 982 | control = I915_READ(pp_ctrl_reg); |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 983 | |
| 984 | control &= ~PANEL_UNLOCK_MASK; |
| 985 | control |= PANEL_UNLOCK_REGS; |
| 986 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 987 | } |
| 988 | |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 989 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 990 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 991 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 992 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 993 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 994 | u32 pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 995 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 996 | if (!is_edp(intel_dp)) |
| 997 | return; |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 998 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 999 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1000 | WARN(intel_dp->want_panel_vdd, |
| 1001 | "eDP VDD already requested on\n"); |
| 1002 | |
| 1003 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1004 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1005 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
| 1006 | DRM_DEBUG_KMS("eDP VDD already on\n"); |
| 1007 | return; |
| 1008 | } |
| 1009 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1010 | if (!ironlake_edp_have_panel_power(intel_dp)) |
| 1011 | ironlake_wait_panel_power_cycle(intel_dp); |
| 1012 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1013 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1014 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1015 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1016 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
| 1017 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 1018 | |
| 1019 | I915_WRITE(pp_ctrl_reg, pp); |
| 1020 | POSTING_READ(pp_ctrl_reg); |
| 1021 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1022 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1023 | /* |
| 1024 | * If the panel wasn't on, delay before accessing aux channel |
| 1025 | */ |
| 1026 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1027 | DRM_DEBUG_KMS("eDP was not running\n"); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1028 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1029 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1030 | } |
| 1031 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1032 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1033 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1034 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1035 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1036 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1037 | u32 pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1038 | |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1039 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 1040 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1041 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1042 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1043 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1044 | |
| 1045 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
| 1046 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 1047 | |
| 1048 | I915_WRITE(pp_ctrl_reg, pp); |
| 1049 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1050 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1051 | /* Make sure sequencer is idle before allowing subsequent activity */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1052 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1053 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1054 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1055 | } |
| 1056 | } |
| 1057 | |
| 1058 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
| 1059 | { |
| 1060 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1061 | struct intel_dp, panel_vdd_work); |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1062 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1063 | |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1064 | mutex_lock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1065 | ironlake_panel_vdd_off_sync(intel_dp); |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1066 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1067 | } |
| 1068 | |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 1069 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1070 | { |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1071 | if (!is_edp(intel_dp)) |
| 1072 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1073 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1074 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
| 1075 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 1076 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1077 | intel_dp->want_panel_vdd = false; |
| 1078 | |
| 1079 | if (sync) { |
| 1080 | ironlake_panel_vdd_off_sync(intel_dp); |
| 1081 | } else { |
| 1082 | /* |
| 1083 | * Queue the timer to fire a long |
| 1084 | * time from now (relative to the power down delay) |
| 1085 | * to keep the panel power up across a sequence of operations |
| 1086 | */ |
| 1087 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
| 1088 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
| 1089 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1090 | } |
| 1091 | |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 1092 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1093 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1094 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1096 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1097 | u32 pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1098 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1099 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1100 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1101 | |
| 1102 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
| 1103 | |
| 1104 | if (ironlake_edp_have_panel_power(intel_dp)) { |
| 1105 | DRM_DEBUG_KMS("eDP power already on\n"); |
Keith Packard | 7d639f3 | 2011-09-29 16:05:34 -0700 | [diff] [blame] | 1106 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1107 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1108 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1109 | ironlake_wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1110 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1111 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1112 | if (IS_GEN5(dev)) { |
| 1113 | /* ILK workaround: disable reset around power sequence */ |
| 1114 | pp &= ~PANEL_POWER_RESET; |
| 1115 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1116 | POSTING_READ(PCH_PP_CONTROL); |
| 1117 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1118 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1119 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1120 | if (!IS_GEN5(dev)) |
| 1121 | pp |= PANEL_POWER_RESET; |
| 1122 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1123 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 1124 | |
| 1125 | I915_WRITE(pp_ctrl_reg, pp); |
| 1126 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1127 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1128 | ironlake_wait_panel_on(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1129 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1130 | if (IS_GEN5(dev)) { |
| 1131 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| 1132 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1133 | POSTING_READ(PCH_PP_CONTROL); |
| 1134 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1135 | } |
| 1136 | |
Paulo Zanoni | 82a4d9c | 2012-10-23 18:30:07 -0200 | [diff] [blame] | 1137 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1138 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1139 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1141 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1142 | u32 pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1143 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1144 | if (!is_edp(intel_dp)) |
| 1145 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1146 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1147 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1148 | |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 1149 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1150 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1151 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1152 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 1153 | * panels get very unhappy and cease to work. */ |
| 1154 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1155 | |
| 1156 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 1157 | |
| 1158 | I915_WRITE(pp_ctrl_reg, pp); |
| 1159 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1160 | |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1161 | intel_dp->want_panel_vdd = false; |
| 1162 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1163 | ironlake_wait_panel_off(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1164 | } |
| 1165 | |
Paulo Zanoni | d6c50ff | 2012-10-23 18:30:06 -0200 | [diff] [blame] | 1166 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1167 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1168 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1169 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1170 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1171 | int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1172 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1173 | u32 pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1174 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1175 | if (!is_edp(intel_dp)) |
| 1176 | return; |
| 1177 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1178 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1179 | /* |
| 1180 | * If we enable the backlight right away following a panel power |
| 1181 | * on, we may see slight flicker as the panel syncs with the eDP |
| 1182 | * link. So delay a bit to make sure the image is solid before |
| 1183 | * allowing it to appear. |
| 1184 | */ |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1185 | msleep(intel_dp->backlight_on_delay); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1186 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1187 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1188 | |
| 1189 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 1190 | |
| 1191 | I915_WRITE(pp_ctrl_reg, pp); |
| 1192 | POSTING_READ(pp_ctrl_reg); |
Daniel Vetter | 035aa3d | 2012-10-20 20:57:42 +0200 | [diff] [blame] | 1193 | |
| 1194 | intel_panel_enable_backlight(dev, pipe); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1195 | } |
| 1196 | |
Paulo Zanoni | d6c50ff | 2012-10-23 18:30:06 -0200 | [diff] [blame] | 1197 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1198 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1199 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1200 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1201 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1202 | u32 pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1203 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1204 | if (!is_edp(intel_dp)) |
| 1205 | return; |
| 1206 | |
Daniel Vetter | 035aa3d | 2012-10-20 20:57:42 +0200 | [diff] [blame] | 1207 | intel_panel_disable_backlight(dev); |
| 1208 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1209 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1210 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1211 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1212 | |
| 1213 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
| 1214 | |
| 1215 | I915_WRITE(pp_ctrl_reg, pp); |
| 1216 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1217 | msleep(intel_dp->backlight_off_delay); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1218 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1219 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1220 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1221 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1222 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1223 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1224 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1225 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1226 | u32 dpa_ctl; |
| 1227 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1228 | assert_pipe_disabled(dev_priv, |
| 1229 | to_intel_crtc(crtc)->pipe); |
| 1230 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1231 | DRM_DEBUG_KMS("\n"); |
| 1232 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1233 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
| 1234 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1235 | |
| 1236 | /* We don't adjust intel_dp->DP while tearing down the link, to |
| 1237 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
| 1238 | * enable bits here to ensure that we don't enable too much. */ |
| 1239 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 1240 | intel_dp->DP |= DP_PLL_ENABLE; |
| 1241 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1242 | POSTING_READ(DP_A); |
| 1243 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1244 | } |
| 1245 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1246 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1247 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1248 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1249 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1250 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1251 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1252 | u32 dpa_ctl; |
| 1253 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1254 | assert_pipe_disabled(dev_priv, |
| 1255 | to_intel_crtc(crtc)->pipe); |
| 1256 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1257 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1258 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
| 1259 | "dp pll off, should be on\n"); |
| 1260 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1261 | |
| 1262 | /* We can't rely on the value tracked for the DP register in |
| 1263 | * intel_dp->DP because link_down must not change that (otherwise link |
| 1264 | * re-training will fail. */ |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1265 | dpa_ctl &= ~DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1266 | I915_WRITE(DP_A, dpa_ctl); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 1267 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1268 | udelay(200); |
| 1269 | } |
| 1270 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1271 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1272 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1273 | { |
| 1274 | int ret, i; |
| 1275 | |
| 1276 | /* Should have a valid DPCD by this point */ |
| 1277 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 1278 | return; |
| 1279 | |
| 1280 | if (mode != DRM_MODE_DPMS_ON) { |
| 1281 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
| 1282 | DP_SET_POWER_D3); |
| 1283 | if (ret != 1) |
| 1284 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
| 1285 | } else { |
| 1286 | /* |
| 1287 | * When turning on, we need to retry for 1ms to give the sink |
| 1288 | * time to wake up. |
| 1289 | */ |
| 1290 | for (i = 0; i < 3; i++) { |
| 1291 | ret = intel_dp_aux_native_write_1(intel_dp, |
| 1292 | DP_SET_POWER, |
| 1293 | DP_SET_POWER_D0); |
| 1294 | if (ret == 1) |
| 1295 | break; |
| 1296 | msleep(1); |
| 1297 | } |
| 1298 | } |
| 1299 | } |
| 1300 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1301 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 1302 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1303 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1304 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1305 | struct drm_device *dev = encoder->base.dev; |
| 1306 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1307 | u32 tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1308 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1309 | if (!(tmp & DP_PORT_EN)) |
| 1310 | return false; |
| 1311 | |
Jesse Barnes | 5d66d5b | 2013-03-01 13:14:30 -0800 | [diff] [blame] | 1312 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1313 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 1314 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
| 1315 | *pipe = PORT_TO_PIPE(tmp); |
| 1316 | } else { |
| 1317 | u32 trans_sel; |
| 1318 | u32 trans_dp; |
| 1319 | int i; |
| 1320 | |
| 1321 | switch (intel_dp->output_reg) { |
| 1322 | case PCH_DP_B: |
| 1323 | trans_sel = TRANS_DP_PORT_SEL_B; |
| 1324 | break; |
| 1325 | case PCH_DP_C: |
| 1326 | trans_sel = TRANS_DP_PORT_SEL_C; |
| 1327 | break; |
| 1328 | case PCH_DP_D: |
| 1329 | trans_sel = TRANS_DP_PORT_SEL_D; |
| 1330 | break; |
| 1331 | default: |
| 1332 | return true; |
| 1333 | } |
| 1334 | |
| 1335 | for_each_pipe(i) { |
| 1336 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
| 1337 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
| 1338 | *pipe = i; |
| 1339 | return true; |
| 1340 | } |
| 1341 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1342 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 1343 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
| 1344 | intel_dp->output_reg); |
| 1345 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1346 | |
Daniel Vetter | 2af8898 | 2013-04-04 01:15:45 +0200 | [diff] [blame] | 1347 | return true; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1348 | } |
| 1349 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1350 | static void intel_dp_get_config(struct intel_encoder *encoder, |
| 1351 | struct intel_crtc_config *pipe_config) |
| 1352 | { |
| 1353 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1354 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 1355 | u32 tmp, flags = 0; |
| 1356 | |
| 1357 | tmp = I915_READ(intel_dp->output_reg); |
| 1358 | |
| 1359 | if (tmp & DP_SYNC_HS_HIGH) |
| 1360 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1361 | else |
| 1362 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 1363 | |
| 1364 | if (tmp & DP_SYNC_VS_HIGH) |
| 1365 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1366 | else |
| 1367 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1368 | |
| 1369 | pipe_config->adjusted_mode.flags |= flags; |
| 1370 | } |
| 1371 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1372 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1373 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1374 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1375 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1376 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 1377 | |
| 1378 | /* Make sure the panel is off before trying to change the mode. But also |
| 1379 | * ensure that we have vdd while we switch off the panel. */ |
| 1380 | ironlake_edp_panel_vdd_on(intel_dp); |
Keith Packard | 21264c6 | 2011-11-01 20:25:21 -0700 | [diff] [blame] | 1381 | ironlake_edp_backlight_off(intel_dp); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1382 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1383 | ironlake_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1384 | |
| 1385 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1386 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1387 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1388 | } |
| 1389 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1390 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1391 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1392 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1393 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1394 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1395 | |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1396 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1397 | intel_dp_link_down(intel_dp); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1398 | if (!IS_VALLEYVIEW(dev)) |
| 1399 | ironlake_edp_pll_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1400 | } |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1401 | } |
| 1402 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1403 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1404 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1405 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1406 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1407 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1408 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1409 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 1410 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 1411 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1412 | |
| 1413 | ironlake_edp_panel_vdd_on(intel_dp); |
| 1414 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 1415 | intel_dp_start_link_train(intel_dp); |
| 1416 | ironlake_edp_panel_on(intel_dp); |
| 1417 | ironlake_edp_panel_vdd_off(intel_dp, true); |
| 1418 | intel_dp_complete_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 1419 | intel_dp_stop_link_train(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1420 | ironlake_edp_backlight_on(intel_dp); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1421 | |
| 1422 | if (IS_VALLEYVIEW(dev)) { |
| 1423 | struct intel_digital_port *dport = |
| 1424 | enc_to_dig_port(&encoder->base); |
| 1425 | int channel = vlv_dport_to_channel(dport); |
| 1426 | |
| 1427 | vlv_wait_port_ready(dev_priv, channel); |
| 1428 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1429 | } |
| 1430 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1431 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1432 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1433 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1434 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1435 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1436 | |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1437 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1438 | ironlake_edp_pll_on(intel_dp); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1439 | |
| 1440 | if (IS_VALLEYVIEW(dev)) { |
| 1441 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 1442 | struct intel_crtc *intel_crtc = |
| 1443 | to_intel_crtc(encoder->base.crtc); |
| 1444 | int port = vlv_dport_to_channel(dport); |
| 1445 | int pipe = intel_crtc->pipe; |
| 1446 | u32 val; |
| 1447 | |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1448 | val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1449 | val = 0; |
| 1450 | if (pipe) |
| 1451 | val |= (1<<21); |
| 1452 | else |
| 1453 | val &= ~(1<<21); |
| 1454 | val |= 0x001000c4; |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1455 | vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1456 | |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1457 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1458 | 0x00760018); |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1459 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1460 | 0x00400888); |
| 1461 | } |
| 1462 | } |
| 1463 | |
| 1464 | static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 1465 | { |
| 1466 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 1467 | struct drm_device *dev = encoder->base.dev; |
| 1468 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1469 | int port = vlv_dport_to_channel(dport); |
| 1470 | |
| 1471 | if (!IS_VALLEYVIEW(dev)) |
| 1472 | return; |
| 1473 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1474 | /* Program Tx lane resets to default */ |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1475 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1476 | DPIO_PCS_TX_LANE2_RESET | |
| 1477 | DPIO_PCS_TX_LANE1_RESET); |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1478 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1479 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 1480 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 1481 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 1482 | DPIO_PCS_CLK_SOFT_RESET); |
| 1483 | |
| 1484 | /* Fix up inter-pair skew failure */ |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1485 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00); |
| 1486 | vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500); |
| 1487 | vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1488 | } |
| 1489 | |
| 1490 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1491 | * Native read with retry for link status and receiver capability reads for |
| 1492 | * cases where the sink may still be asleep. |
| 1493 | */ |
| 1494 | static bool |
| 1495 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
| 1496 | uint8_t *recv, int recv_bytes) |
| 1497 | { |
| 1498 | int ret, i; |
| 1499 | |
| 1500 | /* |
| 1501 | * Sinks are *supposed* to come up within 1ms from an off state, |
| 1502 | * but we're also supposed to retry 3 times per the spec. |
| 1503 | */ |
| 1504 | for (i = 0; i < 3; i++) { |
| 1505 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
| 1506 | recv_bytes); |
| 1507 | if (ret == recv_bytes) |
| 1508 | return true; |
| 1509 | msleep(1); |
| 1510 | } |
| 1511 | |
| 1512 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1513 | } |
| 1514 | |
| 1515 | /* |
| 1516 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 1517 | * link status information |
| 1518 | */ |
| 1519 | static bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1520 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1521 | { |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1522 | return intel_dp_aux_native_read_retry(intel_dp, |
| 1523 | DP_LANE0_1_STATUS, |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1524 | link_status, |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1525 | DP_LINK_STATUS_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1526 | } |
| 1527 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1528 | #if 0 |
| 1529 | static char *voltage_names[] = { |
| 1530 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 1531 | }; |
| 1532 | static char *pre_emph_names[] = { |
| 1533 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 1534 | }; |
| 1535 | static char *link_train_names[] = { |
| 1536 | "pattern 1", "pattern 2", "idle", "off" |
| 1537 | }; |
| 1538 | #endif |
| 1539 | |
| 1540 | /* |
| 1541 | * These are source-specific values; current Intel hardware supports |
| 1542 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 1543 | */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1544 | |
| 1545 | static uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1546 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1547 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1548 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1549 | |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1550 | if (IS_VALLEYVIEW(dev)) |
| 1551 | return DP_TRAIN_VOLTAGE_SWING_1200; |
| 1552 | else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1553 | return DP_TRAIN_VOLTAGE_SWING_800; |
| 1554 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
| 1555 | return DP_TRAIN_VOLTAGE_SWING_1200; |
| 1556 | else |
| 1557 | return DP_TRAIN_VOLTAGE_SWING_800; |
| 1558 | } |
| 1559 | |
| 1560 | static uint8_t |
| 1561 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 1562 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1563 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1564 | |
Paulo Zanoni | 22b8bf1 | 2013-02-18 19:00:23 -0300 | [diff] [blame] | 1565 | if (HAS_DDI(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1566 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1567 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1568 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 1569 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1570 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1571 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1572 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1573 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1574 | default: |
| 1575 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1576 | } |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1577 | } else if (IS_VALLEYVIEW(dev)) { |
| 1578 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1579 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1580 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 1581 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1582 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1583 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1584 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1585 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1586 | default: |
| 1587 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1588 | } |
| 1589 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1590 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1591 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1592 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1593 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1594 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1595 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1596 | default: |
| 1597 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1598 | } |
| 1599 | } else { |
| 1600 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1601 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1602 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1603 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1604 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1605 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1606 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1607 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1608 | default: |
| 1609 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1610 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1611 | } |
| 1612 | } |
| 1613 | |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1614 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
| 1615 | { |
| 1616 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1617 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1618 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 1619 | unsigned long demph_reg_value, preemph_reg_value, |
| 1620 | uniqtranscale_reg_value; |
| 1621 | uint8_t train_set = intel_dp->train_set[0]; |
Jesse Barnes | cece5d5 | 2013-04-19 08:46:35 -0700 | [diff] [blame] | 1622 | int port = vlv_dport_to_channel(dport); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1623 | |
| 1624 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 1625 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 1626 | preemph_reg_value = 0x0004000; |
| 1627 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1628 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1629 | demph_reg_value = 0x2B405555; |
| 1630 | uniqtranscale_reg_value = 0x552AB83A; |
| 1631 | break; |
| 1632 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1633 | demph_reg_value = 0x2B404040; |
| 1634 | uniqtranscale_reg_value = 0x5548B83A; |
| 1635 | break; |
| 1636 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1637 | demph_reg_value = 0x2B245555; |
| 1638 | uniqtranscale_reg_value = 0x5560B83A; |
| 1639 | break; |
| 1640 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1641 | demph_reg_value = 0x2B405555; |
| 1642 | uniqtranscale_reg_value = 0x5598DA3A; |
| 1643 | break; |
| 1644 | default: |
| 1645 | return 0; |
| 1646 | } |
| 1647 | break; |
| 1648 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1649 | preemph_reg_value = 0x0002000; |
| 1650 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1651 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1652 | demph_reg_value = 0x2B404040; |
| 1653 | uniqtranscale_reg_value = 0x5552B83A; |
| 1654 | break; |
| 1655 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1656 | demph_reg_value = 0x2B404848; |
| 1657 | uniqtranscale_reg_value = 0x5580B83A; |
| 1658 | break; |
| 1659 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1660 | demph_reg_value = 0x2B404040; |
| 1661 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 1662 | break; |
| 1663 | default: |
| 1664 | return 0; |
| 1665 | } |
| 1666 | break; |
| 1667 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 1668 | preemph_reg_value = 0x0000000; |
| 1669 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1670 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1671 | demph_reg_value = 0x2B305555; |
| 1672 | uniqtranscale_reg_value = 0x5570B83A; |
| 1673 | break; |
| 1674 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1675 | demph_reg_value = 0x2B2B4040; |
| 1676 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 1677 | break; |
| 1678 | default: |
| 1679 | return 0; |
| 1680 | } |
| 1681 | break; |
| 1682 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1683 | preemph_reg_value = 0x0006000; |
| 1684 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1685 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1686 | demph_reg_value = 0x1B405555; |
| 1687 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 1688 | break; |
| 1689 | default: |
| 1690 | return 0; |
| 1691 | } |
| 1692 | break; |
| 1693 | default: |
| 1694 | return 0; |
| 1695 | } |
| 1696 | |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1697 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000); |
| 1698 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value); |
| 1699 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port), |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1700 | uniqtranscale_reg_value); |
Jani Nikula | ae99258 | 2013-05-22 15:36:19 +0300 | [diff] [blame] | 1701 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040); |
| 1702 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000); |
| 1703 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); |
| 1704 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1705 | |
| 1706 | return 0; |
| 1707 | } |
| 1708 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1709 | static void |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1710 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1711 | { |
| 1712 | uint8_t v = 0; |
| 1713 | uint8_t p = 0; |
| 1714 | int lane; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1715 | uint8_t voltage_max; |
| 1716 | uint8_t preemph_max; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1717 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1718 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 1719 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 1720 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1721 | |
| 1722 | if (this_v > v) |
| 1723 | v = this_v; |
| 1724 | if (this_p > p) |
| 1725 | p = this_p; |
| 1726 | } |
| 1727 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1728 | voltage_max = intel_dp_voltage_max(intel_dp); |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1729 | if (v >= voltage_max) |
| 1730 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1731 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1732 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
| 1733 | if (p >= preemph_max) |
| 1734 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1735 | |
| 1736 | for (lane = 0; lane < 4; lane++) |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1737 | intel_dp->train_set[lane] = v | p; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1738 | } |
| 1739 | |
| 1740 | static uint32_t |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 1741 | intel_gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1742 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1743 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1744 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1745 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1746 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1747 | default: |
| 1748 | signal_levels |= DP_VOLTAGE_0_4; |
| 1749 | break; |
| 1750 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1751 | signal_levels |= DP_VOLTAGE_0_6; |
| 1752 | break; |
| 1753 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1754 | signal_levels |= DP_VOLTAGE_0_8; |
| 1755 | break; |
| 1756 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1757 | signal_levels |= DP_VOLTAGE_1_2; |
| 1758 | break; |
| 1759 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1760 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1761 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 1762 | default: |
| 1763 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 1764 | break; |
| 1765 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1766 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 1767 | break; |
| 1768 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 1769 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 1770 | break; |
| 1771 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1772 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 1773 | break; |
| 1774 | } |
| 1775 | return signal_levels; |
| 1776 | } |
| 1777 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1778 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 1779 | static uint32_t |
| 1780 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 1781 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1782 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1783 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1784 | switch (signal_levels) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1785 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1786 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1787 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 1788 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1789 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1790 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1791 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1792 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1793 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1794 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1795 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1796 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1797 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1798 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1799 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1800 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1801 | "0x%x\n", signal_levels); |
| 1802 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1803 | } |
| 1804 | } |
| 1805 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1806 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 1807 | static uint32_t |
| 1808 | intel_gen7_edp_signal_levels(uint8_t train_set) |
| 1809 | { |
| 1810 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1811 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1812 | switch (signal_levels) { |
| 1813 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1814 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
| 1815 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1816 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
| 1817 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1818 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 1819 | |
| 1820 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1821 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
| 1822 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1823 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 1824 | |
| 1825 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1826 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
| 1827 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1828 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 1829 | |
| 1830 | default: |
| 1831 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1832 | "0x%x\n", signal_levels); |
| 1833 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 1834 | } |
| 1835 | } |
| 1836 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1837 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
| 1838 | static uint32_t |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 1839 | intel_hsw_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1840 | { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1841 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1842 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1843 | switch (signal_levels) { |
| 1844 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1845 | return DDI_BUF_EMP_400MV_0DB_HSW; |
| 1846 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1847 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
| 1848 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1849 | return DDI_BUF_EMP_400MV_6DB_HSW; |
| 1850 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1851 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1852 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1853 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1854 | return DDI_BUF_EMP_600MV_0DB_HSW; |
| 1855 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1856 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
| 1857 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1858 | return DDI_BUF_EMP_600MV_6DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1859 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1860 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1861 | return DDI_BUF_EMP_800MV_0DB_HSW; |
| 1862 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1863 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
| 1864 | default: |
| 1865 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1866 | "0x%x\n", signal_levels); |
| 1867 | return DDI_BUF_EMP_400MV_0DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1868 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1869 | } |
| 1870 | |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 1871 | /* Properly updates "DP" with the correct signal levels. */ |
| 1872 | static void |
| 1873 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
| 1874 | { |
| 1875 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1876 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 1877 | uint32_t signal_levels, mask; |
| 1878 | uint8_t train_set = intel_dp->train_set[0]; |
| 1879 | |
Paulo Zanoni | 22b8bf1 | 2013-02-18 19:00:23 -0300 | [diff] [blame] | 1880 | if (HAS_DDI(dev)) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 1881 | signal_levels = intel_hsw_signal_levels(train_set); |
| 1882 | mask = DDI_BUF_EMP_MASK; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 1883 | } else if (IS_VALLEYVIEW(dev)) { |
| 1884 | signal_levels = intel_vlv_signal_levels(intel_dp); |
| 1885 | mask = 0; |
| 1886 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 1887 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
| 1888 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
| 1889 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
| 1890 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
| 1891 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 1892 | } else { |
| 1893 | signal_levels = intel_gen4_signal_levels(train_set); |
| 1894 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 1895 | } |
| 1896 | |
| 1897 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 1898 | |
| 1899 | *DP = (*DP & ~mask) | signal_levels; |
| 1900 | } |
| 1901 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1902 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1903 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1904 | uint32_t dp_reg_value, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1905 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1906 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 1907 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1908 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1909 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 1910 | enum port port = intel_dig_port->port; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1911 | int ret; |
| 1912 | |
Paulo Zanoni | 22b8bf1 | 2013-02-18 19:00:23 -0300 | [diff] [blame] | 1913 | if (HAS_DDI(dev)) { |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 1914 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1915 | |
| 1916 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 1917 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 1918 | else |
| 1919 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 1920 | |
| 1921 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 1922 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 1923 | case DP_TRAINING_PATTERN_DISABLE: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1924 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 1925 | |
| 1926 | break; |
| 1927 | case DP_TRAINING_PATTERN_1: |
| 1928 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 1929 | break; |
| 1930 | case DP_TRAINING_PATTERN_2: |
| 1931 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 1932 | break; |
| 1933 | case DP_TRAINING_PATTERN_3: |
| 1934 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 1935 | break; |
| 1936 | } |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 1937 | I915_WRITE(DP_TP_CTL(port), temp); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1938 | |
| 1939 | } else if (HAS_PCH_CPT(dev) && |
| 1940 | (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1941 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
| 1942 | |
| 1943 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 1944 | case DP_TRAINING_PATTERN_DISABLE: |
| 1945 | dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; |
| 1946 | break; |
| 1947 | case DP_TRAINING_PATTERN_1: |
| 1948 | dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; |
| 1949 | break; |
| 1950 | case DP_TRAINING_PATTERN_2: |
| 1951 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
| 1952 | break; |
| 1953 | case DP_TRAINING_PATTERN_3: |
| 1954 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 1955 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
| 1956 | break; |
| 1957 | } |
| 1958 | |
| 1959 | } else { |
| 1960 | dp_reg_value &= ~DP_LINK_TRAIN_MASK; |
| 1961 | |
| 1962 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 1963 | case DP_TRAINING_PATTERN_DISABLE: |
| 1964 | dp_reg_value |= DP_LINK_TRAIN_OFF; |
| 1965 | break; |
| 1966 | case DP_TRAINING_PATTERN_1: |
| 1967 | dp_reg_value |= DP_LINK_TRAIN_PAT_1; |
| 1968 | break; |
| 1969 | case DP_TRAINING_PATTERN_2: |
| 1970 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
| 1971 | break; |
| 1972 | case DP_TRAINING_PATTERN_3: |
| 1973 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 1974 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
| 1975 | break; |
| 1976 | } |
| 1977 | } |
| 1978 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1979 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
| 1980 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1981 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1982 | intel_dp_aux_native_write_1(intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1983 | DP_TRAINING_PATTERN_SET, |
| 1984 | dp_train_pat); |
| 1985 | |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1986 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != |
| 1987 | DP_TRAINING_PATTERN_DISABLE) { |
| 1988 | ret = intel_dp_aux_native_write(intel_dp, |
| 1989 | DP_TRAINING_LANE0_SET, |
| 1990 | intel_dp->train_set, |
| 1991 | intel_dp->lane_count); |
| 1992 | if (ret != intel_dp->lane_count) |
| 1993 | return false; |
| 1994 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1995 | |
| 1996 | return true; |
| 1997 | } |
| 1998 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 1999 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
| 2000 | { |
| 2001 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2002 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2003 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2004 | enum port port = intel_dig_port->port; |
| 2005 | uint32_t val; |
| 2006 | |
| 2007 | if (!HAS_DDI(dev)) |
| 2008 | return; |
| 2009 | |
| 2010 | val = I915_READ(DP_TP_CTL(port)); |
| 2011 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2012 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 2013 | I915_WRITE(DP_TP_CTL(port), val); |
| 2014 | |
| 2015 | /* |
| 2016 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 2017 | * we need to set idle transmission mode is to work around a HW issue |
| 2018 | * where we enable the pipe while not in idle link-training mode. |
| 2019 | * In this case there is requirement to wait for a minimum number of |
| 2020 | * idle patterns to be sent. |
| 2021 | */ |
| 2022 | if (port == PORT_A) |
| 2023 | return; |
| 2024 | |
| 2025 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 2026 | 1)) |
| 2027 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 2028 | } |
| 2029 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2030 | /* Enable corresponding port and start training pattern 1 */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2031 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2032 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2033 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2034 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2035 | struct drm_device *dev = encoder->dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2036 | int i; |
| 2037 | uint8_t voltage; |
| 2038 | bool clock_recovery = false; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2039 | int voltage_tries, loop_tries; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2040 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2041 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2042 | if (HAS_DDI(dev)) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2043 | intel_ddi_prepare_link_retrain(encoder); |
| 2044 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2045 | /* Write the link configuration data */ |
| 2046 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
| 2047 | intel_dp->link_configuration, |
| 2048 | DP_LINK_CONFIGURATION_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2049 | |
| 2050 | DP |= DP_PORT_EN; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2051 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2052 | memset(intel_dp->train_set, 0, 4); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2053 | voltage = 0xff; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2054 | voltage_tries = 0; |
| 2055 | loop_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2056 | clock_recovery = false; |
| 2057 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2058 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2059 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 2060 | |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2061 | intel_dp_set_signal_levels(intel_dp, &DP); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2062 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2063 | /* Set training pattern 1 */ |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2064 | if (!intel_dp_set_link_train(intel_dp, DP, |
Adam Jackson | 8105585 | 2011-07-21 17:48:37 -0400 | [diff] [blame] | 2065 | DP_TRAINING_PATTERN_1 | |
| 2066 | DP_LINK_SCRAMBLING_DISABLE)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2067 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2068 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2069 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2070 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 2071 | DRM_ERROR("failed to get link status\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2072 | break; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2073 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2074 | |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 2075 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2076 | DRM_DEBUG_KMS("clock recovery OK\n"); |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2077 | clock_recovery = true; |
| 2078 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2079 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2080 | |
| 2081 | /* Check to see if we've tried the max voltage */ |
| 2082 | for (i = 0; i < intel_dp->lane_count; i++) |
| 2083 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 2084 | break; |
Takashi Iwai | 3b4f819 | 2013-03-11 18:40:16 +0100 | [diff] [blame] | 2085 | if (i == intel_dp->lane_count) { |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2086 | ++loop_tries; |
| 2087 | if (loop_tries == 5) { |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2088 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
| 2089 | break; |
| 2090 | } |
| 2091 | memset(intel_dp->train_set, 0, 4); |
| 2092 | voltage_tries = 0; |
| 2093 | continue; |
| 2094 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2095 | |
| 2096 | /* Check to see if we've tried the same voltage 5 times */ |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2097 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
Chris Wilson | 2477367 | 2012-09-26 16:48:30 +0100 | [diff] [blame] | 2098 | ++voltage_tries; |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2099 | if (voltage_tries == 5) { |
| 2100 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); |
| 2101 | break; |
| 2102 | } |
| 2103 | } else |
| 2104 | voltage_tries = 0; |
| 2105 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2106 | |
| 2107 | /* Compute new intel_dp->train_set as requested by target */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2108 | intel_get_adjust_train(intel_dp, link_status); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2109 | } |
| 2110 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2111 | intel_dp->DP = DP; |
| 2112 | } |
| 2113 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2114 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2115 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 2116 | { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2117 | bool channel_eq = false; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2118 | int tries, cr_tries; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2119 | uint32_t DP = intel_dp->DP; |
| 2120 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2121 | /* channel equalization */ |
| 2122 | tries = 0; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2123 | cr_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2124 | channel_eq = false; |
| 2125 | for (;;) { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2126 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2127 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2128 | if (cr_tries > 5) { |
| 2129 | DRM_ERROR("failed to train DP, aborting\n"); |
| 2130 | intel_dp_link_down(intel_dp); |
| 2131 | break; |
| 2132 | } |
| 2133 | |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2134 | intel_dp_set_signal_levels(intel_dp, &DP); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2135 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2136 | /* channel eq pattern */ |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2137 | if (!intel_dp_set_link_train(intel_dp, DP, |
Adam Jackson | 8105585 | 2011-07-21 17:48:37 -0400 | [diff] [blame] | 2138 | DP_TRAINING_PATTERN_2 | |
| 2139 | DP_LINK_SCRAMBLING_DISABLE)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2140 | break; |
| 2141 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2142 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2143 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2144 | break; |
Jesse Barnes | 869184a | 2010-10-07 16:01:22 -0700 | [diff] [blame] | 2145 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2146 | /* Make sure clock is still ok */ |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 2147 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2148 | intel_dp_start_link_train(intel_dp); |
| 2149 | cr_tries++; |
| 2150 | continue; |
| 2151 | } |
| 2152 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 2153 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2154 | channel_eq = true; |
| 2155 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2156 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2157 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2158 | /* Try 5 times, then try clock recovery if that fails */ |
| 2159 | if (tries > 5) { |
| 2160 | intel_dp_link_down(intel_dp); |
| 2161 | intel_dp_start_link_train(intel_dp); |
| 2162 | tries = 0; |
| 2163 | cr_tries++; |
| 2164 | continue; |
| 2165 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2166 | |
| 2167 | /* Compute new intel_dp->train_set as requested by target */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2168 | intel_get_adjust_train(intel_dp, link_status); |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2169 | ++tries; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2170 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2171 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2172 | intel_dp_set_idle_link_train(intel_dp); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2173 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2174 | intel_dp->DP = DP; |
| 2175 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2176 | if (channel_eq) |
Masanari Iida | 07f4225 | 2013-03-20 11:00:34 +0900 | [diff] [blame] | 2177 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2178 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2179 | } |
| 2180 | |
| 2181 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
| 2182 | { |
| 2183 | intel_dp_set_link_train(intel_dp, intel_dp->DP, |
| 2184 | DP_TRAINING_PATTERN_DISABLE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2185 | } |
| 2186 | |
| 2187 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2188 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2189 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2190 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2191 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2192 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2193 | struct intel_crtc *intel_crtc = |
| 2194 | to_intel_crtc(intel_dig_port->base.base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2195 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2196 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2197 | /* |
| 2198 | * DDI code has a strict mode set sequence and we should try to respect |
| 2199 | * it, otherwise we might hang the machine in many different ways. So we |
| 2200 | * really should be disabling the port only on a complete crtc_disable |
| 2201 | * sequence. This function is just called under two conditions on DDI |
| 2202 | * code: |
| 2203 | * - Link train failed while doing crtc_enable, and on this case we |
| 2204 | * really should respect the mode set sequence and wait for a |
| 2205 | * crtc_disable. |
| 2206 | * - Someone turned the monitor off and intel_dp_check_link_status |
| 2207 | * called us. We don't need to disable the whole port on this case, so |
| 2208 | * when someone turns the monitor on again, |
| 2209 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
| 2210 | * train. |
| 2211 | */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2212 | if (HAS_DDI(dev)) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2213 | return; |
| 2214 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 2215 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 2216 | return; |
| 2217 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 2218 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2219 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2220 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2221 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2222 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2223 | } else { |
| 2224 | DP &= ~DP_LINK_TRAIN_MASK; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2225 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2226 | } |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 2227 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2228 | |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2229 | /* We don't really know why we're doing this */ |
| 2230 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2231 | |
Daniel Vetter | 493a708 | 2012-05-30 12:31:56 +0200 | [diff] [blame] | 2232 | if (HAS_PCH_IBX(dev) && |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 2233 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2234 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 2235 | |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 2236 | /* Hardware workaround: leaving our transcoder select |
| 2237 | * set to transcoder B while it's off will prevent the |
| 2238 | * corresponding HDMI output on transcoder A. |
| 2239 | * |
| 2240 | * Combine this with another hardware workaround: |
| 2241 | * transcoder select bit can only be cleared while the |
| 2242 | * port is enabled. |
| 2243 | */ |
| 2244 | DP &= ~DP_PIPEB_SELECT; |
| 2245 | I915_WRITE(intel_dp->output_reg, DP); |
| 2246 | |
| 2247 | /* Changes to enable or select take place the vblank |
| 2248 | * after being written. |
| 2249 | */ |
Daniel Vetter | ff50afe | 2012-11-29 15:59:34 +0100 | [diff] [blame] | 2250 | if (WARN_ON(crtc == NULL)) { |
| 2251 | /* We should never try to disable a port without a crtc |
| 2252 | * attached. For paranoia keep the code around for a |
| 2253 | * bit. */ |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 2254 | POSTING_READ(intel_dp->output_reg); |
| 2255 | msleep(50); |
| 2256 | } else |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2257 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 2258 | } |
| 2259 | |
Wu Fengguang | 832afda | 2011-12-09 20:42:21 +0800 | [diff] [blame] | 2260 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2261 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 2262 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2263 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2264 | } |
| 2265 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2266 | static bool |
| 2267 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2268 | { |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 2269 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
| 2270 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2271 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2272 | sizeof(intel_dp->dpcd)) == 0) |
| 2273 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2274 | |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 2275 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
| 2276 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
| 2277 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
| 2278 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2279 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 2280 | return false; /* DPCD not present */ |
| 2281 | |
| 2282 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 2283 | DP_DWN_STRM_PORT_PRESENT)) |
| 2284 | return true; /* native DP sink */ |
| 2285 | |
| 2286 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 2287 | return true; /* no per-port downstream info */ |
| 2288 | |
| 2289 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
| 2290 | intel_dp->downstream_ports, |
| 2291 | DP_MAX_DOWNSTREAM_PORTS) == 0) |
| 2292 | return false; /* downstream port status fetch failed */ |
| 2293 | |
| 2294 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2295 | } |
| 2296 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2297 | static void |
| 2298 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 2299 | { |
| 2300 | u8 buf[3]; |
| 2301 | |
| 2302 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 2303 | return; |
| 2304 | |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 2305 | ironlake_edp_panel_vdd_on(intel_dp); |
| 2306 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2307 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
| 2308 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 2309 | buf[0], buf[1], buf[2]); |
| 2310 | |
| 2311 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
| 2312 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 2313 | buf[0], buf[1], buf[2]); |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 2314 | |
| 2315 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2316 | } |
| 2317 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2318 | static bool |
| 2319 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 2320 | { |
| 2321 | int ret; |
| 2322 | |
| 2323 | ret = intel_dp_aux_native_read_retry(intel_dp, |
| 2324 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 2325 | sink_irq_vector, 1); |
| 2326 | if (!ret) |
| 2327 | return false; |
| 2328 | |
| 2329 | return true; |
| 2330 | } |
| 2331 | |
| 2332 | static void |
| 2333 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 2334 | { |
| 2335 | /* NAK by default */ |
Daniel Vetter | 9324cf7 | 2012-10-20 21:13:05 +0200 | [diff] [blame] | 2336 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2337 | } |
| 2338 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2339 | /* |
| 2340 | * According to DP spec |
| 2341 | * 5.1.2: |
| 2342 | * 1. Read DPCD |
| 2343 | * 2. Configure link according to Receiver Capabilities |
| 2344 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 2345 | * 4. Check link status on receipt of hot-plug interrupt |
| 2346 | */ |
| 2347 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2348 | void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2349 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2350 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2351 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2352 | u8 sink_irq_vector; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2353 | u8 link_status[DP_LINK_STATUS_SIZE]; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2354 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2355 | if (!intel_encoder->connectors_active) |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 2356 | return; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 2357 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2358 | if (WARN_ON(!intel_encoder->base.crtc)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2359 | return; |
| 2360 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2361 | /* Try to read receiver status if the link appears to be up */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2362 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2363 | intel_dp_link_down(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2364 | return; |
| 2365 | } |
| 2366 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2367 | /* Now read the DPCD to see if it's actually running */ |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2368 | if (!intel_dp_get_dpcd(intel_dp)) { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 2369 | intel_dp_link_down(intel_dp); |
| 2370 | return; |
| 2371 | } |
| 2372 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2373 | /* Try to read the source of the interrupt */ |
| 2374 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 2375 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 2376 | /* Clear interrupt source */ |
| 2377 | intel_dp_aux_native_write_1(intel_dp, |
| 2378 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 2379 | sink_irq_vector); |
| 2380 | |
| 2381 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 2382 | intel_dp_handle_test_request(intel_dp); |
| 2383 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 2384 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 2385 | } |
| 2386 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 2387 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2388 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2389 | drm_get_encoder_name(&intel_encoder->base)); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2390 | intel_dp_start_link_train(intel_dp); |
| 2391 | intel_dp_complete_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2392 | intel_dp_stop_link_train(intel_dp); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2393 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2394 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2395 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2396 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2397 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2398 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 2399 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2400 | uint8_t *dpcd = intel_dp->dpcd; |
| 2401 | bool hpd; |
| 2402 | uint8_t type; |
| 2403 | |
| 2404 | if (!intel_dp_get_dpcd(intel_dp)) |
| 2405 | return connector_status_disconnected; |
| 2406 | |
| 2407 | /* if there's no downstream port, we're done */ |
| 2408 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2409 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2410 | |
| 2411 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
| 2412 | hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); |
| 2413 | if (hpd) { |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 2414 | uint8_t reg; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2415 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 2416 | ®, 1)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2417 | return connector_status_unknown; |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 2418 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 2419 | : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2420 | } |
| 2421 | |
| 2422 | /* If no HPD, poke DDC gently */ |
| 2423 | if (drm_probe_ddc(&intel_dp->adapter)) |
| 2424 | return connector_status_connected; |
| 2425 | |
| 2426 | /* Well we tried, say unknown for unreliable port types */ |
| 2427 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 2428 | if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) |
| 2429 | return connector_status_unknown; |
| 2430 | |
| 2431 | /* Anything else is out of spec, warn and ignore */ |
| 2432 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2433 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 2434 | } |
| 2435 | |
| 2436 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2437 | ironlake_dp_detect(struct intel_dp *intel_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2438 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2439 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 2440 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2441 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2442 | enum drm_connector_status status; |
| 2443 | |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 2444 | /* Can't disconnect eDP, but you can close the lid... */ |
| 2445 | if (is_edp(intel_dp)) { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2446 | status = intel_panel_detect(dev); |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 2447 | if (status == connector_status_unknown) |
| 2448 | status = connector_status_connected; |
| 2449 | return status; |
| 2450 | } |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 2451 | |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 2452 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
| 2453 | return connector_status_disconnected; |
| 2454 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2455 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2456 | } |
| 2457 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2458 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2459 | g4x_dp_detect(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2460 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2461 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2462 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 34f2be4 | 2013-01-24 15:29:27 +0200 | [diff] [blame] | 2463 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2464 | uint32_t bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2465 | |
Jesse Barnes | 35aad75 | 2013-03-01 13:14:31 -0800 | [diff] [blame] | 2466 | /* Can't disconnect eDP, but you can close the lid... */ |
| 2467 | if (is_edp(intel_dp)) { |
| 2468 | enum drm_connector_status status; |
| 2469 | |
| 2470 | status = intel_panel_detect(dev); |
| 2471 | if (status == connector_status_unknown) |
| 2472 | status = connector_status_connected; |
| 2473 | return status; |
| 2474 | } |
| 2475 | |
Ville Syrjälä | 34f2be4 | 2013-01-24 15:29:27 +0200 | [diff] [blame] | 2476 | switch (intel_dig_port->port) { |
| 2477 | case PORT_B: |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 2478 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2479 | break; |
Ville Syrjälä | 34f2be4 | 2013-01-24 15:29:27 +0200 | [diff] [blame] | 2480 | case PORT_C: |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 2481 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2482 | break; |
Ville Syrjälä | 34f2be4 | 2013-01-24 15:29:27 +0200 | [diff] [blame] | 2483 | case PORT_D: |
Daniel Vetter | 26739f1 | 2013-02-07 12:42:32 +0100 | [diff] [blame] | 2484 | bit = PORTD_HOTPLUG_LIVE_STATUS; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2485 | break; |
| 2486 | default: |
| 2487 | return connector_status_unknown; |
| 2488 | } |
| 2489 | |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2490 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2491 | return connector_status_disconnected; |
| 2492 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2493 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2494 | } |
| 2495 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2496 | static struct edid * |
| 2497 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 2498 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2499 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2500 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2501 | /* use cached edid if we have one */ |
| 2502 | if (intel_connector->edid) { |
| 2503 | struct edid *edid; |
| 2504 | int size; |
| 2505 | |
| 2506 | /* invalid edid */ |
| 2507 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2508 | return NULL; |
| 2509 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2510 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
Thomas Meyer | edbe158 | 2013-05-22 23:07:09 +0200 | [diff] [blame] | 2511 | edid = kmemdup(intel_connector->edid, size, GFP_KERNEL); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2512 | if (!edid) |
| 2513 | return NULL; |
| 2514 | |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2515 | return edid; |
| 2516 | } |
| 2517 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2518 | return drm_get_edid(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2519 | } |
| 2520 | |
| 2521 | static int |
| 2522 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 2523 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2524 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2525 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2526 | /* use cached edid if we have one */ |
| 2527 | if (intel_connector->edid) { |
| 2528 | /* invalid edid */ |
| 2529 | if (IS_ERR(intel_connector->edid)) |
| 2530 | return 0; |
| 2531 | |
| 2532 | return intel_connector_update_modes(connector, |
| 2533 | intel_connector->edid); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2534 | } |
| 2535 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2536 | return intel_ddc_get_modes(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2537 | } |
| 2538 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2539 | static enum drm_connector_status |
| 2540 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 2541 | { |
| 2542 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 2543 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2544 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 2545 | struct drm_device *dev = connector->dev; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2546 | enum drm_connector_status status; |
| 2547 | struct edid *edid = NULL; |
| 2548 | |
| 2549 | intel_dp->has_audio = false; |
| 2550 | |
| 2551 | if (HAS_PCH_SPLIT(dev)) |
| 2552 | status = ironlake_dp_detect(intel_dp); |
| 2553 | else |
| 2554 | status = g4x_dp_detect(intel_dp); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 2555 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2556 | if (status != connector_status_connected) |
| 2557 | return status; |
| 2558 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2559 | intel_dp_probe_oui(intel_dp); |
| 2560 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2561 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
| 2562 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2563 | } else { |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2564 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2565 | if (edid) { |
| 2566 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2567 | kfree(edid); |
| 2568 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2569 | } |
| 2570 | |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 2571 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 2572 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2573 | return connector_status_connected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2574 | } |
| 2575 | |
| 2576 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 2577 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2578 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2579 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 2580 | struct drm_device *dev = connector->dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2581 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2582 | |
| 2583 | /* We should parse the EDID data and find out if it has an audio sink |
| 2584 | */ |
| 2585 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2586 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2587 | if (ret) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2588 | return ret; |
| 2589 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2590 | /* if eDP has no EDID, fall back to fixed mode */ |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2591 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2592 | struct drm_display_mode *mode; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2593 | mode = drm_mode_duplicate(dev, |
| 2594 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2595 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2596 | drm_mode_probed_add(connector, mode); |
| 2597 | return 1; |
| 2598 | } |
| 2599 | } |
| 2600 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2601 | } |
| 2602 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2603 | static bool |
| 2604 | intel_dp_detect_audio(struct drm_connector *connector) |
| 2605 | { |
| 2606 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 2607 | struct edid *edid; |
| 2608 | bool has_audio = false; |
| 2609 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2610 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2611 | if (edid) { |
| 2612 | has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2613 | kfree(edid); |
| 2614 | } |
| 2615 | |
| 2616 | return has_audio; |
| 2617 | } |
| 2618 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2619 | static int |
| 2620 | intel_dp_set_property(struct drm_connector *connector, |
| 2621 | struct drm_property *property, |
| 2622 | uint64_t val) |
| 2623 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2624 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 2625 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2626 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 2627 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2628 | int ret; |
| 2629 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2630 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2631 | if (ret) |
| 2632 | return ret; |
| 2633 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2634 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2635 | int i = val; |
| 2636 | bool has_audio; |
| 2637 | |
| 2638 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2639 | return 0; |
| 2640 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2641 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2642 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2643 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2644 | has_audio = intel_dp_detect_audio(connector); |
| 2645 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2646 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2647 | |
| 2648 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2649 | return 0; |
| 2650 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2651 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2652 | goto done; |
| 2653 | } |
| 2654 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2655 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 2656 | bool old_auto = intel_dp->color_range_auto; |
| 2657 | uint32_t old_range = intel_dp->color_range; |
| 2658 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2659 | switch (val) { |
| 2660 | case INTEL_BROADCAST_RGB_AUTO: |
| 2661 | intel_dp->color_range_auto = true; |
| 2662 | break; |
| 2663 | case INTEL_BROADCAST_RGB_FULL: |
| 2664 | intel_dp->color_range_auto = false; |
| 2665 | intel_dp->color_range = 0; |
| 2666 | break; |
| 2667 | case INTEL_BROADCAST_RGB_LIMITED: |
| 2668 | intel_dp->color_range_auto = false; |
| 2669 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 2670 | break; |
| 2671 | default: |
| 2672 | return -EINVAL; |
| 2673 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 2674 | |
| 2675 | if (old_auto == intel_dp->color_range_auto && |
| 2676 | old_range == intel_dp->color_range) |
| 2677 | return 0; |
| 2678 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2679 | goto done; |
| 2680 | } |
| 2681 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 2682 | if (is_edp(intel_dp) && |
| 2683 | property == connector->dev->mode_config.scaling_mode_property) { |
| 2684 | if (val == DRM_MODE_SCALE_NONE) { |
| 2685 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 2686 | return -EINVAL; |
| 2687 | } |
| 2688 | |
| 2689 | if (intel_connector->panel.fitting_mode == val) { |
| 2690 | /* the eDP scaling property is not changed */ |
| 2691 | return 0; |
| 2692 | } |
| 2693 | intel_connector->panel.fitting_mode = val; |
| 2694 | |
| 2695 | goto done; |
| 2696 | } |
| 2697 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2698 | return -EINVAL; |
| 2699 | |
| 2700 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 2701 | if (intel_encoder->base.crtc) |
| 2702 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2703 | |
| 2704 | return 0; |
| 2705 | } |
| 2706 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2707 | static void |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2708 | intel_dp_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2709 | { |
Jani Nikula | be3cd5e | 2012-10-12 10:33:05 +0300 | [diff] [blame] | 2710 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2711 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2712 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2713 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 2714 | kfree(intel_connector->edid); |
| 2715 | |
Jani Nikula | dc652f9 | 2013-04-12 15:18:38 +0300 | [diff] [blame] | 2716 | if (is_edp(intel_dp)) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2717 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2718 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2719 | drm_sysfs_connector_remove(connector); |
| 2720 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2721 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2722 | } |
| 2723 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 2724 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2725 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2726 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 2727 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 2728 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2729 | |
| 2730 | i2c_del_adapter(&intel_dp->adapter); |
| 2731 | drm_encoder_cleanup(encoder); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2732 | if (is_edp(intel_dp)) { |
| 2733 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 2734 | mutex_lock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2735 | ironlake_panel_vdd_off_sync(intel_dp); |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 2736 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2737 | } |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2738 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2739 | } |
| 2740 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2741 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2742 | .mode_set = intel_dp_mode_set, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2743 | }; |
| 2744 | |
| 2745 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2746 | .dpms = intel_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2747 | .detect = intel_dp_detect, |
| 2748 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2749 | .set_property = intel_dp_set_property, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2750 | .destroy = intel_dp_destroy, |
| 2751 | }; |
| 2752 | |
| 2753 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 2754 | .get_modes = intel_dp_get_modes, |
| 2755 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2756 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2757 | }; |
| 2758 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2759 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2760 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2761 | }; |
| 2762 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 2763 | static void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2764 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2765 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 2766 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2767 | |
Jesse Barnes | 885a501 | 2011-07-07 11:11:01 -0700 | [diff] [blame] | 2768 | intel_dp_check_link_status(intel_dp); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2769 | } |
| 2770 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2771 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 2772 | int |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2773 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2774 | { |
| 2775 | struct drm_device *dev = crtc->dev; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 2776 | struct intel_encoder *intel_encoder; |
| 2777 | struct intel_dp *intel_dp; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2778 | |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 2779 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 2780 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2781 | |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 2782 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 2783 | intel_encoder->type == INTEL_OUTPUT_EDP) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2784 | return intel_dp->output_reg; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2785 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2786 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2787 | return -1; |
| 2788 | } |
| 2789 | |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2790 | /* check the VBT to see whether the eDP is on DP-D port */ |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 2791 | bool intel_dpd_is_edp(struct drm_device *dev) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2792 | { |
| 2793 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2794 | struct child_device_config *p_child; |
| 2795 | int i; |
| 2796 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 2797 | if (!dev_priv->vbt.child_dev_num) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2798 | return false; |
| 2799 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 2800 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
| 2801 | p_child = dev_priv->vbt.child_dev + i; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2802 | |
| 2803 | if (p_child->dvo_port == PORT_IDPD && |
| 2804 | p_child->device_type == DEVICE_TYPE_eDP) |
| 2805 | return true; |
| 2806 | } |
| 2807 | return false; |
| 2808 | } |
| 2809 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2810 | static void |
| 2811 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 2812 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 2813 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2814 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2815 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2816 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2817 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 2818 | |
| 2819 | if (is_edp(intel_dp)) { |
| 2820 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 2821 | drm_object_attach_property( |
| 2822 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 2823 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 2824 | DRM_MODE_SCALE_ASPECT); |
| 2825 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 2826 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2827 | } |
| 2828 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2829 | static void |
| 2830 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 2831 | struct intel_dp *intel_dp, |
| 2832 | struct edp_power_seq *out) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2833 | { |
| 2834 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2835 | struct edp_power_seq cur, vbt, spec, final; |
| 2836 | u32 pp_on, pp_off, pp_div, pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2837 | int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
| 2838 | |
| 2839 | if (HAS_PCH_SPLIT(dev)) { |
| 2840 | pp_control_reg = PCH_PP_CONTROL; |
| 2841 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 2842 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 2843 | pp_div_reg = PCH_PP_DIVISOR; |
| 2844 | } else { |
| 2845 | pp_control_reg = PIPEA_PP_CONTROL; |
| 2846 | pp_on_reg = PIPEA_PP_ON_DELAYS; |
| 2847 | pp_off_reg = PIPEA_PP_OFF_DELAYS; |
| 2848 | pp_div_reg = PIPEA_PP_DIVISOR; |
| 2849 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2850 | |
| 2851 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 2852 | * the very first thing. */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2853 | pp = ironlake_get_pp_control(intel_dp); |
| 2854 | I915_WRITE(pp_control_reg, pp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2855 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2856 | pp_on = I915_READ(pp_on_reg); |
| 2857 | pp_off = I915_READ(pp_off_reg); |
| 2858 | pp_div = I915_READ(pp_div_reg); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2859 | |
| 2860 | /* Pull timing values out of registers */ |
| 2861 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 2862 | PANEL_POWER_UP_DELAY_SHIFT; |
| 2863 | |
| 2864 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 2865 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 2866 | |
| 2867 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 2868 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 2869 | |
| 2870 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 2871 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 2872 | |
| 2873 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 2874 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 2875 | |
| 2876 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 2877 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 2878 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 2879 | vbt = dev_priv->vbt.edp_pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2880 | |
| 2881 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 2882 | * our hw here, which are all in 100usec. */ |
| 2883 | spec.t1_t3 = 210 * 10; |
| 2884 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 2885 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 2886 | spec.t10 = 500 * 10; |
| 2887 | /* This one is special and actually in units of 100ms, but zero |
| 2888 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 2889 | * table multiplies it with 1000 to make it in units of 100usec, |
| 2890 | * too. */ |
| 2891 | spec.t11_t12 = (510 + 100) * 10; |
| 2892 | |
| 2893 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 2894 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 2895 | |
| 2896 | /* Use the max of the register settings and vbt. If both are |
| 2897 | * unset, fall back to the spec limits. */ |
| 2898 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
| 2899 | spec.field : \ |
| 2900 | max(cur.field, vbt.field)) |
| 2901 | assign_final(t1_t3); |
| 2902 | assign_final(t8); |
| 2903 | assign_final(t9); |
| 2904 | assign_final(t10); |
| 2905 | assign_final(t11_t12); |
| 2906 | #undef assign_final |
| 2907 | |
| 2908 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
| 2909 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 2910 | intel_dp->backlight_on_delay = get_delay(t8); |
| 2911 | intel_dp->backlight_off_delay = get_delay(t9); |
| 2912 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 2913 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 2914 | #undef get_delay |
| 2915 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 2916 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 2917 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 2918 | intel_dp->panel_power_cycle_delay); |
| 2919 | |
| 2920 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 2921 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
| 2922 | |
| 2923 | if (out) |
| 2924 | *out = final; |
| 2925 | } |
| 2926 | |
| 2927 | static void |
| 2928 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 2929 | struct intel_dp *intel_dp, |
| 2930 | struct edp_power_seq *seq) |
| 2931 | { |
| 2932 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2933 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
| 2934 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
| 2935 | int pp_on_reg, pp_off_reg, pp_div_reg; |
| 2936 | |
| 2937 | if (HAS_PCH_SPLIT(dev)) { |
| 2938 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 2939 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 2940 | pp_div_reg = PCH_PP_DIVISOR; |
| 2941 | } else { |
| 2942 | pp_on_reg = PIPEA_PP_ON_DELAYS; |
| 2943 | pp_off_reg = PIPEA_PP_OFF_DELAYS; |
| 2944 | pp_div_reg = PIPEA_PP_DIVISOR; |
| 2945 | } |
| 2946 | |
| 2947 | if (IS_VALLEYVIEW(dev)) |
| 2948 | port_sel = I915_READ(pp_on_reg) & 0xc0000000; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 2949 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2950 | /* And finally store the new values in the power sequencer. */ |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 2951 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
| 2952 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 2953 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
| 2954 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2955 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 2956 | * formula. */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2957 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 2958 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2959 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 2960 | |
| 2961 | /* Haswell doesn't have any port selection bits for the panel |
| 2962 | * power sequencer any more. */ |
| 2963 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 2964 | if (is_cpu_edp(intel_dp)) |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2965 | port_sel = PANEL_POWER_PORT_DP_A; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2966 | else |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2967 | port_sel = PANEL_POWER_PORT_DP_D; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2968 | } |
| 2969 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2970 | pp_on |= port_sel; |
| 2971 | |
| 2972 | I915_WRITE(pp_on_reg, pp_on); |
| 2973 | I915_WRITE(pp_off_reg, pp_off); |
| 2974 | I915_WRITE(pp_div_reg, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2975 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 2976 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2977 | I915_READ(pp_on_reg), |
| 2978 | I915_READ(pp_off_reg), |
| 2979 | I915_READ(pp_div_reg)); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2980 | } |
| 2981 | |
| 2982 | void |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 2983 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 2984 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2985 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 2986 | struct drm_connector *connector = &intel_connector->base; |
| 2987 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 2988 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 2989 | struct drm_device *dev = intel_encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2990 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2991 | struct drm_display_mode *fixed_mode = NULL; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 2992 | struct edp_power_seq power_seq = { 0 }; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2993 | enum port port = intel_dig_port->port; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2994 | const char *name = NULL; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2995 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2996 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2997 | /* Preserve the current hw state. */ |
| 2998 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2999 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 3000 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 3001 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 3002 | /* |
| 3003 | * FIXME : We need to initialize built-in panels before external panels. |
| 3004 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
| 3005 | */ |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 3006 | switch (port) { |
| 3007 | case PORT_A: |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 3008 | type = DRM_MODE_CONNECTOR_eDP; |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 3009 | break; |
| 3010 | case PORT_C: |
| 3011 | if (IS_VALLEYVIEW(dev)) |
| 3012 | type = DRM_MODE_CONNECTOR_eDP; |
| 3013 | break; |
| 3014 | case PORT_D: |
| 3015 | if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev)) |
| 3016 | type = DRM_MODE_CONNECTOR_eDP; |
| 3017 | break; |
| 3018 | default: /* silence GCC warning */ |
| 3019 | break; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 3020 | } |
| 3021 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 3022 | /* |
| 3023 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 3024 | * for DP the encoder type can be set by the caller to |
| 3025 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 3026 | */ |
| 3027 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 3028 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 3029 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 3030 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 3031 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 3032 | port_name(port)); |
| 3033 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 3034 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3035 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 3036 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3037 | connector->interlace_allowed = true; |
| 3038 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 3039 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 3040 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
| 3041 | ironlake_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 3042 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 3043 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3044 | drm_sysfs_connector_add(connector); |
| 3045 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 3046 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 3047 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 3048 | else |
| 3049 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
| 3050 | |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 3051 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
| 3052 | if (HAS_DDI(dev)) { |
| 3053 | switch (intel_dig_port->port) { |
| 3054 | case PORT_A: |
| 3055 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
| 3056 | break; |
| 3057 | case PORT_B: |
| 3058 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
| 3059 | break; |
| 3060 | case PORT_C: |
| 3061 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
| 3062 | break; |
| 3063 | case PORT_D: |
| 3064 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
| 3065 | break; |
| 3066 | default: |
| 3067 | BUG(); |
| 3068 | } |
| 3069 | } |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 3070 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3071 | /* Set up the DDC bus. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3072 | switch (port) { |
| 3073 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3074 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3075 | name = "DPDDC-A"; |
| 3076 | break; |
| 3077 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3078 | intel_encoder->hpd_pin = HPD_PORT_B; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3079 | name = "DPDDC-B"; |
| 3080 | break; |
| 3081 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3082 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3083 | name = "DPDDC-C"; |
| 3084 | break; |
| 3085 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 3086 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 3087 | name = "DPDDC-D"; |
| 3088 | break; |
| 3089 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 3090 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3091 | } |
| 3092 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3093 | if (is_edp(intel_dp)) |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3094 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 3095 | |
| 3096 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
| 3097 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3098 | /* Cache DPCD and EDID for edp. */ |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 3099 | if (is_edp(intel_dp)) { |
| 3100 | bool ret; |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3101 | struct drm_display_mode *scan; |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 3102 | struct edid *edid; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 3103 | |
| 3104 | ironlake_edp_panel_vdd_on(intel_dp); |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 3105 | ret = intel_dp_get_dpcd(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 3106 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 3107 | |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 3108 | if (ret) { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 3109 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 3110 | dev_priv->no_aux_handshake = |
| 3111 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 3112 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 3113 | } else { |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 3114 | /* if this fails, presume the device is a ghost */ |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 3115 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3116 | intel_dp_encoder_destroy(&intel_encoder->base); |
| 3117 | intel_dp_destroy(connector); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 3118 | return; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 3119 | } |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 3120 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3121 | /* We now know it's not a ghost, init power sequence regs. */ |
| 3122 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 3123 | &power_seq); |
| 3124 | |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3125 | ironlake_edp_panel_vdd_on(intel_dp); |
| 3126 | edid = drm_get_edid(connector, &intel_dp->adapter); |
| 3127 | if (edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3128 | if (drm_add_edid_modes(connector, edid)) { |
| 3129 | drm_mode_connector_update_edid_property(connector, edid); |
| 3130 | drm_edid_to_eld(connector, edid); |
| 3131 | } else { |
| 3132 | kfree(edid); |
| 3133 | edid = ERR_PTR(-EINVAL); |
| 3134 | } |
| 3135 | } else { |
| 3136 | edid = ERR_PTR(-ENOENT); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3137 | } |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3138 | intel_connector->edid = edid; |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3139 | |
| 3140 | /* prefer fixed mode from EDID if available */ |
| 3141 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 3142 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 3143 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 3144 | break; |
| 3145 | } |
| 3146 | } |
| 3147 | |
| 3148 | /* fallback to VBT if available for eDP */ |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3149 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 3150 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3151 | if (fixed_mode) |
| 3152 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 3153 | } |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3154 | |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3155 | ironlake_edp_panel_vdd_off(intel_dp, false); |
| 3156 | } |
Keith Packard | 552fb0b | 2011-09-28 16:31:53 -0700 | [diff] [blame] | 3157 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 3158 | if (is_edp(intel_dp)) { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3159 | intel_panel_init(&intel_connector->panel, fixed_mode); |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 3160 | intel_panel_setup_backlight(connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3161 | } |
| 3162 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3163 | intel_dp_add_properties(intel_dp, connector); |
| 3164 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3165 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 3166 | * 0xd. Failure to do so will result in spurious interrupts being |
| 3167 | * generated on the port when a cable is not attached. |
| 3168 | */ |
| 3169 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 3170 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 3171 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 3172 | } |
| 3173 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3174 | |
| 3175 | void |
| 3176 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
| 3177 | { |
| 3178 | struct intel_digital_port *intel_dig_port; |
| 3179 | struct intel_encoder *intel_encoder; |
| 3180 | struct drm_encoder *encoder; |
| 3181 | struct intel_connector *intel_connector; |
| 3182 | |
| 3183 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); |
| 3184 | if (!intel_dig_port) |
| 3185 | return; |
| 3186 | |
| 3187 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 3188 | if (!intel_connector) { |
| 3189 | kfree(intel_dig_port); |
| 3190 | return; |
| 3191 | } |
| 3192 | |
| 3193 | intel_encoder = &intel_dig_port->base; |
| 3194 | encoder = &intel_encoder->base; |
| 3195 | |
| 3196 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
| 3197 | DRM_MODE_ENCODER_TMDS); |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3198 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3199 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 3200 | intel_encoder->compute_config = intel_dp_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3201 | intel_encoder->enable = intel_enable_dp; |
| 3202 | intel_encoder->pre_enable = intel_pre_enable_dp; |
| 3203 | intel_encoder->disable = intel_disable_dp; |
| 3204 | intel_encoder->post_disable = intel_post_disable_dp; |
| 3205 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 3206 | intel_encoder->get_config = intel_dp_get_config; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 3207 | if (IS_VALLEYVIEW(dev)) |
| 3208 | intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3209 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3210 | intel_dig_port->port = port; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3211 | intel_dig_port->dp.output_reg = output_reg; |
| 3212 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3213 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 3214 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 3215 | intel_encoder->cloneable = false; |
| 3216 | intel_encoder->hot_plug = intel_dp_hot_plug; |
| 3217 | |
| 3218 | intel_dp_init_connector(intel_dig_port, intel_connector); |
| 3219 | } |