Amit Daniel Kachhap | e6b7991 | 2013-06-24 16:20:28 +0530 | [diff] [blame] | 1 | /* |
| 2 | * exynos_tmu_data.h - Samsung EXYNOS tmu data header file |
| 3 | * |
| 4 | * Copyright (C) 2013 Samsung Electronics |
| 5 | * Amit Daniel Kachhap <amit.daniel@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | #ifndef _EXYNOS_TMU_DATA_H |
| 24 | #define _EXYNOS_TMU_DATA_H |
| 25 | |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 26 | /* Exynos generic registers */ |
| 27 | #define EXYNOS_TMU_REG_TRIMINFO 0x0 |
| 28 | #define EXYNOS_TMU_REG_CONTROL 0x20 |
| 29 | #define EXYNOS_TMU_REG_STATUS 0x28 |
| 30 | #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 |
| 31 | #define EXYNOS_TMU_REG_INTEN 0x70 |
| 32 | #define EXYNOS_TMU_REG_INTSTAT 0x74 |
| 33 | #define EXYNOS_TMU_REG_INTCLEAR 0x78 |
| 34 | |
| 35 | #define EXYNOS_TMU_TEMP_MASK 0xff |
| 36 | #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 |
| 37 | #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f |
| 38 | #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf |
| 39 | #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 |
| 40 | #define EXYNOS_TMU_CORE_EN_SHIFT 0 |
| 41 | |
Chanwoo Choi | 32a7416 | 2014-09-03 12:09:03 +0900 | [diff] [blame] | 42 | /* Exynos3250 specific registers */ |
| 43 | #define EXYNOS_TMU_TRIMINFO_CON1 0x10 |
| 44 | |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 45 | /* Exynos4210 specific registers */ |
| 46 | #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 |
| 47 | #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 48 | |
Chanwoo Choi | 32a7416 | 2014-09-03 12:09:03 +0900 | [diff] [blame] | 49 | /* Exynos5250, Exynos4412, Exynos3250 specific registers */ |
| 50 | #define EXYNOS_TMU_TRIMINFO_CON2 0x14 |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 51 | #define EXYNOS_THD_TEMP_RISE 0x50 |
| 52 | #define EXYNOS_THD_TEMP_FALL 0x54 |
| 53 | #define EXYNOS_EMUL_CON 0x80 |
| 54 | |
Chanwoo Choi | 56c64da | 2014-09-03 12:09:02 +0900 | [diff] [blame] | 55 | #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 56 | #define EXYNOS_TRIMINFO_25_SHIFT 0 |
| 57 | #define EXYNOS_TRIMINFO_85_SHIFT 8 |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 58 | #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 |
| 59 | #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 |
| 60 | #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 |
| 61 | |
| 62 | #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 |
| 63 | #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 |
| 64 | #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 |
| 65 | #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 |
| 66 | #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 |
Amit Daniel Kachhap | b8d582b | 2013-06-24 16:20:31 +0530 | [diff] [blame] | 67 | |
| 68 | #define EXYNOS_EMUL_TIME 0x57F0 |
| 69 | #define EXYNOS_EMUL_TIME_MASK 0xffff |
| 70 | #define EXYNOS_EMUL_TIME_SHIFT 16 |
| 71 | #define EXYNOS_EMUL_DATA_SHIFT 8 |
| 72 | #define EXYNOS_EMUL_DATA_MASK 0xFF |
| 73 | #define EXYNOS_EMUL_ENABLE 0x1 |
| 74 | |
Amit Daniel Kachhap | 7ca04e5 | 2013-06-24 16:20:32 +0530 | [diff] [blame] | 75 | #define EXYNOS_MAX_TRIGGER_PER_REG 4 |
| 76 | |
Naveen Krishna Chatradhi | 923488a | 2013-12-20 17:49:10 +0530 | [diff] [blame] | 77 | /* Exynos5260 specific */ |
| 78 | #define EXYNOS_TMU_REG_CONTROL1 0x24 |
| 79 | #define EXYNOS5260_TMU_REG_INTEN 0xC0 |
| 80 | #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 |
| 81 | #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 |
Naveen Krishna Chatradhi | 923488a | 2013-12-20 17:49:10 +0530 | [diff] [blame] | 82 | #define EXYNOS5260_EMUL_CON 0x100 |
| 83 | |
Lukasz Majewski | 86f5362 | 2013-10-09 08:29:52 +0200 | [diff] [blame] | 84 | /* Exynos4412 specific */ |
| 85 | #define EXYNOS4412_MUX_ADDR_VALUE 6 |
| 86 | #define EXYNOS4412_MUX_ADDR_SHIFT 20 |
| 87 | |
Amit Daniel Kachhap | a0395ee | 2013-06-24 16:20:43 +0530 | [diff] [blame] | 88 | /*exynos5440 specific registers*/ |
| 89 | #define EXYNOS5440_TMU_S0_7_TRIM 0x000 |
| 90 | #define EXYNOS5440_TMU_S0_7_CTRL 0x020 |
| 91 | #define EXYNOS5440_TMU_S0_7_DEBUG 0x040 |
| 92 | #define EXYNOS5440_TMU_S0_7_STATUS 0x060 |
| 93 | #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 |
| 94 | #define EXYNOS5440_TMU_S0_7_TH0 0x110 |
| 95 | #define EXYNOS5440_TMU_S0_7_TH1 0x130 |
| 96 | #define EXYNOS5440_TMU_S0_7_TH2 0x150 |
Amit Daniel Kachhap | a0395ee | 2013-06-24 16:20:43 +0530 | [diff] [blame] | 97 | #define EXYNOS5440_TMU_S0_7_IRQEN 0x210 |
| 98 | #define EXYNOS5440_TMU_S0_7_IRQ 0x230 |
| 99 | /* exynos5440 common registers */ |
| 100 | #define EXYNOS5440_TMU_IRQ_STATUS 0x000 |
| 101 | #define EXYNOS5440_TMU_PMIN 0x004 |
Amit Daniel Kachhap | a0395ee | 2013-06-24 16:20:43 +0530 | [diff] [blame] | 102 | |
Amit Daniel Kachhap | a0395ee | 2013-06-24 16:20:43 +0530 | [diff] [blame] | 103 | #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 |
| 104 | #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 |
| 105 | #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 |
| 106 | #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 |
| 107 | #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 |
Amit Daniel Kachhap | a0395ee | 2013-06-24 16:20:43 +0530 | [diff] [blame] | 108 | #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 |
| 109 | #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 |
| 110 | |
Chanwoo Choi | 1fe56dc | 2014-07-01 09:33:19 +0900 | [diff] [blame] | 111 | #if defined(CONFIG_SOC_EXYNOS3250) |
| 112 | extern struct exynos_tmu_init_data const exynos3250_default_tmu_data; |
| 113 | #define EXYNOS3250_TMU_DRV_DATA (&exynos3250_default_tmu_data) |
| 114 | #else |
| 115 | #define EXYNOS3250_TMU_DRV_DATA (NULL) |
| 116 | #endif |
| 117 | |
Amit Daniel Kachhap | e6b7991 | 2013-06-24 16:20:28 +0530 | [diff] [blame] | 118 | #if defined(CONFIG_CPU_EXYNOS4210) |
Amit Daniel Kachhap | cebe737 | 2013-06-24 16:20:39 +0530 | [diff] [blame] | 119 | extern struct exynos_tmu_init_data const exynos4210_default_tmu_data; |
Amit Daniel Kachhap | e6b7991 | 2013-06-24 16:20:28 +0530 | [diff] [blame] | 120 | #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data) |
| 121 | #else |
| 122 | #define EXYNOS4210_TMU_DRV_DATA (NULL) |
| 123 | #endif |
| 124 | |
Lukasz Majewski | 14ddfae | 2013-10-09 08:29:51 +0200 | [diff] [blame] | 125 | #if defined(CONFIG_SOC_EXYNOS4412) |
| 126 | extern struct exynos_tmu_init_data const exynos4412_default_tmu_data; |
| 127 | #define EXYNOS4412_TMU_DRV_DATA (&exynos4412_default_tmu_data) |
| 128 | #else |
| 129 | #define EXYNOS4412_TMU_DRV_DATA (NULL) |
| 130 | #endif |
| 131 | |
| 132 | #if defined(CONFIG_SOC_EXYNOS5250) |
Amit Daniel Kachhap | cebe737 | 2013-06-24 16:20:39 +0530 | [diff] [blame] | 133 | extern struct exynos_tmu_init_data const exynos5250_default_tmu_data; |
Amit Daniel Kachhap | e6b7991 | 2013-06-24 16:20:28 +0530 | [diff] [blame] | 134 | #define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data) |
| 135 | #else |
| 136 | #define EXYNOS5250_TMU_DRV_DATA (NULL) |
| 137 | #endif |
| 138 | |
Naveen Krishna Chatradhi | 923488a | 2013-12-20 17:49:10 +0530 | [diff] [blame] | 139 | #if defined(CONFIG_SOC_EXYNOS5260) |
| 140 | extern struct exynos_tmu_init_data const exynos5260_default_tmu_data; |
| 141 | #define EXYNOS5260_TMU_DRV_DATA (&exynos5260_default_tmu_data) |
| 142 | #else |
| 143 | #define EXYNOS5260_TMU_DRV_DATA (NULL) |
| 144 | #endif |
| 145 | |
Naveen Krishna Chatradhi | 14a11dc | 2013-12-19 11:36:31 +0530 | [diff] [blame] | 146 | #if defined(CONFIG_SOC_EXYNOS5420) |
| 147 | extern struct exynos_tmu_init_data const exynos5420_default_tmu_data; |
| 148 | #define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data) |
| 149 | #else |
| 150 | #define EXYNOS5420_TMU_DRV_DATA (NULL) |
| 151 | #endif |
| 152 | |
Amit Daniel Kachhap | 9054254 | 2013-06-24 16:20:44 +0530 | [diff] [blame] | 153 | #if defined(CONFIG_SOC_EXYNOS5440) |
| 154 | extern struct exynos_tmu_init_data const exynos5440_default_tmu_data; |
| 155 | #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data) |
| 156 | #else |
| 157 | #define EXYNOS5440_TMU_DRV_DATA (NULL) |
| 158 | #endif |
| 159 | |
Amit Daniel Kachhap | e6b7991 | 2013-06-24 16:20:28 +0530 | [diff] [blame] | 160 | #endif /*_EXYNOS_TMU_DATA_H*/ |