Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/flush.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2002 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/mm.h> |
| 12 | #include <linux/pagemap.h> |
| 13 | |
| 14 | #include <asm/cacheflush.h> |
| 15 | #include <asm/system.h> |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 16 | #include <asm/tlbflush.h> |
| 17 | |
Russell King | 1b2e2b7 | 2006-08-21 17:06:38 +0100 | [diff] [blame] | 18 | #include "mm.h" |
| 19 | |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 20 | #ifdef CONFIG_CPU_CACHE_VIPT |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 21 | |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 22 | #define ALIAS_FLUSH_START 0xffff4000 |
| 23 | |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 24 | static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) |
| 25 | { |
| 26 | unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); |
Catalin Marinas | 141fa40 | 2006-03-10 22:26:47 +0000 | [diff] [blame] | 27 | const int zero = 0; |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 28 | |
| 29 | set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); |
| 30 | flush_tlb_kernel_page(to); |
| 31 | |
| 32 | asm( "mcrr p15, 0, %1, %0, c14\n" |
Catalin Marinas | 141fa40 | 2006-03-10 22:26:47 +0000 | [diff] [blame] | 33 | " mcr p15, 0, %2, c7, c10, 4\n" |
| 34 | " mcr p15, 0, %2, c7, c5, 0\n" |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 35 | : |
Catalin Marinas | 141fa40 | 2006-03-10 22:26:47 +0000 | [diff] [blame] | 36 | : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) |
Catalin Marinas | 481467d | 2005-09-30 16:07:04 +0100 | [diff] [blame] | 37 | : "cc"); |
| 38 | } |
| 39 | |
Russell King | d7b6b35 | 2005-09-08 15:32:23 +0100 | [diff] [blame] | 40 | void flush_cache_mm(struct mm_struct *mm) |
| 41 | { |
| 42 | if (cache_is_vivt()) { |
| 43 | if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) |
| 44 | __cpuc_flush_user_all(); |
| 45 | return; |
| 46 | } |
| 47 | |
| 48 | if (cache_is_vipt_aliasing()) { |
| 49 | asm( "mcr p15, 0, %0, c7, c14, 0\n" |
| 50 | " mcr p15, 0, %0, c7, c5, 0\n" |
| 51 | " mcr p15, 0, %0, c7, c10, 4" |
| 52 | : |
| 53 | : "r" (0) |
| 54 | : "cc"); |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
| 59 | { |
| 60 | if (cache_is_vivt()) { |
| 61 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) |
| 62 | __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), |
| 63 | vma->vm_flags); |
| 64 | return; |
| 65 | } |
| 66 | |
| 67 | if (cache_is_vipt_aliasing()) { |
| 68 | asm( "mcr p15, 0, %0, c7, c14, 0\n" |
| 69 | " mcr p15, 0, %0, c7, c5, 0\n" |
| 70 | " mcr p15, 0, %0, c7, c10, 4" |
| 71 | : |
| 72 | : "r" (0) |
| 73 | : "cc"); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) |
| 78 | { |
| 79 | if (cache_is_vivt()) { |
| 80 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { |
| 81 | unsigned long addr = user_addr & PAGE_MASK; |
| 82 | __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); |
| 83 | } |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | if (cache_is_vipt_aliasing()) |
| 88 | flush_pfn_alias(pfn, user_addr); |
| 89 | } |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 90 | |
| 91 | void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, |
| 92 | unsigned long uaddr, void *kaddr, |
| 93 | unsigned long len, int write) |
| 94 | { |
| 95 | if (cache_is_vivt()) { |
| 96 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { |
| 97 | unsigned long addr = (unsigned long)kaddr; |
| 98 | __cpuc_coherent_kern_range(addr, addr + len); |
| 99 | } |
| 100 | return; |
| 101 | } |
| 102 | |
| 103 | if (cache_is_vipt_aliasing()) { |
| 104 | flush_pfn_alias(page_to_pfn(page), uaddr); |
| 105 | return; |
| 106 | } |
| 107 | |
| 108 | /* VIPT non-aliasing cache */ |
| 109 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask) && |
George G. Davis | a71ebdf | 2006-09-21 03:57:04 +0100 | [diff] [blame^] | 110 | vma->vm_flags & VM_EXEC) { |
George G. Davis | a188ad2 | 2006-09-02 18:43:20 +0100 | [diff] [blame] | 111 | unsigned long addr = (unsigned long)kaddr; |
| 112 | /* only flushing the kernel mapping on non-aliasing VIPT */ |
| 113 | __cpuc_coherent_kern_range(addr, addr + len); |
| 114 | } |
| 115 | } |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 116 | #else |
| 117 | #define flush_pfn_alias(pfn,vaddr) do { } while (0) |
| 118 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 119 | |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 120 | void __flush_dcache_page(struct address_space *mapping, struct page *page) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | /* |
| 123 | * Writeback any data associated with the kernel mapping of this |
| 124 | * page. This ensures that data in the physical page is mutually |
| 125 | * coherent with the kernels mapping. |
| 126 | */ |
| 127 | __cpuc_flush_dcache_page(page_address(page)); |
| 128 | |
| 129 | /* |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 130 | * If this is a page cache page, and we have an aliasing VIPT cache, |
| 131 | * we only need to do one flush - which would be at the relevant |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 132 | * userspace colour, which is congruent with page->index. |
| 133 | */ |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 134 | if (mapping && cache_is_vipt_aliasing()) |
| 135 | flush_pfn_alias(page_to_pfn(page), |
| 136 | page->index << PAGE_CACHE_SHIFT); |
| 137 | } |
| 138 | |
| 139 | static void __flush_dcache_aliases(struct address_space *mapping, struct page *page) |
| 140 | { |
| 141 | struct mm_struct *mm = current->active_mm; |
| 142 | struct vm_area_struct *mpnt; |
| 143 | struct prio_tree_iter iter; |
| 144 | pgoff_t pgoff; |
Russell King | 8d802d2 | 2005-05-10 17:31:43 +0100 | [diff] [blame] | 145 | |
| 146 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | * There are possible user space mappings of this page: |
| 148 | * - VIVT cache: we need to also write back and invalidate all user |
| 149 | * data in the current VM view associated with this page. |
| 150 | * - aliasing VIPT: we only need to find one mapping of this page. |
| 151 | */ |
| 152 | pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT); |
| 153 | |
| 154 | flush_dcache_mmap_lock(mapping); |
| 155 | vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) { |
| 156 | unsigned long offset; |
| 157 | |
| 158 | /* |
| 159 | * If this VMA is not in our MM, we can ignore it. |
| 160 | */ |
| 161 | if (mpnt->vm_mm != mm) |
| 162 | continue; |
| 163 | if (!(mpnt->vm_flags & VM_MAYSHARE)) |
| 164 | continue; |
| 165 | offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; |
| 166 | flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | } |
| 168 | flush_dcache_mmap_unlock(mapping); |
| 169 | } |
| 170 | |
| 171 | /* |
| 172 | * Ensure cache coherency between kernel mapping and userspace mapping |
| 173 | * of this page. |
| 174 | * |
| 175 | * We have three cases to consider: |
| 176 | * - VIPT non-aliasing cache: fully coherent so nothing required. |
| 177 | * - VIVT: fully aliasing, so we need to handle every alias in our |
| 178 | * current VM view. |
| 179 | * - VIPT aliasing: need to handle one alias in our current VM view. |
| 180 | * |
| 181 | * If we need to handle aliasing: |
| 182 | * If the page only exists in the page cache and there are no user |
| 183 | * space mappings, we can be lazy and remember that we may have dirty |
| 184 | * kernel cache lines for later. Otherwise, we assume we have |
| 185 | * aliasing mappings. |
Russell King | df2f5e7 | 2005-11-30 16:02:54 +0000 | [diff] [blame] | 186 | * |
| 187 | * Note that we disable the lazy flush for SMP. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | */ |
| 189 | void flush_dcache_page(struct page *page) |
| 190 | { |
| 191 | struct address_space *mapping = page_mapping(page); |
| 192 | |
Russell King | df2f5e7 | 2005-11-30 16:02:54 +0000 | [diff] [blame] | 193 | #ifndef CONFIG_SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | if (mapping && !mapping_mapped(mapping)) |
| 195 | set_bit(PG_dcache_dirty, &page->flags); |
Russell King | df2f5e7 | 2005-11-30 16:02:54 +0000 | [diff] [blame] | 196 | else |
| 197 | #endif |
| 198 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | __flush_dcache_page(mapping, page); |
Russell King | 8830f04 | 2005-06-20 09:51:03 +0100 | [diff] [blame] | 200 | if (mapping && cache_is_vivt()) |
| 201 | __flush_dcache_aliases(mapping, page); |
| 202 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | } |
| 204 | EXPORT_SYMBOL(flush_dcache_page); |