Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. |
| 3 | * Author: Xing Zheng <zhengxing@rock-chips.com> |
| 4 | * Jeffy Chen <jeffy.chen@rock-chips.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/of_address.h> |
| 20 | #include <linux/syscore_ops.h> |
| 21 | #include <dt-bindings/clock/rk3228-cru.h> |
| 22 | #include "clk.h" |
| 23 | |
| 24 | #define RK3228_GRF_SOC_STATUS0 0x480 |
| 25 | |
| 26 | enum rk3228_plls { |
| 27 | apll, dpll, cpll, gpll, |
| 28 | }; |
| 29 | |
| 30 | static struct rockchip_pll_rate_table rk3228_pll_rates[] = { |
| 31 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ |
| 32 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), |
| 33 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), |
| 34 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), |
| 35 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), |
| 36 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), |
| 37 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), |
| 38 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), |
| 39 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), |
| 40 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), |
| 41 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), |
| 42 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), |
| 43 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), |
| 44 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), |
| 45 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), |
| 46 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), |
| 47 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), |
| 48 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), |
| 49 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), |
| 50 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), |
| 51 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), |
| 52 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), |
| 53 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), |
| 54 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), |
| 55 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), |
| 56 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), |
| 57 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), |
| 58 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), |
| 59 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), |
| 60 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), |
| 61 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), |
| 62 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), |
| 63 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), |
| 64 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), |
| 65 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), |
| 66 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), |
| 67 | RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), |
| 68 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), |
| 69 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), |
| 70 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), |
| 71 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), |
| 72 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), |
| 73 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), |
| 74 | { /* sentinel */ }, |
| 75 | }; |
| 76 | |
| 77 | #define RK3228_DIV_CPU_MASK 0x1f |
| 78 | #define RK3228_DIV_CPU_SHIFT 8 |
| 79 | |
| 80 | #define RK3228_DIV_PERI_MASK 0xf |
| 81 | #define RK3228_DIV_PERI_SHIFT 0 |
| 82 | #define RK3228_DIV_ACLK_MASK 0x7 |
| 83 | #define RK3228_DIV_ACLK_SHIFT 4 |
| 84 | #define RK3228_DIV_HCLK_MASK 0x3 |
| 85 | #define RK3228_DIV_HCLK_SHIFT 8 |
| 86 | #define RK3228_DIV_PCLK_MASK 0x7 |
| 87 | #define RK3228_DIV_PCLK_SHIFT 12 |
| 88 | |
| 89 | #define RK3228_CLKSEL1(_core_peri_div) \ |
| 90 | { \ |
| 91 | .reg = RK2928_CLKSEL_CON(1), \ |
| 92 | .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ |
| 93 | RK3228_DIV_PERI_SHIFT) \ |
| 94 | } |
| 95 | |
| 96 | #define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ |
| 97 | { \ |
| 98 | .prate = _prate, \ |
| 99 | .divs = { \ |
| 100 | RK3228_CLKSEL1(_core_peri_div), \ |
| 101 | }, \ |
| 102 | } |
| 103 | |
| 104 | static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { |
| 105 | RK3228_CPUCLK_RATE(816000000, 4), |
| 106 | RK3228_CPUCLK_RATE(600000000, 4), |
| 107 | RK3228_CPUCLK_RATE(312000000, 4), |
| 108 | }; |
| 109 | |
| 110 | static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { |
| 111 | .core_reg = RK2928_CLKSEL_CON(0), |
| 112 | .div_core_shift = 0, |
| 113 | .div_core_mask = 0x1f, |
Xing Zheng | 268aeba | 2016-03-09 10:37:03 +0800 | [diff] [blame] | 114 | .mux_core_alt = 1, |
| 115 | .mux_core_main = 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 116 | .mux_core_shift = 6, |
Xing Zheng | 268aeba | 2016-03-09 10:37:03 +0800 | [diff] [blame] | 117 | .mux_core_mask = 0x1, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 118 | }; |
| 119 | |
| 120 | PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; |
| 121 | |
| 122 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; |
| 123 | PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; |
| 124 | PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; |
| 125 | PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; |
| 126 | PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; |
| 127 | PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; |
| 128 | |
| 129 | PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; |
| 130 | PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; |
| 131 | PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; |
| 132 | PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; |
| 133 | PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" }; |
| 134 | PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; |
| 135 | PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; |
| 136 | |
| 137 | PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; |
| 138 | |
| 139 | PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; |
| 140 | PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; |
| 141 | |
| 142 | PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; |
| 143 | PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; |
| 144 | PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; |
| 145 | PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; |
| 146 | PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; |
| 147 | |
| 148 | PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; |
| 149 | |
| 150 | PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; |
| 151 | PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; |
| 152 | PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; |
| 153 | |
Xing Zheng | 09f6842 | 2016-06-21 12:53:30 +0800 | [diff] [blame] | 154 | PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" }; |
| 155 | PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" }; |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 156 | PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; |
| 157 | |
| 158 | static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { |
| 159 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), |
| 160 | RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), |
| 161 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), |
| 162 | RK2928_MODE_CON, 4, 6, 0, NULL), |
| 163 | [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), |
| 164 | RK2928_MODE_CON, 8, 8, 0, NULL), |
| 165 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), |
| 166 | RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), |
| 167 | }; |
| 168 | |
| 169 | #define MFLAGS CLK_MUX_HIWORD_MASK |
| 170 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK |
| 171 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) |
| 172 | |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 173 | static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata = |
| 174 | MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, |
| 175 | RK2928_CLKSEL_CON(9), 8, 2, MFLAGS); |
| 176 | |
| 177 | static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata = |
| 178 | MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, |
| 179 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); |
| 180 | |
| 181 | static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata = |
| 182 | MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, |
| 183 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); |
| 184 | |
| 185 | static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata = |
| 186 | MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, |
| 187 | RK2928_CLKSEL_CON(6), 8, 2, MFLAGS); |
| 188 | |
| 189 | static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata = |
| 190 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, |
| 191 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); |
| 192 | |
| 193 | static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata = |
| 194 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, |
| 195 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); |
| 196 | |
| 197 | static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata = |
| 198 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, |
| 199 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); |
| 200 | |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 201 | static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { |
| 202 | /* |
| 203 | * Clock-Architecture Diagram 1 |
| 204 | */ |
| 205 | |
| 206 | DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, |
| 207 | RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), |
| 208 | |
| 209 | /* PD_DDR */ |
| 210 | GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, |
| 211 | RK2928_CLKGATE_CON(0), 2, GFLAGS), |
| 212 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, |
| 213 | RK2928_CLKGATE_CON(0), 2, GFLAGS), |
| 214 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, |
| 215 | RK2928_CLKGATE_CON(0), 2, GFLAGS), |
| 216 | COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, |
| 217 | RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
| 218 | RK2928_CLKGATE_CON(7), 1, GFLAGS), |
| 219 | GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED, |
| 220 | RK2928_CLKGATE_CON(8), 5, GFLAGS), |
Heiko Stuebner | 3671452 | 2015-06-20 16:06:02 +0200 | [diff] [blame] | 221 | FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 222 | RK2928_CLKGATE_CON(7), 0, GFLAGS), |
| 223 | |
| 224 | /* PD_CORE */ |
| 225 | GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, |
| 226 | RK2928_CLKGATE_CON(0), 6, GFLAGS), |
| 227 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, |
| 228 | RK2928_CLKGATE_CON(0), 6, GFLAGS), |
| 229 | GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, |
| 230 | RK2928_CLKGATE_CON(0), 6, GFLAGS), |
| 231 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, |
| 232 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 233 | RK2928_CLKGATE_CON(4), 1, GFLAGS), |
| 234 | COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, |
| 235 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 236 | RK2928_CLKGATE_CON(4), 0, GFLAGS), |
| 237 | |
| 238 | /* PD_MISC */ |
| 239 | MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, |
| 240 | RK2928_MISC_CON, 13, 1, MFLAGS), |
| 241 | MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, |
| 242 | RK2928_MISC_CON, 14, 1, MFLAGS), |
| 243 | MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, |
| 244 | RK2928_MISC_CON, 15, 1, MFLAGS), |
| 245 | |
| 246 | /* PD_BUS */ |
| 247 | GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, |
| 248 | RK2928_CLKGATE_CON(0), 1, GFLAGS), |
| 249 | GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, |
| 250 | RK2928_CLKGATE_CON(0), 1, GFLAGS), |
| 251 | GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, |
| 252 | RK2928_CLKGATE_CON(0), 1, GFLAGS), |
| 253 | COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, |
| 254 | RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), |
| 255 | GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0, |
| 256 | RK2928_CLKGATE_CON(6), 0, GFLAGS), |
| 257 | COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0, |
| 258 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, |
| 259 | RK2928_CLKGATE_CON(6), 1, GFLAGS), |
| 260 | COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, |
| 261 | RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, |
| 262 | RK2928_CLKGATE_CON(6), 2, GFLAGS), |
| 263 | GATE(0, "pclk_cpu", "pclk_bus_src", 0, |
| 264 | RK2928_CLKGATE_CON(6), 3, GFLAGS), |
| 265 | GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, |
| 266 | RK2928_CLKGATE_CON(6), 4, GFLAGS), |
| 267 | GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, |
| 268 | RK2928_CLKGATE_CON(6), 13, GFLAGS), |
| 269 | |
| 270 | /* PD_VIDEO */ |
| 271 | COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, |
| 272 | RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, |
| 273 | RK2928_CLKGATE_CON(3), 11, GFLAGS), |
Heiko Stuebner | 3671452 | 2015-06-20 16:06:02 +0200 | [diff] [blame] | 274 | FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 275 | RK2928_CLKGATE_CON(4), 4, GFLAGS), |
| 276 | |
| 277 | COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, |
| 278 | RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 279 | RK2928_CLKGATE_CON(3), 2, GFLAGS), |
Heiko Stuebner | 3671452 | 2015-06-20 16:06:02 +0200 | [diff] [blame] | 280 | FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 281 | RK2928_CLKGATE_CON(4), 5, GFLAGS), |
| 282 | |
| 283 | COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, |
| 284 | RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 285 | RK2928_CLKGATE_CON(3), 3, GFLAGS), |
| 286 | |
| 287 | COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0, |
| 288 | RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS, |
| 289 | RK2928_CLKGATE_CON(3), 4, GFLAGS), |
| 290 | |
| 291 | /* PD_VIO */ |
| 292 | COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0, |
| 293 | RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS, |
| 294 | RK2928_CLKGATE_CON(3), 0, GFLAGS), |
| 295 | DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0, |
| 296 | RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), |
| 297 | |
| 298 | COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, |
| 299 | RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS, |
| 300 | RK2928_CLKGATE_CON(1), 4, GFLAGS), |
| 301 | |
| 302 | MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, |
| 303 | RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), |
| 304 | COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0, |
| 305 | RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, |
| 306 | RK2928_CLKGATE_CON(1), 2, GFLAGS), |
| 307 | COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0, |
| 308 | RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS, |
| 309 | RK2928_CLKGATE_CON(3), 6, GFLAGS), |
| 310 | |
| 311 | COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0, |
| 312 | RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS, |
| 313 | RK2928_CLKGATE_CON(1), 1, GFLAGS), |
| 314 | |
| 315 | COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0, |
| 316 | RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS, |
| 317 | RK2928_CLKGATE_CON(3), 5, GFLAGS), |
| 318 | |
Yakir Yang | bdc7dee | 2016-02-24 18:16:28 +0800 | [diff] [blame] | 319 | GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 320 | RK2928_CLKGATE_CON(3), 7, GFLAGS), |
| 321 | |
| 322 | COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, |
| 323 | RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS, |
| 324 | RK2928_CLKGATE_CON(3), 8, GFLAGS), |
| 325 | |
| 326 | /* PD_PERI */ |
| 327 | GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, |
| 328 | RK2928_CLKGATE_CON(2), 0, GFLAGS), |
| 329 | GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, |
| 330 | RK2928_CLKGATE_CON(2), 0, GFLAGS), |
| 331 | GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, |
| 332 | RK2928_CLKGATE_CON(2), 0, GFLAGS), |
| 333 | COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, |
| 334 | RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), |
| 335 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, |
| 336 | RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, |
| 337 | RK2928_CLKGATE_CON(5), 2, GFLAGS), |
| 338 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, |
| 339 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS, |
| 340 | RK2928_CLKGATE_CON(5), 1, GFLAGS), |
| 341 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, |
| 342 | RK2928_CLKGATE_CON(5), 0, GFLAGS), |
| 343 | |
| 344 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, |
| 345 | RK2928_CLKGATE_CON(6), 5, GFLAGS), |
| 346 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, |
| 347 | RK2928_CLKGATE_CON(6), 6, GFLAGS), |
| 348 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, |
| 349 | RK2928_CLKGATE_CON(6), 7, GFLAGS), |
| 350 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, |
| 351 | RK2928_CLKGATE_CON(6), 8, GFLAGS), |
| 352 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, |
| 353 | RK2928_CLKGATE_CON(6), 9, GFLAGS), |
| 354 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, |
| 355 | RK2928_CLKGATE_CON(6), 10, GFLAGS), |
| 356 | |
| 357 | COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0, |
| 358 | RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS, |
| 359 | RK2928_CLKGATE_CON(2), 7, GFLAGS), |
| 360 | |
| 361 | COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0, |
| 362 | RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 363 | RK2928_CLKGATE_CON(2), 6, GFLAGS), |
| 364 | |
| 365 | GATE(0, "sclk_hsadc", "ext_hsadc", 0, |
Xing Zheng | 67de790 | 2016-06-21 12:53:27 +0800 | [diff] [blame] | 366 | RK2928_CLKGATE_CON(10), 12, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 367 | |
| 368 | COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, |
| 369 | RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, |
| 370 | RK2928_CLKGATE_CON(2), 15, GFLAGS), |
| 371 | |
| 372 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, |
| 373 | RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 374 | RK2928_CLKGATE_CON(2), 11, GFLAGS), |
| 375 | |
| 376 | COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, |
| 377 | RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, |
| 378 | RK2928_CLKGATE_CON(2), 13, GFLAGS), |
| 379 | DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, |
| 380 | RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), |
| 381 | |
| 382 | COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, |
| 383 | RK2928_CLKSEL_CON(11), 12, 2, MFLAGS, |
| 384 | RK2928_CLKGATE_CON(2), 14, GFLAGS), |
| 385 | DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, |
| 386 | RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), |
| 387 | |
| 388 | /* |
| 389 | * Clock-Architecture Diagram 2 |
| 390 | */ |
| 391 | |
| 392 | GATE(0, "gpll_vop", "gpll", 0, |
| 393 | RK2928_CLKGATE_CON(3), 1, GFLAGS), |
| 394 | GATE(0, "cpll_vop", "cpll", 0, |
| 395 | RK2928_CLKGATE_CON(3), 1, GFLAGS), |
| 396 | MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, |
| 397 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), |
Yakir Yang | bdc7dee | 2016-02-24 18:16:28 +0800 | [diff] [blame] | 398 | DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 399 | RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), |
| 400 | DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, |
| 401 | RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), |
Yakir Yang | 0a9d4ac | 2016-02-24 18:54:18 +0800 | [diff] [blame] | 402 | MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 403 | RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), |
| 404 | |
Heiko Stuebner | 3671452 | 2015-06-20 16:06:02 +0200 | [diff] [blame] | 405 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), |
| 406 | |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 407 | COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, |
| 408 | RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 409 | RK2928_CLKGATE_CON(0), 3, GFLAGS), |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 410 | COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, |
Xing Zheng | 67de790 | 2016-06-21 12:53:27 +0800 | [diff] [blame] | 411 | RK2928_CLKSEL_CON(8), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 412 | RK2928_CLKGATE_CON(0), 4, GFLAGS, |
| 413 | &rk3228_i2s0_fracmux), |
| 414 | GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 415 | RK2928_CLKGATE_CON(0), 5, GFLAGS), |
| 416 | |
| 417 | COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, |
| 418 | RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 419 | RK2928_CLKGATE_CON(0), 10, GFLAGS), |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 420 | COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, |
Xing Zheng | 67de790 | 2016-06-21 12:53:27 +0800 | [diff] [blame] | 421 | RK2928_CLKSEL_CON(7), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 422 | RK2928_CLKGATE_CON(0), 11, GFLAGS, |
| 423 | &rk3228_i2s1_fracmux), |
| 424 | GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 425 | RK2928_CLKGATE_CON(0), 14, GFLAGS), |
| 426 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, |
| 427 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, |
| 428 | RK2928_CLKGATE_CON(0), 13, GFLAGS), |
| 429 | |
| 430 | COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, |
| 431 | RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 432 | RK2928_CLKGATE_CON(0), 7, GFLAGS), |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 433 | COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, |
Xing Zheng | 67de790 | 2016-06-21 12:53:27 +0800 | [diff] [blame] | 434 | RK2928_CLKSEL_CON(30), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 435 | RK2928_CLKGATE_CON(0), 8, GFLAGS, |
| 436 | &rk3228_i2s2_fracmux), |
| 437 | GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 438 | RK2928_CLKGATE_CON(0), 9, GFLAGS), |
| 439 | |
| 440 | COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, |
| 441 | RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, |
| 442 | RK2928_CLKGATE_CON(2), 10, GFLAGS), |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 443 | COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, |
Xing Zheng | 67de790 | 2016-06-21 12:53:27 +0800 | [diff] [blame] | 444 | RK2928_CLKSEL_CON(20), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 445 | RK2928_CLKGATE_CON(2), 12, GFLAGS, |
| 446 | &rk3228_spdif_fracmux), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 447 | |
| 448 | GATE(0, "jtag", "ext_jtag", 0, |
| 449 | RK2928_CLKGATE_CON(1), 3, GFLAGS), |
| 450 | |
| 451 | GATE(0, "sclk_otgphy0", "xin24m", 0, |
| 452 | RK2928_CLKGATE_CON(1), 5, GFLAGS), |
| 453 | GATE(0, "sclk_otgphy1", "xin24m", 0, |
| 454 | RK2928_CLKGATE_CON(1), 6, GFLAGS), |
| 455 | |
Caesar Wang | a3cb9aa | 2016-02-15 15:33:27 +0800 | [diff] [blame] | 456 | COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 457 | RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, |
| 458 | RK2928_CLKGATE_CON(2), 8, GFLAGS), |
| 459 | |
| 460 | GATE(0, "cpll_gpu", "cpll", 0, |
| 461 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
| 462 | GATE(0, "gpll_gpu", "gpll", 0, |
| 463 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
| 464 | GATE(0, "hdmiphy_gpu", "hdmiphy", 0, |
| 465 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
| 466 | GATE(0, "usb480m_gpu", "usb480m", 0, |
| 467 | RK2928_CLKGATE_CON(3), 13, GFLAGS), |
| 468 | COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, |
| 469 | RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), |
| 470 | |
| 471 | COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, |
| 472 | RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, |
| 473 | RK2928_CLKGATE_CON(2), 9, GFLAGS), |
| 474 | |
| 475 | /* PD_UART */ |
| 476 | COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, |
| 477 | RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, |
| 478 | RK2928_CLKGATE_CON(1), 8, GFLAGS), |
| 479 | COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, |
| 480 | RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, |
| 481 | RK2928_CLKGATE_CON(1), 10, GFLAGS), |
| 482 | COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, |
| 483 | 0, RK2928_CLKSEL_CON(15), 12, 2, |
| 484 | MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 485 | COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 486 | RK2928_CLKSEL_CON(17), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 487 | RK2928_CLKGATE_CON(1), 9, GFLAGS, |
| 488 | &rk3228_uart0_fracmux), |
| 489 | COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 490 | RK2928_CLKSEL_CON(18), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 491 | RK2928_CLKGATE_CON(1), 11, GFLAGS, |
| 492 | &rk3228_uart1_fracmux), |
| 493 | COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 494 | RK2928_CLKSEL_CON(19), 0, |
Xing Zheng | cb87df5 | 2016-06-21 12:53:28 +0800 | [diff] [blame] | 495 | RK2928_CLKGATE_CON(1), 13, GFLAGS, |
| 496 | &rk3228_uart2_fracmux), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 497 | |
| 498 | COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, |
| 499 | RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, |
| 500 | RK2928_CLKGATE_CON(1), 0, GFLAGS), |
| 501 | |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 502 | COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 503 | RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS, |
| 504 | RK2928_CLKGATE_CON(1), 7, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 505 | MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 506 | RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 507 | MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 508 | RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 509 | GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 510 | RK2928_CLKGATE_CON(5), 4, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 511 | GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 512 | RK2928_CLKGATE_CON(5), 3, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 513 | GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 514 | RK2928_CLKGATE_CON(5), 5, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 515 | GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 516 | RK2928_CLKGATE_CON(5), 6, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 517 | COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 518 | RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS, |
| 519 | RK2928_CLKGATE_CON(5), 7, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 520 | COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 521 | RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 522 | RK2928_CLKGATE_CON(2), 2, GFLAGS), |
| 523 | |
| 524 | /* |
| 525 | * Clock-Architecture Diagram 3 |
| 526 | */ |
| 527 | |
| 528 | /* PD_VOP */ |
| 529 | GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS), |
| 530 | GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS), |
| 531 | GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS), |
| 532 | GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS), |
| 533 | |
Yakir Yang | 0a9d4ac | 2016-02-24 18:54:18 +0800 | [diff] [blame] | 534 | GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 535 | GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS), |
| 536 | |
| 537 | GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS), |
| 538 | GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS), |
| 539 | |
| 540 | GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS), |
| 541 | GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS), |
Yakir Yang | 0a9d4ac | 2016-02-24 18:54:18 +0800 | [diff] [blame] | 542 | GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 543 | GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS), |
| 544 | GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS), |
| 545 | GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS), |
| 546 | GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS), |
| 547 | GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS), |
Yakir Yang | bdc7dee | 2016-02-24 18:16:28 +0800 | [diff] [blame] | 548 | GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 549 | GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS), |
| 550 | GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS), |
| 551 | |
| 552 | /* PD_PERI */ |
| 553 | GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS), |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 554 | GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 555 | |
| 556 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS), |
| 557 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS), |
| 558 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS), |
| 559 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS), |
| 560 | GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS), |
| 561 | GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS), |
| 562 | GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS), |
| 563 | GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS), |
| 564 | GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS), |
| 565 | GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS), |
| 566 | GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS), |
| 567 | GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS), |
| 568 | GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS), |
| 569 | |
Xing Zheng | 6e3732a | 2016-06-21 12:59:47 +0800 | [diff] [blame] | 570 | GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 571 | GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS), |
| 572 | |
| 573 | /* PD_GPU */ |
| 574 | GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS), |
| 575 | GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS), |
| 576 | |
| 577 | /* PD_BUS */ |
| 578 | GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), |
| 579 | GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), |
| 580 | GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), |
| 581 | GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), |
| 582 | |
| 583 | GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), |
Xing Zheng | a45c072 | 2016-06-21 12:53:29 +0800 | [diff] [blame] | 584 | GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), |
| 585 | GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), |
| 586 | GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), |
| 587 | GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 588 | GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), |
| 589 | GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), |
| 590 | GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), |
| 591 | |
| 592 | GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), |
| 593 | GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), |
| 594 | GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS), |
| 595 | |
| 596 | GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), |
| 597 | GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS), |
| 598 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), |
| 599 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), |
| 600 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), |
| 601 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), |
| 602 | GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS), |
| 603 | GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), |
| 604 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), |
| 605 | GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), |
| 606 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS), |
| 607 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS), |
| 608 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS), |
| 609 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS), |
| 610 | GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), |
| 611 | GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS), |
| 612 | GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS), |
Caesar Wang | a3cb9aa | 2016-02-15 15:33:27 +0800 | [diff] [blame] | 613 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 614 | GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS), |
| 615 | GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), |
| 616 | GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS), |
| 617 | GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), |
| 618 | |
| 619 | GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), |
| 620 | GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS), |
Yakir Yang | bdc7dee | 2016-02-24 18:16:28 +0800 | [diff] [blame] | 621 | GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 622 | GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), |
| 623 | GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), |
| 624 | |
| 625 | GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS), |
| 626 | GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS), |
| 627 | GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS), |
| 628 | GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS), |
| 629 | GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS), |
| 630 | GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS), |
| 631 | GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS), |
| 632 | GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS), |
| 633 | |
| 634 | /* PD_MMC */ |
| 635 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), |
Shawn Lin | bb07698 | 2016-01-26 11:30:18 +0800 | [diff] [blame] | 636 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 637 | |
| 638 | MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), |
Shawn Lin | bb07698 | 2016-01-26 11:30:18 +0800 | [diff] [blame] | 639 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 640 | |
| 641 | MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), |
Shawn Lin | bb07698 | 2016-01-26 11:30:18 +0800 | [diff] [blame] | 642 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 643 | }; |
| 644 | |
| 645 | static const char *const rk3228_critical_clocks[] __initconst = { |
| 646 | "aclk_cpu", |
| 647 | "aclk_peri", |
| 648 | "hclk_peri", |
| 649 | "pclk_peri", |
| 650 | }; |
| 651 | |
| 652 | static void __init rk3228_clk_init(struct device_node *np) |
| 653 | { |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 654 | struct rockchip_clk_provider *ctx; |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 655 | void __iomem *reg_base; |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 656 | |
| 657 | reg_base = of_iomap(np, 0); |
| 658 | if (!reg_base) { |
| 659 | pr_err("%s: could not map cru region\n", __func__); |
| 660 | return; |
| 661 | } |
| 662 | |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 663 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); |
| 664 | if (IS_ERR(ctx)) { |
| 665 | pr_err("%s: rockchip clk init failed\n", __func__); |
Shawn Lin | 1d003eb | 2016-03-13 12:13:22 +0800 | [diff] [blame] | 666 | iounmap(reg_base); |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 667 | return; |
| 668 | } |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 669 | |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 670 | rockchip_clk_register_plls(ctx, rk3228_pll_clks, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 671 | ARRAY_SIZE(rk3228_pll_clks), |
| 672 | RK3228_GRF_SOC_STATUS0); |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 673 | rockchip_clk_register_branches(ctx, rk3228_clk_branches, |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 674 | ARRAY_SIZE(rk3228_clk_branches)); |
| 675 | rockchip_clk_protect_critical(rk3228_critical_clocks, |
| 676 | ARRAY_SIZE(rk3228_critical_clocks)); |
| 677 | |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 678 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 679 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
| 680 | &rk3228_cpuclk_data, rk3228_cpuclk_rates, |
| 681 | ARRAY_SIZE(rk3228_cpuclk_rates)); |
| 682 | |
| 683 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), |
| 684 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
| 685 | |
Xing Zheng | ef1d9fe | 2016-03-09 10:37:04 +0800 | [diff] [blame] | 686 | rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL); |
| 687 | |
| 688 | rockchip_clk_of_add_provider(np, ctx); |
Jeffy Chen | 307a2e9 | 2015-12-11 09:30:50 +0800 | [diff] [blame] | 689 | } |
| 690 | CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); |