Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
| 3 | * Author: Xing Zheng <zhengxing@rock-chips.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/clk-provider.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_address.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/regmap.h> |
| 21 | #include <dt-bindings/clock/rk3399-cru.h> |
| 22 | #include "clk.h" |
| 23 | |
| 24 | enum rk3399_plls { |
| 25 | lpll, bpll, dpll, cpll, gpll, npll, vpll, |
| 26 | }; |
| 27 | |
| 28 | enum rk3399_pmu_plls { |
| 29 | ppll, |
| 30 | }; |
| 31 | |
| 32 | static struct rockchip_pll_rate_table rk3399_pll_rates[] = { |
| 33 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ |
| 34 | RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), |
| 35 | RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), |
| 36 | RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), |
| 37 | RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), |
| 38 | RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), |
| 39 | RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), |
| 40 | RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), |
| 41 | RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), |
| 42 | RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), |
| 43 | RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), |
| 44 | RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), |
| 45 | RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), |
| 46 | RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), |
| 47 | RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), |
| 48 | RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), |
| 49 | RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), |
| 50 | RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), |
| 51 | RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), |
| 52 | RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), |
| 53 | RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), |
| 54 | RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), |
| 55 | RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), |
| 56 | RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), |
| 57 | RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), |
| 58 | RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), |
| 59 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), |
| 60 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), |
| 61 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), |
| 62 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), |
| 63 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), |
| 64 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), |
| 65 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), |
| 66 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), |
| 67 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), |
| 68 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), |
| 69 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), |
| 70 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), |
| 71 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), |
| 72 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), |
| 73 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), |
| 74 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), |
| 75 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), |
| 76 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), |
| 77 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), |
| 78 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), |
| 79 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), |
| 80 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), |
| 81 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), |
| 82 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), |
| 83 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), |
| 84 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), |
| 85 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), |
| 86 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), |
| 87 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), |
| 88 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), |
| 89 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), |
| 90 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), |
| 91 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), |
| 92 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), |
| 93 | RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), |
| 94 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 95 | RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 96 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), |
| 97 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), |
| 98 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), |
| 99 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 100 | RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 101 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 102 | RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), |
Xing Zheng | efc4204 | 2016-08-02 15:22:26 +0800 | [diff] [blame] | 103 | RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 104 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 105 | RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), |
Xing Zheng | efc4204 | 2016-08-02 15:22:26 +0800 | [diff] [blame] | 106 | RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 107 | RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), |
| 108 | RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 109 | { /* sentinel */ }, |
| 110 | }; |
| 111 | |
| 112 | /* CRU parents */ |
| 113 | PNAME(mux_pll_p) = { "xin24m", "xin32k" }; |
| 114 | |
| 115 | PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", |
| 116 | "clk_core_l_bpll_src", |
| 117 | "clk_core_l_dpll_src", |
| 118 | "clk_core_l_gpll_src" }; |
| 119 | PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", |
| 120 | "clk_core_b_bpll_src", |
| 121 | "clk_core_b_dpll_src", |
| 122 | "clk_core_b_gpll_src" }; |
Lin Huang | 464b9ee | 2016-08-22 11:36:19 +0800 | [diff] [blame] | 123 | PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", |
| 124 | "clk_ddrc_bpll_src", |
| 125 | "clk_ddrc_dpll_src", |
| 126 | "clk_ddrc_gpll_src" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 127 | PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", |
| 128 | "gpll_aclk_cci_src", |
| 129 | "npll_aclk_cci_src", |
| 130 | "vpll_aclk_cci_src" }; |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 131 | PNAME(mux_cci_trace_p) = { "cpll_cci_trace", |
| 132 | "gpll_cci_trace" }; |
| 133 | PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", |
| 134 | "npll_cs"}; |
| 135 | PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", |
| 136 | "gpll_aclk_perihp_src" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 137 | |
| 138 | PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; |
| 139 | PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; |
| 140 | PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; |
| 141 | PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; |
| 142 | PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 143 | PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", |
| 144 | "ppll" }; |
| 145 | PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", |
| 146 | "xin24m" }; |
| 147 | PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", |
| 148 | "clk_usbphy_480m" }; |
| 149 | PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", |
| 150 | "npll", "upll" }; |
| 151 | PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", |
| 152 | "upll", "xin24m" }; |
| 153 | PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", |
| 154 | "ppll", "upll", "xin24m" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 155 | |
| 156 | PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 157 | PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", |
| 158 | "npll" }; |
| 159 | PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", |
| 160 | "xin24m" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 161 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 162 | PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", |
| 163 | "dclk_vop0_frac" }; |
| 164 | PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", |
| 165 | "dclk_vop1_frac" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 166 | |
Xing Zheng | fd8bc82 | 2016-04-20 19:11:32 +0800 | [diff] [blame] | 167 | PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 168 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 169 | PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; |
| 170 | PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; |
| 171 | PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", |
| 172 | "cpll", "gpll" }; |
| 173 | PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", |
| 174 | "clk_pcie_core_phy" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 175 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 176 | PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", |
| 177 | "gpll_aclk_emmc_src" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 178 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 179 | PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", |
| 180 | "gpll_aclk_perilp0_src" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 181 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 182 | PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", |
| 183 | "gpll_fclk_cm0s_src" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 184 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 185 | PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", |
| 186 | "gpll_hclk_perilp1_src" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 187 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 188 | PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; |
| 189 | PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 190 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 191 | PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", |
| 192 | "clk_usbphy1_480m_src" }; |
| 193 | PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", |
| 194 | "gpll_aclk_gmac_src" }; |
| 195 | PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; |
| 196 | PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", |
| 197 | "clkin_i2s", "xin12m" }; |
| 198 | PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", |
| 199 | "clkin_i2s", "xin12m" }; |
| 200 | PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", |
| 201 | "clkin_i2s", "xin12m" }; |
| 202 | PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", |
| 203 | "clkin_i2s", "xin12m" }; |
| 204 | PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", |
| 205 | "clk_i2s2" }; |
| 206 | PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 207 | |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 208 | PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; |
| 209 | PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; |
| 210 | PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; |
| 211 | PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 212 | |
| 213 | /* PMU CRU parents */ |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 214 | PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; |
| 215 | PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; |
| 216 | PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; |
| 217 | PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; |
| 218 | PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", |
| 219 | "xin24m" }; |
| 220 | PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 221 | |
| 222 | static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { |
| 223 | [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), |
| 224 | RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), |
| 225 | [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), |
| 226 | RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), |
| 227 | [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), |
| 228 | RK3399_PLL_CON(19), 8, 31, 0, NULL), |
| 229 | [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), |
| 230 | RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
| 231 | [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), |
| 232 | RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
| 233 | [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), |
| 234 | RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
| 235 | [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), |
| 236 | RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
| 237 | }; |
| 238 | |
| 239 | static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { |
| 240 | [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0), |
| 241 | RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), |
| 242 | }; |
| 243 | |
| 244 | #define MFLAGS CLK_MUX_HIWORD_MASK |
| 245 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK |
| 246 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) |
| 247 | #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK |
| 248 | |
| 249 | static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = |
| 250 | MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, |
| 251 | RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); |
| 252 | |
| 253 | static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = |
| 254 | MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, |
| 255 | RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); |
| 256 | |
| 257 | static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = |
| 258 | MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, |
| 259 | RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); |
| 260 | |
| 261 | static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = |
| 262 | MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, |
| 263 | RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); |
| 264 | |
| 265 | static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = |
| 266 | MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, |
| 267 | RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); |
| 268 | |
| 269 | static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = |
| 270 | MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, |
| 271 | RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); |
| 272 | |
| 273 | static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = |
| 274 | MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, |
| 275 | RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); |
| 276 | |
| 277 | static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = |
| 278 | MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, |
| 279 | RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); |
| 280 | |
| 281 | static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = |
| 282 | MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, |
| 283 | RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); |
| 284 | |
| 285 | static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = |
| 286 | MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, |
| 287 | RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); |
| 288 | |
| 289 | static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = |
| 290 | MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, |
| 291 | RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); |
| 292 | |
| 293 | static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = |
| 294 | MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, |
| 295 | RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); |
| 296 | |
| 297 | static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { |
| 298 | .core_reg = RK3399_CLKSEL_CON(0), |
| 299 | .div_core_shift = 0, |
| 300 | .div_core_mask = 0x1f, |
| 301 | .mux_core_alt = 3, |
| 302 | .mux_core_main = 0, |
| 303 | .mux_core_shift = 6, |
| 304 | .mux_core_mask = 0x3, |
| 305 | }; |
| 306 | |
| 307 | static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { |
| 308 | .core_reg = RK3399_CLKSEL_CON(2), |
| 309 | .div_core_shift = 0, |
| 310 | .div_core_mask = 0x1f, |
| 311 | .mux_core_alt = 3, |
| 312 | .mux_core_main = 1, |
| 313 | .mux_core_shift = 6, |
| 314 | .mux_core_mask = 0x3, |
| 315 | }; |
| 316 | |
| 317 | #define RK3399_DIV_ACLKM_MASK 0x1f |
| 318 | #define RK3399_DIV_ACLKM_SHIFT 8 |
| 319 | #define RK3399_DIV_ATCLK_MASK 0x1f |
| 320 | #define RK3399_DIV_ATCLK_SHIFT 0 |
| 321 | #define RK3399_DIV_PCLK_DBG_MASK 0x1f |
| 322 | #define RK3399_DIV_PCLK_DBG_SHIFT 8 |
| 323 | |
| 324 | #define RK3399_CLKSEL0(_offs, _aclkm) \ |
| 325 | { \ |
| 326 | .reg = RK3399_CLKSEL_CON(0 + _offs), \ |
| 327 | .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ |
| 328 | RK3399_DIV_ACLKM_SHIFT), \ |
| 329 | } |
| 330 | #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ |
| 331 | { \ |
| 332 | .reg = RK3399_CLKSEL_CON(1 + _offs), \ |
| 333 | .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ |
| 334 | RK3399_DIV_ATCLK_SHIFT) | \ |
| 335 | HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ |
| 336 | RK3399_DIV_PCLK_DBG_SHIFT), \ |
| 337 | } |
| 338 | |
| 339 | /* cluster_l: aclkm in clksel0, rest in clksel1 */ |
| 340 | #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ |
| 341 | { \ |
| 342 | .prate = _prate##U, \ |
| 343 | .divs = { \ |
| 344 | RK3399_CLKSEL0(0, _aclkm), \ |
| 345 | RK3399_CLKSEL1(0, _atclk, _pdbg), \ |
| 346 | }, \ |
| 347 | } |
| 348 | |
| 349 | /* cluster_b: aclkm in clksel2, rest in clksel3 */ |
| 350 | #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ |
| 351 | { \ |
| 352 | .prate = _prate##U, \ |
| 353 | .divs = { \ |
| 354 | RK3399_CLKSEL0(2, _aclkm), \ |
| 355 | RK3399_CLKSEL1(2, _atclk, _pdbg), \ |
| 356 | }, \ |
| 357 | } |
| 358 | |
| 359 | static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { |
| 360 | RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), |
| 361 | RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), |
| 362 | RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), |
| 363 | RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), |
| 364 | RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), |
| 365 | RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), |
| 366 | RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), |
| 367 | RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), |
| 368 | RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), |
| 369 | RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), |
| 370 | RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), |
| 371 | RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), |
| 372 | RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 373 | RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1), |
| 374 | RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 375 | }; |
| 376 | |
| 377 | static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { |
| 378 | RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), |
| 379 | RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), |
| 380 | RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), |
| 381 | RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), |
Shunqian Zheng | fd75b34 | 2016-09-01 07:06:22 +0800 | [diff] [blame] | 382 | RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 383 | RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), |
| 384 | RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), |
| 385 | RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), |
| 386 | RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), |
| 387 | RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), |
| 388 | RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), |
| 389 | RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), |
| 390 | RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), |
| 391 | RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), |
| 392 | RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), |
| 393 | RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), |
| 394 | RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), |
| 395 | RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), |
| 396 | RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), |
| 397 | RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), |
Xing Zheng | aa2897c | 2016-04-20 19:06:50 +0800 | [diff] [blame] | 398 | RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1), |
| 399 | RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 400 | }; |
| 401 | |
| 402 | static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { |
| 403 | /* |
| 404 | * CRU Clock-Architecture |
| 405 | */ |
| 406 | |
| 407 | /* usbphy */ |
| 408 | GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, |
| 409 | RK3399_CLKGATE_CON(6), 5, GFLAGS), |
| 410 | GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, |
| 411 | RK3399_CLKGATE_CON(6), 6, GFLAGS), |
| 412 | |
| 413 | GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED, |
| 414 | RK3399_CLKGATE_CON(13), 12, GFLAGS), |
| 415 | GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED, |
| 416 | RK3399_CLKGATE_CON(13), 12, GFLAGS), |
| 417 | MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED, |
| 418 | RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), |
| 419 | |
| 420 | MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, |
| 421 | RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), |
| 422 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 423 | COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 424 | RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, |
| 425 | RK3399_CLKGATE_CON(6), 4, GFLAGS), |
| 426 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 427 | COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 428 | RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 429 | RK3399_CLKGATE_CON(12), 0, GFLAGS), |
| 430 | GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED, |
| 431 | RK3399_CLKGATE_CON(30), 0, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 432 | GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 433 | RK3399_CLKGATE_CON(30), 1, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 434 | GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 435 | RK3399_CLKGATE_CON(30), 2, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 436 | GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 437 | RK3399_CLKGATE_CON(30), 3, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 438 | GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 439 | RK3399_CLKGATE_CON(30), 4, GFLAGS), |
| 440 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 441 | GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 442 | RK3399_CLKGATE_CON(12), 1, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 443 | GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 444 | RK3399_CLKGATE_CON(12), 2, GFLAGS), |
| 445 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 446 | COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 447 | RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, |
| 448 | RK3399_CLKGATE_CON(12), 3, GFLAGS), |
| 449 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 450 | COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 451 | RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, |
| 452 | RK3399_CLKGATE_CON(12), 4, GFLAGS), |
| 453 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 454 | COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 455 | RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 456 | RK3399_CLKGATE_CON(13), 4, GFLAGS), |
| 457 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 458 | COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 459 | RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 460 | RK3399_CLKGATE_CON(13), 5, GFLAGS), |
| 461 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 462 | COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 463 | RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 464 | RK3399_CLKGATE_CON(13), 6, GFLAGS), |
| 465 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 466 | COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 467 | RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 468 | RK3399_CLKGATE_CON(13), 7, GFLAGS), |
| 469 | |
| 470 | /* little core */ |
| 471 | GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, |
| 472 | RK3399_CLKGATE_CON(0), 0, GFLAGS), |
| 473 | GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, |
| 474 | RK3399_CLKGATE_CON(0), 1, GFLAGS), |
| 475 | GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, |
| 476 | RK3399_CLKGATE_CON(0), 2, GFLAGS), |
| 477 | GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, |
| 478 | RK3399_CLKGATE_CON(0), 3, GFLAGS), |
| 479 | |
| 480 | COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, |
| 481 | RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 482 | RK3399_CLKGATE_CON(0), 4, GFLAGS), |
| 483 | COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, |
| 484 | RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 485 | RK3399_CLKGATE_CON(0), 5, GFLAGS), |
| 486 | COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, |
| 487 | RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 488 | RK3399_CLKGATE_CON(0), 6, GFLAGS), |
| 489 | |
| 490 | GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED, |
| 491 | RK3399_CLKGATE_CON(14), 12, GFLAGS), |
| 492 | GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, |
| 493 | RK3399_CLKGATE_CON(14), 13, GFLAGS), |
| 494 | |
| 495 | GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, |
| 496 | RK3399_CLKGATE_CON(14), 9, GFLAGS), |
| 497 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED, |
| 498 | RK3399_CLKGATE_CON(14), 10, GFLAGS), |
| 499 | GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, |
| 500 | RK3399_CLKGATE_CON(14), 11, GFLAGS), |
| 501 | GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED, |
| 502 | RK3399_CLKGATE_CON(0), 7, GFLAGS), |
| 503 | |
| 504 | /* big core */ |
| 505 | GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, |
| 506 | RK3399_CLKGATE_CON(1), 0, GFLAGS), |
| 507 | GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, |
| 508 | RK3399_CLKGATE_CON(1), 1, GFLAGS), |
| 509 | GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, |
| 510 | RK3399_CLKGATE_CON(1), 2, GFLAGS), |
| 511 | GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, |
| 512 | RK3399_CLKGATE_CON(1), 3, GFLAGS), |
| 513 | |
| 514 | COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, |
| 515 | RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 516 | RK3399_CLKGATE_CON(1), 4, GFLAGS), |
| 517 | COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, |
| 518 | RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 519 | RK3399_CLKGATE_CON(1), 5, GFLAGS), |
| 520 | COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, |
| 521 | RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, |
| 522 | RK3399_CLKGATE_CON(1), 6, GFLAGS), |
| 523 | |
| 524 | GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED, |
| 525 | RK3399_CLKGATE_CON(14), 5, GFLAGS), |
| 526 | GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, |
| 527 | RK3399_CLKGATE_CON(14), 6, GFLAGS), |
| 528 | |
| 529 | GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, |
| 530 | RK3399_CLKGATE_CON(14), 1, GFLAGS), |
| 531 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED, |
| 532 | RK3399_CLKGATE_CON(14), 3, GFLAGS), |
| 533 | GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, |
| 534 | RK3399_CLKGATE_CON(14), 4, GFLAGS), |
| 535 | |
| 536 | DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, |
| 537 | RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), |
| 538 | |
| 539 | GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, |
| 540 | RK3399_CLKGATE_CON(14), 2, GFLAGS), |
| 541 | |
| 542 | GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED, |
| 543 | RK3399_CLKGATE_CON(1), 7, GFLAGS), |
| 544 | |
| 545 | /* gmac */ |
| 546 | GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, |
| 547 | RK3399_CLKGATE_CON(6), 9, GFLAGS), |
| 548 | GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, |
| 549 | RK3399_CLKGATE_CON(6), 8, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 550 | COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 551 | RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, |
| 552 | RK3399_CLKGATE_CON(6), 10, GFLAGS), |
| 553 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 554 | GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 555 | RK3399_CLKGATE_CON(32), 0, GFLAGS), |
| 556 | GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED, |
| 557 | RK3399_CLKGATE_CON(32), 1, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 558 | GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 559 | RK3399_CLKGATE_CON(32), 4, GFLAGS), |
| 560 | |
| 561 | COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, |
| 562 | RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, |
| 563 | RK3399_CLKGATE_CON(6), 11, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 564 | GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 565 | RK3399_CLKGATE_CON(32), 2, GFLAGS), |
| 566 | GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED, |
| 567 | RK3399_CLKGATE_CON(32), 3, GFLAGS), |
| 568 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 569 | COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 570 | RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 571 | RK3399_CLKGATE_CON(5), 5, GFLAGS), |
| 572 | |
Xing Zheng | 3f92a05 | 2016-04-20 19:06:49 +0800 | [diff] [blame] | 573 | MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 574 | RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 575 | GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 576 | RK3399_CLKGATE_CON(5), 6, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 577 | GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 578 | RK3399_CLKGATE_CON(5), 7, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 579 | GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 580 | RK3399_CLKGATE_CON(5), 8, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 581 | GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 582 | RK3399_CLKGATE_CON(5), 9, GFLAGS), |
| 583 | |
| 584 | /* spdif */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 585 | COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 586 | RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 587 | RK3399_CLKGATE_CON(8), 13, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 588 | COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 589 | RK3399_CLKSEL_CON(99), 0, |
| 590 | RK3399_CLKGATE_CON(8), 14, GFLAGS, |
| 591 | &rk3399_spdif_fracmux), |
| 592 | GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, |
| 593 | RK3399_CLKGATE_CON(8), 15, GFLAGS), |
| 594 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 595 | COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 3770821 | 2016-06-30 10:18:59 +0800 | [diff] [blame] | 596 | RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 597 | RK3399_CLKGATE_CON(10), 6, GFLAGS), |
| 598 | /* i2s */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 599 | COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 600 | RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 601 | RK3399_CLKGATE_CON(8), 3, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 602 | COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 603 | RK3399_CLKSEL_CON(96), 0, |
| 604 | RK3399_CLKGATE_CON(8), 4, GFLAGS, |
| 605 | &rk3399_i2s0_fracmux), |
| 606 | GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, |
| 607 | RK3399_CLKGATE_CON(8), 5, GFLAGS), |
| 608 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 609 | COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 610 | RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 611 | RK3399_CLKGATE_CON(8), 6, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 612 | COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 613 | RK3399_CLKSEL_CON(97), 0, |
| 614 | RK3399_CLKGATE_CON(8), 7, GFLAGS, |
| 615 | &rk3399_i2s1_fracmux), |
| 616 | GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, |
| 617 | RK3399_CLKGATE_CON(8), 8, GFLAGS), |
| 618 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 619 | COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 620 | RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 621 | RK3399_CLKGATE_CON(8), 9, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 622 | COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 623 | RK3399_CLKSEL_CON(98), 0, |
| 624 | RK3399_CLKGATE_CON(8), 10, GFLAGS, |
| 625 | &rk3399_i2s2_fracmux), |
| 626 | GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, |
| 627 | RK3399_CLKGATE_CON(8), 11, GFLAGS), |
| 628 | |
| 629 | MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, |
| 630 | RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), |
| 631 | COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, |
| 632 | RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, |
| 633 | RK3399_CLKGATE_CON(8), 12, GFLAGS), |
| 634 | |
| 635 | /* uart */ |
| 636 | MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, |
| 637 | RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), |
| 638 | COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, |
| 639 | RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, |
| 640 | RK3399_CLKGATE_CON(9), 0, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 641 | COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 642 | RK3399_CLKSEL_CON(100), 0, |
| 643 | RK3399_CLKGATE_CON(9), 1, GFLAGS, |
| 644 | &rk3399_uart0_fracmux), |
| 645 | |
| 646 | MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, |
| 647 | RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), |
| 648 | COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, |
| 649 | RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, |
| 650 | RK3399_CLKGATE_CON(9), 2, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 651 | COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 652 | RK3399_CLKSEL_CON(101), 0, |
| 653 | RK3399_CLKGATE_CON(9), 3, GFLAGS, |
| 654 | &rk3399_uart1_fracmux), |
| 655 | |
| 656 | COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, |
| 657 | RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, |
| 658 | RK3399_CLKGATE_CON(9), 4, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 659 | COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 660 | RK3399_CLKSEL_CON(102), 0, |
| 661 | RK3399_CLKGATE_CON(9), 5, GFLAGS, |
| 662 | &rk3399_uart2_fracmux), |
| 663 | |
| 664 | COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, |
| 665 | RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, |
| 666 | RK3399_CLKGATE_CON(9), 6, GFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 667 | COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 668 | RK3399_CLKSEL_CON(103), 0, |
| 669 | RK3399_CLKGATE_CON(9), 7, GFLAGS, |
| 670 | &rk3399_uart3_fracmux), |
| 671 | |
| 672 | COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, |
| 673 | RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 674 | RK3399_CLKGATE_CON(3), 4, GFLAGS), |
| 675 | |
| 676 | GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 677 | RK3399_CLKGATE_CON(18), 10, GFLAGS), |
| 678 | GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 679 | RK3399_CLKGATE_CON(18), 12, GFLAGS), |
| 680 | GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 681 | RK3399_CLKGATE_CON(18), 15, GFLAGS), |
| 682 | GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, |
| 683 | RK3399_CLKGATE_CON(19), 2, GFLAGS), |
| 684 | |
| 685 | GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED, |
| 686 | RK3399_CLKGATE_CON(4), 11, GFLAGS), |
| 687 | GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED, |
| 688 | RK3399_CLKGATE_CON(3), 5, GFLAGS), |
| 689 | GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED, |
| 690 | RK3399_CLKGATE_CON(3), 6, GFLAGS), |
| 691 | |
| 692 | /* cci */ |
| 693 | GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED, |
| 694 | RK3399_CLKGATE_CON(2), 0, GFLAGS), |
| 695 | GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED, |
| 696 | RK3399_CLKGATE_CON(2), 1, GFLAGS), |
| 697 | GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED, |
| 698 | RK3399_CLKGATE_CON(2), 2, GFLAGS), |
| 699 | GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED, |
| 700 | RK3399_CLKGATE_CON(2), 3, GFLAGS), |
| 701 | |
| 702 | COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED, |
| 703 | RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 704 | RK3399_CLKGATE_CON(2), 4, GFLAGS), |
| 705 | |
| 706 | GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, |
| 707 | RK3399_CLKGATE_CON(15), 0, GFLAGS), |
| 708 | GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, |
| 709 | RK3399_CLKGATE_CON(15), 1, GFLAGS), |
| 710 | GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, |
| 711 | RK3399_CLKGATE_CON(15), 2, GFLAGS), |
| 712 | GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED, |
| 713 | RK3399_CLKGATE_CON(15), 3, GFLAGS), |
| 714 | GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED, |
| 715 | RK3399_CLKGATE_CON(15), 4, GFLAGS), |
| 716 | GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED, |
| 717 | RK3399_CLKGATE_CON(15), 7, GFLAGS), |
| 718 | |
| 719 | GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, |
| 720 | RK3399_CLKGATE_CON(2), 5, GFLAGS), |
| 721 | GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, |
| 722 | RK3399_CLKGATE_CON(2), 6, GFLAGS), |
| 723 | COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, |
| 724 | RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, |
| 725 | RK3399_CLKGATE_CON(2), 7, GFLAGS), |
| 726 | |
| 727 | GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED, |
| 728 | RK3399_CLKGATE_CON(2), 8, GFLAGS), |
| 729 | GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED, |
| 730 | RK3399_CLKGATE_CON(2), 9, GFLAGS), |
| 731 | GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED, |
| 732 | RK3399_CLKGATE_CON(2), 10, GFLAGS), |
| 733 | COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED, |
| 734 | RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), |
| 735 | GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, |
| 736 | RK3399_CLKGATE_CON(15), 5, GFLAGS), |
| 737 | GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED, |
| 738 | RK3399_CLKGATE_CON(15), 6, GFLAGS), |
| 739 | |
| 740 | /* vcodec */ |
| 741 | COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
| 742 | RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 743 | RK3399_CLKGATE_CON(4), 0, GFLAGS), |
| 744 | COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, |
| 745 | RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, |
| 746 | RK3399_CLKGATE_CON(4), 1, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 747 | GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 748 | RK3399_CLKGATE_CON(17), 2, GFLAGS), |
| 749 | GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, |
| 750 | RK3399_CLKGATE_CON(17), 3, GFLAGS), |
| 751 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 752 | GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 753 | RK3399_CLKGATE_CON(17), 0, GFLAGS), |
| 754 | GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, |
| 755 | RK3399_CLKGATE_CON(17), 1, GFLAGS), |
| 756 | |
| 757 | /* vdu */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 758 | COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 759 | RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 760 | RK3399_CLKGATE_CON(4), 4, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 761 | COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 762 | RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 763 | RK3399_CLKGATE_CON(4), 5, GFLAGS), |
| 764 | |
| 765 | COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
| 766 | RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 767 | RK3399_CLKGATE_CON(4), 2, GFLAGS), |
| 768 | COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, |
| 769 | RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, |
| 770 | RK3399_CLKGATE_CON(4), 3, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 771 | GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 772 | RK3399_CLKGATE_CON(17), 10, GFLAGS), |
| 773 | GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED, |
| 774 | RK3399_CLKGATE_CON(17), 11, GFLAGS), |
| 775 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 776 | GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 777 | RK3399_CLKGATE_CON(17), 8, GFLAGS), |
| 778 | GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED, |
| 779 | RK3399_CLKGATE_CON(17), 9, GFLAGS), |
| 780 | |
| 781 | /* iep */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 782 | COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 783 | RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 784 | RK3399_CLKGATE_CON(4), 6, GFLAGS), |
| 785 | COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, |
| 786 | RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, |
| 787 | RK3399_CLKGATE_CON(4), 7, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 788 | GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 789 | RK3399_CLKGATE_CON(16), 2, GFLAGS), |
| 790 | GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED, |
| 791 | RK3399_CLKGATE_CON(16), 3, GFLAGS), |
| 792 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 793 | GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 794 | RK3399_CLKGATE_CON(16), 0, GFLAGS), |
| 795 | GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, |
| 796 | RK3399_CLKGATE_CON(16), 1, GFLAGS), |
| 797 | |
| 798 | /* rga */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 799 | COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 800 | RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 801 | RK3399_CLKGATE_CON(4), 10, GFLAGS), |
| 802 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 803 | COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 804 | RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 805 | RK3399_CLKGATE_CON(4), 8, GFLAGS), |
| 806 | COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, |
| 807 | RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, |
| 808 | RK3399_CLKGATE_CON(4), 9, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 809 | GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 810 | RK3399_CLKGATE_CON(16), 10, GFLAGS), |
| 811 | GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED, |
| 812 | RK3399_CLKGATE_CON(16), 11, GFLAGS), |
| 813 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 814 | GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 815 | RK3399_CLKGATE_CON(16), 8, GFLAGS), |
| 816 | GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, |
| 817 | RK3399_CLKGATE_CON(16), 9, GFLAGS), |
| 818 | |
| 819 | /* center */ |
| 820 | COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, |
| 821 | RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 822 | RK3399_CLKGATE_CON(3), 7, GFLAGS), |
| 823 | GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED, |
| 824 | RK3399_CLKGATE_CON(19), 0, GFLAGS), |
| 825 | GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED, |
| 826 | RK3399_CLKGATE_CON(19), 1, GFLAGS), |
| 827 | |
| 828 | /* gpu */ |
| 829 | COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, |
| 830 | RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, |
| 831 | RK3399_CLKGATE_CON(13), 0, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 832 | GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 833 | RK3399_CLKGATE_CON(30), 8, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 834 | GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 835 | RK3399_CLKGATE_CON(30), 10, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 836 | GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 837 | RK3399_CLKGATE_CON(30), 11, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 838 | GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 839 | RK3399_CLKGATE_CON(13), 1, GFLAGS), |
| 840 | |
| 841 | /* perihp */ |
Xing Zheng | 3bd14ae | 2016-05-13 11:42:17 -0700 | [diff] [blame] | 842 | GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 843 | RK3399_CLKGATE_CON(5), 1, GFLAGS), |
Xing Zheng | 4608d96 | 2016-08-02 15:19:57 +0800 | [diff] [blame] | 844 | GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED, |
| 845 | RK3399_CLKGATE_CON(5), 0, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 846 | COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED, |
| 847 | RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, |
| 848 | RK3399_CLKGATE_CON(5), 2, GFLAGS), |
| 849 | COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, |
| 850 | RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, |
| 851 | RK3399_CLKGATE_CON(5), 3, GFLAGS), |
| 852 | COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, |
| 853 | RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, |
| 854 | RK3399_CLKGATE_CON(5), 4, GFLAGS), |
| 855 | |
Elaine Zhang | 4f4e049 | 2016-08-02 15:22:49 +0800 | [diff] [blame] | 856 | GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 857 | RK3399_CLKGATE_CON(20), 2, GFLAGS), |
Elaine Zhang | 4f4e049 | 2016-08-02 15:22:49 +0800 | [diff] [blame] | 858 | GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 859 | RK3399_CLKGATE_CON(20), 10, GFLAGS), |
| 860 | GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED, |
| 861 | RK3399_CLKGATE_CON(20), 12, GFLAGS), |
| 862 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 863 | GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 864 | RK3399_CLKGATE_CON(20), 5, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 865 | GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 866 | RK3399_CLKGATE_CON(20), 6, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 867 | GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 868 | RK3399_CLKGATE_CON(20), 7, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 869 | GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 870 | RK3399_CLKGATE_CON(20), 8, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 871 | GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 872 | RK3399_CLKGATE_CON(20), 9, GFLAGS), |
| 873 | GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED, |
| 874 | RK3399_CLKGATE_CON(20), 13, GFLAGS), |
| 875 | GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, |
| 876 | RK3399_CLKGATE_CON(20), 15, GFLAGS), |
| 877 | |
| 878 | GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED, |
| 879 | RK3399_CLKGATE_CON(20), 4, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 880 | GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 881 | RK3399_CLKGATE_CON(20), 11, GFLAGS), |
| 882 | GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED, |
| 883 | RK3399_CLKGATE_CON(20), 14, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 884 | GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 885 | RK3399_CLKGATE_CON(31), 8, GFLAGS), |
| 886 | |
| 887 | /* sdio & sdmmc */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 888 | COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 889 | RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 890 | RK3399_CLKGATE_CON(12), 13, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 891 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 892 | RK3399_CLKGATE_CON(33), 8, GFLAGS), |
| 893 | GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED, |
| 894 | RK3399_CLKGATE_CON(33), 9, GFLAGS), |
| 895 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 896 | COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 897 | RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, |
| 898 | RK3399_CLKGATE_CON(6), 0, GFLAGS), |
| 899 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 900 | COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 901 | RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, |
| 902 | RK3399_CLKGATE_CON(6), 1, GFLAGS), |
| 903 | |
Douglas Anderson | 84752e8 | 2016-05-04 16:36:25 -0700 | [diff] [blame] | 904 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), |
| 905 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 906 | |
| 907 | MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), |
| 908 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), |
| 909 | |
| 910 | /* pcie */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 911 | COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 912 | RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, |
| 913 | RK3399_CLKGATE_CON(6), 2, GFLAGS), |
| 914 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 915 | COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 916 | RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, |
| 917 | RK3399_CLKGATE_CON(12), 6, GFLAGS), |
| 918 | MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, |
| 919 | RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), |
| 920 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 921 | COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 922 | RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, |
| 923 | RK3399_CLKGATE_CON(6), 3, GFLAGS), |
| 924 | MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, |
| 925 | RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), |
| 926 | |
| 927 | /* emmc */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 928 | COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 929 | RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, |
| 930 | RK3399_CLKGATE_CON(6), 14, GFLAGS), |
| 931 | |
| 932 | GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 933 | RK3399_CLKGATE_CON(6), 13, GFLAGS), |
Xing Zheng | 20c389e | 2016-08-02 15:19:58 +0800 | [diff] [blame] | 934 | GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, |
| 935 | RK3399_CLKGATE_CON(6), 12, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 936 | COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, |
| 937 | RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), |
| 938 | GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, |
| 939 | RK3399_CLKGATE_CON(32), 8, GFLAGS), |
| 940 | GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED, |
| 941 | RK3399_CLKGATE_CON(32), 9, GFLAGS), |
| 942 | GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, |
| 943 | RK3399_CLKGATE_CON(32), 10, GFLAGS), |
| 944 | |
| 945 | /* perilp0 */ |
| 946 | GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED, |
| 947 | RK3399_CLKGATE_CON(7), 1, GFLAGS), |
| 948 | GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED, |
| 949 | RK3399_CLKGATE_CON(7), 0, GFLAGS), |
| 950 | COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, |
| 951 | RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, |
| 952 | RK3399_CLKGATE_CON(7), 2, GFLAGS), |
| 953 | COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED, |
| 954 | RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, |
| 955 | RK3399_CLKGATE_CON(7), 3, GFLAGS), |
| 956 | COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0, |
| 957 | RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, |
| 958 | RK3399_CLKGATE_CON(7), 4, GFLAGS), |
| 959 | |
| 960 | /* aclk_perilp0 gates */ |
| 961 | GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), |
| 962 | GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), |
| 963 | GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), |
| 964 | GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), |
| 965 | GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), |
| 966 | GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), |
| 967 | GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), |
| 968 | GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), |
| 969 | GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS), |
| 970 | GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), |
| 971 | GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 972 | GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 973 | |
| 974 | /* hclk_perilp0 gates */ |
| 975 | GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 976 | GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS), |
| 977 | GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS), |
| 978 | GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS), |
| 979 | GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 980 | GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), |
| 981 | |
| 982 | /* pclk_perilp0 gates */ |
| 983 | GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS), |
| 984 | |
| 985 | /* crypto */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 986 | COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 987 | RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 988 | RK3399_CLKGATE_CON(7), 7, GFLAGS), |
| 989 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 990 | COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 991 | RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 992 | RK3399_CLKGATE_CON(7), 8, GFLAGS), |
| 993 | |
| 994 | /* cm0s_perilp */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 995 | GATE(0, "cpll_fclk_cm0s_src", "cpll", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 996 | RK3399_CLKGATE_CON(7), 6, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 997 | GATE(0, "gpll_fclk_cm0s_src", "gpll", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 998 | RK3399_CLKGATE_CON(7), 5, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 999 | COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1000 | RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 1001 | RK3399_CLKGATE_CON(7), 9, GFLAGS), |
| 1002 | |
| 1003 | /* fclk_cm0s gates */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1004 | GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS), |
| 1005 | GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS), |
| 1006 | GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS), |
| 1007 | GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1008 | GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), |
| 1009 | |
| 1010 | /* perilp1 */ |
| 1011 | GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED, |
| 1012 | RK3399_CLKGATE_CON(8), 1, GFLAGS), |
| 1013 | GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED, |
| 1014 | RK3399_CLKGATE_CON(8), 0, GFLAGS), |
| 1015 | COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, |
| 1016 | RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), |
| 1017 | COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED, |
| 1018 | RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, |
| 1019 | RK3399_CLKGATE_CON(8), 2, GFLAGS), |
| 1020 | |
| 1021 | /* hclk_perilp1 gates */ |
| 1022 | GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), |
| 1023 | GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1024 | GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS), |
| 1025 | GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS), |
| 1026 | GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS), |
| 1027 | GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS), |
| 1028 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS), |
| 1029 | GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1030 | GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), |
| 1031 | |
| 1032 | /* pclk_perilp1 gates */ |
| 1033 | GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), |
| 1034 | GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), |
| 1035 | GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), |
| 1036 | GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), |
| 1037 | GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), |
| 1038 | GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), |
| 1039 | GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), |
| 1040 | GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), |
| 1041 | GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), |
| 1042 | GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), |
| 1043 | GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), |
| 1044 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), |
| 1045 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), |
| 1046 | GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), |
| 1047 | GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), |
| 1048 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), |
| 1049 | GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), |
| 1050 | GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), |
| 1051 | GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), |
| 1052 | GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), |
| 1053 | GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), |
| 1054 | |
| 1055 | /* saradc */ |
| 1056 | COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, |
| 1057 | RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, |
| 1058 | RK3399_CLKGATE_CON(9), 11, GFLAGS), |
| 1059 | |
| 1060 | /* tsadc */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1061 | COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1062 | RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, |
| 1063 | RK3399_CLKGATE_CON(9), 10, GFLAGS), |
| 1064 | |
| 1065 | /* cif_testout */ |
| 1066 | MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, |
| 1067 | RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), |
| 1068 | COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0, |
| 1069 | RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, |
| 1070 | RK3399_CLKGATE_CON(13), 14, GFLAGS), |
| 1071 | |
| 1072 | MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, |
| 1073 | RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), |
| 1074 | COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0, |
| 1075 | RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, |
| 1076 | RK3399_CLKGATE_CON(13), 15, GFLAGS), |
| 1077 | |
| 1078 | /* vio */ |
| 1079 | COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, |
| 1080 | RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, |
Chris Zhong | a3f457d | 2016-08-09 11:02:33 -0700 | [diff] [blame] | 1081 | RK3399_CLKGATE_CON(11), 0, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1082 | COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, |
| 1083 | RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, |
| 1084 | RK3399_CLKGATE_CON(11), 1, GFLAGS), |
| 1085 | |
| 1086 | GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED, |
| 1087 | RK3399_CLKGATE_CON(29), 0, GFLAGS), |
| 1088 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1089 | GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1090 | RK3399_CLKGATE_CON(29), 1, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1091 | GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1092 | RK3399_CLKGATE_CON(29), 2, GFLAGS), |
| 1093 | GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED, |
| 1094 | RK3399_CLKGATE_CON(29), 12, GFLAGS), |
| 1095 | |
| 1096 | /* hdcp */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1097 | COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1098 | RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 1099 | RK3399_CLKGATE_CON(11), 12, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1100 | COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1101 | RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, |
| 1102 | RK3399_CLKGATE_CON(11), 3, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1103 | COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1104 | RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, |
| 1105 | RK3399_CLKGATE_CON(11), 10, GFLAGS), |
| 1106 | |
| 1107 | GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED, |
| 1108 | RK3399_CLKGATE_CON(29), 4, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1109 | GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1110 | RK3399_CLKGATE_CON(29), 10, GFLAGS), |
| 1111 | |
| 1112 | GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED, |
| 1113 | RK3399_CLKGATE_CON(29), 5, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1114 | GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1115 | RK3399_CLKGATE_CON(29), 9, GFLAGS), |
| 1116 | |
| 1117 | GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED, |
| 1118 | RK3399_CLKGATE_CON(29), 3, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1119 | GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1120 | RK3399_CLKGATE_CON(29), 6, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1121 | GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1122 | RK3399_CLKGATE_CON(29), 7, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1123 | GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1124 | RK3399_CLKGATE_CON(29), 8, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1125 | GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1126 | RK3399_CLKGATE_CON(29), 11, GFLAGS), |
| 1127 | |
| 1128 | /* edp */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1129 | COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1130 | RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1131 | RK3399_CLKGATE_CON(11), 8, GFLAGS), |
| 1132 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1133 | COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1134 | RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 1135 | RK3399_CLKGATE_CON(11), 11, GFLAGS), |
| 1136 | GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, |
| 1137 | RK3399_CLKGATE_CON(32), 12, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1138 | GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1139 | RK3399_CLKGATE_CON(32), 13, GFLAGS), |
| 1140 | |
| 1141 | /* hdmi */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1142 | GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1143 | RK3399_CLKGATE_CON(11), 6, GFLAGS), |
| 1144 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1145 | COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1146 | RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, |
| 1147 | RK3399_CLKGATE_CON(11), 7, GFLAGS), |
| 1148 | |
| 1149 | /* vop0 */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1150 | COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1151 | RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1152 | RK3399_CLKGATE_CON(10), 8, GFLAGS), |
| 1153 | COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, |
| 1154 | RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, |
| 1155 | RK3399_CLKGATE_CON(10), 9, GFLAGS), |
| 1156 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1157 | GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1158 | RK3399_CLKGATE_CON(28), 3, GFLAGS), |
| 1159 | GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED, |
| 1160 | RK3399_CLKGATE_CON(28), 1, GFLAGS), |
| 1161 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1162 | GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1163 | RK3399_CLKGATE_CON(28), 2, GFLAGS), |
| 1164 | GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, |
| 1165 | RK3399_CLKGATE_CON(28), 0, GFLAGS), |
| 1166 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1167 | COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1168 | RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 1169 | RK3399_CLKGATE_CON(10), 12, GFLAGS), |
| 1170 | |
Yakir Yang | 7b0f9e357 | 2016-09-01 20:26:25 -0700 | [diff] [blame] | 1171 | COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1172 | RK3399_CLKSEL_CON(106), 0, |
| 1173 | &rk3399_dclk_vop0_fracmux), |
| 1174 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1175 | COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1176 | RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1177 | RK3399_CLKGATE_CON(10), 14, GFLAGS), |
| 1178 | |
| 1179 | /* vop1 */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1180 | COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1181 | RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1182 | RK3399_CLKGATE_CON(10), 10, GFLAGS), |
| 1183 | COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, |
| 1184 | RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, |
| 1185 | RK3399_CLKGATE_CON(10), 11, GFLAGS), |
| 1186 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1187 | GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1188 | RK3399_CLKGATE_CON(28), 7, GFLAGS), |
| 1189 | GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED, |
| 1190 | RK3399_CLKGATE_CON(28), 5, GFLAGS), |
| 1191 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1192 | GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1193 | RK3399_CLKGATE_CON(28), 6, GFLAGS), |
| 1194 | GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED, |
| 1195 | RK3399_CLKGATE_CON(28), 4, GFLAGS), |
| 1196 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1197 | COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1198 | RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, |
| 1199 | RK3399_CLKGATE_CON(10), 13, GFLAGS), |
| 1200 | |
Yakir Yang | 7b0f9e357 | 2016-09-01 20:26:25 -0700 | [diff] [blame] | 1201 | COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1202 | RK3399_CLKSEL_CON(107), 0, |
| 1203 | &rk3399_dclk_vop1_fracmux), |
| 1204 | |
| 1205 | COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, |
| 1206 | RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1207 | RK3399_CLKGATE_CON(10), 15, GFLAGS), |
| 1208 | |
| 1209 | /* isp */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1210 | COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1211 | RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1212 | RK3399_CLKGATE_CON(12), 8, GFLAGS), |
Xing Zheng | 3f92a05 | 2016-04-20 19:06:49 +0800 | [diff] [blame] | 1213 | COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1214 | RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, |
| 1215 | RK3399_CLKGATE_CON(12), 9, GFLAGS), |
| 1216 | |
| 1217 | GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED, |
| 1218 | RK3399_CLKGATE_CON(27), 1, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1219 | GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1220 | RK3399_CLKGATE_CON(27), 5, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1221 | GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1222 | RK3399_CLKGATE_CON(27), 7, GFLAGS), |
| 1223 | |
| 1224 | GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED, |
| 1225 | RK3399_CLKGATE_CON(27), 0, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1226 | GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1227 | RK3399_CLKGATE_CON(27), 4, GFLAGS), |
| 1228 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1229 | COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1230 | RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1231 | RK3399_CLKGATE_CON(11), 4, GFLAGS), |
| 1232 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1233 | COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1234 | RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, |
| 1235 | RK3399_CLKGATE_CON(12), 10, GFLAGS), |
Xing Zheng | 3f92a05 | 2016-04-20 19:06:49 +0800 | [diff] [blame] | 1236 | COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1237 | RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, |
| 1238 | RK3399_CLKGATE_CON(12), 11, GFLAGS), |
| 1239 | |
| 1240 | GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED, |
| 1241 | RK3399_CLKGATE_CON(27), 3, GFLAGS), |
| 1242 | |
| 1243 | GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED, |
| 1244 | RK3399_CLKGATE_CON(27), 2, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1245 | GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1246 | RK3399_CLKGATE_CON(27), 8, GFLAGS), |
| 1247 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1248 | COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1249 | RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, |
| 1250 | RK3399_CLKGATE_CON(11), 5, GFLAGS), |
| 1251 | |
| 1252 | /* |
| 1253 | * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, |
| 1254 | * so we ignore the mux and make clocks nodes as following, |
| 1255 | * |
| 1256 | * pclkin_cifinv --|-------\ |
| 1257 | * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper |
| 1258 | * pclkin_cif --|-------/ |
| 1259 | */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1260 | GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1261 | RK3399_CLKGATE_CON(27), 6, GFLAGS), |
| 1262 | |
| 1263 | /* cif */ |
Xing Zheng | fd8bc82 | 2016-04-20 19:11:32 +0800 | [diff] [blame] | 1264 | COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0, |
| 1265 | RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1266 | RK3399_CLKGATE_CON(10), 7, GFLAGS), |
Xing Zheng | fd8bc82 | 2016-04-20 19:11:32 +0800 | [diff] [blame] | 1267 | |
| 1268 | COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, |
| 1269 | RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1270 | |
| 1271 | /* gic */ |
| 1272 | COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, |
| 1273 | RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, |
| 1274 | RK3399_CLKGATE_CON(12), 12, GFLAGS), |
| 1275 | |
| 1276 | GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), |
| 1277 | GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), |
| 1278 | GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), |
| 1279 | GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), |
| 1280 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), |
| 1281 | GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), |
| 1282 | |
| 1283 | /* alive */ |
| 1284 | /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ |
| 1285 | DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, |
| 1286 | RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), |
| 1287 | |
| 1288 | GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), |
| 1289 | GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), |
| 1290 | GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), |
| 1291 | GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), |
| 1292 | GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), |
| 1293 | |
| 1294 | GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), |
| 1295 | GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1296 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS), |
| 1297 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS), |
| 1298 | GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS), |
| 1299 | GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS), |
| 1300 | GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1301 | GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), |
| 1302 | GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), |
| 1303 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1304 | GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1305 | GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), |
| 1306 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1307 | GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1308 | GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), |
| 1309 | GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), |
| 1310 | GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), |
| 1311 | |
| 1312 | /* testout */ |
| 1313 | MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, |
| 1314 | RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 1315 | COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1316 | RK3399_CLKSEL_CON(105), 0, |
| 1317 | RK3399_CLKGATE_CON(13), 9, GFLAGS), |
| 1318 | |
| 1319 | DIV(0, "clk_test_24m", "xin24m", 0, |
| 1320 | RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), |
| 1321 | |
| 1322 | /* spi */ |
| 1323 | COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, |
| 1324 | RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 1325 | RK3399_CLKGATE_CON(9), 12, GFLAGS), |
| 1326 | |
| 1327 | COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, |
| 1328 | RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 1329 | RK3399_CLKGATE_CON(9), 13, GFLAGS), |
| 1330 | |
| 1331 | COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, |
| 1332 | RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 1333 | RK3399_CLKGATE_CON(9), 14, GFLAGS), |
| 1334 | |
| 1335 | COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, |
| 1336 | RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 1337 | RK3399_CLKGATE_CON(9), 15, GFLAGS), |
| 1338 | |
| 1339 | COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, |
| 1340 | RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 1341 | RK3399_CLKGATE_CON(13), 13, GFLAGS), |
| 1342 | |
| 1343 | /* i2c */ |
| 1344 | COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, |
| 1345 | RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 1346 | RK3399_CLKGATE_CON(10), 0, GFLAGS), |
| 1347 | |
| 1348 | COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, |
| 1349 | RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 1350 | RK3399_CLKGATE_CON(10), 2, GFLAGS), |
| 1351 | |
| 1352 | COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, |
| 1353 | RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 1354 | RK3399_CLKGATE_CON(10), 4, GFLAGS), |
| 1355 | |
| 1356 | COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, |
| 1357 | RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 1358 | RK3399_CLKGATE_CON(10), 1, GFLAGS), |
| 1359 | |
| 1360 | COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, |
| 1361 | RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 1362 | RK3399_CLKGATE_CON(10), 3, GFLAGS), |
| 1363 | |
| 1364 | COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, |
| 1365 | RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, |
| 1366 | RK3399_CLKGATE_CON(10), 5, GFLAGS), |
| 1367 | |
| 1368 | /* timer */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1369 | GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS), |
| 1370 | GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS), |
| 1371 | GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS), |
| 1372 | GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS), |
| 1373 | GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS), |
| 1374 | GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS), |
| 1375 | GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS), |
| 1376 | GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS), |
| 1377 | GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS), |
| 1378 | GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS), |
| 1379 | GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS), |
| 1380 | GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1381 | |
| 1382 | /* clk_test */ |
| 1383 | /* clk_test_pre is controlled by CRU_MISC_CON[3] */ |
| 1384 | COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, |
| 1385 | RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, |
| 1386 | RK3368_CLKGATE_CON(13), 11, GFLAGS), |
Lin Huang | 464b9ee | 2016-08-22 11:36:19 +0800 | [diff] [blame] | 1387 | |
| 1388 | /* ddrc */ |
| 1389 | GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), |
| 1390 | 0, GFLAGS), |
| 1391 | GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), |
| 1392 | 1, GFLAGS), |
| 1393 | GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), |
| 1394 | 2, GFLAGS), |
| 1395 | GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), |
| 1396 | 3, GFLAGS), |
| 1397 | COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0, |
| 1398 | RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1399 | }; |
| 1400 | |
| 1401 | static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { |
| 1402 | /* |
| 1403 | * PMU CRU Clock-Architecture |
| 1404 | */ |
| 1405 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1406 | GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1407 | RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), |
| 1408 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1409 | COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1410 | RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), |
| 1411 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1412 | COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1413 | RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, |
| 1414 | RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), |
| 1415 | |
| 1416 | COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, |
| 1417 | RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, |
| 1418 | RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), |
| 1419 | |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 1420 | COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1421 | RK3399_PMU_CLKSEL_CON(7), 0, |
| 1422 | &rk3399_pmuclk_wifi_fracmux), |
| 1423 | |
| 1424 | MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, |
| 1425 | RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), |
| 1426 | |
| 1427 | COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, |
| 1428 | RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, |
| 1429 | RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), |
| 1430 | |
| 1431 | COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, |
| 1432 | RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, |
Xing Zheng | f3d4091 | 2016-04-20 19:12:10 +0800 | [diff] [blame] | 1433 | RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1434 | |
| 1435 | COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, |
| 1436 | RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, |
Xing Zheng | f3d4091 | 2016-04-20 19:12:10 +0800 | [diff] [blame] | 1437 | RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1438 | |
| 1439 | DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, |
| 1440 | RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), |
| 1441 | MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, |
| 1442 | RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), |
| 1443 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1444 | COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1445 | RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, |
| 1446 | RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), |
| 1447 | |
Douglas Anderson | 29edecc | 2016-09-01 20:26:23 -0700 | [diff] [blame] | 1448 | COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1449 | RK3399_PMU_CLKSEL_CON(6), 0, |
| 1450 | RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, |
| 1451 | &rk3399_uart4_pmu_fracmux), |
| 1452 | |
| 1453 | DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED, |
| 1454 | RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), |
| 1455 | |
| 1456 | /* pmu clock gates */ |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1457 | GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), |
| 1458 | GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1459 | |
| 1460 | GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), |
| 1461 | |
| 1462 | GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), |
| 1463 | GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), |
| 1464 | GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1465 | GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), |
| 1466 | GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1467 | GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), |
| 1468 | GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1469 | GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), |
| 1470 | GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), |
| 1471 | GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), |
| 1472 | GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), |
| 1473 | GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), |
| 1474 | GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), |
| 1475 | GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), |
| 1476 | GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), |
| 1477 | GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1478 | |
Xing Zheng | 50961e8 | 2016-04-20 19:06:51 +0800 | [diff] [blame] | 1479 | GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), |
| 1480 | GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), |
| 1481 | GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), |
| 1482 | GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1483 | GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), |
| 1484 | }; |
| 1485 | |
| 1486 | static const char *const rk3399_cru_critical_clocks[] __initconst = { |
| 1487 | "aclk_cci_pre", |
Brian Norris | 176df69 | 2016-05-13 11:42:16 -0700 | [diff] [blame] | 1488 | "aclk_gic", |
| 1489 | "aclk_gic_noc", |
Chris Zhong | 5447944 | 2016-08-09 11:02:33 -0700 | [diff] [blame] | 1490 | "aclk_hdcp_noc", |
| 1491 | "hclk_hdcp_noc", |
| 1492 | "pclk_hdcp_noc", |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1493 | "pclk_perilp0", |
| 1494 | "pclk_perilp0", |
| 1495 | "hclk_perilp0", |
| 1496 | "hclk_perilp0_noc", |
| 1497 | "pclk_perilp1", |
| 1498 | "pclk_perilp1_noc", |
| 1499 | "pclk_perihp", |
| 1500 | "pclk_perihp_noc", |
| 1501 | "hclk_perihp", |
| 1502 | "aclk_perihp", |
| 1503 | "aclk_perihp_noc", |
| 1504 | "aclk_perilp0", |
| 1505 | "aclk_perilp0_noc", |
| 1506 | "hclk_perilp1", |
| 1507 | "hclk_perilp1_noc", |
| 1508 | "aclk_dmac0_perilp", |
Xing Zheng | a45f9d4 | 2016-08-24 11:29:39 -0700 | [diff] [blame] | 1509 | "aclk_emmc_noc", |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1510 | "gpll_hclk_perilp1_src", |
| 1511 | "gpll_aclk_perilp0_src", |
| 1512 | "gpll_aclk_perihp_src", |
Chris Zhong | 5447944 | 2016-08-09 11:02:33 -0700 | [diff] [blame] | 1513 | "aclk_vio_noc", |
Lin Huang | 464b9ee | 2016-08-22 11:36:19 +0800 | [diff] [blame] | 1514 | |
| 1515 | /* ddrc */ |
| 1516 | "sclk_ddrc" |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1517 | }; |
| 1518 | |
| 1519 | static const char *const rk3399_pmucru_critical_clocks[] __initconst = { |
| 1520 | "ppll", |
| 1521 | "pclk_pmu_src", |
| 1522 | "fclk_cm0s_src_pmu", |
| 1523 | "clk_timer_src_pmu", |
| 1524 | }; |
| 1525 | |
| 1526 | static void __init rk3399_clk_init(struct device_node *np) |
| 1527 | { |
| 1528 | struct rockchip_clk_provider *ctx; |
| 1529 | void __iomem *reg_base; |
Xing Zheng | 26e0ee1 | 2016-05-25 16:51:56 +0800 | [diff] [blame] | 1530 | struct clk *clk; |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1531 | |
| 1532 | reg_base = of_iomap(np, 0); |
| 1533 | if (!reg_base) { |
| 1534 | pr_err("%s: could not map cru region\n", __func__); |
| 1535 | return; |
| 1536 | } |
| 1537 | |
| 1538 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); |
| 1539 | if (IS_ERR(ctx)) { |
| 1540 | pr_err("%s: rockchip clk init failed\n", __func__); |
Shawn Lin | 62d0e71d | 2016-06-03 08:54:18 +0800 | [diff] [blame] | 1541 | iounmap(reg_base); |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1542 | return; |
| 1543 | } |
| 1544 | |
Xing Zheng | 26e0ee1 | 2016-05-25 16:51:56 +0800 | [diff] [blame] | 1545 | /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ |
| 1546 | clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1); |
| 1547 | if (IS_ERR(clk)) |
| 1548 | pr_warn("%s: could not register clock pclk_wdt: %ld\n", |
| 1549 | __func__, PTR_ERR(clk)); |
| 1550 | else |
| 1551 | rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); |
| 1552 | |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1553 | rockchip_clk_register_plls(ctx, rk3399_pll_clks, |
| 1554 | ARRAY_SIZE(rk3399_pll_clks), -1); |
| 1555 | |
| 1556 | rockchip_clk_register_branches(ctx, rk3399_clk_branches, |
| 1557 | ARRAY_SIZE(rk3399_clk_branches)); |
| 1558 | |
| 1559 | rockchip_clk_protect_critical(rk3399_cru_critical_clocks, |
| 1560 | ARRAY_SIZE(rk3399_cru_critical_clocks)); |
| 1561 | |
| 1562 | rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", |
| 1563 | mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), |
| 1564 | &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, |
| 1565 | ARRAY_SIZE(rk3399_cpuclkl_rates)); |
| 1566 | |
| 1567 | rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", |
| 1568 | mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), |
| 1569 | &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, |
| 1570 | ARRAY_SIZE(rk3399_cpuclkb_rates)); |
| 1571 | |
| 1572 | rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), |
| 1573 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
| 1574 | |
| 1575 | rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL); |
| 1576 | |
| 1577 | rockchip_clk_of_add_provider(np, ctx); |
| 1578 | } |
| 1579 | CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init); |
| 1580 | |
| 1581 | static void __init rk3399_pmu_clk_init(struct device_node *np) |
| 1582 | { |
| 1583 | struct rockchip_clk_provider *ctx; |
| 1584 | void __iomem *reg_base; |
| 1585 | |
| 1586 | reg_base = of_iomap(np, 0); |
| 1587 | if (!reg_base) { |
| 1588 | pr_err("%s: could not map cru pmu region\n", __func__); |
| 1589 | return; |
| 1590 | } |
| 1591 | |
| 1592 | ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); |
| 1593 | if (IS_ERR(ctx)) { |
| 1594 | pr_err("%s: rockchip pmu clk init failed\n", __func__); |
Shawn Lin | 62d0e71d | 2016-06-03 08:54:18 +0800 | [diff] [blame] | 1595 | iounmap(reg_base); |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1596 | return; |
| 1597 | } |
| 1598 | |
| 1599 | rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, |
| 1600 | ARRAY_SIZE(rk3399_pmu_pll_clks), -1); |
| 1601 | |
| 1602 | rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, |
| 1603 | ARRAY_SIZE(rk3399_clk_pmu_branches)); |
| 1604 | |
| 1605 | rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, |
Heiko Stuebner | 995d3fd | 2016-04-19 21:07:01 +0200 | [diff] [blame] | 1606 | ARRAY_SIZE(rk3399_pmucru_critical_clocks)); |
Xing Zheng | 1155100 | 2016-03-28 17:51:37 +0800 | [diff] [blame] | 1607 | |
| 1608 | rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), |
| 1609 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
| 1610 | |
| 1611 | rockchip_clk_of_add_provider(np, ctx); |
| 1612 | } |
| 1613 | CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); |