Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1 | /** |
| 2 | * core.c - DesignWare USB3 DRD Controller Core file |
| 3 | * |
| 4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Authors: Felipe Balbi <balbi@ti.com>, |
| 8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or without |
| 11 | * modification, are permitted provided that the following conditions |
| 12 | * are met: |
| 13 | * 1. Redistributions of source code must retain the above copyright |
| 14 | * notice, this list of conditions, and the following disclaimer, |
| 15 | * without modification. |
| 16 | * 2. Redistributions in binary form must reproduce the above copyright |
| 17 | * notice, this list of conditions and the following disclaimer in the |
| 18 | * documentation and/or other materials provided with the distribution. |
| 19 | * 3. The names of the above-listed copyright holders may not be used |
| 20 | * to endorse or promote products derived from this software without |
| 21 | * specific prior written permission. |
| 22 | * |
| 23 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 24 | * GNU General Public License ("GPL") version 2, as published by the Free |
| 25 | * Software Foundation. |
| 26 | * |
| 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 28 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 29 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 30 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 31 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 32 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 33 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 34 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 35 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 36 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 37 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 38 | */ |
| 39 | |
| 40 | #include <linux/kernel.h> |
| 41 | #include <linux/slab.h> |
| 42 | #include <linux/spinlock.h> |
| 43 | #include <linux/platform_device.h> |
| 44 | #include <linux/pm_runtime.h> |
| 45 | #include <linux/interrupt.h> |
| 46 | #include <linux/ioport.h> |
| 47 | #include <linux/io.h> |
| 48 | #include <linux/list.h> |
| 49 | #include <linux/delay.h> |
| 50 | #include <linux/dma-mapping.h> |
| 51 | |
| 52 | #include <linux/usb/ch9.h> |
| 53 | #include <linux/usb/gadget.h> |
| 54 | |
| 55 | #include "core.h" |
| 56 | #include "gadget.h" |
| 57 | #include "io.h" |
| 58 | |
| 59 | #include "debug.h" |
| 60 | |
| 61 | /** |
| 62 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset |
| 63 | * @dwc: pointer to our context structure |
| 64 | */ |
| 65 | static void dwc3_core_soft_reset(struct dwc3 *dwc) |
| 66 | { |
| 67 | u32 reg; |
| 68 | |
| 69 | /* Before Resetting PHY, put Core in Reset */ |
| 70 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
| 71 | reg |= DWC3_GCTL_CORESOFTRESET; |
| 72 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
| 73 | |
| 74 | /* Assert USB3 PHY reset */ |
| 75 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); |
| 76 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; |
| 77 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
| 78 | |
| 79 | /* Assert USB2 PHY reset */ |
| 80 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
| 81 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; |
| 82 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
| 83 | |
| 84 | mdelay(100); |
| 85 | |
| 86 | /* Clear USB3 PHY reset */ |
| 87 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); |
| 88 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; |
| 89 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
| 90 | |
| 91 | /* Clear USB2 PHY reset */ |
| 92 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); |
| 93 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; |
| 94 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); |
| 95 | |
| 96 | /* After PHYs are stable we can take Core out of reset state */ |
| 97 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
| 98 | reg &= ~DWC3_GCTL_CORESOFTRESET; |
| 99 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
| 100 | } |
| 101 | |
| 102 | /** |
| 103 | * dwc3_free_one_event_buffer - Frees one event buffer |
| 104 | * @dwc: Pointer to our controller context structure |
| 105 | * @evt: Pointer to event buffer to be freed |
| 106 | */ |
| 107 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, |
| 108 | struct dwc3_event_buffer *evt) |
| 109 | { |
| 110 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); |
| 111 | kfree(evt); |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * dwc3_alloc_one_event_buffer - Allocated one event buffer structure |
| 116 | * @dwc: Pointer to our controller context structure |
| 117 | * @length: size of the event buffer |
| 118 | * |
| 119 | * Returns a pointer to the allocated event buffer structure on succes |
| 120 | * otherwise ERR_PTR(errno). |
| 121 | */ |
| 122 | static struct dwc3_event_buffer *__devinit |
| 123 | dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length) |
| 124 | { |
| 125 | struct dwc3_event_buffer *evt; |
| 126 | |
| 127 | evt = kzalloc(sizeof(*evt), GFP_KERNEL); |
| 128 | if (!evt) |
| 129 | return ERR_PTR(-ENOMEM); |
| 130 | |
| 131 | evt->dwc = dwc; |
| 132 | evt->length = length; |
| 133 | evt->buf = dma_alloc_coherent(dwc->dev, length, |
| 134 | &evt->dma, GFP_KERNEL); |
| 135 | if (!evt->buf) { |
| 136 | kfree(evt); |
| 137 | return ERR_PTR(-ENOMEM); |
| 138 | } |
| 139 | |
| 140 | return evt; |
| 141 | } |
| 142 | |
| 143 | /** |
| 144 | * dwc3_free_event_buffers - frees all allocated event buffers |
| 145 | * @dwc: Pointer to our controller context structure |
| 146 | */ |
| 147 | static void dwc3_free_event_buffers(struct dwc3 *dwc) |
| 148 | { |
| 149 | struct dwc3_event_buffer *evt; |
| 150 | int i; |
| 151 | |
| 152 | for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) { |
| 153 | evt = dwc->ev_buffs[i]; |
| 154 | if (evt) { |
| 155 | dwc3_free_one_event_buffer(dwc, evt); |
| 156 | dwc->ev_buffs[i] = NULL; |
| 157 | } |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | /** |
| 162 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length |
| 163 | * @dwc: Pointer to out controller context structure |
| 164 | * @num: number of event buffers to allocate |
| 165 | * @length: size of event buffer |
| 166 | * |
| 167 | * Returns 0 on success otherwise negative errno. In error the case, dwc |
| 168 | * may contain some buffers allocated but not all which were requested. |
| 169 | */ |
| 170 | static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num, |
| 171 | unsigned length) |
| 172 | { |
| 173 | int i; |
| 174 | |
| 175 | for (i = 0; i < num; i++) { |
| 176 | struct dwc3_event_buffer *evt; |
| 177 | |
| 178 | evt = dwc3_alloc_one_event_buffer(dwc, length); |
| 179 | if (IS_ERR(evt)) { |
| 180 | dev_err(dwc->dev, "can't allocate event buffer\n"); |
| 181 | return PTR_ERR(evt); |
| 182 | } |
| 183 | dwc->ev_buffs[i] = evt; |
| 184 | } |
| 185 | |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | /** |
| 190 | * dwc3_event_buffers_setup - setup our allocated event buffers |
| 191 | * @dwc: Pointer to out controller context structure |
| 192 | * |
| 193 | * Returns 0 on success otherwise negative errno. |
| 194 | */ |
| 195 | static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc) |
| 196 | { |
| 197 | struct dwc3_event_buffer *evt; |
| 198 | int n; |
| 199 | |
| 200 | for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) { |
| 201 | evt = dwc->ev_buffs[n]; |
| 202 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", |
| 203 | evt->buf, (unsigned long long) evt->dma, |
| 204 | evt->length); |
| 205 | |
| 206 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
| 207 | lower_32_bits(evt->dma)); |
| 208 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), |
| 209 | upper_32_bits(evt->dma)); |
| 210 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), |
| 211 | evt->length & 0xffff); |
| 212 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
| 213 | } |
| 214 | |
| 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) |
| 219 | { |
| 220 | struct dwc3_event_buffer *evt; |
| 221 | int n; |
| 222 | |
| 223 | for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) { |
| 224 | evt = dwc->ev_buffs[n]; |
| 225 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
| 226 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); |
| 227 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0); |
| 228 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | /** |
| 233 | * dwc3_core_init - Low-level initialization of DWC3 Core |
| 234 | * @dwc: Pointer to our controller context structure |
| 235 | * |
| 236 | * Returns 0 on success otherwise negative errno. |
| 237 | */ |
| 238 | static int __devinit dwc3_core_init(struct dwc3 *dwc) |
| 239 | { |
| 240 | unsigned long timeout; |
| 241 | u32 reg; |
| 242 | int ret; |
| 243 | |
Sebastian Andrzej Siewior | 7650bd7 | 2011-08-29 13:56:36 +0200 | [diff] [blame] | 244 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
| 245 | /* This should read as U3 followed by revision number */ |
| 246 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { |
| 247 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); |
| 248 | ret = -ENODEV; |
| 249 | goto err0; |
| 250 | } |
| 251 | dwc->revision = reg & DWC3_GSNPSREV_MASK; |
| 252 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 253 | dwc3_core_soft_reset(dwc); |
| 254 | |
| 255 | /* issue device SoftReset too */ |
| 256 | timeout = jiffies + msecs_to_jiffies(500); |
| 257 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); |
| 258 | do { |
| 259 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
| 260 | if (!(reg & DWC3_DCTL_CSFTRST)) |
| 261 | break; |
| 262 | |
| 263 | if (time_after(jiffies, timeout)) { |
| 264 | dev_err(dwc->dev, "Reset Timed Out\n"); |
| 265 | ret = -ETIMEDOUT; |
| 266 | goto err0; |
| 267 | } |
| 268 | |
| 269 | cpu_relax(); |
| 270 | } while (true); |
| 271 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 272 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM, |
| 273 | DWC3_EVENT_BUFFERS_SIZE); |
| 274 | if (ret) { |
| 275 | dev_err(dwc->dev, "failed to allocate event buffers\n"); |
| 276 | ret = -ENOMEM; |
| 277 | goto err1; |
| 278 | } |
| 279 | |
| 280 | ret = dwc3_event_buffers_setup(dwc); |
| 281 | if (ret) { |
| 282 | dev_err(dwc->dev, "failed to setup event buffers\n"); |
| 283 | goto err1; |
| 284 | } |
| 285 | |
| 286 | return 0; |
| 287 | |
| 288 | err1: |
| 289 | dwc3_free_event_buffers(dwc); |
| 290 | |
| 291 | err0: |
| 292 | return ret; |
| 293 | } |
| 294 | |
| 295 | static void dwc3_core_exit(struct dwc3 *dwc) |
| 296 | { |
| 297 | dwc3_event_buffers_cleanup(dwc); |
| 298 | dwc3_free_event_buffers(dwc); |
| 299 | } |
| 300 | |
| 301 | #define DWC3_ALIGN_MASK (16 - 1) |
| 302 | |
| 303 | static int __devinit dwc3_probe(struct platform_device *pdev) |
| 304 | { |
| 305 | const struct platform_device_id *id = platform_get_device_id(pdev); |
| 306 | struct resource *res; |
| 307 | struct dwc3 *dwc; |
| 308 | void __iomem *regs; |
| 309 | unsigned int features = id->driver_data; |
| 310 | int ret = -ENOMEM; |
| 311 | int irq; |
| 312 | void *mem; |
| 313 | |
| 314 | mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); |
| 315 | if (!mem) { |
| 316 | dev_err(&pdev->dev, "not enough memory\n"); |
| 317 | goto err0; |
| 318 | } |
| 319 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
| 320 | dwc->mem = mem; |
| 321 | |
| 322 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 323 | if (!res) { |
| 324 | dev_err(&pdev->dev, "missing resource\n"); |
| 325 | goto err1; |
| 326 | } |
| 327 | |
| 328 | res = request_mem_region(res->start, resource_size(res), |
| 329 | dev_name(&pdev->dev)); |
| 330 | if (!res) { |
| 331 | dev_err(&pdev->dev, "can't request mem region\n"); |
| 332 | goto err1; |
| 333 | } |
| 334 | |
| 335 | regs = ioremap(res->start, resource_size(res)); |
| 336 | if (!regs) { |
| 337 | dev_err(&pdev->dev, "ioremap failed\n"); |
| 338 | goto err2; |
| 339 | } |
| 340 | |
| 341 | irq = platform_get_irq(pdev, 0); |
| 342 | if (irq < 0) { |
| 343 | dev_err(&pdev->dev, "missing IRQ\n"); |
| 344 | goto err3; |
| 345 | } |
| 346 | |
| 347 | spin_lock_init(&dwc->lock); |
| 348 | platform_set_drvdata(pdev, dwc); |
| 349 | |
| 350 | dwc->regs = regs; |
| 351 | dwc->regs_size = resource_size(res); |
| 352 | dwc->dev = &pdev->dev; |
| 353 | dwc->irq = irq; |
| 354 | |
| 355 | pm_runtime_enable(&pdev->dev); |
| 356 | pm_runtime_get_sync(&pdev->dev); |
| 357 | pm_runtime_forbid(&pdev->dev); |
| 358 | |
| 359 | ret = dwc3_core_init(dwc); |
| 360 | if (ret) { |
| 361 | dev_err(&pdev->dev, "failed to initialize core\n"); |
| 362 | goto err3; |
| 363 | } |
| 364 | |
| 365 | if (features & DWC3_HAS_PERIPHERAL) { |
| 366 | ret = dwc3_gadget_init(dwc); |
| 367 | if (ret) { |
| 368 | dev_err(&pdev->dev, "failed to initialized gadget\n"); |
| 369 | goto err4; |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | ret = dwc3_debugfs_init(dwc); |
| 374 | if (ret) { |
| 375 | dev_err(&pdev->dev, "failed to initialize debugfs\n"); |
| 376 | goto err5; |
| 377 | } |
| 378 | |
| 379 | pm_runtime_allow(&pdev->dev); |
| 380 | |
| 381 | return 0; |
| 382 | |
| 383 | err5: |
| 384 | if (features & DWC3_HAS_PERIPHERAL) |
| 385 | dwc3_gadget_exit(dwc); |
| 386 | |
| 387 | err4: |
| 388 | dwc3_core_exit(dwc); |
| 389 | |
| 390 | err3: |
| 391 | iounmap(regs); |
| 392 | |
| 393 | err2: |
| 394 | release_mem_region(res->start, resource_size(res)); |
| 395 | |
| 396 | err1: |
| 397 | kfree(dwc->mem); |
| 398 | |
| 399 | err0: |
| 400 | return ret; |
| 401 | } |
| 402 | |
| 403 | static int __devexit dwc3_remove(struct platform_device *pdev) |
| 404 | { |
| 405 | const struct platform_device_id *id = platform_get_device_id(pdev); |
| 406 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
| 407 | struct resource *res; |
| 408 | unsigned int features = id->driver_data; |
| 409 | |
| 410 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 411 | |
| 412 | pm_runtime_put(&pdev->dev); |
| 413 | pm_runtime_disable(&pdev->dev); |
| 414 | |
| 415 | dwc3_debugfs_exit(dwc); |
| 416 | |
| 417 | if (features & DWC3_HAS_PERIPHERAL) |
| 418 | dwc3_gadget_exit(dwc); |
| 419 | |
| 420 | dwc3_core_exit(dwc); |
| 421 | release_mem_region(res->start, resource_size(res)); |
| 422 | iounmap(dwc->regs); |
| 423 | kfree(dwc->mem); |
| 424 | |
| 425 | return 0; |
| 426 | } |
| 427 | |
| 428 | static const struct platform_device_id dwc3_id_table[] __devinitconst = { |
| 429 | { |
| 430 | .name = "dwc3-omap", |
| 431 | .driver_data = (DWC3_HAS_PERIPHERAL |
| 432 | | DWC3_HAS_XHCI |
| 433 | | DWC3_HAS_OTG), |
| 434 | }, |
| 435 | { |
| 436 | .name = "dwc3-pci", |
| 437 | .driver_data = DWC3_HAS_PERIPHERAL, |
| 438 | }, |
| 439 | { }, /* Terminating Entry */ |
| 440 | }; |
| 441 | MODULE_DEVICE_TABLE(platform, dwc3_id_table); |
| 442 | |
| 443 | static struct platform_driver dwc3_driver = { |
| 444 | .probe = dwc3_probe, |
| 445 | .remove = __devexit_p(dwc3_remove), |
| 446 | .driver = { |
| 447 | .name = "dwc3", |
| 448 | }, |
| 449 | .id_table = dwc3_id_table, |
| 450 | }; |
| 451 | |
| 452 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
| 453 | MODULE_LICENSE("Dual BSD/GPL"); |
| 454 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |
| 455 | |
| 456 | static int __devinit dwc3_init(void) |
| 457 | { |
| 458 | return platform_driver_register(&dwc3_driver); |
| 459 | } |
| 460 | module_init(dwc3_init); |
| 461 | |
| 462 | static void __exit dwc3_exit(void) |
| 463 | { |
| 464 | platform_driver_unregister(&dwc3_driver); |
| 465 | } |
| 466 | module_exit(dwc3_exit); |