Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/pxa168.c |
| 3 | * |
| 4 | * Code specific to PXA168 |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/list.h> |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 15 | #include <linux/io.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 16 | #include <linux/clk.h> |
| 17 | |
| 18 | #include <asm/mach/time.h> |
| 19 | #include <mach/addr-map.h> |
| 20 | #include <mach/cputype.h> |
| 21 | #include <mach/regs-apbc.h> |
| 22 | #include <mach/irqs.h> |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 23 | #include <mach/gpio.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 24 | #include <mach/dma.h> |
| 25 | #include <mach/devices.h> |
Eric Miao | a7a89d9 | 2009-01-20 17:20:56 +0800 | [diff] [blame^] | 26 | #include <mach/mfp.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 27 | |
| 28 | #include "common.h" |
| 29 | #include "clock.h" |
| 30 | |
Eric Miao | a7a89d9 | 2009-01-20 17:20:56 +0800 | [diff] [blame^] | 31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) |
| 32 | |
| 33 | static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = |
| 34 | { |
| 35 | MFP_ADDR_X(GPIO0, GPIO36, 0x04c), |
| 36 | MFP_ADDR_X(GPIO37, GPIO55, 0x000), |
| 37 | MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), |
| 38 | MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), |
| 39 | |
| 40 | MFP_ADDR_END, |
| 41 | }; |
| 42 | |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 43 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) |
| 44 | |
| 45 | static void __init pxa168_init_gpio(void) |
| 46 | { |
| 47 | int i; |
| 48 | |
| 49 | /* enable GPIO clock */ |
| 50 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); |
| 51 | |
| 52 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ |
| 53 | for (i = 0; i < 4; i++) |
| 54 | __raw_writel(0xffffffff, APMASK(i)); |
| 55 | |
| 56 | pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); |
| 57 | } |
| 58 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 59 | void __init pxa168_init_irq(void) |
| 60 | { |
| 61 | icu_init_irq(); |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 62 | pxa168_init_gpio(); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | /* APB peripheral clocks */ |
| 66 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); |
| 67 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); |
| 68 | |
| 69 | /* device and clock bindings */ |
| 70 | static struct clk_lookup pxa168_clkregs[] = { |
| 71 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
| 72 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), |
| 73 | }; |
| 74 | |
| 75 | static int __init pxa168_init(void) |
| 76 | { |
| 77 | if (cpu_is_pxa168()) { |
Eric Miao | a7a89d9 | 2009-01-20 17:20:56 +0800 | [diff] [blame^] | 78 | mfp_init_base(MFPR_VIRT_BASE); |
| 79 | mfp_init_addr(pxa168_mfp_addr_map); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 80 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); |
| 81 | clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); |
| 82 | } |
| 83 | |
| 84 | return 0; |
| 85 | } |
| 86 | postcore_initcall(pxa168_init); |
| 87 | |
| 88 | /* system timer - clock enabled, 3.25MHz */ |
| 89 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) |
| 90 | |
| 91 | static void __init pxa168_timer_init(void) |
| 92 | { |
| 93 | /* this is early, we have to initialize the CCU registers by |
| 94 | * ourselves instead of using clk_* API. Clock rate is defined |
| 95 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running |
| 96 | */ |
| 97 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); |
| 98 | |
| 99 | /* 3.25MHz, bus/functional clock enabled, release reset */ |
| 100 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); |
| 101 | |
| 102 | timer_init(IRQ_PXA168_TIMER1); |
| 103 | } |
| 104 | |
| 105 | struct sys_timer pxa168_timer = { |
| 106 | .init = pxa168_timer_init, |
| 107 | }; |
| 108 | |
| 109 | /* on-chip devices */ |
| 110 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); |
| 111 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); |