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Jacob Kellerbeb0dff2014-01-11 05:43:19 +00001/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e.h"
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000028#include <linux/ptp_classify.h>
29
30/* The XL710 timesync is very much like Intel's 82599 design when it comes to
31 * the fundamental clock design. However, the clock operations are much simpler
32 * in the XL710 because the device supports a full 64 bits of nanoseconds.
33 * Because the field is so wide, we can forgo the cycle counter and just
34 * operate with the nanosecond field directly without fear of overflow.
35 *
36 * Much like the 82599, the update period is dependent upon the link speed:
37 * At 40Gb link or no link, the period is 1.6ns.
38 * At 10Gb link, the period is multiplied by 2. (3.2ns)
39 * At 1Gb link, the period is multiplied by 20. (32ns)
40 * 1588 functionality is not supported at 100Mbps.
41 */
42#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
43#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
44#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
45
Jesse Brandeburg41a1d042015-06-04 16:24:02 -040046#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
47#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000048 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000049
50/**
51 * i40e_ptp_read - Read the PHC time from the device
52 * @pf: Board private structure
53 * @ts: timespec structure to hold the current time value
54 *
55 * This function reads the PRTTSYN_TIME registers and stores them in a
56 * timespec. However, since the registers are 64 bits of nanoseconds, we must
57 * convert the result to a timespec before we can return.
58 **/
Richard Cochran6f7a9b82015-03-29 23:12:02 +020059static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000060{
61 struct i40e_hw *hw = &pf->hw;
62 u32 hi, lo;
63 u64 ns;
64
65 /* The timer latches on the lowest register read. */
66 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
67 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
68
69 ns = (((u64)hi) << 32) | lo;
70
Richard Cochran6f7a9b82015-03-29 23:12:02 +020071 *ts = ns_to_timespec64(ns);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000072}
73
74/**
75 * i40e_ptp_write - Write the PHC time to the device
76 * @pf: Board private structure
77 * @ts: timespec structure that holds the new time value
78 *
79 * This function writes the PRTTSYN_TIME registers with the user value. Since
80 * we receive a timespec from the stack, we must convert that timespec into
81 * nanoseconds before programming the registers.
82 **/
Richard Cochran6f7a9b82015-03-29 23:12:02 +020083static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000084{
85 struct i40e_hw *hw = &pf->hw;
Richard Cochran6f7a9b82015-03-29 23:12:02 +020086 u64 ns = timespec64_to_ns(ts);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +000087
88 /* The timer will not update until the high register is written, so
89 * write the low register first.
90 */
91 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
92 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
93}
94
95/**
96 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
97 * @hwtstamps: Timestamp structure to update
98 * @timestamp: Timestamp from the hardware
99 *
100 * We need to convert the NIC clock value into a hwtstamp which can be used by
101 * the upper level timestamping functions. Since the timestamp is simply a 64-
102 * bit nanosecond value, we can call ns_to_ktime directly to handle this.
103 **/
104static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
105 u64 timestamp)
106{
107 memset(hwtstamps, 0, sizeof(*hwtstamps));
108
109 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
110}
111
112/**
113 * i40e_ptp_adjfreq - Adjust the PHC frequency
114 * @ptp: The PTP clock structure
115 * @ppb: Parts per billion adjustment from the base
116 *
117 * Adjust the frequency of the PHC by the indicated parts per billion from the
118 * base frequency.
119 **/
120static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
121{
122 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
123 struct i40e_hw *hw = &pf->hw;
124 u64 adj, freq, diff;
125 int neg_adj = 0;
126
127 if (ppb < 0) {
128 neg_adj = 1;
129 ppb = -ppb;
130 }
131
132 smp_mb(); /* Force any pending update before accessing. */
133 adj = ACCESS_ONCE(pf->ptp_base_adj);
134
135 freq = adj;
136 freq *= ppb;
137 diff = div_u64(freq, 1000000000ULL);
138
139 if (neg_adj)
140 adj -= diff;
141 else
142 adj += diff;
143
144 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
145 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
146
147 return 0;
148}
149
150/**
151 * i40e_ptp_adjtime - Adjust the PHC time
152 * @ptp: The PTP clock structure
153 * @delta: Offset in nanoseconds to adjust the PHC time by
154 *
155 * Adjust the frequency of the PHC by the indicated parts per billion from the
156 * base frequency.
157 **/
158static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
159{
160 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
Jesse Brandeburgcdc3d932016-04-13 03:08:28 -0700161 struct timespec64 now, then;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000162 unsigned long flags;
163
Jesse Brandeburgcdc3d932016-04-13 03:08:28 -0700164 then = ns_to_timespec64(delta);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000165 spin_lock_irqsave(&pf->tmreg_lock, flags);
166
167 i40e_ptp_read(pf, &now);
Richard Cochran6f7a9b82015-03-29 23:12:02 +0200168 now = timespec64_add(now, then);
169 i40e_ptp_write(pf, (const struct timespec64 *)&now);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000170
171 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
172
173 return 0;
174}
175
176/**
177 * i40e_ptp_gettime - Get the time of the PHC
178 * @ptp: The PTP clock structure
179 * @ts: timespec structure to hold the current time value
180 *
181 * Read the device clock and return the correct value on ns, after converting it
182 * into a timespec struct.
183 **/
Richard Cochran6f7a9b82015-03-29 23:12:02 +0200184static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000185{
186 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
187 unsigned long flags;
188
189 spin_lock_irqsave(&pf->tmreg_lock, flags);
190 i40e_ptp_read(pf, ts);
191 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
192
193 return 0;
194}
195
196/**
197 * i40e_ptp_settime - Set the time of the PHC
198 * @ptp: The PTP clock structure
199 * @ts: timespec structure that holds the new time value
200 *
201 * Set the device clock to the user input value. The conversion from timespec
202 * to ns happens in the write function.
203 **/
204static int i40e_ptp_settime(struct ptp_clock_info *ptp,
Richard Cochran6f7a9b82015-03-29 23:12:02 +0200205 const struct timespec64 *ts)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000206{
207 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
208 unsigned long flags;
209
210 spin_lock_irqsave(&pf->tmreg_lock, flags);
211 i40e_ptp_write(pf, ts);
212 spin_unlock_irqrestore(&pf->tmreg_lock, flags);
213
214 return 0;
215}
216
217/**
Jacob Keller69d1a702014-06-04 04:22:42 +0000218 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000219 * @ptp: The PTP clock structure
220 * @rq: The requested feature to change
221 * @on: Enable/disable flag
222 *
223 * The XL710 does not support any of the ancillary features of the PHC
224 * subsystem, so this function may just return.
225 **/
Jacob Keller69d1a702014-06-04 04:22:42 +0000226static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
227 struct ptp_clock_request *rq, int on)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000228{
229 return -EOPNOTSUPP;
230}
231
232/**
233 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
234 * @vsi: The VSI with the rings relevant to 1588
235 *
236 * This watchdog task is scheduled to detect error case where hardware has
237 * dropped an Rx packet that was timestamped when the ring is full. The
238 * particular error is rare but leaves the device in a state unable to timestamp
239 * any future packets.
240 **/
241void i40e_ptp_rx_hang(struct i40e_vsi *vsi)
242{
243 struct i40e_pf *pf = vsi->back;
244 struct i40e_hw *hw = &pf->hw;
245 struct i40e_ring *rx_ring;
246 unsigned long rx_event;
247 u32 prttsyn_stat;
248 int n;
249
Jacob Kellerb535a012014-12-14 01:55:14 +0000250 /* Since we cannot turn off the Rx timestamp logic if the device is
251 * configured for Tx timestamping, we check if Rx timestamping is
252 * configured. We don't want to spuriously warn about Rx timestamp
253 * hangs if we don't care about the timestamps.
254 */
255 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000256 return;
257
258 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
259
260 /* Unless all four receive timestamp registers are latched, we are not
261 * concerned about a possible PTP Rx hang, so just update the timeout
262 * counter and exit.
263 */
264 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK <<
265 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) |
266 (I40E_PRTTSYN_STAT_1_RXT1_MASK <<
267 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) |
268 (I40E_PRTTSYN_STAT_1_RXT2_MASK <<
269 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) |
270 (I40E_PRTTSYN_STAT_1_RXT3_MASK <<
271 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) {
272 pf->last_rx_ptp_check = jiffies;
273 return;
274 }
275
276 /* Determine the most recent watchdog or rx_timestamp event. */
277 rx_event = pf->last_rx_ptp_check;
278 for (n = 0; n < vsi->num_queue_pairs; n++) {
279 rx_ring = vsi->rx_rings[n];
280 if (time_after(rx_ring->last_rx_timestamp, rx_event))
281 rx_event = rx_ring->last_rx_timestamp;
282 }
283
284 /* Only need to read the high RXSTMP register to clear the lock */
285 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
286 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
287 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
288 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
289 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
290 pf->last_rx_ptp_check = jiffies;
291 pf->rx_hwtstamp_cleared++;
Jacob Kellerc4208152016-05-03 15:13:15 -0700292 WARN_ONCE(1, "Detected Rx timestamp register hang\n");
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000293 }
294}
295
296/**
297 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
298 * @pf: Board private structure
299 *
300 * Read the value of the Tx timestamp from the registers, convert it into a
301 * value consumable by the stack, and store that result into the shhwtstamps
302 * struct before returning it up the stack.
303 **/
304void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
305{
306 struct skb_shared_hwtstamps shhwtstamps;
307 struct i40e_hw *hw = &pf->hw;
308 u32 hi, lo;
309 u64 ns;
310
Jacob Keller22b47772014-12-14 01:55:09 +0000311 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
312 return;
313
314 /* don't attempt to timestamp if we don't have an skb */
315 if (!pf->ptp_tx_skb)
316 return;
317
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000318 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
319 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
320
321 ns = (((u64)hi) << 32) | lo;
322
323 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
324 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps);
325 dev_kfree_skb_any(pf->ptp_tx_skb);
326 pf->ptp_tx_skb = NULL;
Jakub Kicinski9ce34f02014-03-15 14:55:42 +0000327 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000328}
329
330/**
331 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
332 * @pf: Board private structure
333 * @skb: Particular skb to send timestamp with
334 * @index: Index into the receive timestamp registers for the timestamp
335 *
336 * The XL710 receives a notification in the receive descriptor with an offset
337 * into the set of RXTIME registers where the timestamp is for that skb. This
338 * function goes and fetches the receive timestamp from that offset, if a valid
339 * one exists. The RXTIME registers are in ns, so we must convert the result
340 * first.
341 **/
342void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
343{
344 u32 prttsyn_stat, hi, lo;
345 struct i40e_hw *hw;
346 u64 ns;
347
348 /* Since we cannot turn off the Rx timestamp logic if the device is
349 * doing Tx timestamping, check if Rx timestamping is configured.
350 */
Jacob Keller22b47772014-12-14 01:55:09 +0000351 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000352 return;
353
354 hw = &pf->hw;
355
356 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
357
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400358 if (!(prttsyn_stat & BIT(index)))
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000359 return;
360
361 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
362 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
363
364 ns = (((u64)hi) << 32) | lo;
365
366 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
367}
368
369/**
370 * i40e_ptp_set_increment - Utility function to update clock increment rate
371 * @pf: Board private structure
372 *
373 * During a link change, the DMA frequency that drives the 1588 logic will
374 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
375 * we must update the increment value per clock tick.
376 **/
377void i40e_ptp_set_increment(struct i40e_pf *pf)
378{
379 struct i40e_link_status *hw_link_info;
380 struct i40e_hw *hw = &pf->hw;
381 u64 incval;
382
383 hw_link_info = &hw->phy.link_info;
384
385 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
386
387 switch (hw_link_info->link_speed) {
388 case I40E_LINK_SPEED_10GB:
389 incval = I40E_PTP_10GB_INCVAL;
390 break;
391 case I40E_LINK_SPEED_1GB:
392 incval = I40E_PTP_1GB_INCVAL;
393 break;
394 case I40E_LINK_SPEED_100MB:
Shannon Nelsone684fa32014-11-11 03:15:03 +0000395 {
396 static int warn_once;
397
398 if (!warn_once) {
399 dev_warn(&pf->pdev->dev,
400 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
401 warn_once++;
402 }
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000403 incval = 0;
404 break;
Shannon Nelsone684fa32014-11-11 03:15:03 +0000405 }
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000406 case I40E_LINK_SPEED_40GB:
407 default:
408 incval = I40E_PTP_40GB_INCVAL;
409 break;
410 }
411
412 /* Write the new increment value into the increment register. The
413 * hardware will not update the clock until both registers have been
414 * written.
415 */
416 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
417 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
418
419 /* Update the base adjustement value. */
420 ACCESS_ONCE(pf->ptp_base_adj) = incval;
421 smp_mb(); /* Force the above update. */
422}
423
424/**
425 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
426 * @pf: Board private structure
427 * @ifreq: ioctl data
428 *
429 * Obtain the current hardware timestamping settigs as requested. To do this,
430 * keep a shadow copy of the timestamp settings rather than attempting to
431 * deconstruct it from the registers.
432 **/
433int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
434{
435 struct hwtstamp_config *config = &pf->tstamp_config;
436
Jacob Kellerfe88bda2014-11-11 20:05:58 +0000437 if (!(pf->flags & I40E_FLAG_PTP))
438 return -EOPNOTSUPP;
439
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000440 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
441 -EFAULT : 0;
442}
443
444/**
Jacob Keller18946452014-06-04 06:08:29 +0000445 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000446 * @pf: Board private structure
Jacob Keller18946452014-06-04 06:08:29 +0000447 * @config: hwtstamp settings requested or saved
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000448 *
Jacob Keller18946452014-06-04 06:08:29 +0000449 * Control hardware registers to enter the specific mode requested by the
450 * user. Also used during reset path to ensure that timestamp settings are
451 * maintained.
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000452 *
Jacob Keller18946452014-06-04 06:08:29 +0000453 * Note: modifies config in place, and may update the requested mode to be
454 * more broad if the specific filter is not directly supported.
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000455 **/
Jacob Keller18946452014-06-04 06:08:29 +0000456static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
457 struct hwtstamp_config *config)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000458{
459 struct i40e_hw *hw = &pf->hw;
Jacob Kellerfe88bda2014-11-11 20:05:58 +0000460 u32 tsyntype, regval;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000461
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000462 /* Reserved for future extensions. */
463 if (config->flags)
464 return -EINVAL;
465
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000466 switch (config->tx_type) {
467 case HWTSTAMP_TX_OFF:
468 pf->ptp_tx = false;
469 break;
470 case HWTSTAMP_TX_ON:
471 pf->ptp_tx = true;
472 break;
473 default:
474 return -ERANGE;
475 }
476
477 switch (config->rx_filter) {
478 case HWTSTAMP_FILTER_NONE:
479 pf->ptp_rx = false;
Jacob Keller4fda14c2014-12-14 01:55:15 +0000480 /* We set the type to V1, but do not enable UDP packet
481 * recognition. In this way, we should be as close to
482 * disabling PTP Rx timestamps as possible since V1 packets
483 * are always UDP, since L2 packets are a V2 feature.
484 */
485 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000486 break;
487 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
488 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
489 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
490 pf->ptp_rx = true;
491 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
492 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
493 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
494 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
495 break;
496 case HWTSTAMP_FILTER_PTP_V2_EVENT:
497 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
498 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
499 case HWTSTAMP_FILTER_PTP_V2_SYNC:
500 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
501 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
502 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
503 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
504 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
505 pf->ptp_rx = true;
506 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
507 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 |
508 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
509 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
510 break;
511 case HWTSTAMP_FILTER_ALL:
512 default:
513 return -ERANGE;
514 }
515
516 /* Clear out all 1588-related registers to clear and unlatch them. */
517 rd32(hw, I40E_PRTTSYN_STAT_0);
518 rd32(hw, I40E_PRTTSYN_TXTIME_H);
519 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
520 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
521 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
522 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
523
524 /* Enable/disable the Tx timestamp interrupt based on user input. */
525 regval = rd32(hw, I40E_PRTTSYN_CTL0);
526 if (pf->ptp_tx)
527 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
528 else
529 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
530 wr32(hw, I40E_PRTTSYN_CTL0, regval);
531
532 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
533 if (pf->ptp_tx)
534 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
535 else
536 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
537 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
538
Jacob Keller4fda14c2014-12-14 01:55:15 +0000539 /* Although there is no simple on/off switch for Rx, we "disable" Rx
540 * timestamps by setting to V1 only mode and clear the UDP
541 * recognition. This ought to disable all PTP Rx timestamps as V1
542 * packets are always over UDP. Note that software is configured to
543 * ignore Rx timestamps via the pf->ptp_rx flag.
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000544 */
Jacob Keller4fda14c2014-12-14 01:55:15 +0000545 regval = rd32(hw, I40E_PRTTSYN_CTL1);
546 /* clear everything but the enable bit */
547 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
548 /* now enable bits for desired Rx timestamps */
549 regval |= tsyntype;
550 wr32(hw, I40E_PRTTSYN_CTL1, regval);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000551
Jacob Keller18946452014-06-04 06:08:29 +0000552 return 0;
553}
554
555/**
556 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
557 * @pf: Board private structure
558 * @ifreq: ioctl data
559 *
560 * Respond to the user filter requests and make the appropriate hardware
561 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
562 * logic, so keep track in software of whether to indicate these timestamps
563 * or not.
564 *
565 * It is permissible to "upgrade" the user request to a broader filter, as long
566 * as the user receives the timestamps they care about and the user is notified
567 * the filter has been broadened.
568 **/
569int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
570{
Jacob Kellerd19af2a2014-06-04 04:22:44 +0000571 struct hwtstamp_config config;
Jacob Keller18946452014-06-04 06:08:29 +0000572 int err;
573
Jacob Kellerfe88bda2014-11-11 20:05:58 +0000574 if (!(pf->flags & I40E_FLAG_PTP))
575 return -EOPNOTSUPP;
576
Jacob Kellerd19af2a2014-06-04 04:22:44 +0000577 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
Jacob Keller18946452014-06-04 06:08:29 +0000578 return -EFAULT;
579
Jacob Kellerd19af2a2014-06-04 04:22:44 +0000580 err = i40e_ptp_set_timestamp_mode(pf, &config);
Jacob Keller18946452014-06-04 06:08:29 +0000581 if (err)
582 return err;
583
Jacob Kellerd19af2a2014-06-04 04:22:44 +0000584 /* save these settings for future reference */
585 pf->tstamp_config = config;
586
587 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000588 -EFAULT : 0;
589}
590
591/**
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000592 * i40e_ptp_create_clock - Create PTP clock device for userspace
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000593 * @pf: Board private structure
594 *
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000595 * This function creates a new PTP clock device. It only creates one if we
596 * don't already have one, so it is safe to call. Will return error if it
597 * can't create one, but success if we already have a device. Should be used
598 * by i40e_ptp_init to create clock initially, and prevent global resets from
599 * creating new clock devices.
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000600 **/
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000601static long i40e_ptp_create_clock(struct i40e_pf *pf)
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000602{
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000603 /* no need to create a clock device if we already have one */
604 if (!IS_ERR_OR_NULL(pf->ptp_clock))
605 return 0;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000606
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000607 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name));
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000608 pf->ptp_caps.owner = THIS_MODULE;
609 pf->ptp_caps.max_adj = 999999999;
610 pf->ptp_caps.n_ext_ts = 0;
611 pf->ptp_caps.pps = 0;
612 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
613 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
Richard Cochran6f7a9b82015-03-29 23:12:02 +0200614 pf->ptp_caps.gettime64 = i40e_ptp_gettime;
615 pf->ptp_caps.settime64 = i40e_ptp_settime;
Jacob Keller69d1a702014-06-04 04:22:42 +0000616 pf->ptp_caps.enable = i40e_ptp_feature_enable;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000617
618 /* Attempt to register the clock before enabling the hardware. */
619 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
Jesse Brandeburg6995b362015-08-28 17:55:54 -0400620 if (IS_ERR(pf->ptp_clock))
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000621 return PTR_ERR(pf->ptp_clock);
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000622
623 /* clear the hwtstamp settings here during clock create, instead of
624 * during regular init, so that we can maintain settings across a
625 * reset or suspend.
626 */
627 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
628 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
629
630 return 0;
631}
632
633/**
634 * i40e_ptp_init - Initialize the 1588 support after device probe or reset
635 * @pf: Board private structure
636 *
637 * This function sets device up for 1588 support. The first time it is run, it
638 * will create a PHC clock device. It does not create a clock device if one
639 * already exists. It also reconfigures the device after a reset.
640 **/
641void i40e_ptp_init(struct i40e_pf *pf)
642{
643 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
644 struct i40e_hw *hw = &pf->hw;
Jacob Kellerfe88bda2014-11-11 20:05:58 +0000645 u32 pf_id;
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000646 long err;
647
Jacob Kellerfe88bda2014-11-11 20:05:58 +0000648 /* Only one PF is assigned to control 1588 logic per port. Do not
649 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID
650 */
651 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
652 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
653 if (hw->pf_id != pf_id) {
654 pf->flags &= ~I40E_FLAG_PTP;
655 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
656 __func__,
657 netdev->name);
658 return;
659 }
660
Jacob Kellerfbd5e2d2014-06-04 04:22:45 +0000661 /* we have to initialize the lock first, since we can't control
662 * when the user will enter the PHC device entry points
663 */
664 spin_lock_init(&pf->tmreg_lock);
665
666 /* ensure we have a clock device */
667 err = i40e_ptp_create_clock(pf);
668 if (err) {
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000669 pf->ptp_clock = NULL;
670 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
671 __func__);
672 } else {
Richard Cochran6f7a9b82015-03-29 23:12:02 +0200673 struct timespec64 ts;
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000674 u32 regval;
675
Shannon Nelson6dec1012015-09-28 14:12:30 -0400676 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
677 dev_info(&pf->pdev->dev, "PHC enabled\n");
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000678 pf->flags |= I40E_FLAG_PTP;
679
680 /* Ensure the clocks are running. */
681 regval = rd32(hw, I40E_PRTTSYN_CTL0);
682 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
683 wr32(hw, I40E_PRTTSYN_CTL0, regval);
684 regval = rd32(hw, I40E_PRTTSYN_CTL1);
685 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
686 wr32(hw, I40E_PRTTSYN_CTL1, regval);
687
688 /* Set the increment value per clock tick. */
689 i40e_ptp_set_increment(pf);
690
Jacob Keller18946452014-06-04 06:08:29 +0000691 /* reset timestamping mode */
692 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000693
694 /* Set the clock value. */
Richard Cochran6f7a9b82015-03-29 23:12:02 +0200695 ts = ktime_to_timespec64(ktime_get_real());
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000696 i40e_ptp_settime(&pf->ptp_caps, &ts);
697 }
698}
699
700/**
701 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
702 * @pf: Board private structure
703 *
704 * This function handles the cleanup work required from the initialization by
705 * clearing out the important information and unregistering the PHC.
706 **/
707void i40e_ptp_stop(struct i40e_pf *pf)
708{
709 pf->flags &= ~I40E_FLAG_PTP;
710 pf->ptp_tx = false;
711 pf->ptp_rx = false;
712
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000713 if (pf->ptp_tx_skb) {
714 dev_kfree_skb_any(pf->ptp_tx_skb);
715 pf->ptp_tx_skb = NULL;
Jakub Kicinski9ce34f02014-03-15 14:55:42 +0000716 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state);
Jacob Kellerbeb0dff2014-01-11 05:43:19 +0000717 }
718
719 if (pf->ptp_clock) {
720 ptp_clock_unregister(pf->ptp_clock);
721 pf->ptp_clock = NULL;
722 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
723 pf->vsi[pf->lan_vsi]->netdev->name);
724 }
725}