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Rob Clarkc8afe682013-06-26 12:44:06 -04001/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/pm.h>
27#include <linux/pm_runtime.h>
28#include <linux/slab.h>
29#include <linux/list.h>
30#include <linux/iommu.h>
31#include <linux/types.h>
32#include <asm/sizes.h>
33
34#ifndef CONFIG_OF
35#include <mach/board.h>
36#include <mach/socinfo.h>
37#include <mach/iommu_domains.h>
38#endif
39
40#include <drm/drmP.h>
41#include <drm/drm_crtc_helper.h>
42#include <drm/drm_fb_helper.h>
Rob Clark7198e6b2013-07-19 12:59:32 -040043#include <drm/msm_drm.h>
Rob Clarkc8afe682013-06-26 12:44:06 -040044
45struct msm_kms;
Rob Clark7198e6b2013-07-19 12:59:32 -040046struct msm_gpu;
Rob Clarkc8afe682013-06-26 12:44:06 -040047
Rob Clark7198e6b2013-07-19 12:59:32 -040048#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
49
50struct msm_file_private {
51 /* currently we don't do anything useful with this.. but when
52 * per-context address spaces are supported we'd keep track of
53 * the context's page-tables here.
54 */
55 int dummy;
56};
Rob Clarkc8afe682013-06-26 12:44:06 -040057
58struct msm_drm_private {
59
60 struct msm_kms *kms;
61
Rob Clark7198e6b2013-07-19 12:59:32 -040062 /* when we have more than one 'msm_gpu' these need to be an array: */
63 struct msm_gpu *gpu;
64 struct msm_file_private *lastctx;
65
Rob Clarkc8afe682013-06-26 12:44:06 -040066 struct drm_fb_helper *fbdev;
67
Rob Clark7198e6b2013-07-19 12:59:32 -040068 uint32_t next_fence, completed_fence;
69 wait_queue_head_t fence_event;
70
Rob Clarkc8afe682013-06-26 12:44:06 -040071 /* list of GEM objects: */
72 struct list_head inactive_list;
73
74 struct workqueue_struct *wq;
75
76 /* registered IOMMU domains: */
77 unsigned int num_iommus;
78 struct iommu_domain *iommus[NUM_DOMAINS];
79
Rob Clarka8623912013-10-08 12:57:48 -040080 unsigned int num_planes;
81 struct drm_plane *planes[8];
82
Rob Clarkc8afe682013-06-26 12:44:06 -040083 unsigned int num_crtcs;
84 struct drm_crtc *crtcs[8];
85
86 unsigned int num_encoders;
87 struct drm_encoder *encoders[8];
88
Rob Clarka3376e32013-08-30 13:02:15 -040089 unsigned int num_bridges;
90 struct drm_bridge *bridges[8];
91
Rob Clarkc8afe682013-06-26 12:44:06 -040092 unsigned int num_connectors;
93 struct drm_connector *connectors[8];
94};
95
96struct msm_format {
97 uint32_t pixel_format;
98};
99
100/* As there are different display controller blocks depending on the
101 * snapdragon version, the kms support is split out and the appropriate
102 * implementation is loaded at runtime. The kms module is responsible
103 * for constructing the appropriate planes/crtcs/encoders/connectors.
104 */
105struct msm_kms_funcs {
106 /* hw initialization: */
107 int (*hw_init)(struct msm_kms *kms);
108 /* irq handling: */
109 void (*irq_preinstall)(struct msm_kms *kms);
110 int (*irq_postinstall)(struct msm_kms *kms);
111 void (*irq_uninstall)(struct msm_kms *kms);
112 irqreturn_t (*irq)(struct msm_kms *kms);
113 int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
114 void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
115 /* misc: */
116 const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
117 long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
118 struct drm_encoder *encoder);
119 /* cleanup: */
120 void (*preclose)(struct msm_kms *kms, struct drm_file *file);
121 void (*destroy)(struct msm_kms *kms);
122};
123
124struct msm_kms {
125 const struct msm_kms_funcs *funcs;
126};
127
128struct msm_kms *mdp4_kms_init(struct drm_device *dev);
129
130int msm_register_iommu(struct drm_device *dev, struct iommu_domain *iommu);
131int msm_iommu_attach(struct drm_device *dev, struct iommu_domain *iommu,
132 const char **names, int cnt);
133
Rob Clark7198e6b2013-07-19 12:59:32 -0400134int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
135 struct timespec *timeout);
136void msm_update_fence(struct drm_device *dev, uint32_t fence);
137
138int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
139 struct drm_file *file);
140
Rob Clarkc8afe682013-06-26 12:44:06 -0400141int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
142int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
143uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
144int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
145 uint32_t *iova);
146int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
Rob Clark05b84912013-09-28 11:28:35 -0400147struct page **msm_gem_get_pages(struct drm_gem_object *obj);
148void msm_gem_put_pages(struct drm_gem_object *obj);
Rob Clarkc8afe682013-06-26 12:44:06 -0400149void msm_gem_put_iova(struct drm_gem_object *obj, int id);
150int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
151 struct drm_mode_create_dumb *args);
Rob Clarkc8afe682013-06-26 12:44:06 -0400152int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
153 uint32_t handle, uint64_t *offset);
Rob Clark05b84912013-09-28 11:28:35 -0400154struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
155void *msm_gem_prime_vmap(struct drm_gem_object *obj);
156void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
157struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
158 size_t size, struct sg_table *sg);
159int msm_gem_prime_pin(struct drm_gem_object *obj);
160void msm_gem_prime_unpin(struct drm_gem_object *obj);
Rob Clarkc8afe682013-06-26 12:44:06 -0400161void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
162void *msm_gem_vaddr(struct drm_gem_object *obj);
163int msm_gem_queue_inactive_work(struct drm_gem_object *obj,
164 struct work_struct *work);
Rob Clark7198e6b2013-07-19 12:59:32 -0400165void msm_gem_move_to_active(struct drm_gem_object *obj,
Rob Clarkbf6811f2013-09-01 13:25:09 -0400166 struct msm_gpu *gpu, bool write, uint32_t fence);
Rob Clark7198e6b2013-07-19 12:59:32 -0400167void msm_gem_move_to_inactive(struct drm_gem_object *obj);
168int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
169 struct timespec *timeout);
170int msm_gem_cpu_fini(struct drm_gem_object *obj);
Rob Clarkc8afe682013-06-26 12:44:06 -0400171void msm_gem_free_object(struct drm_gem_object *obj);
172int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
173 uint32_t size, uint32_t flags, uint32_t *handle);
174struct drm_gem_object *msm_gem_new(struct drm_device *dev,
175 uint32_t size, uint32_t flags);
Rob Clark05b84912013-09-28 11:28:35 -0400176struct drm_gem_object *msm_gem_import(struct drm_device *dev,
177 uint32_t size, struct sg_table *sgt);
Rob Clarkc8afe682013-06-26 12:44:06 -0400178
179struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
180const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
181struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
182 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
183struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
184 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
185
186struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
187
Rob Clarka3376e32013-08-30 13:02:15 -0400188int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
Rob Clarkc8afe682013-06-26 12:44:06 -0400189void __init hdmi_register(void);
190void __exit hdmi_unregister(void);
191
192#ifdef CONFIG_DEBUG_FS
193void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
194void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
195void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
196#endif
197
198void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
199 const char *dbgname);
200void msm_writel(u32 data, void __iomem *addr);
201u32 msm_readl(const void __iomem *addr);
202
203#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
204#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
205
Rob Clarkf816f272013-09-11 17:34:07 -0400206static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
207{
208 struct msm_drm_private *priv = dev->dev_private;
209 return priv->completed_fence >= fence;
210}
211
Rob Clarkc8afe682013-06-26 12:44:06 -0400212static inline int align_pitch(int width, int bpp)
213{
214 int bytespp = (bpp + 7) / 8;
215 /* adreno needs pitch aligned to 32 pixels: */
216 return bytespp * ALIGN(width, 32);
217}
218
219/* for the generated headers: */
220#define INVALID_IDX(idx) ({BUG(); 0;})
Rob Clark7198e6b2013-07-19 12:59:32 -0400221#define fui(x) ({BUG(); 0;})
222#define util_float_to_half(x) ({BUG(); 0;})
223
Rob Clarkc8afe682013-06-26 12:44:06 -0400224
225#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
226
227/* for conditionally setting boolean flag(s): */
228#define COND(bool, val) ((bool) ? (val) : 0)
229
Rob Clarkc8afe682013-06-26 12:44:06 -0400230
231#endif /* __MSM_DRV_H__ */