Dinh Nguyen | cfda590 | 2012-07-11 15:13:16 -0500 | [diff] [blame] | 1 | * Designware APB timer |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc" |
| 5 | - reg: physical base address of the controller and length of memory mapped |
| 6 | region. |
| 7 | - interrupts: IRQ line for the timer. |
Heiko Stuebner | a8b447f | 2013-06-04 11:37:36 +0200 | [diff] [blame^] | 8 | - either clocks+clock-names or clock-frequency properties |
| 9 | |
| 10 | Optional properties: |
| 11 | - clocks : list of clock specifiers, corresponding to entries in |
| 12 | the clock-names property; |
| 13 | - clock-names : should contain "timer" and "pclk" entries, matching entries |
| 14 | in the clocks property. |
Dinh Nguyen | cfda590 | 2012-07-11 15:13:16 -0500 | [diff] [blame] | 15 | - clock-frequency: The frequency in HZ of the timer. |
| 16 | - clock-freq: For backwards compatibility with picoxcell |
| 17 | |
Heiko Stuebner | a8b447f | 2013-06-04 11:37:36 +0200 | [diff] [blame^] | 18 | If using the clock specifiers, the pclk clock is optional, as not all |
| 19 | systems may use one. |
| 20 | |
| 21 | |
Dinh Nguyen | cfda590 | 2012-07-11 15:13:16 -0500 | [diff] [blame] | 22 | Example: |
| 23 | |
| 24 | timer1: timer@ffc09000 { |
| 25 | compatible = "snps,dw-apb-timer-sp"; |
| 26 | interrupts = <0 168 4>; |
| 27 | clock-frequency = <200000000>; |
| 28 | reg = <0xffc09000 0x1000>; |
| 29 | }; |
| 30 | |
| 31 | timer2: timer@ffd00000 { |
| 32 | compatible = "snps,dw-apb-timer-osc"; |
| 33 | interrupts = <0 169 4>; |
| 34 | clock-frequency = <200000000>; |
| 35 | reg = <0xffd00000 0x1000>; |
| 36 | }; |
Heiko Stuebner | a8b447f | 2013-06-04 11:37:36 +0200 | [diff] [blame^] | 37 | |
| 38 | timer3: timer@ffe00000 { |
| 39 | compatible = "snps,dw-apb-timer-osc"; |
| 40 | interrupts = <0 170 4>; |
| 41 | reg = <0xffe00000 0x1000>; |
| 42 | clocks = <&timer_clk>, <&timer_pclk>; |
| 43 | clock-names = "timer", "pclk"; |
| 44 | }; |