Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1 | /* QLogic qed NIC Driver |
| 2 | * Copyright (c) 2015 QLogic Corporation |
| 3 | * |
| 4 | * This software is available under the terms of the GNU General Public License |
| 5 | * (GPL) Version 2, available from the file COPYING in the main directory of |
| 6 | * this source tree. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/types.h> |
| 10 | #include <asm/byteorder.h> |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/dma-mapping.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/mutex.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/string.h> |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 20 | #include <linux/vmalloc.h> |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 21 | #include <linux/etherdevice.h> |
| 22 | #include <linux/qed/qed_chain.h> |
| 23 | #include <linux/qed/qed_if.h> |
| 24 | #include "qed.h" |
| 25 | #include "qed_cxt.h" |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 26 | #include "qed_dcbx.h" |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 27 | #include "qed_dev_api.h" |
| 28 | #include "qed_hsi.h" |
| 29 | #include "qed_hw.h" |
| 30 | #include "qed_init_ops.h" |
| 31 | #include "qed_int.h" |
| 32 | #include "qed_mcp.h" |
| 33 | #include "qed_reg_addr.h" |
| 34 | #include "qed_sp.h" |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 35 | #include "qed_sriov.h" |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 36 | #include "qed_vf.h" |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 37 | |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 38 | static spinlock_t qm_lock; |
| 39 | static bool qm_lock_init = false; |
| 40 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 41 | /* API common to all protocols */ |
Ram Amrani | c2035ee | 2016-03-02 20:26:00 +0200 | [diff] [blame] | 42 | enum BAR_ID { |
| 43 | BAR_ID_0, /* used for GRC */ |
| 44 | BAR_ID_1 /* Used for doorbells */ |
| 45 | }; |
| 46 | |
| 47 | static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, |
| 48 | enum BAR_ID bar_id) |
| 49 | { |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 50 | u32 bar_reg = (bar_id == BAR_ID_0 ? |
| 51 | PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); |
| 52 | u32 val; |
Ram Amrani | c2035ee | 2016-03-02 20:26:00 +0200 | [diff] [blame] | 53 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 54 | if (IS_VF(p_hwfn->cdev)) |
| 55 | return 1 << 17; |
| 56 | |
| 57 | val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); |
Ram Amrani | c2035ee | 2016-03-02 20:26:00 +0200 | [diff] [blame] | 58 | if (val) |
| 59 | return 1 << (val + 15); |
| 60 | |
| 61 | /* Old MFW initialized above registered only conditionally */ |
| 62 | if (p_hwfn->cdev->num_hwfns > 1) { |
| 63 | DP_INFO(p_hwfn, |
| 64 | "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); |
| 65 | return BAR_ID_0 ? 256 * 1024 : 512 * 1024; |
| 66 | } else { |
| 67 | DP_INFO(p_hwfn, |
| 68 | "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); |
| 69 | return 512 * 1024; |
| 70 | } |
| 71 | } |
| 72 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 73 | void qed_init_dp(struct qed_dev *cdev, |
| 74 | u32 dp_module, u8 dp_level) |
| 75 | { |
| 76 | u32 i; |
| 77 | |
| 78 | cdev->dp_level = dp_level; |
| 79 | cdev->dp_module = dp_module; |
| 80 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { |
| 81 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 82 | |
| 83 | p_hwfn->dp_level = dp_level; |
| 84 | p_hwfn->dp_module = dp_module; |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | void qed_init_struct(struct qed_dev *cdev) |
| 89 | { |
| 90 | u8 i; |
| 91 | |
| 92 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { |
| 93 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 94 | |
| 95 | p_hwfn->cdev = cdev; |
| 96 | p_hwfn->my_id = i; |
| 97 | p_hwfn->b_active = false; |
| 98 | |
| 99 | mutex_init(&p_hwfn->dmae_info.mutex); |
| 100 | } |
| 101 | |
| 102 | /* hwfn 0 is always active */ |
| 103 | cdev->hwfns[0].b_active = true; |
| 104 | |
| 105 | /* set the default cache alignment to 128 */ |
| 106 | cdev->cache_shift = 7; |
| 107 | } |
| 108 | |
| 109 | static void qed_qm_info_free(struct qed_hwfn *p_hwfn) |
| 110 | { |
| 111 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; |
| 112 | |
| 113 | kfree(qm_info->qm_pq_params); |
| 114 | qm_info->qm_pq_params = NULL; |
| 115 | kfree(qm_info->qm_vport_params); |
| 116 | qm_info->qm_vport_params = NULL; |
| 117 | kfree(qm_info->qm_port_params); |
| 118 | qm_info->qm_port_params = NULL; |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 119 | kfree(qm_info->wfq_data); |
| 120 | qm_info->wfq_data = NULL; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | void qed_resc_free(struct qed_dev *cdev) |
| 124 | { |
| 125 | int i; |
| 126 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 127 | if (IS_VF(cdev)) |
| 128 | return; |
| 129 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 130 | kfree(cdev->fw_data); |
| 131 | cdev->fw_data = NULL; |
| 132 | |
| 133 | kfree(cdev->reset_stats); |
| 134 | |
| 135 | for_each_hwfn(cdev, i) { |
| 136 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 137 | |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 138 | kfree(p_hwfn->p_tx_cids); |
| 139 | p_hwfn->p_tx_cids = NULL; |
| 140 | kfree(p_hwfn->p_rx_cids); |
| 141 | p_hwfn->p_rx_cids = NULL; |
| 142 | } |
| 143 | |
| 144 | for_each_hwfn(cdev, i) { |
| 145 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 146 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 147 | qed_cxt_mngr_free(p_hwfn); |
| 148 | qed_qm_info_free(p_hwfn); |
| 149 | qed_spq_free(p_hwfn); |
| 150 | qed_eq_free(p_hwfn, p_hwfn->p_eq); |
| 151 | qed_consq_free(p_hwfn, p_hwfn->p_consq); |
| 152 | qed_int_free(p_hwfn); |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 153 | qed_iov_free(p_hwfn); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 154 | qed_dmae_info_free(p_hwfn); |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 155 | qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 156 | } |
| 157 | } |
| 158 | |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 159 | static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 160 | { |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 161 | u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 162 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; |
| 163 | struct init_qm_port_params *p_qm_port; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 164 | u16 num_pqs, multi_cos_tcs = 1; |
Yuval Mintz | cc3d5eb | 2016-05-26 11:01:21 +0300 | [diff] [blame] | 165 | u8 pf_wfq = qm_info->pf_wfq; |
| 166 | u32 pf_rl = qm_info->pf_rl; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 167 | u16 num_vfs = 0; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 168 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 169 | #ifdef CONFIG_QED_SRIOV |
| 170 | if (p_hwfn->cdev->p_iov_info) |
| 171 | num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; |
| 172 | #endif |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 173 | memset(qm_info, 0, sizeof(*qm_info)); |
| 174 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 175 | num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 176 | num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); |
| 177 | |
| 178 | /* Sanity checking that setup requires legal number of resources */ |
| 179 | if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { |
| 180 | DP_ERR(p_hwfn, |
| 181 | "Need too many Physical queues - 0x%04x when only %04x are available\n", |
| 182 | num_pqs, RESC_NUM(p_hwfn, QED_PQ)); |
| 183 | return -EINVAL; |
| 184 | } |
| 185 | |
| 186 | /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. |
| 187 | */ |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 188 | qm_info->qm_pq_params = kcalloc(num_pqs, |
| 189 | sizeof(struct init_qm_pq_params), |
| 190 | b_sleepable ? GFP_KERNEL : GFP_ATOMIC); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 191 | if (!qm_info->qm_pq_params) |
| 192 | goto alloc_err; |
| 193 | |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 194 | qm_info->qm_vport_params = kcalloc(num_vports, |
| 195 | sizeof(struct init_qm_vport_params), |
| 196 | b_sleepable ? GFP_KERNEL |
| 197 | : GFP_ATOMIC); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 198 | if (!qm_info->qm_vport_params) |
| 199 | goto alloc_err; |
| 200 | |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 201 | qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, |
| 202 | sizeof(struct init_qm_port_params), |
| 203 | b_sleepable ? GFP_KERNEL |
| 204 | : GFP_ATOMIC); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 205 | if (!qm_info->qm_port_params) |
| 206 | goto alloc_err; |
| 207 | |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 208 | qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), |
| 209 | b_sleepable ? GFP_KERNEL : GFP_ATOMIC); |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 210 | if (!qm_info->wfq_data) |
| 211 | goto alloc_err; |
| 212 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 213 | vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); |
| 214 | |
| 215 | /* First init per-TC PQs */ |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 216 | for (i = 0; i < multi_cos_tcs; i++) { |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 217 | struct init_qm_pq_params *params = |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 218 | &qm_info->qm_pq_params[curr_queue++]; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 219 | |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 220 | if (p_hwfn->hw_info.personality == QED_PCI_ETH) { |
| 221 | params->vport_id = vport_id; |
| 222 | params->tc_id = p_hwfn->hw_info.non_offload_tc; |
| 223 | params->wrr_group = 1; |
| 224 | } else { |
| 225 | params->vport_id = vport_id; |
| 226 | params->tc_id = p_hwfn->hw_info.offload_tc; |
| 227 | params->wrr_group = 1; |
| 228 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | /* Then init pure-LB PQ */ |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 232 | qm_info->pure_lb_pq = curr_queue; |
| 233 | qm_info->qm_pq_params[curr_queue].vport_id = |
| 234 | (u8) RESC_START(p_hwfn, QED_VPORT); |
| 235 | qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; |
| 236 | qm_info->qm_pq_params[curr_queue].wrr_group = 1; |
| 237 | curr_queue++; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 238 | |
| 239 | qm_info->offload_pq = 0; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 240 | /* Then init per-VF PQs */ |
| 241 | vf_offset = curr_queue; |
| 242 | for (i = 0; i < num_vfs; i++) { |
| 243 | /* First vport is used by the PF */ |
| 244 | qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; |
| 245 | qm_info->qm_pq_params[curr_queue].tc_id = |
| 246 | p_hwfn->hw_info.non_offload_tc; |
| 247 | qm_info->qm_pq_params[curr_queue].wrr_group = 1; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 248 | qm_info->qm_pq_params[curr_queue].rl_valid = 1; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 249 | curr_queue++; |
| 250 | } |
| 251 | |
| 252 | qm_info->vf_queues_offset = vf_offset; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 253 | qm_info->num_pqs = num_pqs; |
| 254 | qm_info->num_vports = num_vports; |
| 255 | |
| 256 | /* Initialize qm port parameters */ |
| 257 | num_ports = p_hwfn->cdev->num_ports_in_engines; |
| 258 | for (i = 0; i < num_ports; i++) { |
| 259 | p_qm_port = &qm_info->qm_port_params[i]; |
| 260 | p_qm_port->active = 1; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 261 | if (num_ports == 4) |
| 262 | p_qm_port->active_phys_tcs = 0x7; |
| 263 | else |
| 264 | p_qm_port->active_phys_tcs = 0x9f; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 265 | p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; |
| 266 | p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; |
| 267 | } |
| 268 | |
| 269 | qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; |
| 270 | |
| 271 | qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); |
| 272 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 273 | qm_info->num_vf_pqs = num_vfs; |
| 274 | qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 275 | |
Manish Chopra | a64b02d | 2016-04-26 10:56:10 -0400 | [diff] [blame] | 276 | for (i = 0; i < qm_info->num_vports; i++) |
| 277 | qm_info->qm_vport_params[i].vport_wfq = 1; |
| 278 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 279 | qm_info->vport_rl_en = 1; |
Manish Chopra | a64b02d | 2016-04-26 10:56:10 -0400 | [diff] [blame] | 280 | qm_info->vport_wfq_en = 1; |
Yuval Mintz | cc3d5eb | 2016-05-26 11:01:21 +0300 | [diff] [blame] | 281 | qm_info->pf_rl = pf_rl; |
| 282 | qm_info->pf_wfq = pf_wfq; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 283 | |
| 284 | return 0; |
| 285 | |
| 286 | alloc_err: |
| 287 | DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 288 | qed_qm_info_free(p_hwfn); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 289 | return -ENOMEM; |
| 290 | } |
| 291 | |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 292 | /* This function reconfigures the QM pf on the fly. |
| 293 | * For this purpose we: |
| 294 | * 1. reconfigure the QM database |
| 295 | * 2. set new values to runtime arrat |
| 296 | * 3. send an sdm_qm_cmd through the rbc interface to stop the QM |
| 297 | * 4. activate init tool in QM_PF stage |
| 298 | * 5. send an sdm_qm_cmd through rbc interface to release the QM |
| 299 | */ |
| 300 | int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
| 301 | { |
| 302 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; |
| 303 | bool b_rc; |
| 304 | int rc; |
| 305 | |
| 306 | /* qm_info is allocated in qed_init_qm_info() which is already called |
| 307 | * from qed_resc_alloc() or previous call of qed_qm_reconf(). |
| 308 | * The allocated size may change each init, so we free it before next |
| 309 | * allocation. |
| 310 | */ |
| 311 | qed_qm_info_free(p_hwfn); |
| 312 | |
| 313 | /* initialize qed's qm data structure */ |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 314 | rc = qed_init_qm_info(p_hwfn, false); |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 315 | if (rc) |
| 316 | return rc; |
| 317 | |
| 318 | /* stop PF's qm queues */ |
| 319 | spin_lock_bh(&qm_lock); |
| 320 | b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, |
| 321 | qm_info->start_pq, qm_info->num_pqs); |
| 322 | spin_unlock_bh(&qm_lock); |
| 323 | if (!b_rc) |
| 324 | return -EINVAL; |
| 325 | |
| 326 | /* clear the QM_PF runtime phase leftovers from previous init */ |
| 327 | qed_init_clear_rt_data(p_hwfn); |
| 328 | |
| 329 | /* prepare QM portion of runtime array */ |
| 330 | qed_qm_init_pf(p_hwfn); |
| 331 | |
| 332 | /* activate init tool on runtime array */ |
| 333 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, |
| 334 | p_hwfn->hw_info.hw_mode); |
| 335 | if (rc) |
| 336 | return rc; |
| 337 | |
| 338 | /* start PF's qm queues */ |
| 339 | spin_lock_bh(&qm_lock); |
| 340 | b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, |
| 341 | qm_info->start_pq, qm_info->num_pqs); |
| 342 | spin_unlock_bh(&qm_lock); |
| 343 | if (!b_rc) |
| 344 | return -EINVAL; |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 349 | int qed_resc_alloc(struct qed_dev *cdev) |
| 350 | { |
| 351 | struct qed_consq *p_consq; |
| 352 | struct qed_eq *p_eq; |
| 353 | int i, rc = 0; |
| 354 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 355 | if (IS_VF(cdev)) |
| 356 | return rc; |
| 357 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 358 | cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); |
| 359 | if (!cdev->fw_data) |
| 360 | return -ENOMEM; |
| 361 | |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 362 | /* Allocate Memory for the Queue->CID mapping */ |
| 363 | for_each_hwfn(cdev, i) { |
| 364 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 365 | int tx_size = sizeof(struct qed_hw_cid_data) * |
| 366 | RESC_NUM(p_hwfn, QED_L2_QUEUE); |
| 367 | int rx_size = sizeof(struct qed_hw_cid_data) * |
| 368 | RESC_NUM(p_hwfn, QED_L2_QUEUE); |
| 369 | |
| 370 | p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); |
| 371 | if (!p_hwfn->p_tx_cids) { |
| 372 | DP_NOTICE(p_hwfn, |
| 373 | "Failed to allocate memory for Tx Cids\n"); |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 374 | rc = -ENOMEM; |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 375 | goto alloc_err; |
| 376 | } |
| 377 | |
| 378 | p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); |
| 379 | if (!p_hwfn->p_rx_cids) { |
| 380 | DP_NOTICE(p_hwfn, |
| 381 | "Failed to allocate memory for Rx Cids\n"); |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 382 | rc = -ENOMEM; |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 383 | goto alloc_err; |
| 384 | } |
| 385 | } |
| 386 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 387 | for_each_hwfn(cdev, i) { |
| 388 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 389 | |
| 390 | /* First allocate the context manager structure */ |
| 391 | rc = qed_cxt_mngr_alloc(p_hwfn); |
| 392 | if (rc) |
| 393 | goto alloc_err; |
| 394 | |
| 395 | /* Set the HW cid/tid numbers (in the contest manager) |
| 396 | * Must be done prior to any further computations. |
| 397 | */ |
| 398 | rc = qed_cxt_set_pf_params(p_hwfn); |
| 399 | if (rc) |
| 400 | goto alloc_err; |
| 401 | |
| 402 | /* Prepare and process QM requirements */ |
Sudarsana Reddy Kalluru | 7952929 | 2016-05-26 11:01:20 +0300 | [diff] [blame] | 403 | rc = qed_init_qm_info(p_hwfn, true); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 404 | if (rc) |
| 405 | goto alloc_err; |
| 406 | |
| 407 | /* Compute the ILT client partition */ |
| 408 | rc = qed_cxt_cfg_ilt_compute(p_hwfn); |
| 409 | if (rc) |
| 410 | goto alloc_err; |
| 411 | |
| 412 | /* CID map / ILT shadow table / T2 |
| 413 | * The talbes sizes are determined by the computations above |
| 414 | */ |
| 415 | rc = qed_cxt_tables_alloc(p_hwfn); |
| 416 | if (rc) |
| 417 | goto alloc_err; |
| 418 | |
| 419 | /* SPQ, must follow ILT because initializes SPQ context */ |
| 420 | rc = qed_spq_alloc(p_hwfn); |
| 421 | if (rc) |
| 422 | goto alloc_err; |
| 423 | |
| 424 | /* SP status block allocation */ |
| 425 | p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, |
| 426 | RESERVED_PTT_DPC); |
| 427 | |
| 428 | rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); |
| 429 | if (rc) |
| 430 | goto alloc_err; |
| 431 | |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 432 | rc = qed_iov_alloc(p_hwfn); |
| 433 | if (rc) |
| 434 | goto alloc_err; |
| 435 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 436 | /* EQ */ |
| 437 | p_eq = qed_eq_alloc(p_hwfn, 256); |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 438 | if (!p_eq) { |
| 439 | rc = -ENOMEM; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 440 | goto alloc_err; |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 441 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 442 | p_hwfn->p_eq = p_eq; |
| 443 | |
| 444 | p_consq = qed_consq_alloc(p_hwfn); |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 445 | if (!p_consq) { |
| 446 | rc = -ENOMEM; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 447 | goto alloc_err; |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 448 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 449 | p_hwfn->p_consq = p_consq; |
| 450 | |
| 451 | /* DMA info initialization */ |
| 452 | rc = qed_dmae_info_alloc(p_hwfn); |
| 453 | if (rc) { |
| 454 | DP_NOTICE(p_hwfn, |
| 455 | "Failed to allocate memory for dmae_info structure\n"); |
| 456 | goto alloc_err; |
| 457 | } |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 458 | |
| 459 | /* DCBX initialization */ |
| 460 | rc = qed_dcbx_info_alloc(p_hwfn); |
| 461 | if (rc) { |
| 462 | DP_NOTICE(p_hwfn, |
| 463 | "Failed to allocate memory for dcbx structure\n"); |
| 464 | goto alloc_err; |
| 465 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 466 | } |
| 467 | |
| 468 | cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); |
| 469 | if (!cdev->reset_stats) { |
| 470 | DP_NOTICE(cdev, "Failed to allocate reset statistics\n"); |
Dan Carpenter | 9b15acb | 2015-11-05 11:41:28 +0300 | [diff] [blame] | 471 | rc = -ENOMEM; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 472 | goto alloc_err; |
| 473 | } |
| 474 | |
| 475 | return 0; |
| 476 | |
| 477 | alloc_err: |
| 478 | qed_resc_free(cdev); |
| 479 | return rc; |
| 480 | } |
| 481 | |
| 482 | void qed_resc_setup(struct qed_dev *cdev) |
| 483 | { |
| 484 | int i; |
| 485 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 486 | if (IS_VF(cdev)) |
| 487 | return; |
| 488 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 489 | for_each_hwfn(cdev, i) { |
| 490 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 491 | |
| 492 | qed_cxt_mngr_setup(p_hwfn); |
| 493 | qed_spq_setup(p_hwfn); |
| 494 | qed_eq_setup(p_hwfn, p_hwfn->p_eq); |
| 495 | qed_consq_setup(p_hwfn, p_hwfn->p_consq); |
| 496 | |
| 497 | /* Read shadow of current MFW mailbox */ |
| 498 | qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); |
| 499 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, |
| 500 | p_hwfn->mcp_info->mfw_mb_cur, |
| 501 | p_hwfn->mcp_info->mfw_mb_length); |
| 502 | |
| 503 | qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 504 | |
| 505 | qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 506 | } |
| 507 | } |
| 508 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 509 | #define FINAL_CLEANUP_POLL_CNT (100) |
| 510 | #define FINAL_CLEANUP_POLL_TIME (10) |
| 511 | int qed_final_cleanup(struct qed_hwfn *p_hwfn, |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 512 | struct qed_ptt *p_ptt, u16 id, bool is_vf) |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 513 | { |
| 514 | u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; |
| 515 | int rc = -EBUSY; |
| 516 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 517 | addr = GTT_BAR0_MAP_REG_USDM_RAM + |
| 518 | USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 519 | |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 520 | if (is_vf) |
| 521 | id += 0x10; |
| 522 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 523 | command |= X_FINAL_CLEANUP_AGG_INT << |
| 524 | SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; |
| 525 | command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; |
| 526 | command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; |
| 527 | command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 528 | |
| 529 | /* Make sure notification is not set before initiating final cleanup */ |
| 530 | if (REG_RD(p_hwfn, addr)) { |
| 531 | DP_NOTICE( |
| 532 | p_hwfn, |
| 533 | "Unexpected; Found final cleanup notification before initiating final cleanup\n"); |
| 534 | REG_WR(p_hwfn, addr, 0); |
| 535 | } |
| 536 | |
| 537 | DP_VERBOSE(p_hwfn, QED_MSG_IOV, |
| 538 | "Sending final cleanup for PFVF[%d] [Command %08x\n]", |
| 539 | id, command); |
| 540 | |
| 541 | qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); |
| 542 | |
| 543 | /* Poll until completion */ |
| 544 | while (!REG_RD(p_hwfn, addr) && count--) |
| 545 | msleep(FINAL_CLEANUP_POLL_TIME); |
| 546 | |
| 547 | if (REG_RD(p_hwfn, addr)) |
| 548 | rc = 0; |
| 549 | else |
| 550 | DP_NOTICE(p_hwfn, |
| 551 | "Failed to receive FW final cleanup notification\n"); |
| 552 | |
| 553 | /* Cleanup afterwards */ |
| 554 | REG_WR(p_hwfn, addr, 0); |
| 555 | |
| 556 | return rc; |
| 557 | } |
| 558 | |
| 559 | static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) |
| 560 | { |
| 561 | int hw_mode = 0; |
| 562 | |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 563 | hw_mode = (1 << MODE_BB_B0); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 564 | |
| 565 | switch (p_hwfn->cdev->num_ports_in_engines) { |
| 566 | case 1: |
| 567 | hw_mode |= 1 << MODE_PORTS_PER_ENG_1; |
| 568 | break; |
| 569 | case 2: |
| 570 | hw_mode |= 1 << MODE_PORTS_PER_ENG_2; |
| 571 | break; |
| 572 | case 4: |
| 573 | hw_mode |= 1 << MODE_PORTS_PER_ENG_4; |
| 574 | break; |
| 575 | default: |
| 576 | DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", |
| 577 | p_hwfn->cdev->num_ports_in_engines); |
| 578 | return; |
| 579 | } |
| 580 | |
| 581 | switch (p_hwfn->cdev->mf_mode) { |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 582 | case QED_MF_DEFAULT: |
| 583 | case QED_MF_NPAR: |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 584 | hw_mode |= 1 << MODE_MF_SI; |
| 585 | break; |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 586 | case QED_MF_OVLAN: |
| 587 | hw_mode |= 1 << MODE_MF_SD; |
| 588 | break; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 589 | default: |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 590 | DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); |
| 591 | hw_mode |= 1 << MODE_MF_SI; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 592 | } |
| 593 | |
| 594 | hw_mode |= 1 << MODE_ASIC; |
| 595 | |
Yuval Mintz | 1af9dcf | 2016-05-26 11:01:22 +0300 | [diff] [blame] | 596 | if (p_hwfn->cdev->num_hwfns > 1) |
| 597 | hw_mode |= 1 << MODE_100G; |
| 598 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 599 | p_hwfn->hw_info.hw_mode = hw_mode; |
Yuval Mintz | 1af9dcf | 2016-05-26 11:01:22 +0300 | [diff] [blame] | 600 | |
| 601 | DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), |
| 602 | "Configuring function for hw_mode: 0x%08x\n", |
| 603 | p_hwfn->hw_info.hw_mode); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 604 | } |
| 605 | |
| 606 | /* Init run time data for all PFs on an engine. */ |
| 607 | static void qed_init_cau_rt_data(struct qed_dev *cdev) |
| 608 | { |
| 609 | u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; |
| 610 | int i, sb_id; |
| 611 | |
| 612 | for_each_hwfn(cdev, i) { |
| 613 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 614 | struct qed_igu_info *p_igu_info; |
| 615 | struct qed_igu_block *p_block; |
| 616 | struct cau_sb_entry sb_entry; |
| 617 | |
| 618 | p_igu_info = p_hwfn->hw_info.p_igu_info; |
| 619 | |
| 620 | for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); |
| 621 | sb_id++) { |
| 622 | p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; |
| 623 | if (!p_block->is_pf) |
| 624 | continue; |
| 625 | |
| 626 | qed_init_cau_sb_entry(p_hwfn, &sb_entry, |
| 627 | p_block->function_id, |
| 628 | 0, 0); |
| 629 | STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, |
| 630 | sb_entry); |
| 631 | } |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | static int qed_hw_init_common(struct qed_hwfn *p_hwfn, |
| 636 | struct qed_ptt *p_ptt, |
| 637 | int hw_mode) |
| 638 | { |
| 639 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; |
| 640 | struct qed_qm_common_rt_init_params params; |
| 641 | struct qed_dev *cdev = p_hwfn->cdev; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 642 | u32 concrete_fid; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 643 | int rc = 0; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 644 | u8 vf_id; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 645 | |
| 646 | qed_init_cau_rt_data(cdev); |
| 647 | |
| 648 | /* Program GTT windows */ |
| 649 | qed_gtt_init(p_hwfn); |
| 650 | |
| 651 | if (p_hwfn->mcp_info) { |
| 652 | if (p_hwfn->mcp_info->func_info.bandwidth_max) |
| 653 | qm_info->pf_rl_en = 1; |
| 654 | if (p_hwfn->mcp_info->func_info.bandwidth_min) |
| 655 | qm_info->pf_wfq_en = 1; |
| 656 | } |
| 657 | |
| 658 | memset(¶ms, 0, sizeof(params)); |
| 659 | params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; |
| 660 | params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; |
| 661 | params.pf_rl_en = qm_info->pf_rl_en; |
| 662 | params.pf_wfq_en = qm_info->pf_wfq_en; |
| 663 | params.vport_rl_en = qm_info->vport_rl_en; |
| 664 | params.vport_wfq_en = qm_info->vport_wfq_en; |
| 665 | params.port_params = qm_info->qm_port_params; |
| 666 | |
| 667 | qed_qm_common_rt_init(p_hwfn, ¶ms); |
| 668 | |
| 669 | qed_cxt_hw_init_common(p_hwfn); |
| 670 | |
| 671 | /* Close gate from NIG to BRB/Storm; By default they are open, but |
| 672 | * we close them to prevent NIG from passing data to reset blocks. |
| 673 | * Should have been done in the ENGINE phase, but init-tool lacks |
| 674 | * proper port-pretend capabilities. |
| 675 | */ |
| 676 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); |
| 677 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); |
| 678 | qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); |
| 679 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); |
| 680 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); |
| 681 | qed_port_unpretend(p_hwfn, p_ptt); |
| 682 | |
| 683 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); |
| 684 | if (rc != 0) |
| 685 | return rc; |
| 686 | |
| 687 | qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); |
| 688 | qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); |
| 689 | |
| 690 | /* Disable relaxed ordering in the PCI config space */ |
| 691 | qed_wr(p_hwfn, p_ptt, 0x20b4, |
| 692 | qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10); |
| 693 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 694 | for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { |
| 695 | concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); |
| 696 | qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); |
| 697 | qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); |
| 698 | } |
| 699 | /* pretend to original PF */ |
| 700 | qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); |
| 701 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 702 | return rc; |
| 703 | } |
| 704 | |
| 705 | static int qed_hw_init_port(struct qed_hwfn *p_hwfn, |
| 706 | struct qed_ptt *p_ptt, |
| 707 | int hw_mode) |
| 708 | { |
| 709 | int rc = 0; |
| 710 | |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 711 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); |
| 712 | if (rc != 0) |
| 713 | return rc; |
| 714 | |
| 715 | if (hw_mode & (1 << MODE_MF_SI)) { |
| 716 | u8 pf_id = 0; |
| 717 | |
| 718 | if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) { |
| 719 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, |
| 720 | "PF[%08x] is first eth on engine\n", pf_id); |
| 721 | |
| 722 | /* We should have configured BIT for ppfid, i.e., the |
| 723 | * relative function number in the port. But there's a |
| 724 | * bug in LLH in BB where the ppfid is actually engine |
| 725 | * based, so we need to take this into account. |
| 726 | */ |
| 727 | qed_wr(p_hwfn, p_ptt, |
| 728 | NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id); |
| 729 | } |
| 730 | |
| 731 | /* Take the protocol-based hit vector if there is a hit, |
| 732 | * otherwise take the other vector. |
| 733 | */ |
| 734 | qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2); |
| 735 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 736 | return rc; |
| 737 | } |
| 738 | |
| 739 | static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, |
| 740 | struct qed_ptt *p_ptt, |
Manish Chopra | 464f664 | 2016-04-14 01:38:29 -0400 | [diff] [blame] | 741 | struct qed_tunn_start_params *p_tunn, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 742 | int hw_mode, |
| 743 | bool b_hw_start, |
| 744 | enum qed_int_mode int_mode, |
| 745 | bool allow_npar_tx_switch) |
| 746 | { |
| 747 | u8 rel_pf_id = p_hwfn->rel_pf_id; |
| 748 | int rc = 0; |
| 749 | |
| 750 | if (p_hwfn->mcp_info) { |
| 751 | struct qed_mcp_function_info *p_info; |
| 752 | |
| 753 | p_info = &p_hwfn->mcp_info->func_info; |
| 754 | if (p_info->bandwidth_min) |
| 755 | p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; |
| 756 | |
| 757 | /* Update rate limit once we'll actually have a link */ |
Manish Chopra | 4b01e51 | 2016-04-26 10:56:09 -0400 | [diff] [blame] | 758 | p_hwfn->qm_info.pf_rl = 100000; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | qed_cxt_hw_init_pf(p_hwfn); |
| 762 | |
| 763 | qed_int_igu_init_rt(p_hwfn); |
| 764 | |
| 765 | /* Set VLAN in NIG if needed */ |
| 766 | if (hw_mode & (1 << MODE_MF_SD)) { |
| 767 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); |
| 768 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); |
| 769 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, |
| 770 | p_hwfn->hw_info.ovlan); |
| 771 | } |
| 772 | |
| 773 | /* Enable classification by MAC if needed */ |
Dan Carpenter | 87aec47 | 2015-11-04 16:29:11 +0300 | [diff] [blame] | 774 | if (hw_mode & (1 << MODE_MF_SI)) { |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 775 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, |
| 776 | "Configuring TAGMAC_CLS_TYPE\n"); |
| 777 | STORE_RT_REG(p_hwfn, |
| 778 | NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); |
| 779 | } |
| 780 | |
| 781 | /* Protocl Configuration */ |
| 782 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0); |
| 783 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); |
| 784 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); |
| 785 | |
| 786 | /* Cleanup chip from previous driver if such remains exist */ |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 787 | rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 788 | if (rc != 0) |
| 789 | return rc; |
| 790 | |
| 791 | /* PF Init sequence */ |
| 792 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); |
| 793 | if (rc) |
| 794 | return rc; |
| 795 | |
| 796 | /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ |
| 797 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); |
| 798 | if (rc) |
| 799 | return rc; |
| 800 | |
| 801 | /* Pure runtime initializations - directly to the HW */ |
| 802 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); |
| 803 | |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 804 | if (hw_mode & (1 << MODE_MF_SI)) { |
| 805 | u8 pf_id = 0; |
| 806 | u32 val; |
| 807 | |
| 808 | if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) { |
| 809 | if (p_hwfn->rel_pf_id == pf_id) { |
| 810 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, |
| 811 | "PF[%d] is first ETH on engine\n", |
| 812 | pf_id); |
| 813 | val = 1; |
| 814 | } |
| 815 | qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val); |
| 816 | } |
| 817 | } |
| 818 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 819 | if (b_hw_start) { |
| 820 | /* enable interrupts */ |
| 821 | qed_int_igu_enable(p_hwfn, p_ptt, int_mode); |
| 822 | |
| 823 | /* send function start command */ |
Yuval Mintz | 831bfb0e | 2016-05-11 16:36:25 +0300 | [diff] [blame] | 824 | rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, |
| 825 | allow_npar_tx_switch); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 826 | if (rc) |
| 827 | DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); |
| 828 | } |
| 829 | return rc; |
| 830 | } |
| 831 | |
| 832 | static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, |
| 833 | struct qed_ptt *p_ptt, |
| 834 | u8 enable) |
| 835 | { |
| 836 | u32 delay_idx = 0, val, set_val = enable ? 1 : 0; |
| 837 | |
| 838 | /* Change PF in PXP */ |
| 839 | qed_wr(p_hwfn, p_ptt, |
| 840 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); |
| 841 | |
| 842 | /* wait until value is set - try for 1 second every 50us */ |
| 843 | for (delay_idx = 0; delay_idx < 20000; delay_idx++) { |
| 844 | val = qed_rd(p_hwfn, p_ptt, |
| 845 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); |
| 846 | if (val == set_val) |
| 847 | break; |
| 848 | |
| 849 | usleep_range(50, 60); |
| 850 | } |
| 851 | |
| 852 | if (val != set_val) { |
| 853 | DP_NOTICE(p_hwfn, |
| 854 | "PFID_ENABLE_MASTER wasn't changed after a second\n"); |
| 855 | return -EAGAIN; |
| 856 | } |
| 857 | |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, |
| 862 | struct qed_ptt *p_main_ptt) |
| 863 | { |
| 864 | /* Read shadow of current MFW mailbox */ |
| 865 | qed_mcp_read_mb(p_hwfn, p_main_ptt); |
| 866 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, |
| 867 | p_hwfn->mcp_info->mfw_mb_cur, |
| 868 | p_hwfn->mcp_info->mfw_mb_length); |
| 869 | } |
| 870 | |
| 871 | int qed_hw_init(struct qed_dev *cdev, |
Manish Chopra | 464f664 | 2016-04-14 01:38:29 -0400 | [diff] [blame] | 872 | struct qed_tunn_start_params *p_tunn, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 873 | bool b_hw_start, |
| 874 | enum qed_int_mode int_mode, |
| 875 | bool allow_npar_tx_switch, |
| 876 | const u8 *bin_fw_data) |
| 877 | { |
Yuval Mintz | 86622ee | 2016-03-02 20:26:02 +0200 | [diff] [blame] | 878 | u32 load_code, param; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 879 | int rc, mfw_rc, i; |
| 880 | |
Sudarsana Reddy Kalluru | bb13ace | 2016-05-26 11:01:23 +0300 | [diff] [blame] | 881 | if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { |
| 882 | DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); |
| 883 | return -EINVAL; |
| 884 | } |
| 885 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 886 | if (IS_PF(cdev)) { |
| 887 | rc = qed_init_fw_data(cdev, bin_fw_data); |
| 888 | if (rc != 0) |
| 889 | return rc; |
| 890 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 891 | |
| 892 | for_each_hwfn(cdev, i) { |
| 893 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 894 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 895 | if (IS_VF(cdev)) { |
| 896 | p_hwfn->b_int_enabled = 1; |
| 897 | continue; |
| 898 | } |
| 899 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 900 | /* Enable DMAE in PXP */ |
| 901 | rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); |
| 902 | |
| 903 | qed_calc_hw_mode(p_hwfn); |
| 904 | |
| 905 | rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, |
| 906 | &load_code); |
| 907 | if (rc) { |
| 908 | DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); |
| 909 | return rc; |
| 910 | } |
| 911 | |
| 912 | qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); |
| 913 | |
| 914 | DP_VERBOSE(p_hwfn, QED_MSG_SP, |
| 915 | "Load request was sent. Resp:0x%x, Load code: 0x%x\n", |
| 916 | rc, load_code); |
| 917 | |
| 918 | p_hwfn->first_on_engine = (load_code == |
| 919 | FW_MSG_CODE_DRV_LOAD_ENGINE); |
| 920 | |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 921 | if (!qm_lock_init) { |
| 922 | spin_lock_init(&qm_lock); |
| 923 | qm_lock_init = true; |
| 924 | } |
| 925 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 926 | switch (load_code) { |
| 927 | case FW_MSG_CODE_DRV_LOAD_ENGINE: |
| 928 | rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, |
| 929 | p_hwfn->hw_info.hw_mode); |
| 930 | if (rc) |
| 931 | break; |
| 932 | /* Fall into */ |
| 933 | case FW_MSG_CODE_DRV_LOAD_PORT: |
| 934 | rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, |
| 935 | p_hwfn->hw_info.hw_mode); |
| 936 | if (rc) |
| 937 | break; |
| 938 | |
| 939 | /* Fall into */ |
| 940 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: |
| 941 | rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, |
Manish Chopra | 464f664 | 2016-04-14 01:38:29 -0400 | [diff] [blame] | 942 | p_tunn, p_hwfn->hw_info.hw_mode, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 943 | b_hw_start, int_mode, |
| 944 | allow_npar_tx_switch); |
| 945 | break; |
| 946 | default: |
| 947 | rc = -EINVAL; |
| 948 | break; |
| 949 | } |
| 950 | |
| 951 | if (rc) |
| 952 | DP_NOTICE(p_hwfn, |
| 953 | "init phase failed for loadcode 0x%x (rc %d)\n", |
| 954 | load_code, rc); |
| 955 | |
| 956 | /* ACK mfw regardless of success or failure of initialization */ |
| 957 | mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, |
| 958 | DRV_MSG_CODE_LOAD_DONE, |
| 959 | 0, &load_code, ¶m); |
| 960 | if (rc) |
| 961 | return rc; |
| 962 | if (mfw_rc) { |
| 963 | DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); |
| 964 | return mfw_rc; |
| 965 | } |
| 966 | |
Sudarsana Reddy Kalluru | 39651ab | 2016-05-17 06:44:26 -0400 | [diff] [blame] | 967 | /* send DCBX attention request command */ |
| 968 | DP_VERBOSE(p_hwfn, |
| 969 | QED_MSG_DCB, |
| 970 | "sending phony dcbx set command to trigger DCBx attention handling\n"); |
| 971 | mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, |
| 972 | DRV_MSG_CODE_SET_DCBX, |
| 973 | 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, |
| 974 | &load_code, ¶m); |
| 975 | if (mfw_rc) { |
| 976 | DP_NOTICE(p_hwfn, |
| 977 | "Failed to send DCBX attention request\n"); |
| 978 | return mfw_rc; |
| 979 | } |
| 980 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 981 | p_hwfn->hw_init_done = true; |
| 982 | } |
| 983 | |
| 984 | return 0; |
| 985 | } |
| 986 | |
| 987 | #define QED_HW_STOP_RETRY_LIMIT (10) |
Yuval Mintz | 8c925c4 | 2016-03-02 20:26:03 +0200 | [diff] [blame] | 988 | static inline void qed_hw_timers_stop(struct qed_dev *cdev, |
| 989 | struct qed_hwfn *p_hwfn, |
| 990 | struct qed_ptt *p_ptt) |
| 991 | { |
| 992 | int i; |
| 993 | |
| 994 | /* close timers */ |
| 995 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); |
| 996 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); |
| 997 | |
| 998 | for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { |
| 999 | if ((!qed_rd(p_hwfn, p_ptt, |
| 1000 | TM_REG_PF_SCAN_ACTIVE_CONN)) && |
| 1001 | (!qed_rd(p_hwfn, p_ptt, |
| 1002 | TM_REG_PF_SCAN_ACTIVE_TASK))) |
| 1003 | break; |
| 1004 | |
| 1005 | /* Dependent on number of connection/tasks, possibly |
| 1006 | * 1ms sleep is required between polls |
| 1007 | */ |
| 1008 | usleep_range(1000, 2000); |
| 1009 | } |
| 1010 | |
| 1011 | if (i < QED_HW_STOP_RETRY_LIMIT) |
| 1012 | return; |
| 1013 | |
| 1014 | DP_NOTICE(p_hwfn, |
| 1015 | "Timers linear scans are not over [Connection %02x Tasks %02x]\n", |
| 1016 | (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), |
| 1017 | (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); |
| 1018 | } |
| 1019 | |
| 1020 | void qed_hw_timers_stop_all(struct qed_dev *cdev) |
| 1021 | { |
| 1022 | int j; |
| 1023 | |
| 1024 | for_each_hwfn(cdev, j) { |
| 1025 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; |
| 1026 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; |
| 1027 | |
| 1028 | qed_hw_timers_stop(cdev, p_hwfn, p_ptt); |
| 1029 | } |
| 1030 | } |
| 1031 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1032 | int qed_hw_stop(struct qed_dev *cdev) |
| 1033 | { |
| 1034 | int rc = 0, t_rc; |
Yuval Mintz | 8c925c4 | 2016-03-02 20:26:03 +0200 | [diff] [blame] | 1035 | int j; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1036 | |
| 1037 | for_each_hwfn(cdev, j) { |
| 1038 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; |
| 1039 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; |
| 1040 | |
| 1041 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); |
| 1042 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1043 | if (IS_VF(cdev)) { |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 1044 | qed_vf_pf_int_cleanup(p_hwfn); |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1045 | continue; |
| 1046 | } |
| 1047 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1048 | /* mark the hw as uninitialized... */ |
| 1049 | p_hwfn->hw_init_done = false; |
| 1050 | |
| 1051 | rc = qed_sp_pf_stop(p_hwfn); |
| 1052 | if (rc) |
Yuval Mintz | 8c925c4 | 2016-03-02 20:26:03 +0200 | [diff] [blame] | 1053 | DP_NOTICE(p_hwfn, |
| 1054 | "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1055 | |
| 1056 | qed_wr(p_hwfn, p_ptt, |
| 1057 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); |
| 1058 | |
| 1059 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); |
| 1060 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); |
| 1061 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); |
| 1062 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); |
| 1063 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); |
| 1064 | |
Yuval Mintz | 8c925c4 | 2016-03-02 20:26:03 +0200 | [diff] [blame] | 1065 | qed_hw_timers_stop(cdev, p_hwfn, p_ptt); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1066 | |
| 1067 | /* Disable Attention Generation */ |
| 1068 | qed_int_igu_disable_int(p_hwfn, p_ptt); |
| 1069 | |
| 1070 | qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); |
| 1071 | qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); |
| 1072 | |
| 1073 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); |
| 1074 | |
| 1075 | /* Need to wait 1ms to guarantee SBs are cleared */ |
| 1076 | usleep_range(1000, 2000); |
| 1077 | } |
| 1078 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1079 | if (IS_PF(cdev)) { |
| 1080 | /* Disable DMAE in PXP - in CMT, this should only be done for |
| 1081 | * first hw-function, and only after all transactions have |
| 1082 | * stopped for all active hw-functions. |
| 1083 | */ |
| 1084 | t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], |
| 1085 | cdev->hwfns[0].p_main_ptt, false); |
| 1086 | if (t_rc != 0) |
| 1087 | rc = t_rc; |
| 1088 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1089 | |
| 1090 | return rc; |
| 1091 | } |
| 1092 | |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 1093 | void qed_hw_stop_fastpath(struct qed_dev *cdev) |
| 1094 | { |
Yuval Mintz | 8c925c4 | 2016-03-02 20:26:03 +0200 | [diff] [blame] | 1095 | int j; |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 1096 | |
| 1097 | for_each_hwfn(cdev, j) { |
| 1098 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; |
Yuval Mintz | dacd88d | 2016-05-11 16:36:16 +0300 | [diff] [blame] | 1099 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; |
| 1100 | |
| 1101 | if (IS_VF(cdev)) { |
| 1102 | qed_vf_pf_int_cleanup(p_hwfn); |
| 1103 | continue; |
| 1104 | } |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 1105 | |
| 1106 | DP_VERBOSE(p_hwfn, |
| 1107 | NETIF_MSG_IFDOWN, |
| 1108 | "Shutting down the fastpath\n"); |
| 1109 | |
| 1110 | qed_wr(p_hwfn, p_ptt, |
| 1111 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); |
| 1112 | |
| 1113 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); |
| 1114 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); |
| 1115 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); |
| 1116 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); |
| 1117 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); |
| 1118 | |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 1119 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); |
| 1120 | |
| 1121 | /* Need to wait 1ms to guarantee SBs are cleared */ |
| 1122 | usleep_range(1000, 2000); |
| 1123 | } |
| 1124 | } |
| 1125 | |
| 1126 | void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) |
| 1127 | { |
Yuval Mintz | dacd88d | 2016-05-11 16:36:16 +0300 | [diff] [blame] | 1128 | if (IS_VF(p_hwfn->cdev)) |
| 1129 | return; |
| 1130 | |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 1131 | /* Re-open incoming traffic */ |
| 1132 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, |
| 1133 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); |
| 1134 | } |
| 1135 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1136 | static int qed_reg_assert(struct qed_hwfn *hwfn, |
| 1137 | struct qed_ptt *ptt, u32 reg, |
| 1138 | bool expected) |
| 1139 | { |
| 1140 | u32 assert_val = qed_rd(hwfn, ptt, reg); |
| 1141 | |
| 1142 | if (assert_val != expected) { |
| 1143 | DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n", |
| 1144 | reg, expected); |
| 1145 | return -EINVAL; |
| 1146 | } |
| 1147 | |
| 1148 | return 0; |
| 1149 | } |
| 1150 | |
| 1151 | int qed_hw_reset(struct qed_dev *cdev) |
| 1152 | { |
| 1153 | int rc = 0; |
| 1154 | u32 unload_resp, unload_param; |
| 1155 | int i; |
| 1156 | |
| 1157 | for_each_hwfn(cdev, i) { |
| 1158 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 1159 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1160 | if (IS_VF(cdev)) { |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 1161 | rc = qed_vf_pf_reset(p_hwfn); |
| 1162 | if (rc) |
| 1163 | return rc; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1164 | continue; |
| 1165 | } |
| 1166 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1167 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); |
| 1168 | |
| 1169 | /* Check for incorrect states */ |
| 1170 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, |
| 1171 | QM_REG_USG_CNT_PF_TX, 0); |
| 1172 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, |
| 1173 | QM_REG_USG_CNT_PF_OTHER, 0); |
| 1174 | |
| 1175 | /* Disable PF in HW blocks */ |
| 1176 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); |
| 1177 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); |
| 1178 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, |
| 1179 | TCFC_REG_STRONG_ENABLE_PF, 0); |
| 1180 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, |
| 1181 | CCFC_REG_STRONG_ENABLE_PF, 0); |
| 1182 | |
| 1183 | /* Send unload command to MCP */ |
| 1184 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, |
| 1185 | DRV_MSG_CODE_UNLOAD_REQ, |
| 1186 | DRV_MB_PARAM_UNLOAD_WOL_MCP, |
| 1187 | &unload_resp, &unload_param); |
| 1188 | if (rc) { |
| 1189 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); |
| 1190 | unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; |
| 1191 | } |
| 1192 | |
| 1193 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, |
| 1194 | DRV_MSG_CODE_UNLOAD_DONE, |
| 1195 | 0, &unload_resp, &unload_param); |
| 1196 | if (rc) { |
| 1197 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); |
| 1198 | return rc; |
| 1199 | } |
| 1200 | } |
| 1201 | |
| 1202 | return rc; |
| 1203 | } |
| 1204 | |
| 1205 | /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ |
| 1206 | static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) |
| 1207 | { |
| 1208 | qed_ptt_pool_free(p_hwfn); |
| 1209 | kfree(p_hwfn->hw_info.p_igu_info); |
| 1210 | } |
| 1211 | |
| 1212 | /* Setup bar access */ |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 1213 | static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1214 | { |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1215 | /* clear indirect access */ |
| 1216 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); |
| 1217 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); |
| 1218 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); |
| 1219 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); |
| 1220 | |
| 1221 | /* Clean Previous errors if such exist */ |
| 1222 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, |
| 1223 | PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, |
| 1224 | 1 << p_hwfn->abs_pf_id); |
| 1225 | |
| 1226 | /* enable internal target-read */ |
| 1227 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, |
| 1228 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1229 | } |
| 1230 | |
| 1231 | static void get_function_id(struct qed_hwfn *p_hwfn) |
| 1232 | { |
| 1233 | /* ME Register */ |
| 1234 | p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); |
| 1235 | |
| 1236 | p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); |
| 1237 | |
| 1238 | p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; |
| 1239 | p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, |
| 1240 | PXP_CONCRETE_FID_PFID); |
| 1241 | p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, |
| 1242 | PXP_CONCRETE_FID_PORT); |
| 1243 | } |
| 1244 | |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1245 | static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) |
| 1246 | { |
| 1247 | u32 *feat_num = p_hwfn->hw_info.feat_num; |
| 1248 | int num_features = 1; |
| 1249 | |
| 1250 | feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / |
| 1251 | num_features, |
| 1252 | RESC_NUM(p_hwfn, QED_L2_QUEUE)); |
| 1253 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, |
| 1254 | "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", |
| 1255 | feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), |
| 1256 | num_features); |
| 1257 | } |
| 1258 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1259 | static void qed_hw_get_resc(struct qed_hwfn *p_hwfn) |
| 1260 | { |
| 1261 | u32 *resc_start = p_hwfn->hw_info.resc_start; |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1262 | u8 num_funcs = p_hwfn->num_funcs_on_engine; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1263 | u32 *resc_num = p_hwfn->hw_info.resc_num; |
Yuval Mintz | 4ac801b | 2016-02-28 12:26:52 +0200 | [diff] [blame] | 1264 | struct qed_sb_cnt_info sb_cnt_info; |
Yuval Mintz | 08feecd | 2016-05-11 16:36:20 +0300 | [diff] [blame] | 1265 | int i, max_vf_vlan_filters; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1266 | |
Yuval Mintz | 4ac801b | 2016-02-28 12:26:52 +0200 | [diff] [blame] | 1267 | memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); |
Yuval Mintz | 08feecd | 2016-05-11 16:36:20 +0300 | [diff] [blame] | 1268 | |
| 1269 | #ifdef CONFIG_QED_SRIOV |
| 1270 | max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS; |
| 1271 | #else |
| 1272 | max_vf_vlan_filters = 0; |
| 1273 | #endif |
| 1274 | |
Yuval Mintz | 4ac801b | 2016-02-28 12:26:52 +0200 | [diff] [blame] | 1275 | qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); |
| 1276 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1277 | resc_num[QED_SB] = min_t(u32, |
| 1278 | (MAX_SB_PER_PATH_BB / num_funcs), |
Yuval Mintz | 4ac801b | 2016-02-28 12:26:52 +0200 | [diff] [blame] | 1279 | sb_cnt_info.sb_cnt); |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1280 | resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1281 | resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1282 | resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1283 | resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; |
| 1284 | resc_num[QED_RL] = 8; |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1285 | resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; |
| 1286 | resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / |
| 1287 | num_funcs; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1288 | resc_num[QED_ILT] = 950; |
| 1289 | |
| 1290 | for (i = 0; i < QED_MAX_RESC; i++) |
| 1291 | resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id; |
| 1292 | |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1293 | qed_hw_set_feat(p_hwfn); |
| 1294 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1295 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, |
| 1296 | "The numbers for each resource are:\n" |
| 1297 | "SB = %d start = %d\n" |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1298 | "L2_QUEUE = %d start = %d\n" |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1299 | "VPORT = %d start = %d\n" |
| 1300 | "PQ = %d start = %d\n" |
| 1301 | "RL = %d start = %d\n" |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1302 | "MAC = %d start = %d\n" |
| 1303 | "VLAN = %d start = %d\n" |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1304 | "ILT = %d start = %d\n", |
| 1305 | p_hwfn->hw_info.resc_num[QED_SB], |
| 1306 | p_hwfn->hw_info.resc_start[QED_SB], |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1307 | p_hwfn->hw_info.resc_num[QED_L2_QUEUE], |
| 1308 | p_hwfn->hw_info.resc_start[QED_L2_QUEUE], |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1309 | p_hwfn->hw_info.resc_num[QED_VPORT], |
| 1310 | p_hwfn->hw_info.resc_start[QED_VPORT], |
| 1311 | p_hwfn->hw_info.resc_num[QED_PQ], |
| 1312 | p_hwfn->hw_info.resc_start[QED_PQ], |
| 1313 | p_hwfn->hw_info.resc_num[QED_RL], |
| 1314 | p_hwfn->hw_info.resc_start[QED_RL], |
Yuval Mintz | 25c089d | 2015-10-26 11:02:26 +0200 | [diff] [blame] | 1315 | p_hwfn->hw_info.resc_num[QED_MAC], |
| 1316 | p_hwfn->hw_info.resc_start[QED_MAC], |
| 1317 | p_hwfn->hw_info.resc_num[QED_VLAN], |
| 1318 | p_hwfn->hw_info.resc_start[QED_VLAN], |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1319 | p_hwfn->hw_info.resc_num[QED_ILT], |
| 1320 | p_hwfn->hw_info.resc_start[QED_ILT]); |
| 1321 | } |
| 1322 | |
| 1323 | static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, |
| 1324 | struct qed_ptt *p_ptt) |
| 1325 | { |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1326 | u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1327 | u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1328 | struct qed_mcp_link_params *link; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1329 | |
| 1330 | /* Read global nvm_cfg address */ |
| 1331 | nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); |
| 1332 | |
| 1333 | /* Verify MCP has initialized it */ |
| 1334 | if (!nvm_cfg_addr) { |
| 1335 | DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); |
| 1336 | return -EINVAL; |
| 1337 | } |
| 1338 | |
| 1339 | /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ |
| 1340 | nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); |
| 1341 | |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1342 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + |
| 1343 | offsetof(struct nvm_cfg1, glob) + |
| 1344 | offsetof(struct nvm_cfg1_glob, core_cfg); |
| 1345 | |
| 1346 | core_cfg = qed_rd(p_hwfn, p_ptt, addr); |
| 1347 | |
| 1348 | switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> |
| 1349 | NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1350 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1351 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; |
| 1352 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1353 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1354 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; |
| 1355 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1356 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1357 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; |
| 1358 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1359 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1360 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; |
| 1361 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1362 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1363 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; |
| 1364 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1365 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1366 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; |
| 1367 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1368 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1369 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; |
| 1370 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1371 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1372 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; |
| 1373 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1374 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1375 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; |
| 1376 | break; |
| 1377 | default: |
| 1378 | DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", |
| 1379 | core_cfg); |
| 1380 | break; |
| 1381 | } |
| 1382 | |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1383 | /* Read default link configuration */ |
| 1384 | link = &p_hwfn->mcp_info->link_input; |
| 1385 | port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + |
| 1386 | offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); |
| 1387 | link_temp = qed_rd(p_hwfn, p_ptt, |
| 1388 | port_cfg_addr + |
| 1389 | offsetof(struct nvm_cfg1_port, speed_cap_mask)); |
| 1390 | link->speed.advertised_speeds = |
| 1391 | link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; |
| 1392 | |
| 1393 | p_hwfn->mcp_info->link_capabilities.speed_capabilities = |
| 1394 | link->speed.advertised_speeds; |
| 1395 | |
| 1396 | link_temp = qed_rd(p_hwfn, p_ptt, |
| 1397 | port_cfg_addr + |
| 1398 | offsetof(struct nvm_cfg1_port, link_settings)); |
| 1399 | switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> |
| 1400 | NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { |
| 1401 | case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: |
| 1402 | link->speed.autoneg = true; |
| 1403 | break; |
| 1404 | case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: |
| 1405 | link->speed.forced_speed = 1000; |
| 1406 | break; |
| 1407 | case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: |
| 1408 | link->speed.forced_speed = 10000; |
| 1409 | break; |
| 1410 | case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: |
| 1411 | link->speed.forced_speed = 25000; |
| 1412 | break; |
| 1413 | case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: |
| 1414 | link->speed.forced_speed = 40000; |
| 1415 | break; |
| 1416 | case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: |
| 1417 | link->speed.forced_speed = 50000; |
| 1418 | break; |
Yuval Mintz | 351a4ded | 2016-06-02 10:23:29 +0300 | [diff] [blame] | 1419 | case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: |
Yuval Mintz | cc875c2 | 2015-10-26 11:02:31 +0200 | [diff] [blame] | 1420 | link->speed.forced_speed = 100000; |
| 1421 | break; |
| 1422 | default: |
| 1423 | DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", |
| 1424 | link_temp); |
| 1425 | } |
| 1426 | |
| 1427 | link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; |
| 1428 | link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; |
| 1429 | link->pause.autoneg = !!(link_temp & |
| 1430 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); |
| 1431 | link->pause.forced_rx = !!(link_temp & |
| 1432 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); |
| 1433 | link->pause.forced_tx = !!(link_temp & |
| 1434 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); |
| 1435 | link->loopback_mode = 0; |
| 1436 | |
| 1437 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 1438 | "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", |
| 1439 | link->speed.forced_speed, link->speed.advertised_speeds, |
| 1440 | link->speed.autoneg, link->pause.autoneg); |
| 1441 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1442 | /* Read Multi-function information from shmem */ |
| 1443 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + |
| 1444 | offsetof(struct nvm_cfg1, glob) + |
| 1445 | offsetof(struct nvm_cfg1_glob, generic_cont0); |
| 1446 | |
| 1447 | generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); |
| 1448 | |
| 1449 | mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> |
| 1450 | NVM_CFG1_GLOB_MF_MODE_OFFSET; |
| 1451 | |
| 1452 | switch (mf_mode) { |
| 1453 | case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1454 | p_hwfn->cdev->mf_mode = QED_MF_OVLAN; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1455 | break; |
| 1456 | case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1457 | p_hwfn->cdev->mf_mode = QED_MF_NPAR; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1458 | break; |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1459 | case NVM_CFG1_GLOB_MF_MODE_DEFAULT: |
| 1460 | p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1461 | break; |
| 1462 | } |
| 1463 | DP_INFO(p_hwfn, "Multi function mode is %08x\n", |
| 1464 | p_hwfn->cdev->mf_mode); |
| 1465 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1466 | /* Read Multi-function information from shmem */ |
| 1467 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + |
| 1468 | offsetof(struct nvm_cfg1, glob) + |
| 1469 | offsetof(struct nvm_cfg1_glob, device_capabilities); |
| 1470 | |
| 1471 | device_capabilities = qed_rd(p_hwfn, p_ptt, addr); |
| 1472 | if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) |
| 1473 | __set_bit(QED_DEV_CAP_ETH, |
| 1474 | &p_hwfn->hw_info.device_capabilities); |
| 1475 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1476 | return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); |
| 1477 | } |
| 1478 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1479 | static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
| 1480 | { |
| 1481 | u32 reg_function_hide, tmp, eng_mask; |
| 1482 | u8 num_funcs; |
| 1483 | |
| 1484 | num_funcs = MAX_NUM_PFS_BB; |
| 1485 | |
| 1486 | /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values |
| 1487 | * in the other bits are selected. |
| 1488 | * Bits 1-15 are for functions 1-15, respectively, and their value is |
| 1489 | * '0' only for enabled functions (function 0 always exists and |
| 1490 | * enabled). |
| 1491 | * In case of CMT, only the "even" functions are enabled, and thus the |
| 1492 | * number of functions for both hwfns is learnt from the same bits. |
| 1493 | */ |
| 1494 | reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); |
| 1495 | |
| 1496 | if (reg_function_hide & 0x1) { |
| 1497 | if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { |
| 1498 | num_funcs = 0; |
| 1499 | eng_mask = 0xaaaa; |
| 1500 | } else { |
| 1501 | num_funcs = 1; |
| 1502 | eng_mask = 0x5554; |
| 1503 | } |
| 1504 | |
| 1505 | /* Get the number of the enabled functions on the engine */ |
| 1506 | tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; |
| 1507 | while (tmp) { |
| 1508 | if (tmp & 0x1) |
| 1509 | num_funcs++; |
| 1510 | tmp >>= 0x1; |
| 1511 | } |
| 1512 | } |
| 1513 | |
| 1514 | p_hwfn->num_funcs_on_engine = num_funcs; |
| 1515 | |
| 1516 | DP_VERBOSE(p_hwfn, |
| 1517 | NETIF_MSG_PROBE, |
| 1518 | "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n", |
| 1519 | p_hwfn->rel_pf_id, |
| 1520 | p_hwfn->abs_pf_id, |
| 1521 | p_hwfn->num_funcs_on_engine); |
| 1522 | } |
| 1523 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1524 | static int |
| 1525 | qed_get_hw_info(struct qed_hwfn *p_hwfn, |
| 1526 | struct qed_ptt *p_ptt, |
| 1527 | enum qed_pci_personality personality) |
| 1528 | { |
| 1529 | u32 port_mode; |
| 1530 | int rc; |
| 1531 | |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 1532 | /* Since all information is common, only first hwfns should do this */ |
| 1533 | if (IS_LEAD_HWFN(p_hwfn)) { |
| 1534 | rc = qed_iov_hw_info(p_hwfn); |
| 1535 | if (rc) |
| 1536 | return rc; |
| 1537 | } |
| 1538 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1539 | /* Read the port mode */ |
| 1540 | port_mode = qed_rd(p_hwfn, p_ptt, |
| 1541 | CNIG_REG_NW_PORT_MODE_BB_B0); |
| 1542 | |
| 1543 | if (port_mode < 3) { |
| 1544 | p_hwfn->cdev->num_ports_in_engines = 1; |
| 1545 | } else if (port_mode <= 5) { |
| 1546 | p_hwfn->cdev->num_ports_in_engines = 2; |
| 1547 | } else { |
| 1548 | DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", |
| 1549 | p_hwfn->cdev->num_ports_in_engines); |
| 1550 | |
| 1551 | /* Default num_ports_in_engines to something */ |
| 1552 | p_hwfn->cdev->num_ports_in_engines = 1; |
| 1553 | } |
| 1554 | |
| 1555 | qed_hw_get_nvm_info(p_hwfn, p_ptt); |
| 1556 | |
| 1557 | rc = qed_int_igu_read_cam(p_hwfn, p_ptt); |
| 1558 | if (rc) |
| 1559 | return rc; |
| 1560 | |
| 1561 | if (qed_mcp_is_init(p_hwfn)) |
| 1562 | ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, |
| 1563 | p_hwfn->mcp_info->func_info.mac); |
| 1564 | else |
| 1565 | eth_random_addr(p_hwfn->hw_info.hw_mac_addr); |
| 1566 | |
| 1567 | if (qed_mcp_is_init(p_hwfn)) { |
| 1568 | if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) |
| 1569 | p_hwfn->hw_info.ovlan = |
| 1570 | p_hwfn->mcp_info->func_info.ovlan; |
| 1571 | |
| 1572 | qed_mcp_cmd_port_init(p_hwfn, p_ptt); |
| 1573 | } |
| 1574 | |
| 1575 | if (qed_mcp_is_init(p_hwfn)) { |
| 1576 | enum qed_pci_personality protocol; |
| 1577 | |
| 1578 | protocol = p_hwfn->mcp_info->func_info.protocol; |
| 1579 | p_hwfn->hw_info.personality = protocol; |
| 1580 | } |
| 1581 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1582 | qed_get_num_funcs(p_hwfn, p_ptt); |
| 1583 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1584 | qed_hw_get_resc(p_hwfn); |
| 1585 | |
| 1586 | return rc; |
| 1587 | } |
| 1588 | |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 1589 | static int qed_get_dev_info(struct qed_dev *cdev) |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1590 | { |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1591 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1592 | u32 tmp; |
| 1593 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1594 | /* Read Vendor Id / Device Id */ |
| 1595 | pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, |
| 1596 | &cdev->vendor_id); |
| 1597 | pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, |
| 1598 | &cdev->device_id); |
| 1599 | cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1600 | MISCS_REG_CHIP_NUM); |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1601 | cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1602 | MISCS_REG_CHIP_REV); |
| 1603 | MASK_FIELD(CHIP_REV, cdev->chip_rev); |
| 1604 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1605 | cdev->type = QED_DEV_TYPE_BB; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1606 | /* Learn number of HW-functions */ |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1607 | tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1608 | MISCS_REG_CMT_ENABLED_FOR_PAIR); |
| 1609 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1610 | if (tmp & (1 << p_hwfn->rel_pf_id)) { |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1611 | DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); |
| 1612 | cdev->num_hwfns = 2; |
| 1613 | } else { |
| 1614 | cdev->num_hwfns = 1; |
| 1615 | } |
| 1616 | |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1617 | cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1618 | MISCS_REG_CHIP_TEST_REG) >> 4; |
| 1619 | MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); |
Yuval Mintz | fc48b7a | 2016-02-15 13:22:35 -0500 | [diff] [blame] | 1620 | cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1621 | MISCS_REG_CHIP_METAL); |
| 1622 | MASK_FIELD(CHIP_METAL, cdev->chip_metal); |
| 1623 | |
| 1624 | DP_INFO(cdev->hwfns, |
| 1625 | "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", |
| 1626 | cdev->chip_num, cdev->chip_rev, |
| 1627 | cdev->chip_bond_id, cdev->chip_metal); |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 1628 | |
| 1629 | if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { |
| 1630 | DP_NOTICE(cdev->hwfns, |
| 1631 | "The chip type/rev (BB A0) is not supported!\n"); |
| 1632 | return -EINVAL; |
| 1633 | } |
| 1634 | |
| 1635 | return 0; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1636 | } |
| 1637 | |
| 1638 | static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, |
| 1639 | void __iomem *p_regview, |
| 1640 | void __iomem *p_doorbells, |
| 1641 | enum qed_pci_personality personality) |
| 1642 | { |
| 1643 | int rc = 0; |
| 1644 | |
| 1645 | /* Split PCI bars evenly between hwfns */ |
| 1646 | p_hwfn->regview = p_regview; |
| 1647 | p_hwfn->doorbells = p_doorbells; |
| 1648 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1649 | if (IS_VF(p_hwfn->cdev)) |
| 1650 | return qed_vf_hw_prepare(p_hwfn); |
| 1651 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1652 | /* Validate that chip access is feasible */ |
| 1653 | if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { |
| 1654 | DP_ERR(p_hwfn, |
| 1655 | "Reading the ME register returns all Fs; Preventing further chip access\n"); |
| 1656 | return -EINVAL; |
| 1657 | } |
| 1658 | |
| 1659 | get_function_id(p_hwfn); |
| 1660 | |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 1661 | /* Allocate PTT pool */ |
| 1662 | rc = qed_ptt_pool_alloc(p_hwfn); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1663 | if (rc) { |
| 1664 | DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n"); |
| 1665 | goto err0; |
| 1666 | } |
| 1667 | |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 1668 | /* Allocate the main PTT */ |
| 1669 | p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); |
| 1670 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1671 | /* First hwfn learns basic information, e.g., number of hwfns */ |
Yuval Mintz | 12e09c6 | 2016-03-02 20:26:01 +0200 | [diff] [blame] | 1672 | if (!p_hwfn->my_id) { |
| 1673 | rc = qed_get_dev_info(p_hwfn->cdev); |
| 1674 | if (rc != 0) |
| 1675 | goto err1; |
| 1676 | } |
| 1677 | |
| 1678 | qed_hw_hwfn_prepare(p_hwfn); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1679 | |
| 1680 | /* Initialize MCP structure */ |
| 1681 | rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); |
| 1682 | if (rc) { |
| 1683 | DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); |
| 1684 | goto err1; |
| 1685 | } |
| 1686 | |
| 1687 | /* Read the device configuration information from the HW and SHMEM */ |
| 1688 | rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); |
| 1689 | if (rc) { |
| 1690 | DP_NOTICE(p_hwfn, "Failed to get HW information\n"); |
| 1691 | goto err2; |
| 1692 | } |
| 1693 | |
| 1694 | /* Allocate the init RT array and initialize the init-ops engine */ |
| 1695 | rc = qed_init_alloc(p_hwfn); |
| 1696 | if (rc) { |
| 1697 | DP_NOTICE(p_hwfn, "Failed to allocate the init array\n"); |
| 1698 | goto err2; |
| 1699 | } |
| 1700 | |
| 1701 | return rc; |
| 1702 | err2: |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 1703 | if (IS_LEAD_HWFN(p_hwfn)) |
| 1704 | qed_iov_free_hw_info(p_hwfn->cdev); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1705 | qed_mcp_free(p_hwfn); |
| 1706 | err1: |
| 1707 | qed_hw_hwfn_free(p_hwfn); |
| 1708 | err0: |
| 1709 | return rc; |
| 1710 | } |
| 1711 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1712 | int qed_hw_prepare(struct qed_dev *cdev, |
| 1713 | int personality) |
| 1714 | { |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1715 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
| 1716 | int rc; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1717 | |
| 1718 | /* Store the precompiled init data ptrs */ |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1719 | if (IS_PF(cdev)) |
| 1720 | qed_init_iro_array(cdev); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1721 | |
| 1722 | /* Initialize the first hwfn - will learn number of hwfns */ |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1723 | rc = qed_hw_prepare_single(p_hwfn, |
| 1724 | cdev->regview, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1725 | cdev->doorbells, personality); |
| 1726 | if (rc) |
| 1727 | return rc; |
| 1728 | |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1729 | personality = p_hwfn->hw_info.personality; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1730 | |
| 1731 | /* Initialize the rest of the hwfns */ |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1732 | if (cdev->num_hwfns > 1) { |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1733 | void __iomem *p_regview, *p_doorbell; |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1734 | u8 __iomem *addr; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1735 | |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1736 | /* adjust bar offset for second engine */ |
Ram Amrani | c2035ee | 2016-03-02 20:26:00 +0200 | [diff] [blame] | 1737 | addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1738 | p_regview = addr; |
| 1739 | |
| 1740 | /* adjust doorbell bar offset for second engine */ |
Ram Amrani | c2035ee | 2016-03-02 20:26:00 +0200 | [diff] [blame] | 1741 | addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1742 | p_doorbell = addr; |
| 1743 | |
| 1744 | /* prepare second hw function */ |
| 1745 | rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1746 | p_doorbell, personality); |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1747 | |
| 1748 | /* in case of error, need to free the previously |
| 1749 | * initiliazed hwfn 0. |
| 1750 | */ |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1751 | if (rc) { |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1752 | if (IS_PF(cdev)) { |
| 1753 | qed_init_free(p_hwfn); |
| 1754 | qed_mcp_free(p_hwfn); |
| 1755 | qed_hw_hwfn_free(p_hwfn); |
| 1756 | } |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1757 | } |
| 1758 | } |
| 1759 | |
Ariel Elior | c78df14 | 2015-12-07 06:25:58 -0500 | [diff] [blame] | 1760 | return rc; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1761 | } |
| 1762 | |
| 1763 | void qed_hw_remove(struct qed_dev *cdev) |
| 1764 | { |
| 1765 | int i; |
| 1766 | |
| 1767 | for_each_hwfn(cdev, i) { |
| 1768 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 1769 | |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1770 | if (IS_VF(cdev)) { |
Yuval Mintz | 0b55e27 | 2016-05-11 16:36:15 +0300 | [diff] [blame] | 1771 | qed_vf_pf_release(p_hwfn); |
Yuval Mintz | 1408cc1f | 2016-05-11 16:36:14 +0300 | [diff] [blame] | 1772 | continue; |
| 1773 | } |
| 1774 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1775 | qed_init_free(p_hwfn); |
| 1776 | qed_hw_hwfn_free(p_hwfn); |
| 1777 | qed_mcp_free(p_hwfn); |
| 1778 | } |
Yuval Mintz | 32a47e7 | 2016-05-11 16:36:12 +0300 | [diff] [blame] | 1779 | |
| 1780 | qed_iov_free_hw_info(cdev); |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 1781 | } |
| 1782 | |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 1783 | static void qed_chain_free_next_ptr(struct qed_dev *cdev, |
| 1784 | struct qed_chain *p_chain) |
| 1785 | { |
| 1786 | void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; |
| 1787 | dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; |
| 1788 | struct qed_chain_next *p_next; |
| 1789 | u32 size, i; |
| 1790 | |
| 1791 | if (!p_virt) |
| 1792 | return; |
| 1793 | |
| 1794 | size = p_chain->elem_size * p_chain->usable_per_page; |
| 1795 | |
| 1796 | for (i = 0; i < p_chain->page_cnt; i++) { |
| 1797 | if (!p_virt) |
| 1798 | break; |
| 1799 | |
| 1800 | p_next = (struct qed_chain_next *)((u8 *)p_virt + size); |
| 1801 | p_virt_next = p_next->next_virt; |
| 1802 | p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); |
| 1803 | |
| 1804 | dma_free_coherent(&cdev->pdev->dev, |
| 1805 | QED_CHAIN_PAGE_SIZE, p_virt, p_phys); |
| 1806 | |
| 1807 | p_virt = p_virt_next; |
| 1808 | p_phys = p_phys_next; |
| 1809 | } |
| 1810 | } |
| 1811 | |
| 1812 | static void qed_chain_free_single(struct qed_dev *cdev, |
| 1813 | struct qed_chain *p_chain) |
| 1814 | { |
| 1815 | if (!p_chain->p_virt_addr) |
| 1816 | return; |
| 1817 | |
| 1818 | dma_free_coherent(&cdev->pdev->dev, |
| 1819 | QED_CHAIN_PAGE_SIZE, |
| 1820 | p_chain->p_virt_addr, p_chain->p_phys_addr); |
| 1821 | } |
| 1822 | |
| 1823 | static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) |
| 1824 | { |
| 1825 | void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; |
| 1826 | u32 page_cnt = p_chain->page_cnt, i, pbl_size; |
| 1827 | u8 *p_pbl_virt = p_chain->pbl.p_virt_table; |
| 1828 | |
| 1829 | if (!pp_virt_addr_tbl) |
| 1830 | return; |
| 1831 | |
| 1832 | if (!p_chain->pbl.p_virt_table) |
| 1833 | goto out; |
| 1834 | |
| 1835 | for (i = 0; i < page_cnt; i++) { |
| 1836 | if (!pp_virt_addr_tbl[i]) |
| 1837 | break; |
| 1838 | |
| 1839 | dma_free_coherent(&cdev->pdev->dev, |
| 1840 | QED_CHAIN_PAGE_SIZE, |
| 1841 | pp_virt_addr_tbl[i], |
| 1842 | *(dma_addr_t *)p_pbl_virt); |
| 1843 | |
| 1844 | p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; |
| 1845 | } |
| 1846 | |
| 1847 | pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; |
| 1848 | dma_free_coherent(&cdev->pdev->dev, |
| 1849 | pbl_size, |
| 1850 | p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); |
| 1851 | out: |
| 1852 | vfree(p_chain->pbl.pp_virt_addr_tbl); |
| 1853 | } |
| 1854 | |
| 1855 | void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) |
| 1856 | { |
| 1857 | switch (p_chain->mode) { |
| 1858 | case QED_CHAIN_MODE_NEXT_PTR: |
| 1859 | qed_chain_free_next_ptr(cdev, p_chain); |
| 1860 | break; |
| 1861 | case QED_CHAIN_MODE_SINGLE: |
| 1862 | qed_chain_free_single(cdev, p_chain); |
| 1863 | break; |
| 1864 | case QED_CHAIN_MODE_PBL: |
| 1865 | qed_chain_free_pbl(cdev, p_chain); |
| 1866 | break; |
| 1867 | } |
| 1868 | } |
| 1869 | |
| 1870 | static int |
| 1871 | qed_chain_alloc_sanity_check(struct qed_dev *cdev, |
| 1872 | enum qed_chain_cnt_type cnt_type, |
| 1873 | size_t elem_size, u32 page_cnt) |
| 1874 | { |
| 1875 | u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; |
| 1876 | |
| 1877 | /* The actual chain size can be larger than the maximal possible value |
| 1878 | * after rounding up the requested elements number to pages, and after |
| 1879 | * taking into acount the unusuable elements (next-ptr elements). |
| 1880 | * The size of a "u16" chain can be (U16_MAX + 1) since the chain |
| 1881 | * size/capacity fields are of a u32 type. |
| 1882 | */ |
| 1883 | if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && |
| 1884 | chain_size > 0x10000) || |
| 1885 | (cnt_type == QED_CHAIN_CNT_TYPE_U32 && |
| 1886 | chain_size > 0x100000000ULL)) { |
| 1887 | DP_NOTICE(cdev, |
| 1888 | "The actual chain size (0x%llx) is larger than the maximal possible value\n", |
| 1889 | chain_size); |
| 1890 | return -EINVAL; |
| 1891 | } |
| 1892 | |
| 1893 | return 0; |
| 1894 | } |
| 1895 | |
| 1896 | static int |
| 1897 | qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) |
| 1898 | { |
| 1899 | void *p_virt = NULL, *p_virt_prev = NULL; |
| 1900 | dma_addr_t p_phys = 0; |
| 1901 | u32 i; |
| 1902 | |
| 1903 | for (i = 0; i < p_chain->page_cnt; i++) { |
| 1904 | p_virt = dma_alloc_coherent(&cdev->pdev->dev, |
| 1905 | QED_CHAIN_PAGE_SIZE, |
| 1906 | &p_phys, GFP_KERNEL); |
| 1907 | if (!p_virt) { |
| 1908 | DP_NOTICE(cdev, "Failed to allocate chain memory\n"); |
| 1909 | return -ENOMEM; |
| 1910 | } |
| 1911 | |
| 1912 | if (i == 0) { |
| 1913 | qed_chain_init_mem(p_chain, p_virt, p_phys); |
| 1914 | qed_chain_reset(p_chain); |
| 1915 | } else { |
| 1916 | qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, |
| 1917 | p_virt, p_phys); |
| 1918 | } |
| 1919 | |
| 1920 | p_virt_prev = p_virt; |
| 1921 | } |
| 1922 | /* Last page's next element should point to the beginning of the |
| 1923 | * chain. |
| 1924 | */ |
| 1925 | qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, |
| 1926 | p_chain->p_virt_addr, |
| 1927 | p_chain->p_phys_addr); |
| 1928 | |
| 1929 | return 0; |
| 1930 | } |
| 1931 | |
| 1932 | static int |
| 1933 | qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) |
| 1934 | { |
| 1935 | dma_addr_t p_phys = 0; |
| 1936 | void *p_virt = NULL; |
| 1937 | |
| 1938 | p_virt = dma_alloc_coherent(&cdev->pdev->dev, |
| 1939 | QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); |
| 1940 | if (!p_virt) { |
| 1941 | DP_NOTICE(cdev, "Failed to allocate chain memory\n"); |
| 1942 | return -ENOMEM; |
| 1943 | } |
| 1944 | |
| 1945 | qed_chain_init_mem(p_chain, p_virt, p_phys); |
| 1946 | qed_chain_reset(p_chain); |
| 1947 | |
| 1948 | return 0; |
| 1949 | } |
| 1950 | |
| 1951 | static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) |
| 1952 | { |
| 1953 | u32 page_cnt = p_chain->page_cnt, size, i; |
| 1954 | dma_addr_t p_phys = 0, p_pbl_phys = 0; |
| 1955 | void **pp_virt_addr_tbl = NULL; |
| 1956 | u8 *p_pbl_virt = NULL; |
| 1957 | void *p_virt = NULL; |
| 1958 | |
| 1959 | size = page_cnt * sizeof(*pp_virt_addr_tbl); |
| 1960 | pp_virt_addr_tbl = vmalloc(size); |
| 1961 | if (!pp_virt_addr_tbl) { |
| 1962 | DP_NOTICE(cdev, |
| 1963 | "Failed to allocate memory for the chain virtual addresses table\n"); |
| 1964 | return -ENOMEM; |
| 1965 | } |
| 1966 | memset(pp_virt_addr_tbl, 0, size); |
| 1967 | |
| 1968 | /* The allocation of the PBL table is done with its full size, since it |
| 1969 | * is expected to be successive. |
| 1970 | * qed_chain_init_pbl_mem() is called even in a case of an allocation |
| 1971 | * failure, since pp_virt_addr_tbl was previously allocated, and it |
| 1972 | * should be saved to allow its freeing during the error flow. |
| 1973 | */ |
| 1974 | size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; |
| 1975 | p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, |
| 1976 | size, &p_pbl_phys, GFP_KERNEL); |
| 1977 | qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, |
| 1978 | pp_virt_addr_tbl); |
| 1979 | if (!p_pbl_virt) { |
| 1980 | DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n"); |
| 1981 | return -ENOMEM; |
| 1982 | } |
| 1983 | |
| 1984 | for (i = 0; i < page_cnt; i++) { |
| 1985 | p_virt = dma_alloc_coherent(&cdev->pdev->dev, |
| 1986 | QED_CHAIN_PAGE_SIZE, |
| 1987 | &p_phys, GFP_KERNEL); |
| 1988 | if (!p_virt) { |
| 1989 | DP_NOTICE(cdev, "Failed to allocate chain memory\n"); |
| 1990 | return -ENOMEM; |
| 1991 | } |
| 1992 | |
| 1993 | if (i == 0) { |
| 1994 | qed_chain_init_mem(p_chain, p_virt, p_phys); |
| 1995 | qed_chain_reset(p_chain); |
| 1996 | } |
| 1997 | |
| 1998 | /* Fill the PBL table with the physical address of the page */ |
| 1999 | *(dma_addr_t *)p_pbl_virt = p_phys; |
| 2000 | /* Keep the virtual address of the page */ |
| 2001 | p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; |
| 2002 | |
| 2003 | p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; |
| 2004 | } |
| 2005 | |
| 2006 | return 0; |
| 2007 | } |
| 2008 | |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 2009 | int qed_chain_alloc(struct qed_dev *cdev, |
| 2010 | enum qed_chain_use_mode intended_use, |
| 2011 | enum qed_chain_mode mode, |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 2012 | enum qed_chain_cnt_type cnt_type, |
| 2013 | u32 num_elems, size_t elem_size, struct qed_chain *p_chain) |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 2014 | { |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 2015 | u32 page_cnt; |
| 2016 | int rc = 0; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 2017 | |
| 2018 | if (mode == QED_CHAIN_MODE_SINGLE) |
| 2019 | page_cnt = 1; |
| 2020 | else |
| 2021 | page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); |
| 2022 | |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 2023 | rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); |
| 2024 | if (rc) { |
| 2025 | DP_NOTICE(cdev, |
| 2026 | "Cannot allocate a chain with the given arguments:\n" |
| 2027 | "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", |
| 2028 | intended_use, mode, cnt_type, num_elems, elem_size); |
| 2029 | return rc; |
| 2030 | } |
| 2031 | |
| 2032 | qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, |
| 2033 | mode, cnt_type); |
| 2034 | |
| 2035 | switch (mode) { |
| 2036 | case QED_CHAIN_MODE_NEXT_PTR: |
| 2037 | rc = qed_chain_alloc_next_ptr(cdev, p_chain); |
| 2038 | break; |
| 2039 | case QED_CHAIN_MODE_SINGLE: |
| 2040 | rc = qed_chain_alloc_single(cdev, p_chain); |
| 2041 | break; |
| 2042 | case QED_CHAIN_MODE_PBL: |
| 2043 | rc = qed_chain_alloc_pbl(cdev, p_chain); |
| 2044 | break; |
| 2045 | } |
| 2046 | if (rc) |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 2047 | goto nomem; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 2048 | |
| 2049 | return 0; |
| 2050 | |
| 2051 | nomem: |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 2052 | qed_chain_free(cdev, p_chain); |
| 2053 | return rc; |
Yuval Mintz | fe56b9e | 2015-10-26 11:02:25 +0200 | [diff] [blame] | 2054 | } |
| 2055 | |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 2056 | int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 2057 | { |
| 2058 | if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { |
| 2059 | u16 min, max; |
| 2060 | |
Yuval Mintz | a91eb52 | 2016-06-03 14:35:32 +0300 | [diff] [blame^] | 2061 | min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); |
Manish Chopra | cee4d26 | 2015-10-26 11:02:28 +0200 | [diff] [blame] | 2062 | max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); |
| 2063 | DP_NOTICE(p_hwfn, |
| 2064 | "l2_queue id [%d] is not valid, available indices [%d - %d]\n", |
| 2065 | src_id, min, max); |
| 2066 | |
| 2067 | return -EINVAL; |
| 2068 | } |
| 2069 | |
| 2070 | *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; |
| 2071 | |
| 2072 | return 0; |
| 2073 | } |
| 2074 | |
| 2075 | int qed_fw_vport(struct qed_hwfn *p_hwfn, |
| 2076 | u8 src_id, u8 *dst_id) |
| 2077 | { |
| 2078 | if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { |
| 2079 | u8 min, max; |
| 2080 | |
| 2081 | min = (u8)RESC_START(p_hwfn, QED_VPORT); |
| 2082 | max = min + RESC_NUM(p_hwfn, QED_VPORT); |
| 2083 | DP_NOTICE(p_hwfn, |
| 2084 | "vport id [%d] is not valid, available indices [%d - %d]\n", |
| 2085 | src_id, min, max); |
| 2086 | |
| 2087 | return -EINVAL; |
| 2088 | } |
| 2089 | |
| 2090 | *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; |
| 2091 | |
| 2092 | return 0; |
| 2093 | } |
| 2094 | |
| 2095 | int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, |
| 2096 | u8 src_id, u8 *dst_id) |
| 2097 | { |
| 2098 | if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { |
| 2099 | u8 min, max; |
| 2100 | |
| 2101 | min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); |
| 2102 | max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); |
| 2103 | DP_NOTICE(p_hwfn, |
| 2104 | "rss_eng id [%d] is not valid, available indices [%d - %d]\n", |
| 2105 | src_id, min, max); |
| 2106 | |
| 2107 | return -EINVAL; |
| 2108 | } |
| 2109 | |
| 2110 | *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; |
| 2111 | |
| 2112 | return 0; |
| 2113 | } |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 2114 | |
| 2115 | /* Calculate final WFQ values for all vports and configure them. |
| 2116 | * After this configuration each vport will have |
| 2117 | * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) |
| 2118 | */ |
| 2119 | static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, |
| 2120 | struct qed_ptt *p_ptt, |
| 2121 | u32 min_pf_rate) |
| 2122 | { |
| 2123 | struct init_qm_vport_params *vport_params; |
| 2124 | int i; |
| 2125 | |
| 2126 | vport_params = p_hwfn->qm_info.qm_vport_params; |
| 2127 | |
| 2128 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { |
| 2129 | u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; |
| 2130 | |
| 2131 | vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / |
| 2132 | min_pf_rate; |
| 2133 | qed_init_vport_wfq(p_hwfn, p_ptt, |
| 2134 | vport_params[i].first_tx_pq_id, |
| 2135 | vport_params[i].vport_wfq); |
| 2136 | } |
| 2137 | } |
| 2138 | |
| 2139 | static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, |
| 2140 | u32 min_pf_rate) |
| 2141 | |
| 2142 | { |
| 2143 | int i; |
| 2144 | |
| 2145 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) |
| 2146 | p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; |
| 2147 | } |
| 2148 | |
| 2149 | static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, |
| 2150 | struct qed_ptt *p_ptt, |
| 2151 | u32 min_pf_rate) |
| 2152 | { |
| 2153 | struct init_qm_vport_params *vport_params; |
| 2154 | int i; |
| 2155 | |
| 2156 | vport_params = p_hwfn->qm_info.qm_vport_params; |
| 2157 | |
| 2158 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { |
| 2159 | qed_init_wfq_default_param(p_hwfn, min_pf_rate); |
| 2160 | qed_init_vport_wfq(p_hwfn, p_ptt, |
| 2161 | vport_params[i].first_tx_pq_id, |
| 2162 | vport_params[i].vport_wfq); |
| 2163 | } |
| 2164 | } |
| 2165 | |
| 2166 | /* This function performs several validations for WFQ |
| 2167 | * configuration and required min rate for a given vport |
| 2168 | * 1. req_rate must be greater than one percent of min_pf_rate. |
| 2169 | * 2. req_rate should not cause other vports [not configured for WFQ explicitly] |
| 2170 | * rates to get less than one percent of min_pf_rate. |
| 2171 | * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. |
| 2172 | */ |
| 2173 | static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, |
| 2174 | u16 vport_id, u32 req_rate, |
| 2175 | u32 min_pf_rate) |
| 2176 | { |
| 2177 | u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; |
| 2178 | int non_requested_count = 0, req_count = 0, i, num_vports; |
| 2179 | |
| 2180 | num_vports = p_hwfn->qm_info.num_vports; |
| 2181 | |
| 2182 | /* Accounting for the vports which are configured for WFQ explicitly */ |
| 2183 | for (i = 0; i < num_vports; i++) { |
| 2184 | u32 tmp_speed; |
| 2185 | |
| 2186 | if ((i != vport_id) && |
| 2187 | p_hwfn->qm_info.wfq_data[i].configured) { |
| 2188 | req_count++; |
| 2189 | tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; |
| 2190 | total_req_min_rate += tmp_speed; |
| 2191 | } |
| 2192 | } |
| 2193 | |
| 2194 | /* Include current vport data as well */ |
| 2195 | req_count++; |
| 2196 | total_req_min_rate += req_rate; |
| 2197 | non_requested_count = num_vports - req_count; |
| 2198 | |
| 2199 | if (req_rate < min_pf_rate / QED_WFQ_UNIT) { |
| 2200 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 2201 | "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", |
| 2202 | vport_id, req_rate, min_pf_rate); |
| 2203 | return -EINVAL; |
| 2204 | } |
| 2205 | |
| 2206 | if (num_vports > QED_WFQ_UNIT) { |
| 2207 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 2208 | "Number of vports is greater than %d\n", |
| 2209 | QED_WFQ_UNIT); |
| 2210 | return -EINVAL; |
| 2211 | } |
| 2212 | |
| 2213 | if (total_req_min_rate > min_pf_rate) { |
| 2214 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 2215 | "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", |
| 2216 | total_req_min_rate, min_pf_rate); |
| 2217 | return -EINVAL; |
| 2218 | } |
| 2219 | |
| 2220 | total_left_rate = min_pf_rate - total_req_min_rate; |
| 2221 | |
| 2222 | left_rate_per_vp = total_left_rate / non_requested_count; |
| 2223 | if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { |
| 2224 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 2225 | "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", |
| 2226 | left_rate_per_vp, min_pf_rate); |
| 2227 | return -EINVAL; |
| 2228 | } |
| 2229 | |
| 2230 | p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; |
| 2231 | p_hwfn->qm_info.wfq_data[vport_id].configured = true; |
| 2232 | |
| 2233 | for (i = 0; i < num_vports; i++) { |
| 2234 | if (p_hwfn->qm_info.wfq_data[i].configured) |
| 2235 | continue; |
| 2236 | |
| 2237 | p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; |
| 2238 | } |
| 2239 | |
| 2240 | return 0; |
| 2241 | } |
| 2242 | |
Yuval Mintz | 733def6 | 2016-05-11 16:36:22 +0300 | [diff] [blame] | 2243 | static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, |
| 2244 | struct qed_ptt *p_ptt, u16 vp_id, u32 rate) |
| 2245 | { |
| 2246 | struct qed_mcp_link_state *p_link; |
| 2247 | int rc = 0; |
| 2248 | |
| 2249 | p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; |
| 2250 | |
| 2251 | if (!p_link->min_pf_rate) { |
| 2252 | p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; |
| 2253 | p_hwfn->qm_info.wfq_data[vp_id].configured = true; |
| 2254 | return rc; |
| 2255 | } |
| 2256 | |
| 2257 | rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); |
| 2258 | |
| 2259 | if (rc == 0) |
| 2260 | qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, |
| 2261 | p_link->min_pf_rate); |
| 2262 | else |
| 2263 | DP_NOTICE(p_hwfn, |
| 2264 | "Validation failed while configuring min rate\n"); |
| 2265 | |
| 2266 | return rc; |
| 2267 | } |
| 2268 | |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 2269 | static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, |
| 2270 | struct qed_ptt *p_ptt, |
| 2271 | u32 min_pf_rate) |
| 2272 | { |
| 2273 | bool use_wfq = false; |
| 2274 | int rc = 0; |
| 2275 | u16 i; |
| 2276 | |
| 2277 | /* Validate all pre configured vports for wfq */ |
| 2278 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { |
| 2279 | u32 rate; |
| 2280 | |
| 2281 | if (!p_hwfn->qm_info.wfq_data[i].configured) |
| 2282 | continue; |
| 2283 | |
| 2284 | rate = p_hwfn->qm_info.wfq_data[i].min_speed; |
| 2285 | use_wfq = true; |
| 2286 | |
| 2287 | rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); |
| 2288 | if (rc) { |
| 2289 | DP_NOTICE(p_hwfn, |
| 2290 | "WFQ validation failed while configuring min rate\n"); |
| 2291 | break; |
| 2292 | } |
| 2293 | } |
| 2294 | |
| 2295 | if (!rc && use_wfq) |
| 2296 | qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); |
| 2297 | else |
| 2298 | qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); |
| 2299 | |
| 2300 | return rc; |
| 2301 | } |
| 2302 | |
Yuval Mintz | 733def6 | 2016-05-11 16:36:22 +0300 | [diff] [blame] | 2303 | /* Main API for qed clients to configure vport min rate. |
| 2304 | * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] |
| 2305 | * rate - Speed in Mbps needs to be assigned to a given vport. |
| 2306 | */ |
| 2307 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) |
| 2308 | { |
| 2309 | int i, rc = -EINVAL; |
| 2310 | |
| 2311 | /* Currently not supported; Might change in future */ |
| 2312 | if (cdev->num_hwfns > 1) { |
| 2313 | DP_NOTICE(cdev, |
| 2314 | "WFQ configuration is not supported for this device\n"); |
| 2315 | return rc; |
| 2316 | } |
| 2317 | |
| 2318 | for_each_hwfn(cdev, i) { |
| 2319 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 2320 | struct qed_ptt *p_ptt; |
| 2321 | |
| 2322 | p_ptt = qed_ptt_acquire(p_hwfn); |
| 2323 | if (!p_ptt) |
| 2324 | return -EBUSY; |
| 2325 | |
| 2326 | rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); |
| 2327 | |
| 2328 | if (!rc) { |
| 2329 | qed_ptt_release(p_hwfn, p_ptt); |
| 2330 | return rc; |
| 2331 | } |
| 2332 | |
| 2333 | qed_ptt_release(p_hwfn, p_ptt); |
| 2334 | } |
| 2335 | |
| 2336 | return rc; |
| 2337 | } |
| 2338 | |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 2339 | /* API to configure WFQ from mcp link change */ |
| 2340 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) |
| 2341 | { |
| 2342 | int i; |
| 2343 | |
Yuval Mintz | 3e7cfce | 2016-05-26 11:01:24 +0300 | [diff] [blame] | 2344 | if (cdev->num_hwfns > 1) { |
| 2345 | DP_VERBOSE(cdev, |
| 2346 | NETIF_MSG_LINK, |
| 2347 | "WFQ configuration is not supported for this device\n"); |
| 2348 | return; |
| 2349 | } |
| 2350 | |
Manish Chopra | bcd197c | 2016-04-26 10:56:08 -0400 | [diff] [blame] | 2351 | for_each_hwfn(cdev, i) { |
| 2352 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 2353 | |
| 2354 | __qed_configure_vp_wfq_on_link_change(p_hwfn, |
| 2355 | p_hwfn->p_dpc_ptt, |
| 2356 | min_pf_rate); |
| 2357 | } |
| 2358 | } |
Manish Chopra | 4b01e51 | 2016-04-26 10:56:09 -0400 | [diff] [blame] | 2359 | |
| 2360 | int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, |
| 2361 | struct qed_ptt *p_ptt, |
| 2362 | struct qed_mcp_link_state *p_link, |
| 2363 | u8 max_bw) |
| 2364 | { |
| 2365 | int rc = 0; |
| 2366 | |
| 2367 | p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; |
| 2368 | |
| 2369 | if (!p_link->line_speed && (max_bw != 100)) |
| 2370 | return rc; |
| 2371 | |
| 2372 | p_link->speed = (p_link->line_speed * max_bw) / 100; |
| 2373 | p_hwfn->qm_info.pf_rl = p_link->speed; |
| 2374 | |
| 2375 | /* Since the limiter also affects Tx-switched traffic, we don't want it |
| 2376 | * to limit such traffic in case there's no actual limit. |
| 2377 | * In that case, set limit to imaginary high boundary. |
| 2378 | */ |
| 2379 | if (max_bw == 100) |
| 2380 | p_hwfn->qm_info.pf_rl = 100000; |
| 2381 | |
| 2382 | rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, |
| 2383 | p_hwfn->qm_info.pf_rl); |
| 2384 | |
| 2385 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 2386 | "Configured MAX bandwidth to be %08x Mb/sec\n", |
| 2387 | p_link->speed); |
| 2388 | |
| 2389 | return rc; |
| 2390 | } |
| 2391 | |
| 2392 | /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ |
| 2393 | int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) |
| 2394 | { |
| 2395 | int i, rc = -EINVAL; |
| 2396 | |
| 2397 | if (max_bw < 1 || max_bw > 100) { |
| 2398 | DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); |
| 2399 | return rc; |
| 2400 | } |
| 2401 | |
| 2402 | for_each_hwfn(cdev, i) { |
| 2403 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 2404 | struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); |
| 2405 | struct qed_mcp_link_state *p_link; |
| 2406 | struct qed_ptt *p_ptt; |
| 2407 | |
| 2408 | p_link = &p_lead->mcp_info->link_output; |
| 2409 | |
| 2410 | p_ptt = qed_ptt_acquire(p_hwfn); |
| 2411 | if (!p_ptt) |
| 2412 | return -EBUSY; |
| 2413 | |
| 2414 | rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, |
| 2415 | p_link, max_bw); |
| 2416 | |
| 2417 | qed_ptt_release(p_hwfn, p_ptt); |
| 2418 | |
| 2419 | if (rc) |
| 2420 | break; |
| 2421 | } |
| 2422 | |
| 2423 | return rc; |
| 2424 | } |
Manish Chopra | a64b02d | 2016-04-26 10:56:10 -0400 | [diff] [blame] | 2425 | |
| 2426 | int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, |
| 2427 | struct qed_ptt *p_ptt, |
| 2428 | struct qed_mcp_link_state *p_link, |
| 2429 | u8 min_bw) |
| 2430 | { |
| 2431 | int rc = 0; |
| 2432 | |
| 2433 | p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; |
| 2434 | p_hwfn->qm_info.pf_wfq = min_bw; |
| 2435 | |
| 2436 | if (!p_link->line_speed) |
| 2437 | return rc; |
| 2438 | |
| 2439 | p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; |
| 2440 | |
| 2441 | rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); |
| 2442 | |
| 2443 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, |
| 2444 | "Configured MIN bandwidth to be %d Mb/sec\n", |
| 2445 | p_link->min_pf_rate); |
| 2446 | |
| 2447 | return rc; |
| 2448 | } |
| 2449 | |
| 2450 | /* Main API to configure PF min bandwidth where bw range is [1-100] */ |
| 2451 | int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) |
| 2452 | { |
| 2453 | int i, rc = -EINVAL; |
| 2454 | |
| 2455 | if (min_bw < 1 || min_bw > 100) { |
| 2456 | DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); |
| 2457 | return rc; |
| 2458 | } |
| 2459 | |
| 2460 | for_each_hwfn(cdev, i) { |
| 2461 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
| 2462 | struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); |
| 2463 | struct qed_mcp_link_state *p_link; |
| 2464 | struct qed_ptt *p_ptt; |
| 2465 | |
| 2466 | p_link = &p_lead->mcp_info->link_output; |
| 2467 | |
| 2468 | p_ptt = qed_ptt_acquire(p_hwfn); |
| 2469 | if (!p_ptt) |
| 2470 | return -EBUSY; |
| 2471 | |
| 2472 | rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, |
| 2473 | p_link, min_bw); |
| 2474 | if (rc) { |
| 2475 | qed_ptt_release(p_hwfn, p_ptt); |
| 2476 | return rc; |
| 2477 | } |
| 2478 | |
| 2479 | if (p_link->min_pf_rate) { |
| 2480 | u32 min_rate = p_link->min_pf_rate; |
| 2481 | |
| 2482 | rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, |
| 2483 | p_ptt, |
| 2484 | min_rate); |
| 2485 | } |
| 2486 | |
| 2487 | qed_ptt_release(p_hwfn, p_ptt); |
| 2488 | } |
| 2489 | |
| 2490 | return rc; |
| 2491 | } |
Yuval Mintz | 733def6 | 2016-05-11 16:36:22 +0300 | [diff] [blame] | 2492 | |
| 2493 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
| 2494 | { |
| 2495 | struct qed_mcp_link_state *p_link; |
| 2496 | |
| 2497 | p_link = &p_hwfn->mcp_info->link_output; |
| 2498 | |
| 2499 | if (p_link->min_pf_rate) |
| 2500 | qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, |
| 2501 | p_link->min_pf_rate); |
| 2502 | |
| 2503 | memset(p_hwfn->qm_info.wfq_data, 0, |
| 2504 | sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); |
| 2505 | } |