Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Low-level exception handling code |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Ltd. |
| 5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> |
| 6 | * Will Deacon <will.deacon@arm.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
Marc Zyngier | be331630 | 2018-07-20 10:56:22 +0100 | [diff] [blame] | 21 | #include <linux/arm-smccc.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 22 | #include <linux/init.h> |
| 23 | #include <linux/linkage.h> |
| 24 | |
Marc Zyngier | 8d883b2 | 2015-06-01 10:47:41 +0100 | [diff] [blame] | 25 | #include <asm/alternative.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 26 | #include <asm/assembler.h> |
| 27 | #include <asm/asm-offsets.h> |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 28 | #include <asm/cpufeature.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 29 | #include <asm/errno.h> |
Marc Zyngier | 5c1ce6f | 2013-04-08 17:17:03 +0100 | [diff] [blame] | 30 | #include <asm/esr.h> |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 31 | #include <asm/irq.h> |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 32 | #include <asm/memory.h> |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 33 | #include <asm/mmu.h> |
Mark Rutland | 27eeced | 2018-04-12 12:10:59 +0100 | [diff] [blame] | 34 | #include <asm/processor.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 35 | #include <asm/ptrace.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 36 | #include <asm/thread_info.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 37 | #include <asm/uaccess.h> |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 38 | #include <asm/asm-uaccess.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 39 | #include <asm/unistd.h> |
Will Deacon | 78a0cec | 2018-04-03 12:09:04 +0100 | [diff] [blame] | 40 | #include <asm/kernel-pgtable.h> |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 41 | |
| 42 | /* |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 43 | * Context tracking subsystem. Used to instrument transitions |
| 44 | * between user and kernel mode. |
| 45 | */ |
| 46 | .macro ct_user_exit, syscall = 0 |
| 47 | #ifdef CONFIG_CONTEXT_TRACKING |
| 48 | bl context_tracking_user_exit |
| 49 | .if \syscall == 1 |
| 50 | /* |
| 51 | * Save/restore needed during syscalls. Restore syscall arguments from |
| 52 | * the values already saved on stack during kernel_entry. |
| 53 | */ |
| 54 | ldp x0, x1, [sp] |
| 55 | ldp x2, x3, [sp, #S_X2] |
| 56 | ldp x4, x5, [sp, #S_X4] |
| 57 | ldp x6, x7, [sp, #S_X6] |
| 58 | .endif |
| 59 | #endif |
| 60 | .endm |
| 61 | |
| 62 | .macro ct_user_enter |
| 63 | #ifdef CONFIG_CONTEXT_TRACKING |
| 64 | bl context_tracking_user_enter |
| 65 | #endif |
| 66 | .endm |
| 67 | |
| 68 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 69 | * Bad Abort numbers |
| 70 | *----------------- |
| 71 | */ |
| 72 | #define BAD_SYNC 0 |
| 73 | #define BAD_IRQ 1 |
| 74 | #define BAD_FIQ 2 |
| 75 | #define BAD_ERROR 3 |
| 76 | |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 77 | .macro kernel_ventry, el, label, regsize = 64 |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 78 | .align 7 |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 79 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 80 | alternative_if ARM64_UNMAP_KERNEL_AT_EL0 |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 81 | .if \el == 0 |
| 82 | .if \regsize == 64 |
| 83 | mrs x30, tpidrro_el0 |
| 84 | msr tpidrro_el0, xzr |
| 85 | .else |
| 86 | mov x30, xzr |
| 87 | .endif |
| 88 | .endif |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 89 | alternative_else_nop_endif |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 90 | #endif |
| 91 | |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 92 | sub sp, sp, #S_FRAME_SIZE |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 93 | b el\()\el\()_\label |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 94 | .endm |
| 95 | |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 96 | .macro tramp_alias, dst, sym |
| 97 | mov_q \dst, TRAMP_VALIAS |
| 98 | add \dst, \dst, #(\sym - .entry.tramp.text) |
| 99 | .endm |
| 100 | |
Marc Zyngier | be331630 | 2018-07-20 10:56:22 +0100 | [diff] [blame] | 101 | // This macro corrupts x0-x3. It is the caller's duty |
| 102 | // to save/restore them if required. |
Marc Zyngier | d8174bd | 2018-07-20 10:56:23 +0100 | [diff] [blame] | 103 | .macro apply_ssbd, state, targ, tmp1, tmp2 |
Marc Zyngier | be331630 | 2018-07-20 10:56:22 +0100 | [diff] [blame] | 104 | #ifdef CONFIG_ARM64_SSBD |
Marc Zyngier | 42f967d | 2018-07-20 10:56:27 +0100 | [diff] [blame] | 105 | alternative_cb arm64_enable_wa2_handling |
| 106 | b \targ |
| 107 | alternative_cb_end |
Marc Zyngier | d8174bd | 2018-07-20 10:56:23 +0100 | [diff] [blame] | 108 | ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 |
| 109 | cbz \tmp2, \targ |
Amit Pundir | 0137ea2 | 2018-08-01 10:20:28 +0530 | [diff] [blame] | 110 | ldr \tmp2, [tsk, #TSK_TI_FLAGS] |
Marc Zyngier | cf14b89 | 2018-07-20 10:56:29 +0100 | [diff] [blame] | 111 | tbnz \tmp2, #TIF_SSBD, \targ |
Marc Zyngier | be331630 | 2018-07-20 10:56:22 +0100 | [diff] [blame] | 112 | mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 |
| 113 | mov w1, #\state |
| 114 | alternative_cb arm64_update_smccc_conduit |
| 115 | nop // Patched to SMC/HVC #0 |
| 116 | alternative_cb_end |
| 117 | #endif |
| 118 | .endm |
| 119 | |
Mark Rutland | 17d3592 | 2017-07-19 17:24:49 +0100 | [diff] [blame] | 120 | .macro kernel_entry, el, regsize = 64 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 121 | .if \regsize == 32 |
| 122 | mov w0, w0 // zero upper 32 bits of x0 |
| 123 | .endif |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 124 | stp x0, x1, [sp, #16 * 0] |
| 125 | stp x2, x3, [sp, #16 * 1] |
| 126 | stp x4, x5, [sp, #16 * 2] |
| 127 | stp x6, x7, [sp, #16 * 3] |
| 128 | stp x8, x9, [sp, #16 * 4] |
| 129 | stp x10, x11, [sp, #16 * 5] |
| 130 | stp x12, x13, [sp, #16 * 6] |
| 131 | stp x14, x15, [sp, #16 * 7] |
| 132 | stp x16, x17, [sp, #16 * 8] |
| 133 | stp x18, x19, [sp, #16 * 9] |
| 134 | stp x20, x21, [sp, #16 * 10] |
| 135 | stp x22, x23, [sp, #16 * 11] |
| 136 | stp x24, x25, [sp, #16 * 12] |
| 137 | stp x26, x27, [sp, #16 * 13] |
| 138 | stp x28, x29, [sp, #16 * 14] |
| 139 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 140 | .if \el == 0 |
| 141 | mrs x21, sp_el0 |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 142 | ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, |
| 143 | ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 144 | disable_step_tsk x19, x20 // exceptions when scheduling. |
James Morse | 49003a8 | 2015-12-10 10:22:41 +0000 | [diff] [blame] | 145 | |
Marc Zyngier | d8174bd | 2018-07-20 10:56:23 +0100 | [diff] [blame] | 146 | apply_ssbd 1, 1f, x22, x23 |
Marc Zyngier | be331630 | 2018-07-20 10:56:22 +0100 | [diff] [blame] | 147 | |
| 148 | #ifdef CONFIG_ARM64_SSBD |
| 149 | ldp x0, x1, [sp, #16 * 0] |
| 150 | ldp x2, x3, [sp, #16 * 1] |
| 151 | #endif |
Marc Zyngier | d8174bd | 2018-07-20 10:56:23 +0100 | [diff] [blame] | 152 | 1: |
Marc Zyngier | be331630 | 2018-07-20 10:56:22 +0100 | [diff] [blame] | 153 | |
James Morse | 49003a8 | 2015-12-10 10:22:41 +0000 | [diff] [blame] | 154 | mov x29, xzr // fp pointed to user-space |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 155 | .else |
| 156 | add x21, sp, #S_FRAME_SIZE |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 157 | get_thread_info tsk |
Mark Rutland | c910086 | 2018-04-12 12:11:00 +0100 | [diff] [blame] | 158 | /* Save the task's original addr_limit and set USER_DS */ |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 159 | ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 160 | str x20, [sp, #S_ORIG_ADDR_LIMIT] |
Mark Rutland | c910086 | 2018-04-12 12:11:00 +0100 | [diff] [blame] | 161 | mov x20, #USER_DS |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 162 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
Vladimir Murzin | 563cada | 2016-09-01 14:35:59 +0100 | [diff] [blame] | 163 | /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 164 | .endif /* \el == 0 */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 165 | mrs x22, elr_el1 |
| 166 | mrs x23, spsr_el1 |
| 167 | stp lr, x21, [sp, #S_LR] |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 168 | |
| 169 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 170 | /* |
| 171 | * Set the TTBR0 PAN bit in SPSR. When the exception is taken from |
| 172 | * EL0, there is no need to check the state of TTBR0_EL1 since |
| 173 | * accesses are always enabled. |
| 174 | * Note that the meaning of this bit differs from the ARMv8.1 PAN |
| 175 | * feature as all TTBR0_EL1 accesses are disabled, not just those to |
| 176 | * user mappings. |
| 177 | */ |
| 178 | alternative_if ARM64_HAS_PAN |
| 179 | b 1f // skip TTBR0 PAN |
| 180 | alternative_else_nop_endif |
| 181 | |
| 182 | .if \el != 0 |
Catalin Marinas | 8788313 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 183 | mrs x21, ttbr0_el1 |
Will Deacon | d7013ed | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 184 | tst x21, #TTBR_ASID_MASK // Check for the reserved ASID |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 185 | orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR |
| 186 | b.eq 1f // TTBR0 access already disabled |
| 187 | and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR |
| 188 | .endif |
| 189 | |
| 190 | __uaccess_ttbr0_disable x21 |
| 191 | 1: |
| 192 | #endif |
| 193 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 194 | stp x22, x23, [sp, #S_PC] |
| 195 | |
| 196 | /* |
| 197 | * Set syscallno to -1 by default (overridden later if real syscall). |
| 198 | */ |
| 199 | .if \el == 0 |
| 200 | mvn x21, xzr |
| 201 | str x21, [sp, #S_SYSCALLNO] |
| 202 | .endif |
| 203 | |
| 204 | /* |
Jungseok Lee | 6cdf9c7 | 2015-12-04 11:02:25 +0000 | [diff] [blame] | 205 | * Set sp_el0 to current thread_info. |
| 206 | */ |
| 207 | .if \el == 0 |
| 208 | msr sp_el0, tsk |
| 209 | .endif |
| 210 | |
| 211 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 212 | * Registers that may be useful after this macro is invoked: |
| 213 | * |
| 214 | * x21 - aborted SP |
| 215 | * x22 - aborted PC |
| 216 | * x23 - aborted PSTATE |
| 217 | */ |
| 218 | .endm |
| 219 | |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 220 | .macro kernel_exit, el |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 221 | .if \el != 0 |
| 222 | /* Restore the task's original addr_limit. */ |
| 223 | ldr x20, [sp, #S_ORIG_ADDR_LIMIT] |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 224 | str x20, [tsk, #TSK_TI_ADDR_LIMIT] |
James Morse | e19a6ee | 2016-06-20 18:28:01 +0100 | [diff] [blame] | 225 | |
| 226 | /* No need to restore UAO, it will be restored from SPSR_EL1 */ |
| 227 | .endif |
| 228 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 229 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
| 230 | .if \el == 0 |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 231 | ct_user_enter |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 232 | .endif |
| 233 | |
| 234 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 235 | /* |
| 236 | * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR |
| 237 | * PAN bit checking. |
| 238 | */ |
| 239 | alternative_if ARM64_HAS_PAN |
| 240 | b 2f // skip TTBR0 PAN |
| 241 | alternative_else_nop_endif |
| 242 | |
| 243 | .if \el != 0 |
| 244 | tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set |
| 245 | .endif |
| 246 | |
Will Deacon | 599c71f | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 247 | __uaccess_ttbr0_enable x0, x1 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 248 | |
| 249 | .if \el == 0 |
| 250 | /* |
| 251 | * Enable errata workarounds only if returning to user. The only |
| 252 | * workaround currently required for TTBR0_EL1 changes are for the |
| 253 | * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache |
| 254 | * corruption). |
| 255 | */ |
Marc Zyngier | 95bfec6 | 2018-01-02 18:19:39 +0000 | [diff] [blame] | 256 | bl post_ttbr_update_workaround |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 257 | .endif |
| 258 | 1: |
| 259 | .if \el != 0 |
| 260 | and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit |
| 261 | .endif |
| 262 | 2: |
| 263 | #endif |
| 264 | |
| 265 | .if \el == 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 266 | ldr x23, [sp, #S_SP] // load return stack pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 267 | msr sp_el0, x23 |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 268 | tst x22, #PSR_MODE32_BIT // native task? |
| 269 | b.eq 3f |
| 270 | |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 271 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 272 | alternative_if ARM64_WORKAROUND_845719 |
Daniel Thompson | e28cabf | 2015-07-22 12:21:03 +0100 | [diff] [blame] | 273 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
| 274 | mrs x29, contextidr_el1 |
| 275 | msr contextidr_el1, x29 |
| 276 | #else |
| 277 | msr contextidr_el1, xzr |
| 278 | #endif |
Mark Rutland | 6ba3b55 | 2016-09-07 11:07:09 +0100 | [diff] [blame] | 279 | alternative_else_nop_endif |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 280 | #endif |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 281 | 3: |
Marc Zyngier | d8174bd | 2018-07-20 10:56:23 +0100 | [diff] [blame] | 282 | apply_ssbd 0, 5f, x0, x1 |
| 283 | 5: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 284 | .endif |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 285 | |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 286 | msr elr_el1, x21 // set up the return data |
| 287 | msr spsr_el1, x22 |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 288 | ldp x0, x1, [sp, #16 * 0] |
Will Deacon | 63648dd | 2014-09-29 12:26:41 +0100 | [diff] [blame] | 289 | ldp x2, x3, [sp, #16 * 1] |
| 290 | ldp x4, x5, [sp, #16 * 2] |
| 291 | ldp x6, x7, [sp, #16 * 3] |
| 292 | ldp x8, x9, [sp, #16 * 4] |
| 293 | ldp x10, x11, [sp, #16 * 5] |
| 294 | ldp x12, x13, [sp, #16 * 6] |
| 295 | ldp x14, x15, [sp, #16 * 7] |
| 296 | ldp x16, x17, [sp, #16 * 8] |
| 297 | ldp x18, x19, [sp, #16 * 9] |
| 298 | ldp x20, x21, [sp, #16 * 10] |
| 299 | ldp x22, x23, [sp, #16 * 11] |
| 300 | ldp x24, x25, [sp, #16 * 12] |
| 301 | ldp x26, x27, [sp, #16 * 13] |
| 302 | ldp x28, x29, [sp, #16 * 14] |
| 303 | ldr lr, [sp, #S_LR] |
| 304 | add sp, sp, #S_FRAME_SIZE // restore sp |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 305 | |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 306 | .if \el == 0 |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 307 | alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 |
| 308 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 309 | bne 4f |
| 310 | msr far_el1, x30 |
| 311 | tramp_alias x30, tramp_exit_native |
| 312 | br x30 |
| 313 | 4: |
| 314 | tramp_alias x30, tramp_exit_compat |
| 315 | br x30 |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 316 | #endif |
Will Deacon | c27a2258 | 2017-11-14 14:24:29 +0000 | [diff] [blame] | 317 | .else |
| 318 | eret |
| 319 | .endif |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 320 | .endm |
| 321 | |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 322 | .macro irq_stack_entry |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 323 | mov x19, sp // preserve the original sp |
| 324 | |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 325 | /* |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 326 | * Compare sp with the base of the task stack. |
| 327 | * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, |
| 328 | * and should switch to the irq stack. |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 329 | */ |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 330 | ldr x25, [tsk, TSK_STACK] |
| 331 | eor x25, x25, x19 |
| 332 | and x25, x25, #~(THREAD_SIZE - 1) |
| 333 | cbnz x25, 9998f |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 334 | |
Mark Rutland | 8b6c9c9 | 2016-11-03 20:23:12 +0000 | [diff] [blame] | 335 | adr_this_cpu x25, irq_stack, x26 |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 336 | mov x26, #IRQ_STACK_START_SP |
| 337 | add x26, x25, x26 |
James Morse | d224a69 | 2015-12-18 16:01:47 +0000 | [diff] [blame] | 338 | |
| 339 | /* switch to the irq stack */ |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 340 | mov sp, x26 |
| 341 | |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 342 | /* |
| 343 | * Add a dummy stack frame, this non-standard format is fixed up |
| 344 | * by unwind_frame() |
| 345 | */ |
| 346 | stp x29, x19, [sp, #-16]! |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 347 | mov x29, sp |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 348 | |
| 349 | 9998: |
| 350 | .endm |
| 351 | |
| 352 | /* |
| 353 | * x19 should be preserved between irq_stack_entry and |
| 354 | * irq_stack_exit. |
| 355 | */ |
| 356 | .macro irq_stack_exit |
| 357 | mov sp, x19 |
| 358 | .endm |
| 359 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 360 | /* |
| 361 | * These are the registers used in the syscall handler, and allow us to |
| 362 | * have in theory up to 7 arguments to a function - x0 to x6. |
| 363 | * |
| 364 | * x7 is reserved for the system call number in 32-bit mode. |
| 365 | */ |
| 366 | sc_nr .req x25 // number of system calls |
| 367 | scno .req x26 // syscall number |
| 368 | stbl .req x27 // syscall table pointer |
| 369 | tsk .req x28 // current thread_info |
| 370 | |
| 371 | /* |
| 372 | * Interrupt handling. |
| 373 | */ |
| 374 | .macro irq_handler |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 375 | ldr_l x1, handle_arch_irq |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 376 | mov x0, sp |
James Morse | 971c67c | 2015-12-15 11:21:25 +0000 | [diff] [blame] | 377 | irq_stack_entry |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 378 | blr x1 |
James Morse | 8e23dac | 2015-12-04 11:02:27 +0000 | [diff] [blame] | 379 | irq_stack_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 380 | .endm |
| 381 | |
| 382 | .text |
| 383 | |
| 384 | /* |
| 385 | * Exception vectors. |
| 386 | */ |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 387 | .pushsection ".entry.text", "ax" |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 388 | |
| 389 | .align 11 |
| 390 | ENTRY(vectors) |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 391 | kernel_ventry 1, sync_invalid // Synchronous EL1t |
| 392 | kernel_ventry 1, irq_invalid // IRQ EL1t |
| 393 | kernel_ventry 1, fiq_invalid // FIQ EL1t |
| 394 | kernel_ventry 1, error_invalid // Error EL1t |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 395 | |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 396 | kernel_ventry 1, sync // Synchronous EL1h |
| 397 | kernel_ventry 1, irq // IRQ EL1h |
| 398 | kernel_ventry 1, fiq_invalid // FIQ EL1h |
| 399 | kernel_ventry 1, error_invalid // Error EL1h |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 400 | |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 401 | kernel_ventry 0, sync // Synchronous 64-bit EL0 |
| 402 | kernel_ventry 0, irq // IRQ 64-bit EL0 |
| 403 | kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 |
| 404 | kernel_ventry 0, error_invalid // Error 64-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 405 | |
| 406 | #ifdef CONFIG_COMPAT |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 407 | kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 |
| 408 | kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 |
| 409 | kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 |
| 410 | kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 411 | #else |
Will Deacon | 8fdbffb | 2017-11-14 14:20:21 +0000 | [diff] [blame] | 412 | kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 |
| 413 | kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 |
| 414 | kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 |
| 415 | kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 416 | #endif |
| 417 | END(vectors) |
| 418 | |
| 419 | /* |
| 420 | * Invalid mode handlers |
| 421 | */ |
| 422 | .macro inv_entry, el, reason, regsize = 64 |
Ard Biesheuvel | b660950 | 2016-03-18 10:58:09 +0100 | [diff] [blame] | 423 | kernel_entry \el, \regsize |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 424 | mov x0, sp |
| 425 | mov x1, #\reason |
| 426 | mrs x2, esr_el1 |
| 427 | b bad_mode |
| 428 | .endm |
| 429 | |
| 430 | el0_sync_invalid: |
| 431 | inv_entry 0, BAD_SYNC |
| 432 | ENDPROC(el0_sync_invalid) |
| 433 | |
| 434 | el0_irq_invalid: |
| 435 | inv_entry 0, BAD_IRQ |
| 436 | ENDPROC(el0_irq_invalid) |
| 437 | |
| 438 | el0_fiq_invalid: |
| 439 | inv_entry 0, BAD_FIQ |
| 440 | ENDPROC(el0_fiq_invalid) |
| 441 | |
| 442 | el0_error_invalid: |
| 443 | inv_entry 0, BAD_ERROR |
| 444 | ENDPROC(el0_error_invalid) |
| 445 | |
| 446 | #ifdef CONFIG_COMPAT |
| 447 | el0_fiq_invalid_compat: |
| 448 | inv_entry 0, BAD_FIQ, 32 |
| 449 | ENDPROC(el0_fiq_invalid_compat) |
| 450 | |
| 451 | el0_error_invalid_compat: |
| 452 | inv_entry 0, BAD_ERROR, 32 |
| 453 | ENDPROC(el0_error_invalid_compat) |
| 454 | #endif |
| 455 | |
| 456 | el1_sync_invalid: |
| 457 | inv_entry 1, BAD_SYNC |
| 458 | ENDPROC(el1_sync_invalid) |
| 459 | |
| 460 | el1_irq_invalid: |
| 461 | inv_entry 1, BAD_IRQ |
| 462 | ENDPROC(el1_irq_invalid) |
| 463 | |
| 464 | el1_fiq_invalid: |
| 465 | inv_entry 1, BAD_FIQ |
| 466 | ENDPROC(el1_fiq_invalid) |
| 467 | |
| 468 | el1_error_invalid: |
| 469 | inv_entry 1, BAD_ERROR |
| 470 | ENDPROC(el1_error_invalid) |
| 471 | |
| 472 | /* |
| 473 | * EL1 mode handlers. |
| 474 | */ |
| 475 | .align 6 |
| 476 | el1_sync: |
| 477 | kernel_entry 1 |
| 478 | mrs x1, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 479 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
| 480 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 481 | b.eq el1_da |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 482 | cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 |
| 483 | b.eq el1_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 484 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 485 | b.eq el1_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 486 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 487 | b.eq el1_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 488 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 489 | b.eq el1_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 490 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 491 | b.eq el1_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 492 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 493 | b.ge el1_dbg |
| 494 | b el1_inv |
Laura Abbott | 9adeb8e | 2016-08-09 18:25:26 -0700 | [diff] [blame] | 495 | |
| 496 | el1_ia: |
| 497 | /* |
| 498 | * Fall through to the Data abort case |
| 499 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 500 | el1_da: |
| 501 | /* |
| 502 | * Data abort handling |
| 503 | */ |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 504 | mrs x3, far_el1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 505 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 506 | // re-enable interrupts if they were enabled in the aborted context |
| 507 | tbnz x23, #7, 1f // PSR_I_BIT |
| 508 | enable_irq |
| 509 | 1: |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 510 | clear_address_tag x0, x3 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 511 | mov x2, sp // struct pt_regs |
| 512 | bl do_mem_abort |
| 513 | |
| 514 | // disable interrupts before pulling preserved data off the stack |
| 515 | disable_irq |
| 516 | kernel_exit 1 |
| 517 | el1_sp_pc: |
| 518 | /* |
| 519 | * Stack or PC alignment exception handling |
| 520 | */ |
| 521 | mrs x0, far_el1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 522 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 523 | mov x2, sp |
| 524 | b do_sp_pc_abort |
| 525 | el1_undef: |
| 526 | /* |
| 527 | * Undefined instruction |
| 528 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 529 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 530 | mov x0, sp |
| 531 | b do_undefinstr |
| 532 | el1_dbg: |
| 533 | /* |
| 534 | * Debug exception handling |
| 535 | */ |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 536 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
Sandeepa Prabhu | ee6214c | 2013-12-04 05:50:20 +0000 | [diff] [blame] | 537 | cinc x24, x24, eq // set bit '0' |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 538 | tbz x24, #0, el1_inv // EL1 only |
| 539 | mrs x0, far_el1 |
| 540 | mov x2, sp // struct pt_regs |
| 541 | bl do_debug_exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 542 | kernel_exit 1 |
| 543 | el1_inv: |
| 544 | // TODO: add support for undefined instructions in kernel mode |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 545 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 546 | mov x0, sp |
Mark Rutland | 1b42804 | 2015-07-07 18:00:49 +0100 | [diff] [blame] | 547 | mov x2, x1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 548 | mov x1, #BAD_SYNC |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 549 | b bad_mode |
| 550 | ENDPROC(el1_sync) |
| 551 | |
| 552 | .align 6 |
| 553 | el1_irq: |
| 554 | kernel_entry 1 |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 555 | enable_dbg |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 556 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 557 | bl trace_hardirqs_off |
| 558 | #endif |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 559 | |
| 560 | irq_handler |
| 561 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 562 | #ifdef CONFIG_PREEMPT |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 563 | ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count |
Marc Zyngier | 717321f | 2013-11-04 20:14:58 +0000 | [diff] [blame] | 564 | cbnz w24, 1f // preempt count != 0 |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 565 | ldr x0, [tsk, #TSK_TI_FLAGS] // get flags |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 566 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
| 567 | bl el1_preempt |
| 568 | 1: |
| 569 | #endif |
| 570 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 571 | bl trace_hardirqs_on |
| 572 | #endif |
| 573 | kernel_exit 1 |
| 574 | ENDPROC(el1_irq) |
| 575 | |
| 576 | #ifdef CONFIG_PREEMPT |
| 577 | el1_preempt: |
| 578 | mov x24, lr |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 579 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 580 | ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 581 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? |
| 582 | ret x24 |
| 583 | #endif |
| 584 | |
| 585 | /* |
| 586 | * EL0 mode handlers. |
| 587 | */ |
| 588 | .align 6 |
| 589 | el0_sync: |
| 590 | kernel_entry 0 |
| 591 | mrs x25, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 592 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
| 593 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 594 | b.eq el0_svc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 595 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 596 | b.eq el0_da |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 597 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 598 | b.eq el0_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 599 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 600 | b.eq el0_fpsimd_acc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 601 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 602 | b.eq el0_fpsimd_exc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 603 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 604 | b.eq el0_sys |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 605 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 606 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 607 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 608 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 609 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 610 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 611 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 612 | b.ge el0_dbg |
| 613 | b el0_inv |
| 614 | |
| 615 | #ifdef CONFIG_COMPAT |
| 616 | .align 6 |
| 617 | el0_sync_compat: |
| 618 | kernel_entry 0, 32 |
| 619 | mrs x25, esr_el1 // read the syndrome register |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 620 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
| 621 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 622 | b.eq el0_svc_compat |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 623 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 624 | b.eq el0_da |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 625 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 626 | b.eq el0_ia |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 627 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 628 | b.eq el0_fpsimd_acc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 629 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 630 | b.eq el0_fpsimd_exc |
Mark Salyzyn | 77f3228f | 2015-10-13 14:30:51 -0700 | [diff] [blame] | 631 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
| 632 | b.eq el0_sp_pc |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 633 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 634 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 635 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 636 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 637 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 638 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 639 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 640 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 641 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 642 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 643 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
Mark Rutland | 381cc2b | 2013-05-24 12:02:35 +0100 | [diff] [blame] | 644 | b.eq el0_undef |
Mark Rutland | aed40e0 | 2014-11-24 12:31:40 +0000 | [diff] [blame] | 645 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 646 | b.ge el0_dbg |
| 647 | b el0_inv |
| 648 | el0_svc_compat: |
| 649 | /* |
| 650 | * AArch32 syscall handling |
| 651 | */ |
Catalin Marinas | 0156411 | 2015-01-06 16:42:32 +0000 | [diff] [blame] | 652 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 653 | uxtw scno, w7 // syscall number in w7 (r7) |
| 654 | mov sc_nr, #__NR_compat_syscalls |
| 655 | b el0_svc_naked |
| 656 | |
| 657 | .align 6 |
| 658 | el0_irq_compat: |
| 659 | kernel_entry 0, 32 |
| 660 | b el0_irq_naked |
| 661 | #endif |
| 662 | |
| 663 | el0_da: |
| 664 | /* |
| 665 | * Data abort handling |
| 666 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 667 | mrs x26, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 668 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 669 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 670 | ct_user_exit |
Kristina Martsenko | 9e09d90 | 2017-06-06 20:14:10 +0100 | [diff] [blame] | 671 | clear_address_tag x0, x26 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 672 | mov x1, x25 |
| 673 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 674 | bl do_mem_abort |
| 675 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 676 | el0_ia: |
| 677 | /* |
| 678 | * Instruction abort handling |
| 679 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 680 | mrs x26, far_el1 |
Mark Rutland | 4732001 | 2018-04-12 12:11:13 +0100 | [diff] [blame] | 681 | msr daifclr, #(8 | 4 | 1) |
| 682 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 683 | bl trace_hardirqs_off |
| 684 | #endif |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 685 | ct_user_exit |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 686 | mov x0, x26 |
Mark Rutland | 541ec87 | 2016-05-31 12:33:03 +0100 | [diff] [blame] | 687 | mov x1, x25 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 688 | mov x2, sp |
Mark Rutland | 4732001 | 2018-04-12 12:11:13 +0100 | [diff] [blame] | 689 | bl do_el0_ia_bp_hardening |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 690 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 691 | el0_fpsimd_acc: |
| 692 | /* |
| 693 | * Floating Point or Advanced SIMD access |
| 694 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 695 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 696 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 697 | mov x0, x25 |
| 698 | mov x1, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 699 | bl do_fpsimd_acc |
| 700 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 701 | el0_fpsimd_exc: |
| 702 | /* |
| 703 | * Floating Point or Advanced SIMD exception |
| 704 | */ |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 705 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 706 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 707 | mov x0, x25 |
| 708 | mov x1, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 709 | bl do_fpsimd_exc |
| 710 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 711 | el0_sp_pc: |
| 712 | /* |
| 713 | * Stack or PC alignment exception handling |
| 714 | */ |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 715 | mrs x26, far_el1 |
Mark Rutland | e7c3b24 | 2018-04-12 12:11:17 +0100 | [diff] [blame] | 716 | enable_dbg |
| 717 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 718 | bl trace_hardirqs_off |
| 719 | #endif |
Mark Rutland | 46b0567 | 2015-06-15 16:40:27 +0100 | [diff] [blame] | 720 | ct_user_exit |
Larry Bassel | 6ab6463 | 2014-05-30 20:34:14 +0100 | [diff] [blame] | 721 | mov x0, x26 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 722 | mov x1, x25 |
| 723 | mov x2, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 724 | bl do_sp_pc_abort |
| 725 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 726 | el0_undef: |
| 727 | /* |
| 728 | * Undefined instruction |
| 729 | */ |
Catalin Marinas | 2600e13 | 2013-08-22 11:47:37 +0100 | [diff] [blame] | 730 | // enable interrupts before calling the main handler |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 731 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 732 | ct_user_exit |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 733 | mov x0, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 734 | bl do_undefinstr |
| 735 | b ret_to_user |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 736 | el0_sys: |
| 737 | /* |
| 738 | * System instructions, for trapped cache maintenance instructions |
| 739 | */ |
| 740 | enable_dbg_and_irq |
| 741 | ct_user_exit |
| 742 | mov x0, x25 |
| 743 | mov x1, sp |
| 744 | bl do_sysinstr |
| 745 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 746 | el0_dbg: |
| 747 | /* |
| 748 | * Debug exception handling |
| 749 | */ |
| 750 | tbnz x24, #0, el0_inv // EL0 only |
| 751 | mrs x0, far_el1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 752 | mov x1, x25 |
| 753 | mov x2, sp |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 754 | bl do_debug_exception |
| 755 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 756 | ct_user_exit |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 757 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 758 | el0_inv: |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 759 | enable_dbg |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 760 | ct_user_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 761 | mov x0, sp |
| 762 | mov x1, #BAD_SYNC |
Mark Rutland | 1b42804 | 2015-07-07 18:00:49 +0100 | [diff] [blame] | 763 | mov x2, x25 |
Mark Rutland | de32794 | 2017-01-18 17:23:41 +0000 | [diff] [blame] | 764 | bl bad_el0_sync |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 765 | b ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 766 | ENDPROC(el0_sync) |
| 767 | |
| 768 | .align 6 |
| 769 | el0_irq: |
| 770 | kernel_entry 0 |
| 771 | el0_irq_naked: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 772 | enable_dbg |
| 773 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 774 | bl trace_hardirqs_off |
| 775 | #endif |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 776 | |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 777 | ct_user_exit |
Mark Rutland | 34dc20b | 2018-04-12 12:11:18 +0100 | [diff] [blame] | 778 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
| 779 | tbz x22, #55, 1f |
| 780 | bl do_el0_irq_bp_hardening |
| 781 | 1: |
| 782 | #endif |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 783 | irq_handler |
Marc Zyngier | 6468178 | 2013-11-12 17:11:53 +0000 | [diff] [blame] | 784 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 785 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 786 | bl trace_hardirqs_on |
| 787 | #endif |
| 788 | b ret_to_user |
| 789 | ENDPROC(el0_irq) |
| 790 | |
| 791 | /* |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 792 | * Register switch for AArch64. The callee-saved registers need to be saved |
| 793 | * and restored. On entry: |
| 794 | * x0 = previous task_struct (must be preserved across the switch) |
| 795 | * x1 = next task_struct |
| 796 | * Previous and next are guaranteed not to be the same. |
| 797 | * |
| 798 | */ |
| 799 | ENTRY(cpu_switch_to) |
Will Deacon | c0d3fce | 2015-07-20 15:14:53 +0100 | [diff] [blame] | 800 | mov x10, #THREAD_CPU_CONTEXT |
| 801 | add x8, x0, x10 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 802 | mov x9, sp |
| 803 | stp x19, x20, [x8], #16 // store callee-saved registers |
| 804 | stp x21, x22, [x8], #16 |
| 805 | stp x23, x24, [x8], #16 |
| 806 | stp x25, x26, [x8], #16 |
| 807 | stp x27, x28, [x8], #16 |
| 808 | stp x29, x9, [x8], #16 |
| 809 | str lr, [x8] |
Will Deacon | c0d3fce | 2015-07-20 15:14:53 +0100 | [diff] [blame] | 810 | add x8, x1, x10 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 811 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
| 812 | ldp x21, x22, [x8], #16 |
| 813 | ldp x23, x24, [x8], #16 |
| 814 | ldp x25, x26, [x8], #16 |
| 815 | ldp x27, x28, [x8], #16 |
| 816 | ldp x29, x9, [x8], #16 |
| 817 | ldr lr, [x8] |
| 818 | mov sp, x9 |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 819 | msr sp_el0, x1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 820 | ret |
| 821 | ENDPROC(cpu_switch_to) |
| 822 | |
| 823 | /* |
| 824 | * This is the fast syscall return path. We do as little as possible here, |
| 825 | * and this includes saving x0 back into the kernel stack. |
| 826 | */ |
| 827 | ret_fast_syscall: |
| 828 | disable_irq // disable interrupts |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 829 | str x0, [sp, #S_X0] // returned x0 |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 830 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing |
Josh Stone | 04d7e09 | 2015-06-05 14:28:03 -0700 | [diff] [blame] | 831 | and x2, x1, #_TIF_SYSCALL_WORK |
| 832 | cbnz x2, ret_fast_syscall_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 833 | and x2, x1, #_TIF_WORK_MASK |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 834 | cbnz x2, work_pending |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 835 | enable_step_tsk x1, x2 |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 836 | kernel_exit 0 |
Josh Stone | 04d7e09 | 2015-06-05 14:28:03 -0700 | [diff] [blame] | 837 | ret_fast_syscall_trace: |
| 838 | enable_irq // enable interrupts |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 839 | b __sys_trace_return_skipped // we already saved x0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 840 | |
| 841 | /* |
| 842 | * Ok, we need to do extra processing, enter the slow path. |
| 843 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 844 | work_pending: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 845 | mov x0, sp // 'regs' |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 846 | bl do_notify_resume |
Catalin Marinas | db3899a | 2015-12-04 12:42:29 +0000 | [diff] [blame] | 847 | #ifdef CONFIG_TRACE_IRQFLAGS |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 848 | bl trace_hardirqs_on // enabled while in userspace |
Catalin Marinas | db3899a | 2015-12-04 12:42:29 +0000 | [diff] [blame] | 849 | #endif |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 850 | ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 851 | b finish_ret_to_user |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 852 | /* |
| 853 | * "slow" syscall return path. |
| 854 | */ |
Catalin Marinas | 59dc67b | 2012-09-10 16:11:46 +0100 | [diff] [blame] | 855 | ret_to_user: |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 856 | disable_irq // disable interrupts |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 857 | ldr x1, [tsk, #TSK_TI_FLAGS] |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 858 | and x2, x1, #_TIF_WORK_MASK |
| 859 | cbnz x2, work_pending |
Chris Metcalf | 421dd6f | 2016-07-14 16:48:14 -0400 | [diff] [blame] | 860 | finish_ret_to_user: |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 861 | enable_step_tsk x1, x2 |
Will Deacon | 412fcb6 | 2015-08-19 15:57:09 +0100 | [diff] [blame] | 862 | kernel_exit 0 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 863 | ENDPROC(ret_to_user) |
| 864 | |
| 865 | /* |
| 866 | * This is how we return from a fork. |
| 867 | */ |
| 868 | ENTRY(ret_from_fork) |
| 869 | bl schedule_tail |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 870 | cbz x19, 1f // not a kernel thread |
| 871 | mov x0, x20 |
| 872 | blr x19 |
| 873 | 1: get_thread_info tsk |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 874 | b ret_to_user |
| 875 | ENDPROC(ret_from_fork) |
| 876 | |
| 877 | /* |
| 878 | * SVC handler. |
| 879 | */ |
| 880 | .align 6 |
| 881 | el0_svc: |
| 882 | adrp stbl, sys_call_table // load syscall table pointer |
| 883 | uxtw scno, w8 // syscall number in w8 |
| 884 | mov sc_nr, #__NR_syscalls |
| 885 | el0_svc_naked: // compat entry point |
| 886 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number |
Will Deacon | 2a28307 | 2014-04-29 19:04:06 +0100 | [diff] [blame] | 887 | enable_dbg_and_irq |
Larry Bassel | 6c81fe7 | 2014-05-30 12:34:15 -0700 | [diff] [blame] | 888 | ct_user_exit 1 |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 889 | |
Mark Rutland | 5b7e8f7 | 2016-11-03 20:23:13 +0000 | [diff] [blame] | 890 | ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks |
AKASHI Takahiro | 449f81a | 2014-04-30 10:51:29 +0100 | [diff] [blame] | 891 | tst x16, #_TIF_SYSCALL_WORK |
| 892 | b.ne __sys_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 893 | cmp scno, sc_nr // check upper syscall limit |
| 894 | b.hs ni_sys |
Mark Rutland | f3ed64a | 2018-04-12 12:11:02 +0100 | [diff] [blame] | 895 | mask_nospec64 scno, sc_nr, x19 // enforce bounds for syscall number |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 896 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 897 | blr x16 // call sys_* routine |
| 898 | b ret_fast_syscall |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 899 | ni_sys: |
| 900 | mov x0, sp |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 901 | bl do_ni_syscall |
| 902 | b ret_fast_syscall |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 903 | ENDPROC(el0_svc) |
| 904 | |
| 905 | /* |
| 906 | * This is the really slow path. We're going to be doing context |
| 907 | * switches, and waiting for our parent to respond. |
| 908 | */ |
| 909 | __sys_trace: |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 910 | mov w0, #-1 // set default errno for |
| 911 | cmp scno, x0 // user-issued syscall(-1) |
| 912 | b.ne 1f |
| 913 | mov x0, #-ENOSYS |
| 914 | str x0, [sp, #S_X0] |
| 915 | 1: mov x0, sp |
AKASHI Takahiro | 3157858 | 2014-04-30 10:51:30 +0100 | [diff] [blame] | 916 | bl syscall_trace_enter |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 917 | cmp w0, #-1 // skip the syscall? |
| 918 | b.eq __sys_trace_return_skipped |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 919 | uxtw scno, w0 // syscall number (possibly new) |
| 920 | mov x1, sp // pointer to regs |
| 921 | cmp scno, sc_nr // check upper syscall limit |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 922 | b.hs __ni_sys_trace |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 923 | ldp x0, x1, [sp] // restore the syscall args |
| 924 | ldp x2, x3, [sp, #S_X2] |
| 925 | ldp x4, x5, [sp, #S_X4] |
| 926 | ldp x6, x7, [sp, #S_X6] |
| 927 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 928 | blr x16 // call sys_* routine |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 929 | |
| 930 | __sys_trace_return: |
AKASHI Takahiro | 1014c81 | 2014-11-28 05:26:35 +0000 | [diff] [blame] | 931 | str x0, [sp, #S_X0] // save returned x0 |
| 932 | __sys_trace_return_skipped: |
AKASHI Takahiro | 3157858 | 2014-04-30 10:51:30 +0100 | [diff] [blame] | 933 | mov x0, sp |
| 934 | bl syscall_trace_exit |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 935 | b ret_to_user |
| 936 | |
Will Deacon | d54e81f | 2014-09-29 11:44:01 +0100 | [diff] [blame] | 937 | __ni_sys_trace: |
| 938 | mov x0, sp |
| 939 | bl do_ni_syscall |
| 940 | b __sys_trace_return |
| 941 | |
Pratyush Anand | 888b3c8 | 2016-07-08 12:35:50 -0400 | [diff] [blame] | 942 | .popsection // .entry.text |
| 943 | |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 944 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
| 945 | /* |
| 946 | * Exception vectors trampoline. |
| 947 | */ |
| 948 | .pushsection ".entry.tramp.text", "ax" |
| 949 | |
| 950 | .macro tramp_map_kernel, tmp |
| 951 | mrs \tmp, ttbr1_el1 |
| 952 | sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
| 953 | bic \tmp, \tmp, #USER_ASID_FLAG |
| 954 | msr ttbr1_el1, \tmp |
Will Deacon | 04b77fe | 2017-11-14 14:29:19 +0000 | [diff] [blame] | 955 | #ifdef CONFIG_ARCH_MSM8996 |
| 956 | /* ASID already in \tmp[63:48] */ |
| 957 | movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) |
| 958 | movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) |
| 959 | /* 2MB boundary containing the vectors, so we nobble the walk cache */ |
| 960 | movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) |
| 961 | isb |
| 962 | tlbi vae1, \tmp |
| 963 | dsb nsh |
| 964 | #endif /* CONFIG_ARCH_MSM8996 */ |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 965 | .endm |
| 966 | |
| 967 | .macro tramp_unmap_kernel, tmp |
| 968 | mrs \tmp, ttbr1_el1 |
| 969 | add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) |
| 970 | orr \tmp, \tmp, #USER_ASID_FLAG |
| 971 | msr ttbr1_el1, \tmp |
| 972 | /* |
Will Deacon | a80d8e2 | 2018-04-03 12:09:22 +0100 | [diff] [blame] | 973 | * We avoid running the post_ttbr_update_workaround here because |
| 974 | * it's only needed by Cavium ThunderX, which requires KPTI to be |
| 975 | * disabled. |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 976 | */ |
| 977 | .endm |
| 978 | |
| 979 | .macro tramp_ventry, regsize = 64 |
| 980 | .align 7 |
| 981 | 1: |
| 982 | .if \regsize == 64 |
| 983 | msr tpidrro_el0, x30 // Restored in kernel_ventry |
| 984 | .endif |
Will Deacon | f6af532 | 2018-04-03 12:09:11 +0100 | [diff] [blame] | 985 | /* |
| 986 | * Defend against branch aliasing attacks by pushing a dummy |
| 987 | * entry onto the return stack and using a RET instruction to |
| 988 | * enter the full-fat kernel vectors. |
| 989 | */ |
Will Deacon | 7535936 | 2017-11-14 16:15:59 +0000 | [diff] [blame] | 990 | bl 2f |
| 991 | b . |
| 992 | 2: |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 993 | tramp_map_kernel x30 |
Will Deacon | 06fe41f | 2017-12-06 11:24:02 +0000 | [diff] [blame] | 994 | #ifdef CONFIG_RANDOMIZE_BASE |
| 995 | adr x30, tramp_vectors + PAGE_SIZE |
Todd Poynor | b328e52 | 2018-01-08 12:22:41 -0800 | [diff] [blame] | 996 | #ifndef CONFIG_ARCH_MSM8996 |
| 997 | isb |
| 998 | #endif |
Will Deacon | 06fe41f | 2017-12-06 11:24:02 +0000 | [diff] [blame] | 999 | ldr x30, [x30] |
| 1000 | #else |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 1001 | ldr x30, =vectors |
Will Deacon | 06fe41f | 2017-12-06 11:24:02 +0000 | [diff] [blame] | 1002 | #endif |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 1003 | prfm plil1strm, [x30, #(1b - tramp_vectors)] |
| 1004 | msr vbar_el1, x30 |
| 1005 | add x30, x30, #(1b - tramp_vectors) |
| 1006 | isb |
Will Deacon | 7535936 | 2017-11-14 16:15:59 +0000 | [diff] [blame] | 1007 | ret |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 1008 | .endm |
| 1009 | |
| 1010 | .macro tramp_exit, regsize = 64 |
| 1011 | adr x30, tramp_vectors |
| 1012 | msr vbar_el1, x30 |
| 1013 | tramp_unmap_kernel x30 |
| 1014 | .if \regsize == 64 |
| 1015 | mrs x30, far_el1 |
| 1016 | .endif |
| 1017 | eret |
| 1018 | .endm |
| 1019 | |
| 1020 | .align 11 |
| 1021 | ENTRY(tramp_vectors) |
| 1022 | .space 0x400 |
| 1023 | |
| 1024 | tramp_ventry |
| 1025 | tramp_ventry |
| 1026 | tramp_ventry |
| 1027 | tramp_ventry |
| 1028 | |
| 1029 | tramp_ventry 32 |
| 1030 | tramp_ventry 32 |
| 1031 | tramp_ventry 32 |
| 1032 | tramp_ventry 32 |
| 1033 | END(tramp_vectors) |
| 1034 | |
| 1035 | ENTRY(tramp_exit_native) |
| 1036 | tramp_exit |
| 1037 | END(tramp_exit_native) |
| 1038 | |
| 1039 | ENTRY(tramp_exit_compat) |
| 1040 | tramp_exit 32 |
| 1041 | END(tramp_exit_compat) |
| 1042 | |
| 1043 | .ltorg |
| 1044 | .popsection // .entry.tramp.text |
Will Deacon | 06fe41f | 2017-12-06 11:24:02 +0000 | [diff] [blame] | 1045 | #ifdef CONFIG_RANDOMIZE_BASE |
| 1046 | .pushsection ".rodata", "a" |
| 1047 | .align PAGE_SHIFT |
| 1048 | .globl __entry_tramp_data_start |
| 1049 | __entry_tramp_data_start: |
| 1050 | .quad vectors |
| 1051 | .popsection // .rodata |
| 1052 | #endif /* CONFIG_RANDOMIZE_BASE */ |
Will Deacon | a329b06 | 2017-11-14 14:07:40 +0000 | [diff] [blame] | 1053 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ |
| 1054 | |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1055 | /* |
| 1056 | * Special system call wrappers. |
| 1057 | */ |
Catalin Marinas | 60ffc30 | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1058 | ENTRY(sys_rt_sigreturn_wrapper) |
| 1059 | mov x0, sp |
| 1060 | b sys_rt_sigreturn |
| 1061 | ENDPROC(sys_rt_sigreturn_wrapper) |