blob: ad0adb5a1e0eb62b025abc56006d068f92771d32 [file] [log] [blame]
Tony Lindgren90c62bf2008-12-10 17:37:17 -08001/*
Adrian Hunterd02a900b2010-02-15 10:03:34 -08002 * linux/arch/arm/mach-omap2/hsmmc.c
Tony Lindgren90c62bf2008-12-10 17:37:17 -08003 *
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080012#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/string.h>
Tony Lindgren90c62bf2008-12-10 17:37:17 -080015#include <linux/delay.h>
Silesh C V5e4698f2011-07-04 04:10:00 -070016#include <linux/gpio.h>
Tony Lindgren90c62bf2008-12-10 17:37:17 -080017#include <mach/hardware.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070018#include <plat/mmc.h>
Adrian Huntere3df0fb2010-02-15 10:03:34 -080019#include <plat/omap-pm.h>
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +053020#include <plat/mux.h>
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +053021#include <plat/omap_device.h>
Tony Lindgren90c62bf2008-12-10 17:37:17 -080022
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +053023#include "mux.h"
Adrian Hunterd02a900b2010-02-15 10:03:34 -080024#include "hsmmc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060025#include "control.h"
Tony Lindgren90c62bf2008-12-10 17:37:17 -080026
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080027#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
Tony Lindgren90c62bf2008-12-10 17:37:17 -080028
Tony Lindgren90c62bf2008-12-10 17:37:17 -080029static u16 control_pbias_offset;
30static u16 control_devconf1_offset;
kishore kadiyalac83c8e62010-05-15 18:21:25 +000031static u16 control_mmc1;
Tony Lindgren90c62bf2008-12-10 17:37:17 -080032
33#define HSMMC_NAME_LEN 9
34
Denis Karpov1887bde2009-09-22 16:44:40 -070035#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36
Adrian Hunter68ff0422010-02-15 10:03:34 -080037static int hsmmc_get_context_loss(struct device *dev)
Denis Karpov1887bde2009-09-22 16:44:40 -070038{
Adrian Huntere3df0fb2010-02-15 10:03:34 -080039 return omap_pm_get_dev_context_loss_count(dev);
Denis Karpov1887bde2009-09-22 16:44:40 -070040}
41
42#else
Adrian Hunter68ff0422010-02-15 10:03:34 -080043#define hsmmc_get_context_loss NULL
Denis Karpov1887bde2009-09-22 16:44:40 -070044#endif
45
kishore kadiyalac83c8e62010-05-15 18:21:25 +000046static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080047 int power_on, int vdd)
Tony Lindgren90c62bf2008-12-10 17:37:17 -080048{
Madhu555d5032009-11-22 10:11:08 -080049 u32 reg, prog_io;
Tony Lindgren90c62bf2008-12-10 17:37:17 -080050 struct omap_mmc_platform_data *mmc = dev->platform_data;
51
Adrian Hunterce6f0012010-02-15 10:03:34 -080052 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
54
David Brownell0329c372009-03-23 18:23:47 -070055 /*
56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
David Brownellb583f262009-05-28 14:04:03 -070057 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
David Brownell0329c372009-03-23 18:23:47 -070058 * 1.8V and 3.0V modes, controlled by the PBIAS register.
59 *
60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61 * is most naturally TWL VSIM; those pins also use PBIAS.
David Brownellb583f262009-05-28 14:04:03 -070062 *
63 * FIXME handle VMMC1A as needed ...
David Brownell0329c372009-03-23 18:23:47 -070064 */
Tony Lindgren90c62bf2008-12-10 17:37:17 -080065 if (power_on) {
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
70 else
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
73 }
74
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
79 }
80
81 reg = omap_ctrl_readl(control_pbias_offset);
Madhu555d5032009-11-22 10:11:08 -080082 if (cpu_is_omap3630()) {
83 /* Set MMC I/O to 52Mhz */
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
87 } else {
88 reg |= OMAP2_PBIASSPEEDCTRL0;
89 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -080090 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080092 } else {
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
96 }
97}
Tony Lindgren90c62bf2008-12-10 17:37:17 -080098
kishore kadiyalac83c8e62010-05-15 18:21:25 +000099static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800100 int power_on, int vdd)
101{
102 u32 reg;
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800103
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800104 /* 100ms delay required for PBIAS configuration */
105 msleep(100);
106
107 if (power_on) {
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
112 else
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
115 } else {
116 reg = omap_ctrl_readl(control_pbias_offset);
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
120 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800121}
122
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000123static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
125{
126 u32 reg;
127
128 /*
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000132 */
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600133 reg = omap4_ctrl_pad_readl(control_pbias_offset);
134 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
Balaji T Kff2beb12011-10-03 17:52:50 +0530135 OMAP4_MMC1_PWRDNZ_MASK |
136 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600137 omap4_ctrl_pad_writel(reg, control_pbias_offset);
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000138}
139
140static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
141 int power_on, int vdd)
142{
143 u32 reg;
Balaji T K1fcecf22011-06-01 16:45:22 +0530144 unsigned long timeout;
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000145
146 if (power_on) {
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600147 reg = omap4_ctrl_pad_readl(control_pbias_offset);
148 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000149 if ((1 << vdd) <= MMC_VDD_165_195)
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600150 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000151 else
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600152 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
153 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
Bryan Buckley3696d302011-09-30 11:05:55 -0700154 OMAP4_MMC1_PWRDNZ_MASK);
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600155 omap4_ctrl_pad_writel(reg, control_pbias_offset);
Balaji T K1fcecf22011-06-01 16:45:22 +0530156
157 timeout = jiffies + msecs_to_jiffies(5);
158 do {
159 reg = omap4_ctrl_pad_readl(control_pbias_offset);
160 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
161 break;
162 usleep_range(100, 200);
163 } while (!time_after(jiffies, timeout));
164
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600165 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000166 pr_err("Pbias Voltage is not same as LDO\n");
167 /* Caution : On VMODE_ERROR Power Down MMC IO */
Bryan Buckley3696d302011-09-30 11:05:55 -0700168 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000170 }
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000171 }
172}
173
Igor Grinberge62245b2011-11-29 11:37:48 +0200174static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
175{
176 u32 reg;
177
Grazvydas Ignotasd82e5192012-01-12 16:26:45 +0200178 reg = omap_ctrl_readl(control_devconf1_offset);
179 if (mmc->slots[0].internal_clock)
Igor Grinberge62245b2011-11-29 11:37:48 +0200180 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
Grazvydas Ignotasd82e5192012-01-12 16:26:45 +0200181 else
182 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
183 omap_ctrl_writel(reg, control_devconf1_offset);
Igor Grinberge62245b2011-11-29 11:37:48 +0200184}
185
Grazvydas Ignotasffa1e4e2011-12-18 02:35:47 +0200186static void hsmmc2_before_set_reg(struct device *dev, int slot,
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800187 int power_on, int vdd)
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800188{
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800189 struct omap_mmc_platform_data *mmc = dev->platform_data;
Grazvydas Ignotas762ad3a42009-06-23 13:30:22 +0300190
Adrian Hunterce6f0012010-02-15 10:03:34 -0800191 if (mmc->slots[0].remux)
192 mmc->slots[0].remux(dev, slot, power_on);
193
Igor Grinberge62245b2011-11-29 11:37:48 +0200194 if (power_on)
195 hsmmc2_select_input_clk_src(mmc);
196}
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800197
Igor Grinberge62245b2011-11-29 11:37:48 +0200198static int am35x_hsmmc2_set_power(struct device *dev, int slot,
199 int power_on, int vdd)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 if (power_on)
204 hsmmc2_select_input_clk_src(mmc);
205
206 return 0;
Adrian Hunter9b7c18e2009-09-22 16:44:50 -0700207}
208
stanley.miao03e7e172010-05-13 12:39:31 +0000209static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
210 int vdd)
211{
212 return 0;
213}
214
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +0530215static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
216 int controller_nr)
217{
Thomas Webera15164f2011-11-17 22:39:40 +0100218 if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
219 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +0530220 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
221 OMAP_PIN_INPUT_PULLUP);
Thomas Webera15164f2011-11-17 22:39:40 +0100222 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
223 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +0530224 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
225 OMAP_PIN_INPUT_PULLUP);
226 if (cpu_is_omap34xx()) {
227 if (controller_nr == 0) {
228 omap_mux_init_signal("sdmmc1_clk",
229 OMAP_PIN_INPUT_PULLUP);
230 omap_mux_init_signal("sdmmc1_cmd",
231 OMAP_PIN_INPUT_PULLUP);
232 omap_mux_init_signal("sdmmc1_dat0",
233 OMAP_PIN_INPUT_PULLUP);
234 if (mmc_controller->slots[0].caps &
235 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
236 omap_mux_init_signal("sdmmc1_dat1",
237 OMAP_PIN_INPUT_PULLUP);
238 omap_mux_init_signal("sdmmc1_dat2",
239 OMAP_PIN_INPUT_PULLUP);
240 omap_mux_init_signal("sdmmc1_dat3",
241 OMAP_PIN_INPUT_PULLUP);
242 }
243 if (mmc_controller->slots[0].caps &
244 MMC_CAP_8_BIT_DATA) {
245 omap_mux_init_signal("sdmmc1_dat4",
246 OMAP_PIN_INPUT_PULLUP);
247 omap_mux_init_signal("sdmmc1_dat5",
248 OMAP_PIN_INPUT_PULLUP);
249 omap_mux_init_signal("sdmmc1_dat6",
250 OMAP_PIN_INPUT_PULLUP);
251 omap_mux_init_signal("sdmmc1_dat7",
252 OMAP_PIN_INPUT_PULLUP);
253 }
254 }
255 if (controller_nr == 1) {
256 /* MMC2 */
257 omap_mux_init_signal("sdmmc2_clk",
258 OMAP_PIN_INPUT_PULLUP);
259 omap_mux_init_signal("sdmmc2_cmd",
260 OMAP_PIN_INPUT_PULLUP);
261 omap_mux_init_signal("sdmmc2_dat0",
262 OMAP_PIN_INPUT_PULLUP);
263
264 /*
265 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
266 * need to be muxed in the board-*.c files
267 */
268 if (mmc_controller->slots[0].caps &
269 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
270 omap_mux_init_signal("sdmmc2_dat1",
271 OMAP_PIN_INPUT_PULLUP);
272 omap_mux_init_signal("sdmmc2_dat2",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat3",
275 OMAP_PIN_INPUT_PULLUP);
276 }
277 if (mmc_controller->slots[0].caps &
278 MMC_CAP_8_BIT_DATA) {
279 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
280 OMAP_PIN_INPUT_PULLUP);
281 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
282 OMAP_PIN_INPUT_PULLUP);
283 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
284 OMAP_PIN_INPUT_PULLUP);
285 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
286 OMAP_PIN_INPUT_PULLUP);
287 }
288 }
289
290 /*
291 * For MMC3 the pins need to be muxed in the board-*.c files
292 */
293 }
294}
295
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530296static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
297 struct omap_mmc_platform_data *mmc)
298{
299 char *hc_name;
300
301 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
302 if (!hc_name) {
303 pr_err("Cannot allocate memory for controller slot name\n");
304 kfree(hc_name);
305 return -ENOMEM;
306 }
307
308 if (c->name)
309 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
310 else
311 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
312 c->mmc, 1);
313 mmc->slots[0].name = hc_name;
314 mmc->nr_slots = 1;
315 mmc->slots[0].caps = c->caps;
Eliad Peller6fdc75d2011-11-22 16:02:18 +0200316 mmc->slots[0].pm_caps = c->pm_caps;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530317 mmc->slots[0].internal_clock = !c->ext_clock;
318 mmc->dma_mask = 0xffffffff;
319 if (cpu_is_omap44xx())
320 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
321 else
322 mmc->reg_offset = 0;
323
324 mmc->get_context_loss_count = hsmmc_get_context_loss;
325
326 mmc->slots[0].switch_pin = c->gpio_cd;
327 mmc->slots[0].gpio_wp = c->gpio_wp;
328
329 mmc->slots[0].remux = c->remux;
330 mmc->slots[0].init_card = c->init_card;
331
332 if (c->cover_only)
333 mmc->slots[0].cover = 1;
334
335 if (c->nonremovable)
336 mmc->slots[0].nonremovable = 1;
337
338 if (c->power_saving)
339 mmc->slots[0].power_saving = 1;
340
341 if (c->no_off)
342 mmc->slots[0].no_off = 1;
343
Balaji T Kb1c1df72011-05-30 19:55:34 +0530344 if (c->no_off_init)
345 mmc->slots[0].no_regulator_off_init = c->no_off_init;
346
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530347 if (c->vcc_aux_disable_is_sleep)
348 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
349
350 /*
351 * NOTE: MMC slots should have a Vcc regulator set up.
352 * This may be from a TWL4030-family chip, another
353 * controllable regulator, or a fixed supply.
354 *
355 * temporary HACK: ocr_mask instead of fixed supply
356 */
Abhilash K Ve89715a2011-12-09 12:27:36 -0800357 if (cpu_is_omap3505() || cpu_is_omap3517())
358 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
359 MMC_VDD_26_27 |
360 MMC_VDD_27_28 |
361 MMC_VDD_29_30 |
362 MMC_VDD_30_31 |
363 MMC_VDD_31_32;
364 else
365 mmc->slots[0].ocr_mask = c->ocr_mask;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530366
Igor Grinberge62245b2011-11-29 11:37:48 +0200367 if (!cpu_is_omap3517() && !cpu_is_omap3505())
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530368 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
369
370 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
371 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
372
373 switch (c->mmc) {
374 case 1:
375 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
376 /* on-chip level shifting via PBIAS0/PBIAS1 */
377 if (cpu_is_omap44xx()) {
378 mmc->slots[0].before_set_reg =
379 omap4_hsmmc1_before_set_reg;
380 mmc->slots[0].after_set_reg =
381 omap4_hsmmc1_after_set_reg;
382 } else {
383 mmc->slots[0].before_set_reg =
384 omap_hsmmc1_before_set_reg;
385 mmc->slots[0].after_set_reg =
386 omap_hsmmc1_after_set_reg;
387 }
388 }
389
Igor Grinberge62245b2011-11-29 11:37:48 +0200390 if (cpu_is_omap3517() || cpu_is_omap3505())
391 mmc->slots[0].set_power = nop_mmc_set_power;
392
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530393 /* OMAP3630 HSMMC1 supports only 4-bit */
394 if (cpu_is_omap3630() &&
395 (c->caps & MMC_CAP_8_BIT_DATA)) {
396 c->caps &= ~MMC_CAP_8_BIT_DATA;
397 c->caps |= MMC_CAP_4_BIT_DATA;
398 mmc->slots[0].caps = c->caps;
399 }
400 break;
401 case 2:
Igor Grinberge62245b2011-11-29 11:37:48 +0200402 if (cpu_is_omap3517() || cpu_is_omap3505())
403 mmc->slots[0].set_power = am35x_hsmmc2_set_power;
404
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530405 if (c->ext_clock)
406 c->transceiver = 1;
407 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
408 c->caps &= ~MMC_CAP_8_BIT_DATA;
409 c->caps |= MMC_CAP_4_BIT_DATA;
410 }
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530411 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
412 /* off-chip level shifting, or none */
Grazvydas Ignotasffa1e4e2011-12-18 02:35:47 +0200413 mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530414 mmc->slots[0].after_set_reg = NULL;
415 }
416 break;
Grazvydas Ignotasffa1e4e2011-12-18 02:35:47 +0200417 case 3:
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530418 case 4:
419 case 5:
420 mmc->slots[0].before_set_reg = NULL;
421 mmc->slots[0].after_set_reg = NULL;
422 break;
423 default:
424 pr_err("MMC%d configuration not supported!\n", c->mmc);
425 kfree(hc_name);
426 return -ENODEV;
427 }
428 return 0;
429}
430
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530431#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
432
433void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
434{
435 struct omap_hwmod *oh;
Kevin Hilman3528c582011-07-21 13:48:45 -0700436 struct platform_device *pdev;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530437 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
438 struct omap_mmc_platform_data *mmc_data;
439 struct omap_mmc_dev_attr *mmc_dev_attr;
440 char *name;
441 int l;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530442
443 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
444 if (!mmc_data) {
445 pr_err("Cannot allocate memory for mmc device!\n");
446 goto done;
447 }
448
449 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
450 pr_err("%s fails!\n", __func__);
451 goto done;
452 }
453 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
454
Kishore Kadiyala0005ae72011-02-28 20:48:05 +0530455 name = "omap_hsmmc";
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530456
457 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
458 "mmc%d", ctrl_nr);
459 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
460 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
461 oh = omap_hwmod_lookup(oh_name);
462 if (!oh) {
463 pr_err("Could not look up %s\n", oh_name);
464 kfree(mmc_data->slots[0].name);
465 goto done;
466 }
467
468 if (oh->dev_attr != NULL) {
469 mmc_dev_attr = oh->dev_attr;
470 mmc_data->controller_flags = mmc_dev_attr->flags;
471 }
472
Kevin Hilman3528c582011-07-21 13:48:45 -0700473 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
Benoit Coussonf718e2c2011-08-10 15:30:09 +0200474 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
Kevin Hilman3528c582011-07-21 13:48:45 -0700475 if (IS_ERR(pdev)) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300476 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530477 kfree(mmc_data->slots[0].name);
478 goto done;
479 }
480 /*
481 * return device handle to board setup code
482 * required to populate for regulator framework structure
483 */
Kevin Hilman3528c582011-07-21 13:48:45 -0700484 hsmmcinfo->dev = &pdev->dev;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530485
486done:
487 kfree(mmc_data);
488}
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800489
Adrian Hunter68ff0422010-02-15 10:03:34 -0800490void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800491{
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000492 u32 reg;
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800493
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000494 if (!cpu_is_omap44xx()) {
495 if (cpu_is_omap2430()) {
496 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
497 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
498 } else {
499 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
500 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
501 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800502 } else {
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600503 control_pbias_offset =
504 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
505 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
506 reg = omap4_ctrl_pad_readl(control_mmc1);
507 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
508 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
509 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
510 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
Balaji T Kc862dd72011-10-03 17:52:51 +0530511 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600512 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
513 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
514 omap4_ctrl_pad_writel(reg, control_mmc1);
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800515 }
516
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530517 for (; controllers->mmc; controllers++)
518 omap_init_hsmmc(controllers, controllers->mmc);
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800519
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800520}
521
522#endif