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Alan9b13b682006-12-07 08:59:14 -08001/*
2 * pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
3 *
4 * The IT8213 is a very Intel ICH like device for timing purposes, having
5 * a similar register layout and the same split clock arrangement. Cable
6 * detection is different, and it does not have slave channels or all the
7 * clutter of later ICH/SATA setups.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/init.h>
14#include <linux/blkdev.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <scsi/scsi_host.h>
18#include <linux/libata.h>
19#include <linux/ata.h>
20
21#define DRV_NAME "pata_it8213"
Jeff Garzik8bc3fc42007-05-21 20:26:38 -040022#define DRV_VERSION "0.0.3"
Alan9b13b682006-12-07 08:59:14 -080023
24/**
25 * it8213_pre_reset - check for 40/80 pin
Tejun Heocc0680a2007-08-06 18:36:23 +090026 * @link: link
Tejun Heod4b2bab2007-02-02 16:50:52 +090027 * @deadline: deadline jiffies for the operation
Alan9b13b682006-12-07 08:59:14 -080028 *
Alan Cox5816fbb2007-03-07 16:46:20 +000029 * Filter out ports by the enable bits before doing the normal reset
30 * and probe.
Alan9b13b682006-12-07 08:59:14 -080031 */
32
Tejun Heocc0680a2007-08-06 18:36:23 +090033static int it8213_pre_reset(struct ata_link *link, unsigned long deadline)
Alan9b13b682006-12-07 08:59:14 -080034{
35 static const struct pci_bits it8213_enable_bits[] = {
36 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
37 };
Tejun Heocc0680a2007-08-06 18:36:23 +090038 struct ata_port *ap = link->ap;
Alan9b13b682006-12-07 08:59:14 -080039 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan9b13b682006-12-07 08:59:14 -080040 if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
41 return -ENOENT;
Tejun Heod4b2bab2007-02-02 16:50:52 +090042
Tejun Heocc0680a2007-08-06 18:36:23 +090043 return ata_std_prereset(link, deadline);
Alan9b13b682006-12-07 08:59:14 -080044}
45
46/**
Alan Cox5816fbb2007-03-07 16:46:20 +000047 * it8213_error_handler - Probe specified port on PATA host controller
Alan9b13b682006-12-07 08:59:14 -080048 * @ap: Port to probe
49 *
50 * LOCKING:
51 * None (inherited from caller).
52 */
53
54static void it8213_error_handler(struct ata_port *ap)
55{
56 ata_bmdma_drive_eh(ap, it8213_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
57}
58
59/**
Alan Cox5816fbb2007-03-07 16:46:20 +000060 * it8213_cable_detect - check for 40/80 pin
61 * @ap: Port
62 *
63 * Perform cable detection for the 8213 ATA interface. This is
64 * different to the PIIX arrangement
65 */
66
67static int it8213_cable_detect(struct ata_port *ap)
68{
69 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
70 u8 tmp;
71 pci_read_config_byte(pdev, 0x42, &tmp);
72 if (tmp & 2) /* The initial docs are incorrect */
73 return ATA_CBL_PATA40;
74 return ATA_CBL_PATA80;
75}
76
77/**
Alan9b13b682006-12-07 08:59:14 -080078 * it8213_set_piomode - Initialize host controller PATA PIO timings
79 * @ap: Port whose timings we are configuring
Alan Cox5816fbb2007-03-07 16:46:20 +000080 * @adev: Device whose timings we are configuring
Alan9b13b682006-12-07 08:59:14 -080081 *
82 * Set PIO mode for device, in host controller PCI config space.
83 *
84 * LOCKING:
85 * None (inherited from caller).
86 */
87
88static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
89{
90 unsigned int pio = adev->pio_mode - XFER_PIO_0;
91 struct pci_dev *dev = to_pci_dev(ap->host->dev);
92 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
93 u16 idetm_data;
94 int control = 0;
95
96 /*
97 * See Intel Document 298600-004 for the timing programing rules
98 * for PIIX/ICH. The 8213 is a clone so very similar
99 */
100
101 static const /* ISP RTC */
102 u8 timings[][2] = { { 0, 0 },
103 { 0, 0 },
104 { 1, 0 },
105 { 2, 1 },
106 { 2, 3 }, };
107
108 if (pio > 2)
109 control |= 1; /* TIME1 enable */
110 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
111 control |= 2; /* IORDY enable */
112 /* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
113 if (adev->class != ATA_DEV_ATA)
114 control |= 4;
115
116 pci_read_config_word(dev, idetm_port, &idetm_data);
117
118 /* Enable PPE, IE and TIME as appropriate */
119
120 if (adev->devno == 0) {
121 idetm_data &= 0xCCF0;
122 idetm_data |= control;
123 idetm_data |= (timings[pio][0] << 12) |
124 (timings[pio][1] << 8);
125 } else {
126 u8 slave_data;
127
128 idetm_data &= 0xCC0F;
129 idetm_data |= (control << 4);
130
131 /* Slave timing in seperate register */
132 pci_read_config_byte(dev, 0x44, &slave_data);
133 slave_data &= 0xF0;
134 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << 4;
135 pci_write_config_byte(dev, 0x44, slave_data);
136 }
137
138 idetm_data |= 0x4000; /* Ensure SITRE is enabled */
139 pci_write_config_word(dev, idetm_port, idetm_data);
140}
141
142/**
143 * it8213_set_dmamode - Initialize host controller PATA DMA timings
144 * @ap: Port whose timings we are configuring
145 * @adev: Device to program
146 *
147 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
148 * This device is basically an ICH alike.
149 *
150 * LOCKING:
151 * None (inherited from caller).
152 */
153
154static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
155{
156 struct pci_dev *dev = to_pci_dev(ap->host->dev);
157 u16 master_data;
158 u8 speed = adev->dma_mode;
159 int devid = adev->devno;
160 u8 udma_enable;
161
162 static const /* ISP RTC */
163 u8 timings[][2] = { { 0, 0 },
164 { 0, 0 },
165 { 1, 0 },
166 { 2, 1 },
167 { 2, 3 }, };
168
169 pci_read_config_word(dev, 0x40, &master_data);
170 pci_read_config_byte(dev, 0x48, &udma_enable);
171
172 if (speed >= XFER_UDMA_0) {
173 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
174 u16 udma_timing;
175 u16 ideconf;
176 int u_clock, u_speed;
177
178 /* Clocks follow the PIIX style */
179 u_speed = min(2 - (udma & 1), udma);
180 if (udma == 5)
181 u_clock = 0x1000; /* 100Mhz */
182 else if (udma > 2)
183 u_clock = 1; /* 66Mhz */
184 else
185 u_clock = 0; /* 33Mhz */
186
187 udma_enable |= (1 << devid);
188
189 /* Load the UDMA mode number */
190 pci_read_config_word(dev, 0x4A, &udma_timing);
191 udma_timing &= ~(3 << (4 * devid));
192 udma_timing |= (udma & 3) << (4 * devid);
193 pci_write_config_word(dev, 0x4A, udma_timing);
194
195 /* Load the clock selection */
196 pci_read_config_word(dev, 0x54, &ideconf);
197 ideconf &= ~(0x1001 << devid);
198 ideconf |= u_clock << devid;
199 pci_write_config_word(dev, 0x54, ideconf);
200 } else {
201 /*
202 * MWDMA is driven by the PIO timings. We must also enable
203 * IORDY unconditionally along with TIME1. PPE has already
204 * been set when the PIO timing was set.
205 */
206 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
207 unsigned int control;
208 u8 slave_data;
209 static const unsigned int needed_pio[3] = {
210 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
211 };
212 int pio = needed_pio[mwdma] - XFER_PIO_0;
213
214 control = 3; /* IORDY|TIME1 */
215
216 /* If the drive MWDMA is faster than it can do PIO then
217 we must force PIO into PIO0 */
218
219 if (adev->pio_mode < needed_pio[mwdma])
220 /* Enable DMA timing only */
221 control |= 8; /* PIO cycles in PIO0 */
222
223 if (devid) { /* Slave */
224 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
225 master_data |= control << 4;
226 pci_read_config_byte(dev, 0x44, &slave_data);
227 slave_data &= (0x0F + 0xE1 * ap->port_no);
228 /* Load the matching timing */
229 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
230 pci_write_config_byte(dev, 0x44, slave_data);
231 } else { /* Master */
232 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
233 and master timing bits */
234 master_data |= control;
235 master_data |=
236 (timings[pio][0] << 12) |
237 (timings[pio][1] << 8);
238 }
239 udma_enable &= ~(1 << devid);
240 pci_write_config_word(dev, 0x40, master_data);
241 }
242 pci_write_config_byte(dev, 0x48, udma_enable);
243}
244
245static struct scsi_host_template it8213_sht = {
246 .module = THIS_MODULE,
247 .name = DRV_NAME,
248 .ioctl = ata_scsi_ioctl,
249 .queuecommand = ata_scsi_queuecmd,
250 .can_queue = ATA_DEF_QUEUE,
251 .this_id = ATA_SHT_THIS_ID,
252 .sg_tablesize = LIBATA_MAX_PRD,
253 .max_sectors = ATA_MAX_SECTORS,
254 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
255 .emulated = ATA_SHT_EMULATED,
256 .use_clustering = ATA_SHT_USE_CLUSTERING,
257 .proc_name = DRV_NAME,
258 .dma_boundary = ATA_DMA_BOUNDARY,
259 .slave_configure = ata_scsi_slave_config,
260 .bios_param = ata_std_bios_param,
Alan9b13b682006-12-07 08:59:14 -0800261};
262
263static const struct ata_port_operations it8213_ops = {
Alan9b13b682006-12-07 08:59:14 -0800264 .set_piomode = it8213_set_piomode,
265 .set_dmamode = it8213_set_dmamode,
266 .mode_filter = ata_pci_default_filter,
267
268 .tf_load = ata_tf_load,
269 .tf_read = ata_tf_read,
270 .check_status = ata_check_status,
271 .exec_command = ata_exec_command,
272 .dev_select = ata_std_dev_select,
273
274 .freeze = ata_bmdma_freeze,
275 .thaw = ata_bmdma_thaw,
276 .error_handler = it8213_error_handler,
277 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Cox5816fbb2007-03-07 16:46:20 +0000278 .cable_detect = it8213_cable_detect,
Alan9b13b682006-12-07 08:59:14 -0800279
280 .bmdma_setup = ata_bmdma_setup,
281 .bmdma_start = ata_bmdma_start,
282 .bmdma_stop = ata_bmdma_stop,
283 .bmdma_status = ata_bmdma_status,
284 .qc_prep = ata_qc_prep,
285 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900286 .data_xfer = ata_data_xfer,
Alan9b13b682006-12-07 08:59:14 -0800287
288 .irq_handler = ata_interrupt,
289 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900290 .irq_on = ata_irq_on,
Alan9b13b682006-12-07 08:59:14 -0800291
Alan Cox81ad1832007-08-22 22:55:41 +0100292 .port_start = ata_sff_port_start,
Alan9b13b682006-12-07 08:59:14 -0800293};
294
295
296/**
297 * it8213_init_one - Register 8213 ATA PCI device with kernel services
298 * @pdev: PCI device to register
299 * @ent: Entry in it8213_pci_tbl matching with @pdev
300 *
301 * Called from kernel PCI layer.
302 *
303 * LOCKING:
304 * Inherited from PCI layer (may sleep).
305 *
306 * RETURNS:
307 * Zero on success, or -ERRNO value.
308 */
309
310static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
311{
312 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +0200313 static const struct ata_port_info info = {
Alan9b13b682006-12-07 08:59:14 -0800314 .sht = &it8213_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400315 .flags = ATA_FLAG_SLAVE_POSS,
Alan9b13b682006-12-07 08:59:14 -0800316 .pio_mask = 0x1f, /* pio0-4 */
317 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400318 .udma_mask = ATA_UDMA4, /* FIXME: want UDMA 100? */
Alan9b13b682006-12-07 08:59:14 -0800319 .port_ops = &it8213_ops,
320 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200321 /* Current IT8213 stuff is single port */
322 const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
Alan9b13b682006-12-07 08:59:14 -0800323
324 if (!printed_version++)
325 dev_printk(KERN_DEBUG, &pdev->dev,
326 "version " DRV_VERSION "\n");
327
Tejun Heo1626aeb2007-05-04 12:43:58 +0200328 return ata_pci_init_one(pdev, ppi);
Alan9b13b682006-12-07 08:59:14 -0800329}
330
331static const struct pci_device_id it8213_pci_tbl[] = {
332 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },
333
334 { } /* terminate list */
335};
336
337static struct pci_driver it8213_pci_driver = {
338 .name = DRV_NAME,
339 .id_table = it8213_pci_tbl,
340 .probe = it8213_init_one,
341 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900342#ifdef CONFIG_PM
Alan9b13b682006-12-07 08:59:14 -0800343 .suspend = ata_pci_device_suspend,
344 .resume = ata_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900345#endif
Alan9b13b682006-12-07 08:59:14 -0800346};
347
348static int __init it8213_init(void)
349{
350 return pci_register_driver(&it8213_pci_driver);
351}
352
353static void __exit it8213_exit(void)
354{
355 pci_unregister_driver(&it8213_pci_driver);
356}
357
358module_init(it8213_init);
359module_exit(it8213_exit);
360
361MODULE_AUTHOR("Alan Cox");
362MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
363MODULE_LICENSE("GPL");
364MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
365MODULE_VERSION(DRV_VERSION);