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Viresh Kumard3f797d2012-04-20 20:15:34 +05301* Synopsys Designware DMA Controller
2
3Required properties:
4- compatible: "snps,dma-spear1340"
5- reg: Address range of the DMAC registers
6- interrupt-parent: Should be the phandle for the interrupt controller
7 that services interrupts for this device
8- interrupt: Should contain the DMAC interrupt number
Viresh Kumara9ddb572012-10-16 09:49:17 +05309- nr_channels: Number of channels supported by hardware
10- is_private: The device channels should be marked as private and not for by the
11 general purpose DMA channel allocator. False if not passed.
12- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 1: descending
14- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
15 increase from chan n->0
16- block_size: Maximum block size supported by the controller
17- nr_masters: Number of AHB masters supported by the controller
18- data_width: Maximum data width supported by hardware per AHB master
19 (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
20- slave_info:
21 - bus_id: name of this device channel, not just a device name since
22 devices may have more than one channel e.g. "foo_tx". For using the
23 dw_generic_filter(), slave drivers must pass exactly this string as
24 param to filter function.
25 - cfg_hi: Platform-specific initializer for the CFG_HI register
26 - cfg_lo: Platform-specific initializer for the CFG_LO register
27 - src_master: src master for transfers on allocated channel.
28 - dst_master: dest master for transfers on allocated channel.
Viresh Kumard3f797d2012-04-20 20:15:34 +053029
30Example:
31
32 dma@fc000000 {
33 compatible = "snps,dma-spear1340";
34 reg = <0xfc000000 0x1000>;
35 interrupt-parent = <&vic1>;
36 interrupts = <12>;
Viresh Kumara9ddb572012-10-16 09:49:17 +053037
38 nr_channels = <8>;
39 chan_allocation_order = <1>;
40 chan_priority = <1>;
41 block_size = <0xfff>;
42 nr_masters = <2>;
43 data_width = <3 3 0 0>;
44
45 slave_info {
46 uart0-tx {
47 bus_id = "uart0-tx";
48 cfg_hi = <0x4000>; /* 0x8 << 11 */
49 cfg_lo = <0>;
50 src_master = <0>;
51 dst_master = <1>;
52 };
53 spi0-tx {
54 bus_id = "spi0-tx";
55 cfg_hi = <0x2000>; /* 0x4 << 11 */
56 cfg_lo = <0>;
57 src_master = <0>;
58 dst_master = <0>;
59 };
60 };
Viresh Kumard3f797d2012-04-20 20:15:34 +053061 };