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Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +03001/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -06006 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +03008 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -06009 * Rajendra Nayak <rnayak@ti.com>
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030010 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley4267b5d2009-06-19 19:08:27 -060011 * Paul Walmsley
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030012 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#include <linux/linkage.h>
Tony Lindgrenee0839c2012-02-24 10:34:35 -080029
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030030#include <asm/assembler.h>
Tony Lindgrenee0839c2012-02-24 10:34:35 -080031
Tony Lindgrendbc04162012-08-31 10:59:07 -070032#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080033#include "iomap.h"
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030034#include "sdrc.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070035#include "cm2xxx_3xxx.h"
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030036
Dave Martinef7a87d2011-03-04 15:33:56 +000037/*
38 * This file needs be built unconditionally as ARM to interoperate correctly
39 * with non-Thumb-2-capable firmware.
40 */
41 .arm
42
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030043 .text
44
Jean Pihet58cda882009-07-24 19:43:25 -060045/* r1 parameters */
Paul Walmsleydf14e472009-06-19 19:08:28 -060046#define SDRC_NO_UNLOCK_DLL 0x0
47#define SDRC_UNLOCK_DLL 0x1
48
49/* SDRC_DLLA_CTRL bit settings */
Paul Walmsley7b7bcef2009-06-19 19:08:29 -060050#define FIXEDDELAY_SHIFT 24
51#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
Paul Walmsleydf14e472009-06-19 19:08:28 -060052#define DLLIDLE_MASK 0x4
53
Paul Walmsley7b7bcef2009-06-19 19:08:29 -060054/*
55 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
56 * FIXEDDELAY should be initialized to 0xf. This apparently was
57 * empirically determined during process testing, so no derivation
58 * was provided.
59 */
60#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
61
Paul Walmsleydf14e472009-06-19 19:08:28 -060062/* SDRC_DLLA_STATUS bit settings */
63#define LOCKSTATUS_MASK 0x4
64
65/* SDRC_POWER bit settings */
66#define SRFRONIDLEREQ_MASK 0x40
Paul Walmsleydf14e472009-06-19 19:08:28 -060067
68/* CM_IDLEST1_CORE bit settings */
69#define ST_SDRC_MASK 0x2
70
71/* CM_ICLKEN1_CORE bit settings */
72#define EN_SDRC_MASK 0x2
73
74/* CM_CLKSEL1_PLL bit settings */
75#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
76
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030077/*
Paul Walmsley4267b5d2009-06-19 19:08:27 -060078 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
Paul Walmsleyc9812d02009-06-19 19:08:26 -060079 *
Jean Pihet58cda882009-07-24 19:43:25 -060080 * Params passed in registers:
81 * r0 = new M2 divider setting (only 1 and 2 supported right now)
82 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
83 * SDRC rates < 83MHz
84 * r2 = number of MPU cycles to wait for SDRC to stabilize after
85 * reprogramming the SDRC when switching to a slower MPU speed
86 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
87 *
88 * Params passed via the stack. The needed params will be copied in SRAM
89 * before use by the code in SRAM (SDRAM is not accessible during SDRC
90 * reconfiguration):
91 * new SDRC_RFR_CTRL_0 register contents
92 * new SDRC_ACTIM_CTRL_A_0 register contents
93 * new SDRC_ACTIM_CTRL_B_0 register contents
94 * new SDRC_MR_0 register value
95 * new SDRC_RFR_CTRL_1 register contents
96 * new SDRC_ACTIM_CTRL_A_1 register contents
97 * new SDRC_ACTIM_CTRL_B_1 register contents
98 * new SDRC_MR_1 register value
99 *
Paul Walmsley18862cb2009-12-08 16:33:14 -0700100 * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
101 * the SDRC CS1 registers
102 *
103 * NOTE: This code no longer attempts to program the SDRC AC timing and MR
104 * registers. This is because the code currently cannot ensure that all
105 * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
106 * SDRAM when the registers are written. If the registers are changed while
107 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
108 * may enter an unpredictable state. In the future, the intent is to
109 * re-enable this code in cases where we can ensure that no initiators are
110 * touching the SDRAM. Until that time, users who know that their use case
111 * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
112 * option.
Paul Walmsley1124d2f2010-12-21 21:08:14 -0700113 *
114 * Richard Woodruff notes that any changes to this code must be carefully
115 * audited and tested to ensure that they don't cause a TLB miss while
116 * the SDRAM is inaccessible. Such a situation will crash the system
117 * since it will cause the ARM MMU to attempt to walk the page tables.
118 * These crashes may be intermittent.
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300119 */
Jean Pihetb6338bd2011-02-02 16:38:06 +0100120 .align 3
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300121ENTRY(omap3_sram_configure_core_dpll)
122 stmfd sp!, {r1-r12, lr} @ store regs to stack
Jean Pihet58cda882009-07-24 19:43:25 -0600123
124 @ pull the extra args off the stack
125 @ and store them in SRAM
Dave Martinef7a87d2011-03-04 15:33:56 +0000126
127/*
128 * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
129 * in Thumb-2: use a r7 as a base instead.
130 * Be careful not to clobber r7 when maintaing this file.
131 */
132 THUMB( adr r7, omap3_sram_configure_core_dpll )
133 .macro strtext Rt:req, label:req
134 ARM( str \Rt, \label )
135 THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
136 .endm
137
Jean Pihet58cda882009-07-24 19:43:25 -0600138 ldr r4, [sp, #52]
Dave Martinef7a87d2011-03-04 15:33:56 +0000139 strtext r4, omap_sdrc_rfr_ctrl_0_val
Jean Pihet58cda882009-07-24 19:43:25 -0600140 ldr r4, [sp, #56]
Dave Martinef7a87d2011-03-04 15:33:56 +0000141 strtext r4, omap_sdrc_actim_ctrl_a_0_val
Jean Pihet58cda882009-07-24 19:43:25 -0600142 ldr r4, [sp, #60]
Dave Martinef7a87d2011-03-04 15:33:56 +0000143 strtext r4, omap_sdrc_actim_ctrl_b_0_val
Jean Pihet58cda882009-07-24 19:43:25 -0600144 ldr r4, [sp, #64]
Dave Martinef7a87d2011-03-04 15:33:56 +0000145 strtext r4, omap_sdrc_mr_0_val
Jean Pihet58cda882009-07-24 19:43:25 -0600146 ldr r4, [sp, #68]
Dave Martinef7a87d2011-03-04 15:33:56 +0000147 strtext r4, omap_sdrc_rfr_ctrl_1_val
Jean Pihet58cda882009-07-24 19:43:25 -0600148 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
149 beq skip_cs1_params @ do not use cs1 params
150 ldr r4, [sp, #72]
Dave Martinef7a87d2011-03-04 15:33:56 +0000151 strtext r4, omap_sdrc_actim_ctrl_a_1_val
Jean Pihet58cda882009-07-24 19:43:25 -0600152 ldr r4, [sp, #76]
Dave Martinef7a87d2011-03-04 15:33:56 +0000153 strtext r4, omap_sdrc_actim_ctrl_b_1_val
Jean Pihet58cda882009-07-24 19:43:25 -0600154 ldr r4, [sp, #80]
Dave Martinef7a87d2011-03-04 15:33:56 +0000155 strtext r4, omap_sdrc_mr_1_val
Jean Pihet58cda882009-07-24 19:43:25 -0600156skip_cs1_params:
Jon Huntera3fed9b2010-09-27 14:02:59 -0600157 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
158 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
159 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
Paul Walmsley69d42552009-05-12 17:27:09 -0600160 dsb @ flush buffered writes to interconnect
Jon Huntera3fed9b2010-09-27 14:02:59 -0600161 isb @ prevent speculative exec past here
Jean Pihet58cda882009-07-24 19:43:25 -0600162 cmp r3, #1 @ if increasing SDRC clk rate,
Tero Kristo3afec6332009-06-19 19:08:29 -0600163 bleq configure_sdrc @ program the SDRC regs early (for RFR)
Jean Pihet58cda882009-07-24 19:43:25 -0600164 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600165 bleq unlock_dll
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300166 blne lock_dll
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600167 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
168 bl configure_core_dpll @ change the DPLL3 M2 divider
Rajendra Nayakdf565562009-07-24 19:44:02 -0600169 mov r12, r2
170 bl wait_clk_stable @ wait for SDRC to stabilize
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600171 bl enable_sdrc @ take SDRC out of idle
Jean Pihet58cda882009-07-24 19:43:25 -0600172 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600173 bleq wait_dll_unlock
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300174 blne wait_dll_lock
Jean Pihet58cda882009-07-24 19:43:25 -0600175 cmp r3, #1 @ if increasing SDRC clk rate,
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600176 beq return_to_sdram @ return to SDRAM code, otherwise,
177 bl configure_sdrc @ reprogram SDRC regs now
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600178return_to_sdram:
Jon Huntera3fed9b2010-09-27 14:02:59 -0600179 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
Paul Walmsley69d42552009-05-12 17:27:09 -0600180 isb @ prevent speculative exec past here
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300181 mov r0, #0 @ return value
182 ldmfd sp!, {r1-r12, pc} @ restore regs and return
183unlock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600184 ldr r11, omap3_sdrc_dlla_ctrl
185 ldr r12, [r11]
Rajendra Nayak8ff120e2009-07-24 19:44:01 -0600186 bic r12, r12, #FIXEDDELAY_MASK
Paul Walmsley7b7bcef2009-06-19 19:08:29 -0600187 orr r12, r12, #FIXEDDELAY_DEFAULT
Paul Walmsleydf14e472009-06-19 19:08:28 -0600188 orr r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600189 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300190 bx lr
191lock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600192 ldr r11, omap3_sdrc_dlla_ctrl
193 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600194 bic r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600195 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300196 bx lr
197sdram_in_selfrefresh:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600198 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
199 ldr r12, [r11] @ read the contents of SDRC_POWER
200 mov r9, r12 @ keep a copy of SDRC_POWER bits
Paul Walmsleydf14e472009-06-19 19:08:28 -0600201 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600202 str r12, [r11] @ write back to SDRC_POWER register
203 ldr r12, [r11] @ posted-write barrier for SDRC
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600204idle_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600205 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
206 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600207 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600208 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300209wait_sdrc_idle:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600210 ldr r11, omap3_cm_idlest1_core
211 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600212 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
213 cmp r12, #ST_SDRC_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300214 bne wait_sdrc_idle
215 bx lr
216configure_core_dpll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600217 ldr r11, omap3_cm_clksel1_pll
218 ldr r12, [r11]
219 ldr r10, core_m2_mask_val @ modify m2 for core dpll
220 and r12, r12, r10
Jean Pihet58cda882009-07-24 19:43:25 -0600221 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600222 str r12, [r11]
223 ldr r12, [r11] @ posted-write barrier for CM
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300224 bx lr
225wait_clk_stable:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600226 subs r12, r12, #1
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300227 bne wait_clk_stable
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300228 bx lr
229enable_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600230 ldr r11, omap3_cm_iclken1_core
231 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600232 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600233 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300234wait_sdrc_idle1:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600235 ldr r11, omap3_cm_idlest1_core
236 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600237 and r12, r12, #ST_SDRC_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600238 cmp r12, #0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300239 bne wait_sdrc_idle1
Paul Walmsleyfa0406a2009-05-12 17:27:09 -0600240restore_sdrc_power_val:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600241 ldr r11, omap3_sdrc_power
242 str r9, [r11] @ restore SDRC_POWER, no barrier needed
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300243 bx lr
244wait_dll_lock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600245 ldr r11, omap3_sdrc_dlla_status
246 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600247 and r12, r12, #LOCKSTATUS_MASK
248 cmp r12, #LOCKSTATUS_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300249 bne wait_dll_lock
250 bx lr
251wait_dll_unlock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600252 ldr r11, omap3_sdrc_dlla_status
253 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600254 and r12, r12, #LOCKSTATUS_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600255 cmp r12, #0x0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300256 bne wait_dll_unlock
257 bx lr
258configure_sdrc:
Jean Pihet58cda882009-07-24 19:43:25 -0600259 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
260 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
261 str r12, [r11] @ store
Paul Walmsley18862cb2009-12-08 16:33:14 -0700262#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
Jean Pihet58cda882009-07-24 19:43:25 -0600263 ldr r12, omap_sdrc_actim_ctrl_a_0_val
264 ldr r11, omap3_sdrc_actim_ctrl_a_0
265 str r12, [r11]
266 ldr r12, omap_sdrc_actim_ctrl_b_0_val
267 ldr r11, omap3_sdrc_actim_ctrl_b_0
268 str r12, [r11]
269 ldr r12, omap_sdrc_mr_0_val
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600270 ldr r11, omap3_sdrc_mr_0
Jean Pihet58cda882009-07-24 19:43:25 -0600271 str r12, [r11]
Paul Walmsley18862cb2009-12-08 16:33:14 -0700272#endif
Jean Pihet58cda882009-07-24 19:43:25 -0600273 ldr r12, omap_sdrc_rfr_ctrl_1_val
274 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
275 beq skip_cs1_prog @ do not program cs1 params
276 ldr r11, omap3_sdrc_rfr_ctrl_1
277 str r12, [r11]
Paul Walmsley18862cb2009-12-08 16:33:14 -0700278#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
Jean Pihet58cda882009-07-24 19:43:25 -0600279 ldr r12, omap_sdrc_actim_ctrl_a_1_val
280 ldr r11, omap3_sdrc_actim_ctrl_a_1
281 str r12, [r11]
282 ldr r12, omap_sdrc_actim_ctrl_b_1_val
283 ldr r11, omap3_sdrc_actim_ctrl_b_1
284 str r12, [r11]
285 ldr r12, omap_sdrc_mr_1_val
286 ldr r11, omap3_sdrc_mr_1
287 str r12, [r11]
Paul Walmsley18862cb2009-12-08 16:33:14 -0700288#endif
Jean Pihet58cda882009-07-24 19:43:25 -0600289skip_cs1_prog:
290 ldr r12, [r11] @ posted-write barrier for SDRC
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300291 bx lr
292
Dave Martinef7a87d2011-03-04 15:33:56 +0000293 .align
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300294omap3_sdrc_power:
295 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
296omap3_cm_clksel1_pll:
297 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
298omap3_cm_idlest1_core:
299 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
300omap3_cm_iclken1_core:
301 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
Jean Pihet58cda882009-07-24 19:43:25 -0600302
303omap3_sdrc_rfr_ctrl_0:
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300304 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600305omap3_sdrc_rfr_ctrl_1:
306 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
307omap3_sdrc_actim_ctrl_a_0:
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300308 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600309omap3_sdrc_actim_ctrl_a_1:
310 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
311omap3_sdrc_actim_ctrl_b_0:
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300312 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600313omap3_sdrc_actim_ctrl_b_1:
314 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600315omap3_sdrc_mr_0:
316 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600317omap3_sdrc_mr_1:
318 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
319omap_sdrc_rfr_ctrl_0_val:
320 .word 0xDEADBEEF
321omap_sdrc_rfr_ctrl_1_val:
322 .word 0xDEADBEEF
323omap_sdrc_actim_ctrl_a_0_val:
324 .word 0xDEADBEEF
325omap_sdrc_actim_ctrl_a_1_val:
326 .word 0xDEADBEEF
327omap_sdrc_actim_ctrl_b_0_val:
328 .word 0xDEADBEEF
329omap_sdrc_actim_ctrl_b_1_val:
330 .word 0xDEADBEEF
331omap_sdrc_mr_0_val:
332 .word 0xDEADBEEF
333omap_sdrc_mr_1_val:
334 .word 0xDEADBEEF
335
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300336omap3_sdrc_dlla_status:
337 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
338omap3_sdrc_dlla_ctrl:
339 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
340core_m2_mask_val:
341 .word 0x07FFFFFF
Dave Martinef7a87d2011-03-04 15:33:56 +0000342ENDPROC(omap3_sram_configure_core_dpll)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300343
344ENTRY(omap3_sram_configure_core_dpll_sz)
345 .word . - omap3_sram_configure_core_dpll
Jean Pihet58cda882009-07-24 19:43:25 -0600346